Semiconductor device, memory system, and method of manufacturing semiconductor device

Abstract

The embodiment of the invention provides a semiconductor device, a manufacturing method thereof and a memory system. The semiconductor device comprises a first stack structure comprising first dielectric layers and plate line layers which are alternately stacked; the storage column penetrates through the first stacking structure and comprises a storage function layer, an inner electrode layer and a conductive contact part which are sequentially arranged from outside to inside; the channel structure is located on one side of the first stacking structure and comprises a gate dielectric layer and a channel column which are sequentially arranged from outside to inside; wherein the conductive contact portion is in contact with the channel column.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a memory system, and a method for manufacturing a semiconductor device. Background Art

[0002] The new memory is widely used in portable medical devices, wearable devices, IoT sensors, industrial and automotive applications due to its advantages such as high-speed interface, ultra-low power operation, instant non-volatile storage and unlimited read and write cycle endurance.

[0003] In the novel memory, each memory cell may include a transistor and a capacitor. Currently, how to optimize the connection structure between the transistor and the capacitor is one of the problems to be solved urgently. Summary of the invention

[0004] The present application provides a semiconductor device, a memory system, and a method for manufacturing a semiconductor device that can at least partially solve the above-mentioned problems existing in the related art or other problems in the art.

[0005] In a first aspect, some embodiments of the present application provide a semiconductor device. The semiconductor device includes: a first stacking structure, including alternately stacked first dielectric layers and plate line layers; a storage pillar, passing through the first stacking structure, and including a storage function layer, an inner electrode layer, and a conductive contact portion arranged in sequence from the outside to the inside; and a channel structure, located on one side of the first stacking structure, and including a gate dielectric layer and a channel pillar arranged in sequence from the outside to the inside; wherein the conductive contact portion contacts the channel pillar.

[0006] In some embodiments, at a contact interface between the conductive contact portion and the channel pillar, a size of the conductive contact portion is larger than a size of the channel pillar.

[0007] In some embodiments, the conductive contact portion is a polysilicon column, and the polysilicon column extends along a stacking direction of the first stacking structure.

[0008] In some embodiments, the memory pillar further includes a first metal silicide layer surrounding the polysilicon pillar.

[0009] In some embodiments, the conductive contact portion is a polysilicon plug, which is disposed close to the channel column; the storage column further includes an insulating column, which is located inside the inner electrode layer and on a side of the polysilicon plug away from the channel column.

[0010] In some embodiments, the memory pillar further includes a second metal silicide layer surrounding the polysilicon plug.

[0011] In some embodiments, the inner electrode layer includes a first metal nitride layer and a first metal layer sequentially disposed from the outside to the inside.

[0012] In some embodiments, the material of the first metal nitride layer includes titanium nitride, and the material of the first metal layer includes tungsten.

[0013] In some embodiments, the semiconductor device further includes: a second stacked structure located on one side of the first stacked structure and including a gate layer and a second dielectric layer located on opposite sides of the gate layer; wherein the channel structure penetrates the second stacked structure.

[0014] In some embodiments, the semiconductor device has a storage area and a connection area, and the memory device further includes a plurality of contact structures located in the connection area, and the plurality of contact structures respectively extend to different board line layers along the stacking direction of the first stacking structure.

[0015] In some embodiments, the contact structure includes a second metal nitride layer and a second metal layer disposed from outside to inside.

[0016] In some embodiments, the material of the channel layer includes polysilicon having a first conductivity type dopant, and the material of the conductive contact includes polysilicon having a second conductivity type dopant.

[0017] In some embodiments, the material of the storage function layer includes a ferroelectric material.

[0018] In a second aspect, some embodiments of the present application provide a memory system, which includes: a memory device, including a semiconductor device as mentioned in any of the above embodiments; and a controller, coupled to the memory device, for controlling the memory device to store data.

[0019] In a third aspect, some embodiments of the present application provide a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes: forming a first stack structure including a first dielectric layer and a plate line layer alternately stacked; forming a storage column passing through the first stack structure, the storage column including a storage function layer, an inner electrode layer, and a conductive contact portion sequentially arranged from the outside to the inside; and forming a channel structure on one side of the first stack structure, the channel structure including a gate dielectric layer and a channel column sequentially arranged from the outside to the inside, the channel column contacting the conductive contact portion.

[0020] In some embodiments, forming a storage column passing through the first stacking structure includes: forming a storage hole passing through the first stacking structure; sequentially forming a storage function layer and an inner electrode layer on an inner wall of the storage hole; and forming a conductive contact portion in at least a portion of a space enclosed by the inner electrode layer.

[0021] In some embodiments, forming a conductive contact in at least a portion of the inner electrode layer enclosed space includes forming a polysilicon pillar in the inner electrode layer enclosed space.

[0022] In some embodiments, forming a polysilicon column in the space enclosed by the inner electrode layer includes: heat treating the polysilicon column by a furnace annealing process.

[0023] In some embodiments, the manufacturing method of the semiconductor device also includes: forming an insulating column at the bottom of the space enclosed by the inner electrode layer; wherein, forming a conductive contact portion in at least a portion of the space enclosed by the inner electrode layer includes: forming a polysilicon plug in the space enclosed by the inner electrode layer and the insulating column.

[0024] In some embodiments, forming a polysilicon plug in the space surrounded by the inner electrode layer and the insulating pillar includes: thermally treating the polysilicon plug by a laser annealing process.

[0025] In some embodiments, sequentially forming a storage function layer and an inner electrode layer on the inner wall of the storage hole includes: sequentially forming a first metal nitride layer and a first metal layer on the inner wall of the storage function layer to form an inner electrode layer. According to at least one embodiment of the present application, the semiconductor device, memory system and semiconductor device manufacturing method provided by the present application can increase the contact area between the channel column and the inner electrode layer by providing a conductive contact portion in the storage column and making the conductive contact portion contact with the channel column, thereby improving the electrical connection performance and reliability between the channel column and the inner electrode layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0027] Figure 1A is a block diagram of a system having a memory system provided by an embodiment of the present application;

[0028] Figure 1B and Figure 1C is a schematic diagram of a memory system provided by an embodiment of the present application;

[0029] Figure 2 is a circuit diagram of a storage unit provided in an embodiment of the present application;

[0030] Figure 3 is a schematic diagram of a top view of a semiconductor device provided in an embodiment of the present application;

[0031] Figure 4 The embodiment of the present application provides Figure 3 A schematic cross-sectional structure diagram taken along line AA' is shown;

[0032] Figure 5 is a schematic diagram of a cross-sectional structure of a semiconductor device provided by an embodiment of the present application taken within a connection region;

[0033] Figure 6is a schematic cross-sectional structural diagram of a semiconductor device provided in another embodiment of the present application;

[0034] Figure 7 yes Figure 6 An enlarged schematic diagram of region B is shown;

[0035] Figure 8 is a schematic cross-sectional structural diagram of a semiconductor device provided in yet another embodiment of the present application;

[0036] Fig. 9 is a schematic cross-sectional structural diagram of a semiconductor device provided in yet another embodiment of the present application;

[0037] Fig.10 is a schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0038] FIG. 11A to FIG. 11C is a schematic diagram of a cross-sectional structure of a semiconductor device provided in an embodiment of the present application during a manufacturing process; and

[0039] Fig.12 It is a schematic diagram of the cross-sectional structure of a semiconductor device during the manufacturing process provided by another embodiment of the present application. DETAILED DESCRIPTION

[0040] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0041] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first stacking structure discussed in this application may also be referred to as the second stacking structure, and vice versa.

[0042] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0043] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0044] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0045] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method recorded in this application are not necessarily limited to the recorded order, but can be performed in any order or in parallel.

[0046] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0047] The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0048] Figure 1A 1 is a block diagram of a system having a memory system provided by an embodiment of the present application. For example, the memory system 12 may be a ferroelectric random access memory (FeRAM).

[0049] like Figure 1A As shown, the system 11 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device has the memory system 12 located therein). Figure 1AAs shown, the system 11 may include a host 18 and a memory system 12. The memory system 12 has one or more memory devices 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from the memory device 14.

[0050] In some embodiments, the controller 16 is coupled to the memory device 14 and the host 18, and is configured to control the memory device 14. For example, the controller 16 may be configured to control the memory device 14 such as read, erase, and program operations. The controller 16 may also manage data stored in the memory device 14 and communicate with the host 18. For example, the controller 16 may communicate with an external device (e.g., the host 18) according to a specific communication protocol.

[0051] In some embodiments, the controller 16 and one or more memory devices 14 may be integrated into various types of memory systems. Figure 1B In one example shown in FIG. 1 , the controller 16 and the single memory device 14 may be integrated into a memory card 22. The memory card 22 may further include a memory card connector 24 that couples the memory card 22 to a host (e.g., the host 18 in FIG. A). Figure 1C In another example shown in FIG. 1 , the controller 16 and the plurality of memory devices 14 may be integrated into an SSD 26. The SSD 26 may further include a processor that interfaces the SSD 26 with a host (e.g., Figure 1A An SSD connector 28 coupled to the host 18).

[0052] Figure 2 is a circuit diagram of a storage unit provided in an embodiment of the present application. Figure 2 As shown, the storage unit 111 includes a transistor T. For example, the transistor T may include a metal-oxide-semiconductor field-effect transistor (MOSFET). In some embodiments, the transistor T may be an NMOS (N-channel metal-oxide-semiconductor transistor) or a PMOS (P-channel metal-oxide-semiconductor transistor). The storage unit 111 also includes at least two capacitors. For example, the capacitor C may include a ferroelectric capacitor. Figure 2It is exemplarily shown that the storage unit 111 includes three capacitors C. Of course, it may also include two capacitors C, or more capacitors C.

[0053] In the memory cell 111, the first electrode of the transistor T is electrically connected to the bit line BL, the control terminal of the transistor T is electrically connected to the word line WL, the first terminals of the plurality of capacitors C are electrically connected to the second electrode of the transistor T, and the second terminal of each capacitor C is electrically connected to the plate line PL. In the present application, one of the drain or source of the transistor T is referred to as the first electrode, the corresponding other electrode is referred to as the second electrode, and the control terminal of the transistor T is the gate.

[0054] In this embodiment, a storage unit 111 includes a plurality of capacitors C electrically connected to a transistor T, so that a storage unit 111 can be used to store multiple bits of data to increase the storage capacity of each storage unit. From another perspective, a plurality of capacitors C share a transistor T, which can reduce the number of transistors T in each storage unit 111 to increase storage density.

[0055] for Figure 2 For a storage unit 111 shown, when the capacitor C is a ferroelectric capacitor, in the writing stage, the word line WL is used to receive the word line control signal, so that the transistor T is turned on, the bit line BL is used to receive the bit line control signal, and the plate line PL electrically connected to the selected capacitor C is used to receive the plate line control signal. The voltage difference between the bit line control signal and the plate line control signal causes the ferroelectric layer of the selected capacitor C to be positively polarized or negatively polarized, so as to write different logical information in the selected capacitor C. For example, when the ferroelectric layer is positively polarized, the logical signal "0" is written. For another example, when the ferroelectric layer is negatively polarized, the logical signal "1" is written.

[0056] The reading stage includes a first reading stage, a second reading stage and a third reading stage. In the first reading stage, the word line WL is used to receive a word line control signal to turn on the transistor T, and the bit line BL is used to receive a bit line control signal to precharge the voltage of the first end of the selected capacitor C; in the second reading stage, the word line WL is used to receive another word line control signal to turn off the transistor T, and the plate line PL electrically connected to the selected capacitor C is used to receive the plate line control signal. The voltage difference between the plate line control signal and the first end may keep the polarization direction of the ferroelectric layer of the selected capacitor C unchanged, or may cause the polarization direction of the ferroelectric layer of the selected capacitor C to flip, so as to release the polarization charge and change the voltage on the bit line BL; in the third reading stage, the word line WL is used to receive a word line electrical control signal to turn on the transistor T, detect the voltage or current on the bit line BL, determine whether the polarization direction of the selected capacitor C is flipped, and then read the logic information stored therein.

[0057] Will Figure 2 The memory cells 111 shown are arranged in an array to obtain a memory cell array. The circuit structure of each memory cell 111 is the same. Those skilled in the art can design the arrangement of the memory cells 111 and the number of the memory cells 111 in the memory cell array according to the storage capacity requirements of the memory system.

[0058] Figure 3 It is a schematic diagram of the top view structure of the semiconductor device provided in an embodiment of the present application. Figure 4 The embodiment of the present application provides Figure 3 The cross-sectional structure schematic diagram taken along line AA' is shown. Figure 5 1 is a schematic diagram of a cross-sectional structure of a semiconductor device provided by an embodiment of the present application taken in a connection region. For example, the semiconductor device may be a part of a memory device in the above-mentioned memory system.

[0059] It should be noted that, in the following, the x-direction, y-direction, and z-direction in each figure illustrate the spatial relationship of the components in the semiconductor device. For example, the z-direction is the stacking direction of the first stacking structure, and the x-direction and the y-direction are two directions perpendicular to each other on a plane perpendicular to the stacking direction. The same concept will be used throughout this application to describe the spatial relationship of the components in the semiconductor device.

[0060] like Figure 4 As shown, the semiconductor device 200 includes a first stacked structure 221. The first stacked structure 221 includes first dielectric layers 222 and board line layers 223 that are alternately stacked. For example, the first dielectric layer 222 may be silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. Exemplarily, the material of the plate line layer 223 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polycrystalline silicon (Poly-Si), indium tin oxide (ITO) or any other suitable conductive material. In the first stacked structure 221, the thickness of each of the multiple first dielectric layers 222 may be the same or different, and the thickness of each of the multiple plate line layers 223 may be the same or different. The thickness of the first dielectric layer 222 and the plate line layer 223 can be selected according to actual needs. In addition, Figure 4 It is exemplarily shown that the first stacking structure 221 includes two board line layers 223. In an optional embodiment, the first stacking structure 221 may also include three board line layers 223, or more board line layers 223, and the present application does not impose any specific limitation on this.

[0061] In some embodiments, Figure 4As shown, the first stacked structure 221 is located on one side of the substrate 211. For example, the substrate 211 can be used to support the first stacked structure 221. Exemplarily, the substrate 211 can be a semiconductor substrate. For example, the material of the substrate 211 can be silicon (Si), germanium (Ge), gallium arsenide (GaAs) or indium phosphide (InP). Exemplarily, the substrate 211 can be a silicon on insulator (SOI) or germanium on insulator (GeOI) substrate, etc.

[0062] like Figure 4 As shown, the semiconductor device 200 further includes a storage column 231. The storage column 231 may have an outer contour that is approximately cylindrical, and, for example, passes through the first stacked structure 221 along the z direction. For example, the storage column 231 extends from the surface of the first stacked structure 221 away from the substrate 211 toward the substrate 211, and stays in the first dielectric layer 222 closest to the substrate 211. The storage column 231 includes a storage function layer 232, an inner electrode layer 233, and a polysilicon column 234 that are sequentially arranged from the outside to the inside. The storage function layer 232 and the inner electrode layer 233 may be approximately tubular structures with closed ends close to the substrate 211, and the inner electrode layer 233 is embedded in the inner side of the storage function layer 232 and contacts it. In this embodiment, the polysilicon column 234 is located on the inner side of the inner electrode layer 233 as a conductive contact portion. The polysilicon column 234 extends along the z direction to occupy the entire inner space of the inner electrode layer 233. Exemplarily, the material of the polysilicon pillar 234 is polysilicon with a second conductivity type dopant, such as phosphorus (P), so that the polysilicon pillar 234 is N-type conductive.

[0063] In some embodiments, the material of the storage function layer 232 may be a ferroelectric material. When an electric field is applied to the ferroelectric layer, the central atoms stop at a low energy state along the electric field. Conversely, when the electric field is reversed and applied to the ferroelectric layer, the central atoms move in the crystal along the direction of the electric field and stop at another low energy state. A large number of central atoms move and couple in the crystal unit cell to form ferroelectric domains, which form polarized charges under the action of the electric field. The polarized charge formed by the reversal of the ferroelectric domain under the electric field is higher, and the polarized charge formed by the non-reversal of the ferroelectric domain under the electric field is lower. The binary stable state of this ferroelectric material allows it to be used as a storage function layer to store logical information. Exemplarily, the ferroelectric material may include zirconium oxide (ZrO2), hafnium oxide (HfO2), aluminum (Al) doped HfO2, silicon (Si) doped HfO2, zirconium (Zr) doped HfO2, lanthanum (La) doped HfO2, yttrium (Y) doped HfO2, and one or more of other elements doped based on the ferroelectric material.

[0064] In some embodiments, the material of the inner electrode layer 233 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polycrystalline silicon (Poly-Si), indium tin oxide (ITO) or any other suitable conductive material.

[0065] In the semiconductor device 200, the portion of the storage function layer 232 and the inner electrode layer 233 respectively surrounded by a plate line layer 223, and the portion of the plate line layer 223 in contact with the storage function layer 232 constitute a capacitor C. For example, a ferroelectric capacitor C. Among them, the portion of the inner electrode layer 233 surrounded by the plate line layer 223 serves as the first end of the capacitor C, the portion of the plate line layer 223 in contact with the storage function layer 232 serves as the second end of the capacitor, and the other portion of the plate line layer 223 serves as the plate line PL. In this way, multiple capacitors C are arranged along the z direction, and the first ends of the multiple capacitors C share the inner electrode layer 233 to achieve electrical connection with each other.

[0066] like Figure 4 As shown, the semiconductor device 200 also includes a channel structure 241. The channel structure 241 is located on a side of the first stacked structure 221 away from the substrate 211, and includes a gate dielectric layer 242 and a channel column 243 arranged in sequence from the outside to the inside. The channel structure 241 may have an outer contour that is roughly cylindrical. The gate dielectric layer 242 may be roughly a tubular structure with two ends open, and the channel column 243 is located on the inner side of the gate dielectric layer 242. In other words, the gate dielectric layer 242 surrounds the outer side wall of the channel column 243. Exemplarily, the material of the gate dielectric layer 242 may be silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. Exemplarily, the material of the channel pillar 243 may be one or more of semiconductor materials such as polycrystalline silicon (Poly-Si), amorphous silicon (α-Si), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium tin oxide (ITO), etc. For example, the material of the channel pillar 243 may be polycrystalline silicon with a first conductive type dopant. Optionally, the dopant of the first conductive type may include boron (B), so that the channel pillar 243 is P-type conductive. That is, the transistor T may be an NMOS tube.

[0067] In some embodiments, the semiconductor device 200 may further include a second stacked structure 251. The second stacked structure 251 is located on a side of the first stacked structure 221 away from the substrate 211, and includes a gate layer 253 and a second dielectric layer 252 located on opposite sides of the gate layer 253. The channel structure 241 may penetrate the second stacked structure 251 and be connected to the storage pillar 231. For example, the material of the second dielectric layer 252 may be silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. The material of the gate layer 253 can be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO) or any other suitable conductive material.

[0068] In the semiconductor device 200, the channel pillar 243, the gate dielectric layer 242, and a portion of the gate layer 253 in contact with the gate dielectric layer 242 constitute a transistor T. For example, a vertical channel transistor T. For example, the end of the channel pillar 243 away from the storage pillar 231 serves as the first electrode of the transistor T, the end of the polysilicon pillar 234 (i.e., the conductive contact portion) close to the channel pillar 243 serves as the second electrode of the transistor T, a portion of the gate layer 253 in contact with the gate dielectric layer 242 serves as the gate of the transistor T, and the other portion of the gate layer 253 serves as the word line WL. In this way, the transistor T and the plurality of capacitors C constitute a storage unit.

[0069] The channel pillar 243 in the channel structure 241 is in direct contact with the polysilicon pillar 234 in the storage pillar 231, so that the end of the channel pillar 243 close to the storage pillar 231 is electrically connected to the inner electrode layer 233 through the polysilicon pillar 234. For example, at the contact interface between the polysilicon pillar 234 and the channel pillar 243, the size (e.g., diameter) of the polysilicon pillar 234 is greater than the size (e.g., diameter) of the channel pillar 243.

[0070] In this embodiment, by providing a polysilicon column 234 as a conductive contact portion in the storage column 231 , the contact area between the channel column 243 and the internal electrode layer 233 can be increased, thereby improving the electrical connection performance and reliability between the channel column 243 and the internal electrode layer 233 .

[0071] In some embodiments, Figure 3 and Figure 4As shown, the substrate 211 and the first stacked structure 221 extend laterally along the x-direction and the y-direction, and are divided into a storage area 201 and a connection area 202 along the y-direction. In the storage area 201, a plurality of storage cells (corresponding to the channel structure 241) are arranged in an array along the x-direction and the y-direction. In the connection area 202, the semiconductor device 200 may further include a plurality of contact structures (not shown) and gate contacts (not shown), which are respectively used to lead the plate line layer 223 and the gate layer 253 out along the z-direction, which will be described in detail below.

[0072] In some embodiments, Figure 3 and Figure 4 As shown, the semiconductor device 200 may further include an isolation structure 261. For example, the isolation structure 261 penetrates the second stacked structure 251 and extends into the first dielectric layer 222 closest to the substrate 211 in the first stacked structure 221. The isolation structure 261 may also extend in the storage area 201 and the connection area 202 along the y direction to divide the storage blocks. It should be noted that the position and arrangement of the storage area 201 and the connection area 202 may be selected according to actual needs, and this application does not impose any specific restrictions on this.

[0073] In some embodiments, Figure 4 As shown, the semiconductor device 200 may further include a bit line contact 262 and a gate contact 263. The bit line contact 262 is located on a side of the second stacked structure 251 away from the first stacked structure 221, and is electrically connected to the channel pillar 243. For example, the bit line contact 262 may serve as a connection structure between a bit line (not shown) and the channel pillar 243. The gate contact 263 is located on a side of the second stacked structure 251 away from the first stacked structure 221, and, for example, extends along the z direction into the gate layer 253 to be electrically connected to the gate layer 253. Exemplarily, the material of the bit line contact 262 and the gate contact 263 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material.

[0074] In some embodiments, Figure 5As shown, in the connection area 202, the semiconductor device 200 may further include a plurality of contact structures 264. For example, each contact structure 264 may have an outer contour that is approximately cylindrical. The plurality of contact structures 264 extend to the plate line layers 223 of different layers along the z direction, respectively, to be electrically connected to the plate line layers 223 of different layers, and to lead the plate line layers 223 out along the z direction. Exemplarily, the contact structure 264 may include a second metal nitride layer 265 and a second metal layer 266 arranged from the outside to the inside. For example, the second metal nitride layer 265 may be approximately a tubular structure with an end portion closed near the substrate 211, and the second metal layer 266 may be approximately a hollow columnar structure and embedded inside the second metal nitride layer 265. Exemplarily, the material of the second metal nitride layer 265 may include titanium nitride (TiN) and / or tantalum nitride (TaN). The material of the second metal layer 266 can be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti) or any other appropriate metal material. The second metal layer 266 can improve the conductivity of the contact structure 264, and the second metal nitride layer 265 can improve the bonding performance between the second metal layer 266 and other outer film layers.

[0075] In some embodiments, the semiconductor device 200 may further include a protective layer 267. The protective layer 267 may be sleeved outside the contact structure 264 and used to protect the plate line layer 223 from being damaged during the manufacturing process of the contact structure 264. Exemplarily, the material of the protective layer 267 may be different from the material of the plate line layer 223, so that the protective layer 267 and the plate line layer 223 have different etching selectivities relative to the same etching material. For example, the material of the protective layer 267 may be silicon oxide (SiO2).

[0076] Figure 6 It is a schematic cross-sectional structure diagram of a semiconductor device provided in another embodiment of the present application. Figure 7 yes Figure 6 An enlarged schematic diagram of region B is shown. For the purpose of concise description, the same structure as the semiconductor device 200 described in the above embodiment will not be described in detail in the following embodiments.

[0077] like Figure 6As shown, unlike the semiconductor device 200, in the semiconductor device 300, the storage column 331 includes a storage function layer 332, an inner electrode layer 333, a first metal silicide layer 335 and a polysilicon column 334 arranged in sequence from the outside to the inside. The first metal silicide layer 335 can be roughly a tubular structure with a closed end close to the substrate 311, and is located between the inner electrode layer 333 and the polysilicon column 334. Exemplarily, the material of the first metal silicide layer 335 may include one or more of titanium silicide (TiSi2), cobalt silicide (TiSi2), platinum nickel alloy silicide (NiPtSi), etc. In this embodiment, by providing the first metal silicide layer 335, the contact resistance between the polysilicon column 334 and the inner electrode layer 333 can be reduced, and the conductivity can be improved.

[0078] In some embodiments, Figure 7 As shown, in the storage column 331, the inner electrode layer 333 includes a first metal nitride layer 3331 and a first metal layer 3332 arranged in sequence from the outside to the inside. Exemplarily, the material of the first metal nitride layer 3331 may include titanium nitride (TiN) and / or tantalum nitride (TaN). The material of the first metal layer 3332 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti) or any other appropriate metal material. The first metal layer 3332 can improve the overall conductivity of the inner electrode layer 333, and the first metal nitride layer 3331 can improve the bonding performance between the first metal layer 3332 and the storage function layer 332.

[0079] Figure 8 FIG. 1 is a schematic diagram of a cross-sectional structure of a semiconductor device provided by another embodiment of the present application. Figure 8 As shown, unlike the semiconductor device 200, in the semiconductor device 400, the storage column 431 includes a storage function layer 432, an inner electrode layer 433 and a polysilicon plug 436 arranged in sequence from the outside to the inside. Among them, the polysilicon plug 436 serves as a conductive contact. In this embodiment, the polysilicon plug 436 is arranged near the channel column 443. For example, the polysilicon plug 436 is located on the inner side of the inner electrode layer 433 and occupies part of the inner space of the inner electrode layer 433 near the channel column 443. Exemplarily, the material of the polysilicon plug 436 is polysilicon with a second conductivity type dopant. For example, the second conductivity type dopant may include phosphorus (P), so that the polysilicon plug 436 is N-type conductive.

[0080] The storage pillar 431 may further include an insulating pillar 437. The insulating pillar 437 is located on the inner side of the inner electrode layer 433 and on the side of the polysilicon plug 436 away from the channel pillar 443, and the insulating pillar 437 is in contact with the polysilicon plug 436. For example, the insulating pillar 437 occupies part of the inner space of the inner electrode layer 433 away from the channel pillar 443, and occupies the entire inner space of the inner electrode layer 433 together with the polysilicon plug 436. Exemplarily, the insulating pillar 437 may be made of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. For example, the insulating column 437 can play a role in supporting the polysilicon plug 436.

[0081] In this embodiment, by providing a polysilicon plug 436 as a conductive contact portion in the storage column 431, the contact area between the channel column 443 and the internal electrode layer 433 can be increased, thereby improving the electrical connection performance and reliability between the channel column 443 and the internal electrode layer 433. At the same time, the thermal budget in the manufacturing process can be reduced, and the impact on the thermal degradation of the storage function layer 432 can also be reduced.

[0082] Fig. 9 FIG. 1 is a schematic diagram of a cross-sectional structure of a semiconductor device provided in yet another embodiment of the present application. Fig. 9 As shown, in the semiconductor device 500, the storage column 531 includes a storage function layer 532 and an inner electrode layer 533 which are sequentially arranged from the outside to the inside. On the inner side of the inner electrode layer 533, the polysilicon plug 536 is arranged close to the channel column 543, and the insulating column 537 is arranged away from the channel column 543. The storage column 531 may also include a second metal silicide layer 538. The second metal silicide layer 538 surrounds the polysilicon plug 536. For example, the second metal silicide layer 538 is located at the sidewall and bottom (close to the end of the substrate 511) of the polysilicon plug 536, so that the top of the polysilicon plug 536 (away from the end of the substrate 511) is in contact with the channel column 543. Exemplarily, the material of the second metal silicide layer 538 may include one or more of titanium silicide (TiSi2), cobalt silicide (TiSi2), platinum nickel alloy silicide (NiPtSi), etc.

[0083] In this embodiment, the second metal silicide layer 538 is provided to reduce the contact resistance between the polysilicon plug 536 and the internal electrode layer 533 and improve the conductivity.

[0084] An embodiment of the present application also provides a method for manufacturing a semiconductor device. Fig.10 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application. Fig.10As shown, a method 600 for manufacturing a semiconductor device (hereinafter referred to as manufacturing method 600 ) may include the following steps.

[0085] S610 , forming a first stack structure including first dielectric layers and board line layers alternately stacked.

[0086] S620, forming a storage column passing through the first stacking structure, the storage column including a storage function layer, an inner electrode layer and a conductive contact portion arranged in sequence from the outside to the inside.

[0087] S630, forming a channel structure on one side of the first stack structure, the channel structure comprising a gate dielectric layer and a channel column arranged in sequence from outside to inside, the channel column being in contact with the conductive contact portion.

[0088] According to the manufacturing method of the semiconductor device provided in this embodiment, by setting a conductive contact portion in the storage column and making the conductive contact portion contact with the channel column, the contact area between the channel column and the internal electrode layer can be increased, thereby improving the electrical connection performance and reliability between the channel column and the internal electrode layer.

[0089] FIG. 11A to FIG. 11C is a schematic diagram of a cross-sectional structure of a semiconductor device during the manufacturing process provided by an embodiment of the present application. For example, the intermediate structure of the semiconductor device during the manufacturing process in this embodiment can be based on Fig.10 The manufacturing method shown is formed and used to form Figure 4 The semiconductor device 200 is shown. FIG. 11A to FIG. 11C as well as Figure 4 The above-mentioned steps S610 to S630 are described.

[0090] In step S610, Fig.11A As shown, the first dielectric layer 222 and the board line layer 223 may be alternately formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, thereby forming a first stacked structure 221.

[0091] In step S620, if Fig. 11C As shown, a storage column 231 passing through the first stacked structure 221 can be formed by photolithography and etching processes and thin film deposition processes. The storage column 231 includes a storage function layer 232, an inner electrode layer 233 and a polysilicon column 234 arranged in sequence from the outside to the inside. The polysilicon column 234 serves as a conductive contact portion.

[0092] In some embodiments, the storage pillar 231 may be formed by a manufacturing method described below. First, Fig.11A and Fig. 11B As shown, a storage hole 239 passing through the first stacked structure 221 may be formed by photolithography and etching (eg, dry etching or wet etching) processes. Fig. 11B and Fig. 11C As shown, a storage function layer 232 may be formed on the inner wall of the storage hole 239 by using a thin film deposition process such as CVD, PVD, ALD or any combination thereof, and an inner electrode layer 233 may be formed on the surface of the storage function layer 232. Then, a polysilicon column 234 is formed in the space surrounded by the inner electrode layer 233. Optionally, a first metal nitride layer 3331 and a first metal layer 3332 may be sequentially formed on the surface of the storage function layer 232 (see Figure 7 ) to form the internal electrode layer 233.

[0093] In some embodiments, the material of the polysilicon column 234 may be polysilicon with a second conductivity type dopant. For example, an in-situ doping process may be used to directly form a polysilicon column 234 with a second conductivity type in the space enclosed by the inner electrode layer 233. For another example, the polysilicon column 234 may be first formed in the space enclosed by the inner electrode layer 233, and then a dopant with a second conductivity type may be doped into the polysilicon column 234. Optionally, the dopant of the second conductivity type may include phosphorus (P), so that the polysilicon column 234 is N-type conductive. In some embodiments, after the polysilicon column 234 is formed, the polysilicon column 234 may be heat treated by a furnace annealing process to activate the dopant and repair damage.

[0094] In step S630, Figure 4 As shown, a channel structure 241 is formed on one side of the first stacked structure 221 . The channel structure 241 includes a gate dielectric layer 242 and a channel column 243 which are sequentially arranged from the outside to the inside. The channel column 243 is in contact with the polysilicon column 234 .

[0095] In this embodiment, by forming a polysilicon column 234 in the storage column 231 and making the polysilicon column 234 contact with the channel column 243, the contact area between the channel column 243 and the internal electrode layer 233 can be increased, thereby improving the electrical connection performance and reliability between the channel column 243 and the internal electrode layer 233.

[0096] Fig.12 FIG. 1 is a schematic diagram of a cross-sectional structure of a semiconductor device during the manufacturing process provided by another embodiment of the present application. For example, the intermediate structure of the semiconductor device during the manufacturing process in this embodiment can be based on Fig.10 The manufacturing method shown is formed and used to form Figure 8 The semiconductor device 400 is shown. In this embodiment, step S610 is the same as the previous embodiment, and the present application will not repeat it here. Fig.12 and Figure 8Steps S620 and S630 are described.

[0097] In step S620, if Fig.12 As shown, a storage column 431 passing through the first stacked structure 421 can be formed by photolithography and etching processes and thin film deposition processes. The storage column 431 includes a storage function layer 432 and an inner electrode layer 433 arranged in sequence from the outside to the inside. A polysilicon plug 436 and an insulating column 437 are located inside the inner electrode layer 433. Among them, the polysilicon plug 436 serves as a conductive contact portion.

[0098] In some embodiments, the storage pillar 431 may be formed by a manufacturing method described below. First, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to deposit a thin film in the storage hole 239 (see FIG. Fig. 11B ) is formed on the inner wall of the storage function layer 432, and an inner electrode layer 433 is formed on the surface of the storage function layer 432. Then, an insulating column 437 is formed at the bottom of the space surrounded by the inner electrode layer 433, and a polysilicon plug 436 is formed in the space surrounded by the inner electrode layer 433 and the insulating column 437.

[0099] In some embodiments, the material of the polysilicon plug 436 may be polysilicon with a second conductivity type dopant. For example, the polysilicon plug 436 with the second conductivity type may be formed directly in the space enclosed by the inner electrode layer 433 and the insulating pillar 437 by an in-situ doping process. For another example, the polysilicon plug 436 may be first formed in the space enclosed by the inner electrode layer 433 and the insulating pillar 437, and then the dopant with the second conductivity type may be doped into the polysilicon plug 436. Optionally, the dopant of the second conductivity type may include phosphorus (P), so that the polysilicon plug 436 is N-type conductive. In some embodiments, after the polysilicon plug 436 is formed, the polysilicon plug 436 may be heat treated by a laser annealing process to activate the dopant and repair damage.

[0100] In step S630, Figure 8 As shown, a channel structure 441 is formed on one side of the first stacked structure 421 . The channel structure 441 includes a gate dielectric layer 442 and a channel pillar 443 which are sequentially arranged from the outside to the inside. The channel pillar 443 is in contact with the polysilicon plug 436 .

[0101] In this embodiment, by forming a polysilicon plug 436 in the storage pillar 431 and making the polysilicon plug 436 contact the channel pillar 443, the contact area between the channel pillar 443 and the internal electrode layer 433 can be increased, thereby improving the electrical connection performance and reliability between the channel pillar 443 and the internal electrode layer 433. In addition, since the volume of the polysilicon plug 436 is relatively small, the heat treatment of the polysilicon plug 436 through the laser annealing process can reduce the thermal budget and reduce the impact of thermal degradation on the storage function layer 432.

[0102] The above description is only an implementation method of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor device, characterized in that: include: A first stacking structure includes first dielectric layers and board line layers alternately stacked; A storage column, passing through the first stacking structure, and comprising a storage function layer, an inner electrode layer and a conductive contact portion arranged in sequence from the outside to the inside; as well as A channel structure, located on one side of the first stacked structure, and comprising a gate dielectric layer and a channel column arranged in sequence from outside to inside; Wherein, the conductive contact portion contacts the channel pillar.

2. The semiconductor device according to claim 1, wherein At a contact interface between the conductive contact portion and the channel pillar, a size of the conductive contact portion is larger than a size of the channel pillar.

3. The semiconductor device according to claim 1, wherein The conductive contact portion is a polysilicon column, and the polysilicon column extends along a stacking direction of the first stacking structure.

4. The semiconductor device according to claim 3, wherein: The storage pillar further includes a first metal silicide layer surrounding the polysilicon pillar.

5. The semiconductor device according to claim 1, wherein The conductive contact portion is a polysilicon plug, and the polysilicon plug is arranged close to the channel pillar; The storage column further includes an insulating column, which is located inside the inner electrode layer and on a side of the polysilicon plug away from the channel column.

6. The semiconductor device according to claim 5, wherein: The storage pillar further includes a second metal silicide layer surrounding the polysilicon plug.

7. The semiconductor device according to claim 3 or 5, wherein: The inner electrode layer includes a first metal nitride layer and a first metal layer which are sequentially arranged from the outside to the inside.

8. The semiconductor device according to claim 7, wherein: The material of the first metal nitride layer includes titanium nitride, and the material of the first metal layer includes tungsten.

9. The semiconductor device according to claim 1, wherein: Also includes: A second stacked structure, located on one side of the first stacked structure, and comprising a gate layer and a second dielectric layer located on two opposite sides of the gate layer; Wherein, the channel structure runs through the second stacking structure.

10. The semiconductor device according to claim 1, wherein The semiconductor device has a storage area and a connection area. The memory device further comprises a plurality of contact structures located in the connection area. The plurality of contact structures extend to different board line layers respectively along the stacking direction of the first stacking structure.

11. The semiconductor device according to claim 10, wherein: The contact structure includes a second metal nitride layer and a second metal layer arranged from outside to inside.

12. The semiconductor device according to claim 1, wherein The material of the channel layer includes polysilicon having a first conductive type dopant, and the material of the conductive contact includes polysilicon having a second conductive type dopant.

13. The semiconductor device according to claim 1, wherein The material of the storage function layer includes ferroelectric material.

14. A memory system, characterized in that: include: A memory device comprising the semiconductor device according to any one of claims 1 to 13; as well as The controller is coupled to the memory device and is used to control the memory device to store data.

15. A method for manufacturing a semiconductor device, characterized in that: include: forming a first stack structure including first dielectric layers and board line layers alternately stacked; forming a storage column passing through the first stack structure, wherein the storage column comprises a storage function layer, an inner electrode layer and a conductive contact portion arranged in sequence from outside to inside; as well as A channel structure is formed on one side of the first stacked structure, wherein the channel structure includes a gate dielectric layer and a channel column which are sequentially arranged from the outside to the inside, and the channel column is in contact with the conductive contact portion.

16. The manufacturing method according to claim 15, wherein: Forming a storage column passing through the first stack structure includes: forming a storage hole through the first stacking structure; forming the storage function layer and the inner electrode layer in sequence on the inner wall of the storage hole; and The conductive contact portion is formed in at least a portion of the inner electrode layer enclosed space.

17. The manufacturing method according to claim 16, wherein: Forming the conductive contact portion in at least a portion of the inner electrode layer enclosed space includes: A polysilicon column is formed in the inner electrode layer enclosed space.

18. The manufacturing method according to claim 17, wherein: Forming a polysilicon column in the inner electrode layer enclosed space includes: The polysilicon column is heat treated by a furnace annealing process.

19. The manufacturing method according to claim 16, wherein: Also includes: forming an insulating column at the bottom of the space enclosed by the inner electrode layer; Wherein, forming the conductive contact portion in at least a portion of the space enclosed by the inner electrode layer comprises: A polysilicon plug is formed in the space surrounded by the inner electrode layer and the insulating column.

20. The manufacturing method according to claim 19, wherein: Forming a polysilicon plug in the space enclosed by the inner electrode layer and the insulating column comprises: The polysilicon plug is thermally treated by a laser annealing process.

21. The manufacturing method according to claim 16, wherein: Sequentially forming the storage function layer and the inner electrode layer on the inner wall of the storage hole comprises: A first metal nitride layer and a first metal layer are sequentially formed on the inner wall of the storage function layer to form the inner electrode layer.

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