Groove type IGBT device with low Miller capacitance

Abstract

The invention discloses a groove type IGBT device with low Miller capacitance, and belongs to the field of semiconductor devices. Comprising collector metal, a P-type collector region, an N-type field stop layer, an N-type drift region, an N-type storage layer, a P-type body region and emitter metal which are sequentially arranged from bottom to top, and an N + contact region is arranged in the P-type body region. A cross-shaped groove is arranged in the N-type drift region, and the cross-shaped groove divides the region from the N-type drift region to the N + contact region into a left part and a right part. The bottom of the cross-shaped groove is provided with a second oxide layer medium and first grid polycrystalline silicon which divides the second oxide layer medium into a left part and a right part, and the top of the cross-shaped groove is provided with a third oxide layer medium and second grid polycrystalline silicon which divides the third oxide layer medium into a left part and a right part. And the top end of the second grid polycrystalline silicon is flush with the bottom end of the emitter metal. According to the trench type IGBT device with the low Miller capacitance provided by the invention, the Miller capacitance and the conduction voltage drop can be effectively reduced.

Description

Technical Field

[0001] The invention relates to a semiconductor device, in particular to a trench IGBT device with low Miller capacitance. Background Art

[0002] Insulated gate bipolar transistor (IGBT) is a new type of power electronic device that combines MOS field effect and bipolar transistor. It not only has the advantages of MOSFET, large input resistance, easy to drive and simple control, but also has the advantages of bipolar transistor, such as low on-state voltage drop and large on-state current. It has become one of the core components in modern power electronic circuits and is widely used in transportation, energy, industry, household appliances and other fields.

[0003] Since the IGBT was introduced in the early 1980s, after more than 30 years of development, the process manufacturing level of the structure of IGBT devices has been continuously improved, and it has now developed to the seventh generation of charge storage insulated gate bipolar transistors (CSTBT). The seventh generation CSTBT introduces an N-type charge storage layer with a higher doping concentration under the surface P-type base region, and introduces a hole barrier under the P-type base region, so that the hole concentration near the emitter end when the device is forward-conducted is greatly increased, thereby enabling the IGBT to obtain a lower forward conduction voltage drop. However, with the continuous increase in the doping concentration of the N-type charge storage layer, the breakdown voltage of the CSTBT device has dropped significantly. In addition, as the cell width becomes smaller and the trench density becomes higher, the gate capacitance also increases. The increase in gate capacitance causes the switching speed of the device to slow down, thereby increasing the switching loss of the device. Summary of the invention

[0004] Purpose of the invention: The purpose of the present invention is to provide a trench IGBT device with low Miller capacitance in which Miller capacitance and on-state voltage drop are effectively reduced.

[0005] Technical solution: The trench IGBT device with low Miller capacitance described in the present invention includes a collector metal, a P-type collector region, an N-type field stop layer, and an N-type drift region arranged in sequence from bottom to top, an N-type storage layer, a P-type body region, and an emitter metal are arranged in sequence above the N-type drift region, an N+ contact region is arranged in the P-type body region, and a first oxide layer medium is arranged in the middle of the bottom of the emitter metal.

[0006] Preferably, the cross-shaped groove is bilaterally symmetrical, and its top is flush with the bottom of the emitter metal.

[0007] Preferably, a second oxide layer dielectric and a first gate polysilicon dividing the second oxide layer dielectric into left and right parts are provided at the bottom of the cross-shaped groove, a third oxide layer dielectric and a second gate polysilicon dividing the third oxide layer dielectric into left and right parts are provided at the top of the cross-shaped groove, and the top of the second gate polysilicon is flush with the bottom of the emitter metal.

[0008] Preferably, the bottom end of the N-type storage layer is not lower than the bottom end of the first gate polysilicon.

[0009] Preferably, a cross-shaped groove is provided in the N-type drift region, and the cross-shaped groove divides the N-type drift region, the N-type storage layer, the P-type body region and the N+ contact region into two left and right parts.

[0010] Preferably, a straight polysilicon gate is provided between the first gate polysilicon and the second gate polysilicon, and the straight polysilicon gate and the first gate polysilicon are in contact with each other to form a T-shaped polysilicon gate.

[0011] Further preferably, the length of the inline polysilicon gate is greater than the width of the second gate polysilicon.

[0012] Further preferably, the potential of the T-type polysilicon gate is equal to the emitter metal potential.

[0013] Preferably, a straight polysilicon gate is provided between the first gate polysilicon and the second gate polysilicon, and the straight polysilicon gate and the second gate polysilicon are in contact with each other to form an inverted T-shaped polysilicon gate.

[0014] Further preferably, the length of the inline polysilicon gate is greater than the width of the first gate polysilicon.

[0015] Further preferably, the potential of the inverted T-shaped polysilicon gate is equal to the emitter metal potential.

[0016] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages: (1) In the reverse blocking state of the device, the wide portion of the cross-shaped groove can effectively assist in depleting the N-type carrier storage layer. Therefore, at the same breakdown voltage, the structure has a higher concentration of N-type carrier storage layer, thereby having a lower on-state voltage drop; (2) The present invention provides a trench-type IGBT device with low Miller capacitance. Since the width of the T-type polysilicon gate width portion is wider than the width of the first gate polysilicon (or the width of the inverted T-type polysilicon gate width portion is wider than the width of the second gate polysilicon), during the device switching process, the change of the gate signal is effectively shielded by the wider T-type or inverted T-type polysilicon, thereby having a lower Miller capacitance, faster switching speed, and lower switching loss; (3) In the reverse blocking state of the device, the wide portion of the T-type or inverted T-type groove can effectively assist in depleting the N-type carrier storage layer. Therefore, at the same breakdown voltage, the IGBT device has a higher concentration of N-type carrier storage layer, thereby having a lower on-state voltage drop. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1is a schematic diagram of a cell structure of a trench IGBT device with low Miller capacitance according to Example 1;

[0018] Figure 2 is a schematic diagram of a cell structure of a trench IGBT device with low Miller capacitance as described in Example 2;

[0019] Figure 3 It is a schematic diagram of the cell structure of the trench IGBT device with low Miller capacitance described in Example 3. DETAILED DESCRIPTION

[0020] The technical solution of the present invention is further described below in conjunction with embodiments.

[0021] Example 1

[0022] like Figure 1 As shown, the trench IGBT device with low Miller capacitance of the present invention comprises a collector metal 1, a P-type collector region 2, an N-type field stop layer 3, and an N-type drift region 4 arranged in sequence from bottom to top, an N-type storage layer 5, a P-type body region 6, and an emitter metal 9 are arranged in sequence above the N-type drift region 4, an N+ contact region 7 is arranged in the P-type body region 6, and a first oxide layer medium 8 is arranged in the middle of the bottom of the emitter metal 9. A cross-shaped groove is arranged in the N-type drift region 4, and the cross-shaped groove divides the N-type drift region 4, the N-type storage layer 5, the P-type body region 6, and the N+ contact region 7 into two parts, left and right.

[0023] The cross-shaped groove is bilaterally symmetrical, and its top is flush with the bottom of the emitter metal 9 .

[0024] A second oxide layer dielectric 10 and a first gate polysilicon 11 that divides the second oxide layer dielectric 10 into two left and right parts are provided at the bottom of the cross-shaped groove, and a third oxide layer dielectric 12 and a second gate polysilicon 13 that divides the third oxide layer dielectric 12 into two left and right parts are provided at the top of the cross-shaped groove, and the top of the second gate polysilicon 13 is flush with the bottom of the emitter metal 9.

[0025] The bottom end of the N-type storage layer 5 is not lower than the bottom end of the first gate polysilicon 11 .

[0026] A straight-line polysilicon gate 14 is disposed between the first gate polysilicon 11 and the second gate polysilicon 13 . The straight-line polysilicon gate 14 and the first gate polysilicon 11 are in contact with each other to form a T-shaped polysilicon gate.

[0027] The length of the inline polysilicon gate 14 is greater than the width of the second gate polysilicon 13 .

[0028] The potential of the T-type polysilicon gate is equal to the potential of the emitter metal 9.

[0029] The working principle of the trench IGBT device with low Miller capacitance described in the present invention is as follows:

[0030] When the collector metal 1 is connected to a positive bias, the second gate polysilicon 13, the T-type polysilicon gate, and the emitter metal 9 are connected to a low voltage, the device is in a blocking state. At this time, the T-type polysilicon gate can assist in depleting the N-type storage layer 5, thereby effectively reducing the impact of the N-type storage layer 5 on the device breakdown voltage. When the collector metal 1 is connected to a positive bias, the second gate polysilicon 13 is connected to a positive bias higher than the device threshold voltage, and the T-type polysilicon gate and the emitter metal 9 are connected to a low voltage, the device is in a conducting state. At this time, since the N-type storage layer 5 forms a hole barrier, the carrier concentration on the emitter side is effectively increased, thereby greatly reducing the on-resistance of the device, thereby reducing the on-voltage drop of the device.

[0031] Example 2

[0032] like Figure 2 As shown, the trench IGBT device with low Miller capacitance of the present invention comprises a collector metal 1, a P-type collector region 2, an N-type field stop layer 3, and an N-type drift region 4 arranged in sequence from bottom to top, an N-type storage layer 5, a P-type body region 6, and an emitter metal 9 are arranged in sequence above the N-type drift region 4, an N+ contact region 7 is arranged in the P-type body region 6, and a first oxide layer medium 8 is arranged in the middle of the bottom of the emitter metal 9. A cross-shaped groove is arranged in the N-type drift region 4, and the cross-shaped groove divides the N-type drift region 4, the N-type storage layer 5, the P-type body region 6, and the N+ contact region 7 into two parts, left and right.

[0033] The cross-shaped groove is bilaterally symmetrical, and its top is flush with the bottom of the emitter metal 9 .

[0034] A second oxide layer dielectric 10 and a first gate polysilicon 11 that divides the second oxide layer dielectric 10 into two left and right parts are provided at the bottom of the cross-shaped groove, and a third oxide layer dielectric 12 and a second gate polysilicon 13 that divides the third oxide layer dielectric 12 into two left and right parts are provided at the top of the cross-shaped groove, and the top of the second gate polysilicon 13 is flush with the bottom of the emitter metal 9.

[0035] The bottom end of the N-type storage layer 5 is not lower than the bottom end of the first gate polysilicon 11 .

[0036] Example 3

[0037] like Figure 3As shown, the trench IGBT device with low Miller capacitance of the present invention comprises a collector metal 1, a P-type collector region 2, an N-type field stop layer 3, and an N-type drift region 4 arranged in sequence from bottom to top, an N-type storage layer 5, a P-type body region 6, and an emitter metal 9 are arranged in sequence above the N-type drift region 4, an N+ contact region 7 is arranged in the P-type body region 6, and a first oxide layer medium 8 is arranged in the middle of the bottom of the emitter metal 9. A cross-shaped groove is arranged in the N-type drift region 4, and the cross-shaped groove divides the N-type drift region 4, the N-type storage layer 5, the P-type body region 6, and the N+ contact region 7 into two parts, left and right.

[0038] The cross-shaped groove is bilaterally symmetrical, and its top is flush with the bottom of the emitter metal 9 .

[0039] A second oxide layer dielectric 10 and a first gate polysilicon 11 that divides the second oxide layer dielectric 10 into two left and right parts are provided at the bottom of the cross-shaped groove, and a third oxide layer dielectric 12 and a second gate polysilicon 13 that divides the third oxide layer dielectric 12 into two left and right parts are provided at the top of the cross-shaped groove, and the top of the second gate polysilicon 13 is flush with the bottom of the emitter metal 9.

[0040] The bottom end of the N-type storage layer 5 is not lower than the bottom end of the first gate polysilicon 11 .

[0041] An in-line polysilicon gate 14 is disposed between the first gate polysilicon 11 and the second gate polysilicon 13 . The in-line polysilicon gate 14 and the second gate polysilicon 12 are in contact with each other to form an inverted T-shaped polysilicon gate.

[0042] The length of the inline polysilicon gate 14 is greater than the width of the first gate polysilicon 11 .

[0043] The potential of the inverted T-shaped polysilicon gate is equal to the potential of the emitter metal 9.

[0044] Comparison of the advantages and effects of the three structures:

[0045] (1) In the structure of Example 1, the shielding effect of the first gate polysilicon 11 on the second gate polysilicon 13 is the strongest, and the switching speed is the fastest; and because of the existence of the lateral wide portion, it is beneficial to assist in depleting the carrier storage layer, so the withstand voltage is also higher and the on-state voltage drop is lower.

[0046] (2) The shielding effect of the first gate polysilicon 11 on the second gate polysilicon 13 is not as good as that of Example 1, and the switching speed is relatively slow; however, there is no lateral wide portion, which is not conducive to assisting the depletion of the carrier storage layer, so the withstand voltage is lower than that of Example 1, and the on-state voltage drop is higher. However, its device structure is simpler and the manufacturing cost is lower.

[0047] (3) The shielding effect of the first gate polysilicon 11 on the second gate polysilicon 3 is not as good as that of embodiments 1 and 2, and the switching speed is relatively slow.

Claims

1. A trench IGBT device with low Miller capacitance, comprising a collector metal (1), a P-type collector region (2), an N-type field stop layer (3), and an N-type drift region (4) arranged in sequence from bottom to top, an N-type storage layer (5), a P-type body region (6), and an emitter metal (9) arranged in sequence above the N-type drift region (4), an N+ contact region (7) arranged in the P-type body region (6), and a first oxide layer medium (8) arranged in the middle of the bottom of the emitter metal (9), characterized in that: A cross-shaped groove is provided in the N-type drift region (4).

2. The low Miller capacitance trench IGBT device according to claim 1, characterized in that: The cross-shaped groove is bilaterally symmetrical, and its top is flush with the bottom of the emitter metal (9).

3. The trench IGBT device with low Miller capacitance according to claim 1, characterized in that: A second oxide layer medium (10) and a first gate polysilicon (11) are provided at the bottom of the cross-shaped groove, which divides the second oxide layer medium (10) into two left and right parts; a third oxide layer medium (12) and a second gate polysilicon (13) are provided at the top of the cross-shaped groove, which divides the third oxide layer medium (12) into two left and right parts; and the top of the second gate polysilicon (13) is flush with the bottom of the emitter metal (9).

4. The trench IGBT device with low Miller capacitance according to claim 3, characterized in that: The bottom end of the N-type storage layer (5) is not lower than the bottom end of the first gate polysilicon (11).

5. The trench IGBT device with low Miller capacitance according to claim 1, characterized in that: The cross-shaped groove divides the N-type drift region (4), the N-type storage layer (5), the P-type body region (6) and the N+ contact region (7) into two parts, the left and the right.

6. The trench IGBT device with low Miller capacitance according to claim 3, characterized in that: A straight-line polysilicon gate (14) is provided between the first gate polysilicon (11) and the second gate polysilicon (13); the straight-line polysilicon gate (14) and the first gate polysilicon (11) are in contact with each other to form a T-shaped polysilicon gate.

7. The trench IGBT device with low Miller capacitance according to claim 6, characterized in that: The length of the inline polysilicon gate (14) is greater than the width of the second gate polysilicon (13).

8. The trench IGBT device with low Miller capacitance according to claim 6, characterized in that: The potential of the T-type polysilicon gate is equal to the potential of the emitter metal (9).

9. The trench IGBT device with low Miller capacitance according to claim 3, characterized in that: An inline polysilicon gate (14) is provided between the first gate polysilicon (11) and the second gate polysilicon (13); the inline polysilicon gate (14) and the second gate polysilicon (12) are in contact with each other to form an inverted T-shaped polysilicon gate.

10. The trench IGBT device with low Miller capacitance according to claim 9, characterized in that: The length of the inline polysilicon gate (14) is greater than the width of the first gate polysilicon (11).

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