Preparation method of silicon carbide trench gate type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) power device

Abstract

The invention discloses a preparation method of a silicon carbide trench gate type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) power device, which belongs to the technical field of semiconductor devices and comprises the following steps of: 1, forming an N-Drift region and an N-CSL layer on an N-type substrate; 2, arranging a P + transition region and a P + source contact region on the N-CSL layer; 3, sequentially forming a P-well region and an N + active region on the N-CSL layer; 4, etching a gate trench; 5, depositing a field oxide layer; 6, only the field oxide layer on the outer side of the P + transition region is reserved through etching; 7, depositing polycrystalline silicon; 8, only the polycrystalline silicon in the gate trench, right above the P + source contact region and right above the P + transition region is reserved through etching; 9, arranging a source electrode through hole and arranging a source electrode contact; 11, setting a gate through hole and setting gate contact; and 12, arranging a source electrode, a gate electrode and a drain electrode. According to the method, the technical problems of high manufacturing difficulty, high cost and high specific on-resistance in the prior art are solved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to a method for preparing a silicon carbide trench gate MOSFET power device. Background Art

[0002] Semiconductor power devices are the core elements for efficient conversion, control and regulation of electric energy. In recent years, silicon carbide power devices, with their excellent high-voltage resistance, high-temperature resistance, low-loss and other properties, can effectively meet the high-efficiency, miniaturization and lightweight requirements of electronic power systems. They have obvious advantages in new energy vehicles, photovoltaic power generation, rail transit, smart grids and other fields. Therefore, the research and application of power devices based on silicon carbide materials has become one of the frontiers and hot spots of current semiconductor power device research.

[0003] At present, silicon carbide metal oxide semiconductor field effect transistors are mainly divided into planar gate structure and trench gate structure, and trench gate metal oxide semiconductor field effect transistors are further divided into single trench structure and double trench structure. The practical application of silicon carbide power devices with planar gate structure is limited by their low channel carrier mobility and large device cell size, which leads to excessive device specific on-resistance. However, silicon carbide power devices with trench gate structure have become a mainstream direction of silicon carbide power device research today because they use a vertical gate structure, reduce the cell size area and increase the channel carrier mobility.

[0004] For the above-mentioned trench-gate silicon carbide power device, the patent document with publication number CN118538763A discloses a trench-gate silicon carbide metal oxide semiconductor field effect transistor and a manufacturing method thereof, which includes:

[0005] It comprises a P+ substrate, wherein an N+ buffer layer is epitaxially grown on the front side of the P+ substrate; an N-drift region is epitaxially grown on the front side of the N+ buffer layer; an N-type CSL layer is epitaxially formed on the upper surface of the N-drift region; a P-base region is provided on the upper surface of the N-type CSL layer; a P-channel region is provided at the center of the P-base region; an N+ emitter region is provided on the upper surfaces of the P-base region and the P-channel region; a P+ contact region is provided at the edge positions of the N+ emitter region and the P-base region; a deep groove is provided at the center of the N+ emitter region, a P+ shielding region is provided at the bottom of the deep groove, and a polysilicon gate is provided in the deep groove above the front side of the P+ shielding region.

[0006] Although this method can produce devices that meet high withstand voltage and high gate oxide reliability, this technology still has the following technical problems:

[0007] 1. Because the distance between the bottom of the gate trench and the P-base region is very close, a JFET effect will occur between the two P regions during conduction, narrowing the conductive channel, resulting in a decrease in the on-current, thereby increasing the on-resistance and affecting the device's specific on-resistance.

[0008] 2. When preparing devices, this technology requires extremely high precision in etching the gate polysilicon in order to ensure isolation between the gate and the source, and to ensure that the source contact covers the top of N+ without excessively increasing the width of the device. This is because if the left and right error deviations of the etching are large, not only will the source contact area above N+ be insufficient, making the device unable to turn on; it will also cause the gate and source to be connected, causing device failure.

[0009] 3. This technology uses a double trench and deep trench structure, which increases the difficulty of trench etching and process costs.

[0010] Therefore, it is necessary to provide a new preparation method to solve the above technical problems. Summary of the invention

[0011] The purpose of the present invention is to overcome the above-mentioned problems existing in the prior art and provide a method for preparing a silicon carbide trench gate MOSFET power device, which solves the technical problems existing in the prior art, such as the difficulty of the manufacturing process, the high production cost, and the high specific on-resistance of the prepared device.

[0012] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0013] A method for preparing a silicon carbide trench gate MOSFET power device comprises the following steps:

[0014] Step 1: forming a doped N-Drift region and an N-CSL layer in sequence on a heavily doped N-type substrate;

[0015] Step 2: a P+ transition region is arranged around the N-CSL layer, a plurality of P+ source contact regions are evenly arranged on the N-CSL layer, the plurality of P+ source contact regions divide the N-CSL layer into a plurality of blocks, and the plurality of P+ source contact regions and the plurality of N-CSL layers are alternately arranged in the P+ transition region;

[0016] Step 3: Use ion implantation to sequentially form a P-well region and an N+ active region directly above each N-CSL layer, followed by annealing at high temperature to activate the impurities;

[0017] Step 4: Etching from the middle of each N+ active region downward to the upper part of the N-CSL layer to form a gate trench;

[0018] Step 5: depositing a field oxide layer by chemical vapor deposition to cover the P+ transition region and the area within the P+ transition region;

[0019] Step 6: Remove the field oxide layer inside the P+ transition region and in the P+ transition region by photolithography and etching, retain only the field oxide layer outside the P+ transition region, and then grow a gate oxide layer corresponding to the position where the field oxide layer is removed;

[0020] Step 7: depositing polysilicon to cover the field oxide layer and the gate oxide layer at the same time;

[0021] Step 8: Remove excess polysilicon by photolithography and etching, leaving only the polysilicon in the gate trench, just above the P+ source contact area, and just above the P+ transition area;

[0022] Step nine: depositing an ILD isolation layer by chemical vapor deposition to cover the polysilicon and the area between the polysilicon;

[0023] Step 10: etching a notch on the ILD isolation layer above each P+ source contact region by dry photolithography, removing the ILD isolation layer and polysilicon below the notch by wet etching to form a source through hole, and then depositing Ni alloy in the source through hole to form a source contact;

[0024] Step 11: depositing a mask layer on the ILD isolation layer, etching the ILD isolation layer directly above the field oxide layer by photolithography to form a gate through hole, and then depositing a Ti alloy in the gate through hole to form a gate contact;

[0025] Step 12: Deposit a metal layer to cover the source contact and the gate contact at the same time, apply glue on the metal layer, and form mutually isolated source and gate electrodes through photolithography and etching. Finally, deposit metal under the N-type substrate to form a drain electrode to complete the preparation.

[0026] In step 1, the N-Drift region on the N-type substrate is formed by an epitaxial process, and the N-CSL layer can be formed by an epitaxial process or by doping by high-energy ion implantation, and the doping concentration of the N-type substrate is 10 19 ~10 20 cm -3 The doping concentration of N-Drift region is 10 14 ~10 16 cm -3 The doping concentration of N-CSL layer is 10 15 ~10 17 cm -3 Magnitude.

[0027] In step 2, the P+ transition region and the P+ source contact region are formed by first digging grooves on the N-CSL layer and then using high-energy implantation. The P+ transition region is surrounded by the N-CSL layer in an end-to-end manner. The width of the P+ transition region is 40 to 200 μm, and the width of the P+ source contact region is 0.3 to 1.2 μm; the depths of the P+ source contact region and the P+ transition region are both 2.0 to 2.5 μm.

[0028] In step 3, the doping concentration of the P-well region is 10 16 ~10 17 cm -3 The doping concentration of the N+ active region is 10 18 ~10 20 cm -3 Magnitude.

[0029] In step 4, after etching to obtain the gate trench, the gate trench is also subjected to a trench surface roughness treatment, a trench corner fillet treatment, and a sacrificial oxidation treatment in sequence.

[0030] In step 4, the gate trench has a width of 0.5-1.5 μm and a depth of 0.9-1.5 μm.

[0031] In step five, the thickness of the field oxide layer located above the P+ transition region is 1-2 μm.

[0032] In step six, the inner side of the P+ transition zone refers to the side of the upper surface of the P+ transition zone close to the N-CSL layer, and the outer side of the P+ transition zone refers to the side of the upper surface of the P+ transition zone away from the N-CSL layer, and the area of ​​the inner side is smaller than the area of ​​the outer side.

[0033] In step eight, the polysilicon in the gate trench and the polysilicon directly above the P+ source contact region are both located below the gate oxide layer directly above the N+ active region.

[0034] In step ten, two sides of the source through hole extend to two adjacent N-CSL layers respectively, and two sides of the source contact also cover the two adjacent N-CSL layers respectively.

[0035] The advantages of adopting the present invention are:

[0036] 1. The present invention adopts specific steps and has the following advantages respectively. Specifically,

[0037] The advantages of step one are: using a heavily doped N-type substrate has the effect of reducing resistance when forming an ohmic contact on the back of the device; using the N-Drift region has the effect of carrying a higher forward withstand voltage; using the N-CSL layer has the effect of increasing the channel carrier mobility, reducing the leakage current and reducing the specific on-resistance.

[0038] The advantage of step 2 is that a P+ transition zone is set around the N-CSL layer, which is conducive to reducing the electric field concentration at the edge of the chip and introducing the electric field peak from the surface into the body, thereby increasing the device breakdown voltage. In addition, this step also evenly sets multiple P+ source contact areas on the N-CSL layer. Since multiple P+ source contact areas separate the N-CSL layer into multiple blocks, and multiple P+ source contact areas and multiple N-CSL layers are alternately set in the P+ transition zone, this is conducive to reducing the device area and improving the chip area utilization.

[0039] The advantages of step three are: setting a lightly doped P-well region is conducive to forming a conductive channel, and setting a heavily doped N+ active region is conducive to accessing the source electrode.

[0040] The advantage of step four is that compared with the planar MOS, the conductive channel of the trench-type gate is changed from horizontal to vertical, which improves the mobility of carriers and reduces the size of the device cell.

[0041] The advantage of step five is that the chemical vapor deposition method for depositing the field oxide layer has the advantages of low deposition temperature (<500° C.) and fast deposition speed.

[0042] The advantage of step six is ​​that the grown gate oxide layer has excellent step coverage capability and has the advantages of high purity and uniformity.

[0043] The advantages of steps seven and eight are that they are helpful in ensuring effective isolation between the gate and the source.

[0044] The advantages of steps nine and ten are: depositing the ILD isolation layer is beneficial to isolating the gate source, first dry etching a notch, and then wet etching the remaining polysilicon to ensure that the polysilicon can be completely removed.

[0045] The advantages of steps eleven and twelve are: it is conducive to forming a gate through hole, and at the same time, the deposited metal layer can be vertically connected to the source contact and the gate contact respectively. When etching polysilicon, even if there is an error in the horizontal direction, the device will not fail to conduct. At the same time, the width of the device can be reduced, and the specific on-resistance can be reduced.

[0046] In summary, the present invention adopts the above-mentioned specific process. When preparing the device, only shallow gate trenches and shallow source trenches are needed to complete the preparation of the device. This not only simplifies the manufacturing process and reduces production costs, but also reduces the device's specific on-resistance, resulting in better results.

[0047] 2. The present invention adopts specific doping concentrations for the N-type substrate, N-Drift region and N-CSL layer, which has the effect of further reducing resistance, increasing the forward withstand voltage, and reducing leakage current and specific on-resistance. On the contrary, if the doping concentration exceeds the specified range, it will affect the corresponding performance of the device.

[0048] 3. After etching the gate trench, the present invention sequentially performs trench surface roughness treatment, trench corner fillet treatment, and sacrificial oxidation treatment on the gate trench, thereby reducing the micro-trench effect of the trench, improving the reliability of the gate oxide, and reducing lattice damage.

[0049] 4. The present invention limits specific widths and depths for the P+ transition region, the P+ source contact region and the gate trench, respectively, which comprehensively considers the cost and performance of the device and can reduce the production cost of the device while ensuring better performance of the device.

[0050] 5. The present invention extends both sides of the source through hole to two adjacent N-CSL layers, and covers both sides of the source contact on two adjacent N-CSL layers. The advantage is that it can ensure effective contact between the source and the N+ active area, so that the device maintains better conductivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 This is a schematic diagram of the planar structure of step one;

[0052] Figure 2 It is a schematic diagram of the plane structure of step 2;

[0053] Figure 3 This is a schematic diagram of the plane structure of step three;

[0054] Figure 4 This is a schematic diagram of the plane structure of step 4;

[0055] Figure 5 This is a schematic diagram of the plane structure of step five;

[0056] Figure 6 This is a schematic diagram of the plane structure of step six;

[0057] Figure 7 This is a schematic diagram of the planar structure of step seven;

[0058] Figure 8 This is a schematic diagram of the planar structure of step eight;

[0059] Fig. 9 This is a schematic diagram of the planar structure of step nine;

[0060] Fig.10 This is a schematic diagram of the planar structure of step ten;

[0061] Fig.11 This is a schematic diagram of the planar structure of step 11;

[0062] Fig.12 This is a schematic diagram of the planar structure of step twelve;

[0063] Fig.13 This is a simulation result diagram of the threshold voltage and specific on-resistance of the device prepared by the present invention;

[0064] Figure 14-16 The electric field simulation and data diagram of the bottom of the gate trench when a voltage of 1600V is applied to the gate of the present invention;

[0065] Fig.17 The injection energy diagram is when the P+ transition region and the P+ source contact region are directly set on the N-CSL layer without trenching;

[0066] Fig.18 This is the injection energy diagram when setting the P+ transition region and P+ source contact region by trenching on the N-CSL layer.

[0067] Markings in the figure are: 1-1, N-type substrate, 1-2, N-Drift region, 1-3, N-CSL layer, 1-4, P+ source contact region, 1-5, P+ transition region, 1-6, P-well region, 1-7, N+ active region, 1-8, gate trench, 1-9, field oxide layer, 1-10, gate oxide layer, 1-11, polysilicon, 1-12, ILD isolation layer, 1-13, source contact, 1-14, gate contact, 1-15, source electrode, 1-16, drain electrode, 1-17, gate electrode. DETAILED DESCRIPTION

[0068] Example 1

[0069] This embodiment provides a method for preparing a silicon carbide trench gate MOSFET power device, which comprises the following steps:

[0070] Step 1: If Figure 1 As shown, a doped N-Drift region 1-2 and an N-CSL layer 1-3 are sequentially formed on the upper surface of a heavily doped N-type substrate 1-1. The N-Drift region 1-2 and the N-CSL layer 1-3 on the N-type substrate 1-1 can be formed by doping through an epitaxial process, wherein the N-CSL layer 1-3 can also be formed by doping through high-energy ion implantation, and the doping concentration of the N-CSL layer 1-3 is higher than the doping concentration of the N-Drift region 1-2.

[0071] Preferably, the doping concentration of the N-type substrate 1-1 is 10 19 cm -3 The doping concentration of N-Drift region 1-2 is 10 14 cm -3 The doping concentration of N-CSL layer 1-3 is 10 15 cm -3The specific doping concentration used in this embodiment is beneficial to further reduce resistance, increase forward withstand voltage, reduce leakage current and reduce specific on-resistance.

[0072] Step 2: If Figure 2 As shown, a P+ transition region 1-5 is set by trenching around the N-CSL layer 1-3, and a plurality of P+ source contact regions 1-4 are evenly set by trenching on the N-CSL layer 1-3. The plurality of P+ source contact regions 1-4 divide the N-CSL layer 1-3 into a plurality of blocks. The plurality of P+ source contact regions 1-4 and the plurality of N-CSL layers 1-3 are alternately set in the P+ transition region 1-5, and a cell region is formed between the P+ source contact regions 1-4.

[0073] Preferably, the above-mentioned P+ transition region 1-5 and P+ source contact region 1-4 are formed by first digging a groove on the N-CSL layer 1-3 and then adopting a high-energy injection method, and the P+ transition region 1-5 is enclosed around the N-CSL layer 1-3 in an end-to-end manner to wrap the N-CSL layer 1-3. In addition, the width of the P+ transition region 1-5 is 40μm, and the width of the P+ source contact region 1-4 is 0.3μm; the depths of the P+ source contact region 1-4 and the P+ transition region 1-5 are both 2.0μm. This embodiment adopts this specific parameter, which is conducive to reducing the production cost of the device while ensuring the better performance of the device.

[0074] Step 3: If Figure 3 As shown, P-well regions 1-6 and N+ active regions 1-7 are sequentially formed directly above each N-CSL layer 1-3 by ion implantation, and then annealing is performed at a high temperature to activate the impurities.

[0075] Preferably, the doping concentration of the P-well regions 1-6 is 10 16 cm -3 The doping concentration of N+ active region 1-7 is 10 18 cm -3 This embodiment uses the P-well regions 1-6 and N+ active regions 1-7 with the specific doping concentration, which is beneficial to forming a conductive channel and accessing the source electrode.

[0076] Step 4: If Figure 4 As shown, after annealing to activate the impurities, a gate trench 1-8 is formed by etching downward from the middle of each N+ active region 1-7 to the upper portion of the N-CSL layer 1-3. The width of the gate trench 1-8 is typically 0.5 μm and the depth is 0.9 μm.

[0077] Furthermore, after etching to obtain the gate trench 1-8, the gate trench 1-8 is subjected to groove surface roughness treatment, groove corner rounding treatment, and sacrificial oxidation treatment in sequence, which is beneficial to reducing the micro-groove effect at the bottom of the trench, thereby improving gate oxide reliability and gate breakdown voltage.

[0078] Step 5: If Figure 5 As shown, the field oxide layer 1-9 is deposited by chemical vapor deposition to cover the P+ transition region 1-5 and the area within the P+ transition region 1-5, specifically, to completely cover the upper surface of the device after the processing in step 4. After the field oxide layer 1-9 is deposited, the thickness of the field oxide layer 1-9 located above the P+ transition region 1-5 is ensured to be 1 μm.

[0079] Step 6: If Figure 6 As shown, the field oxide layer 1-9 inside the P+ transition region 1-5 and located in the P+ transition region 1-5 is removed by photolithography and etching, leaving only the field oxide layer 1-9 outside the P+ transition region 1-5, and then a gate oxide layer 1-10 is grown corresponding to the position where the field oxide layer 1-9 is removed.

[0080] Those skilled in the art can understand that the inner side of the above-mentioned P+ transition zone 1-5 refers to the side of the upper surface of the P+ transition zone 1-5 close to the N-CSL layer 1-3, and the outer side of the P+ transition zone 1-5 refers to the side of the upper surface of the P+ transition zone 1-5 away from the N-CSL layer 1-3, and the area of ​​the inner side is smaller than the area of ​​the outer side.

[0081] Step 7: If Figure 7 As shown, the deposited polysilicon 1-11 covers the field oxide layer 1-9 and the gate oxide layer 1-10 at the same time, and to facilitate subsequent etching, the deposited polysilicon 1-11 also fills the groove on the upper surface of the device processed in step six.

[0082] Step 8: If Figure 8 As shown, the redundant polysilicon 1-11 is removed by photolithography and etching, and only the polysilicon 1-11 in the gate trench 1-8, the upper part of the trench corresponding to the P+ source contact area 1-4, and the polysilicon 1-11 directly above the P+ transition area 1-5 is retained.

[0083] It should be noted that when etching the excess polysilicon 1-11, the polysilicon 1-11 at the top of the gate trench 1-8 and the polysilicon 1-11 at the top of the trench corresponding to the P+ source contact area 1-4 need to be overetched by a few tenths of a micron, so that the polysilicon 1-11 in the gate trench 1-8 and the polysilicon 1-11 just above the P+ source contact area 1-4 are both located below the gate oxide layer 1-10 just above the N+ active area 1-7, thereby ensuring effective isolation between the gate and the source.

[0084] Step 9: If Fig. 9As shown, the ILD isolation layer 1-12 is deposited by chemical vapor deposition to cover the polysilicon 1-11 and the area between the polysilicon 1-11. Specifically, the ILD isolation layer 1-12 is deposited to cover the upper surface of the device after the processing in step eight.

[0085] Step 10: Fig.10 As shown, a notch is first etched on the ILD isolation layer 1-12 above each P+ source contact area 1-4 using a dry photolithography method, and then the ILD isolation layer 1-12 and polysilicon 1-11 below the notch are removed using a wet etching method to form a source through hole, and then Ni alloy is deposited in the source through hole to form a source contact 1-13.

[0086] It should be noted that both sides of the source through hole extend to the two adjacent N-CSL layers 1-3 respectively, and both sides of the source contact 1-13 also cover the two adjacent N-CSL layers 1-3 respectively, so as to ensure the effective conduction of the device by making the source effectively contact with the N+ active area 1-7.

[0087] Step 11: Fig.11 As shown, a mask layer is deposited on the ILD isolation layer 1-12, the ILD isolation layer 1-12 directly above the field oxide layer 1-9 is etched by photolithography to form a gate through hole, and then a Ti alloy is deposited in the gate through hole to form a gate contact 1-14.

[0088] Step 12: Fig.12 As shown, a metal layer is deposited to cover the source contact 1-13 and the gate contact 1-14 at the same time, a glue is applied on the metal layer, and mutually isolated source electrodes 1-15 and gate electrodes 1-17 are formed by photolithography and etching, the source electrode 1-15 is vertically fixed on each source contact 1-13 at the same time, and the gate electrode 1-17 is vertically fixed on the gate contact 1-14. Finally, metal is deposited under the N-type substrate 1-1 to form a drain electrode 1-16, and the preparation is completed.

[0089] Example 2

[0090] This embodiment provides a method for preparing a silicon carbide trench gate MOSFET power device, which comprises the following steps:

[0091] Step 1: If Figure 1 As shown, a doped N-Drift region 1-2 and an N-CSL layer 1-3 are sequentially formed on the upper surface of a heavily doped N-type substrate 1-1. The N-Drift region 1-2 and the N-CSL layer 1-3 on the N-type substrate 1-1 can be formed by doping through an epitaxial process, wherein the N-CSL layer 1-3 can also be formed by doping through high-energy ion implantation, and the doping concentration of the N-CSL layer 1-3 is higher than the doping concentration of the N-Drift region 1-2.

[0092] Preferably, the doping concentration of the N-type substrate 1-1 is 5×10 19 cm -3 The doping concentration of N-Drift region 1-2 is 10 15 cm -3 The doping concentration of N-CSL layer 1-3 is 10 16 cm -3 The specific doping concentration used in this embodiment is beneficial to further reduce resistance, increase forward withstand voltage, reduce leakage current and reduce specific on-resistance.

[0093] Step 2: If Figure 2 As shown, a P+ transition region 1-5 is set by trenching around the N-CSL layer 1-3, and a plurality of P+ source contact regions 1-4 are evenly set by trenching on the N-CSL layer 1-3. The plurality of P+ source contact regions 1-4 divide the N-CSL layer 1-3 into a plurality of blocks. The plurality of P+ source contact regions 1-4 and the plurality of N-CSL layers 1-3 are alternately set in the P+ transition region 1-5, and a cell region is formed between the P+ source contact regions 1-4.

[0094] Preferably, the above-mentioned P+ transition region 1-5 and P+ source contact region 1-4 are formed by first digging a groove on the N-CSL layer 1-3 and then adopting a high-energy injection method, and the P+ transition region 1-5 is surrounded by the N-CSL layer 1-3 in an end-to-end manner and wraps the N-CSL layer 1-3. In addition, the width of the P+ transition region 1-5 is usually 120μm, and the width of the P+ source contact region 1-4 is usually 0.8μm; the depths of the P+ source contact region 1-4 and the P+ transition region 1-5 are both 2.2μm. This embodiment adopts this specific parameter, which is conducive to reducing the production cost of the device while ensuring the better performance of the device.

[0095] Step 3: If Figure 3 As shown, P-well regions 1-6 and N+ active regions 1-7 are sequentially formed directly above each N-CSL layer 1-3 by ion implantation, and then annealing is performed at a high temperature to activate the impurities.

[0096] Preferably, the doping concentration of the P-well regions 1-6 is 5×10 16 The doping concentration of N+ active region 1-7 is 10 19 cm -3 This embodiment uses the P-well regions 1-6 and N+ active regions 1-7 with the specific doping concentration, which is beneficial to forming a conductive channel and accessing the source electrode.

[0097] Step 4: If Figure 4As shown, after annealing to activate the impurities, a gate trench 1-8 is formed by etching downward from the middle of each N+ active region 1-7 to the upper portion of the N-CSL layer 1-3. The width of the gate trench 1-8 is typically 1 μm and the depth is 1.2 μm.

[0098] Furthermore, after etching to obtain the gate trench 1-8, the gate trench 1-8 is subjected to groove surface roughness treatment, groove corner rounding treatment, and sacrificial oxidation treatment in sequence, which is beneficial to reducing the micro-groove effect at the bottom of the trench, thereby improving gate oxide reliability and gate breakdown voltage.

[0099] Step 5: If Figure 5 As shown, the field oxide layer 1-9 is deposited by chemical vapor deposition to cover the P+ transition region 1-5 and the area within the P+ transition region 1-5, specifically, to completely cover the upper surface of the device after the processing in step 4. After the field oxide layer 1-9 is deposited, the thickness of the field oxide layer 1-9 located above the P+ transition region 1-5 is ensured to be 1.5 μm.

[0100] Step 6: If Figure 6 As shown, the field oxide layer 1-9 inside the P+ transition region 1-5 and located in the P+ transition region 1-5 is removed by photolithography and etching, leaving only the field oxide layer 1-9 outside the P+ transition region 1-5, and then a gate oxide layer 1-10 is grown corresponding to the position where the field oxide layer 1-9 is removed.

[0101] Step 7: If Figure 7 As shown, the deposited polysilicon 1-11 covers the field oxide layer 1-9 and the gate oxide layer 1-10 at the same time, and to facilitate subsequent etching, the deposited polysilicon 1-11 also fills the groove on the upper surface of the device processed in step six.

[0102] Step 8: If Figure 8 As shown, the redundant polysilicon 1-11 is removed by photolithography and etching, and only the polysilicon 1-11 in the gate trench 1-8, the upper part of the trench corresponding to the P+ source contact area 1-4, and the polysilicon 1-11 directly above the P+ transition area 1-5 is retained.

[0103] It should be noted that when etching the excess polysilicon 1-11, the polysilicon 1-11 at the top of the gate trench 1-8 and the polysilicon 1-11 at the top of the trench corresponding to the P+ source contact area 1-4 need to be overetched by a few tenths of a micron, so that the polysilicon 1-11 in the gate trench 1-8 and the polysilicon 1-11 just above the P+ source contact area 1-4 are both located below the gate oxide layer 1-10 just above the N+ active area 1-7, thereby ensuring effective isolation between the gate and the source.

[0104] Step 9: If Fig. 9As shown, the ILD isolation layer 1-12 is deposited by chemical vapor deposition to cover the polysilicon 1-11 and the area between the polysilicon 1-11. Specifically, the ILD isolation layer 1-12 is deposited to cover the upper surface of the device after the processing in step eight.

[0105] Step 10: Fig.10 As shown, a notch is first etched on the ILD isolation layer 1-12 above each P+ source contact area 1-4 using a dry photolithography method, and then the ILD isolation layer 1-12 and polysilicon 1-11 below the notch are removed using a wet etching method to form a source through hole, and then Ni alloy is deposited in the source through hole to form a source contact 1-13.

[0106] It should be noted that both sides of the source through hole extend to the two adjacent N-CSL layers 1-3 respectively, and both sides of the source contact 1-13 also cover the two adjacent N-CSL layers 1-3 respectively, so as to ensure the effective conduction of the device by making the source effectively contact with the N+ active area 1-7.

[0107] Step 11: Fig.11 As shown, a mask layer is deposited on the ILD isolation layer 1-12, the ILD isolation layer 1-12 directly above the field oxide layer 1-9 is etched by photolithography to form a gate through hole, and then a Ti alloy is deposited in the gate through hole to form a gate contact 1-14.

[0108] Step 12: Fig.12 As shown, a metal layer is deposited to cover the source contact 1-13 and the gate contact 1-14 at the same time, a glue is applied on the metal layer, and mutually isolated source electrodes 1-15 and gate electrodes 1-17 are formed by photolithography and etching, the source electrode 1-15 is vertically fixed on each source contact 1-13 at the same time, and the gate electrode 1-17 is vertically fixed on the gate contact 1-14. Finally, metal is deposited under the N-type substrate 1-1 to form a drain electrode 1-16, and the preparation is completed.

[0109] Example 3

[0110] This embodiment provides a method for preparing a silicon carbide trench gate MOSFET power device, which comprises the following steps:

[0111] Step 1: If Figure 1 As shown, a doped N-Drift region 1-2 and an N-CSL layer 1-3 are sequentially formed on the upper surface of a heavily doped N-type substrate 1-1. The N-Drift region 1-2 and the N-CSL layer 1-3 on the N-type substrate 1-1 can be formed by doping through an epitaxial process, wherein the N-CSL layer 1-3 can also be formed by doping through high-energy ion implantation, and the doping concentration of the N-CSL layer 1-3 is higher than the doping concentration of the N-Drift region 1-2.

[0112] Preferably, the doping concentration of the N-type substrate 1-1 is 10 20 cm -3 The doping concentration of N-Drift region 1-2 is 10 16 cm -3 The doping concentration of N-CSL layer 1-3 is 10 17 cm -3 The specific doping concentration used in this embodiment is beneficial to further reduce resistance, increase forward withstand voltage, reduce leakage current and reduce specific on-resistance.

[0113] Step 2: If Figure 2 As shown, a P+ transition region 1-5 is set by trenching around the N-CSL layer 1-3, and a plurality of P+ source contact regions 1-4 are evenly set by trenching on the N-CSL layer 1-3. The plurality of P+ source contact regions 1-4 divide the N-CSL layer 1-3 into a plurality of blocks. The plurality of P+ source contact regions 1-4 and the plurality of N-CSL layers 1-3 are alternately set in the P+ transition region 1-5, and a cell region is formed between the P+ source contact regions 1-4.

[0114] Preferably, the above-mentioned P+ transition region 1-5 and P+ source contact region 1-4 are formed by first digging a groove on the N-CSL layer 1-3 and then adopting a high-energy injection method, and the P+ transition region 1-5 is enclosed around the N-CSL layer 1-3 in an end-to-end manner to wrap the N-CSL layer 1-3. In addition, the width of the P+ transition region 1-5 is usually 200μm, and the width of the P+ source contact region 1-4 is usually 1.2μm; the depths of the P+ source contact region 1-4 and the P+ transition region 1-5 are both 2.5μm. The use of this specific parameter in this embodiment is conducive to reducing the production cost of the device while ensuring the better performance of the device.

[0115] Step 3: If Figure 3 As shown, P-well regions 1-6 and N+ active regions 1-7 are sequentially formed directly above each N-CSL layer 1-3 by ion implantation, and then annealing is performed at a high temperature to activate the impurities.

[0116] Preferably, the doping concentration of the P-well regions 1-6 is 10 17 cm -3 The doping concentration of N+ active region 1-7 is 10 20 cm -3 This embodiment uses the P-well regions 1-6 and N+ active regions 1-7 with the specific doping concentration, which is beneficial to forming a conductive channel and accessing the source electrode.

[0117] Step 4: If Figure 4As shown, after annealing to activate the impurities, a gate trench 1-8 is formed by etching downward from the middle of each N+ active region 1-7 to the upper portion of the N-CSL layer 1-3. The width of the gate trench 1-8 is typically 1.5 μm and the depth is 1.5 μm.

[0118] Furthermore, after etching to obtain the gate trench 1-8, the gate trench 1-8 is subjected to groove surface roughness treatment, groove corner rounding treatment, and sacrificial oxidation treatment in sequence, which is beneficial to reducing the micro-groove effect at the bottom of the trench, thereby improving gate oxide reliability and gate breakdown voltage.

[0119] Step 5: If Figure 5 As shown, the field oxide layer 1-9 is deposited by chemical vapor deposition to cover the P+ transition region 1-5 and the area within the P+ transition region 1-5, specifically, to completely cover the upper surface of the device after the processing in step 4. After the field oxide layer 1-9 is deposited, the thickness of the field oxide layer 1-9 located above the P+ transition region 1-5 is ensured to be 2 μm.

[0120] Step 6: If Figure 6 As shown, the field oxide layer 1-9 inside the P+ transition region 1-5 and located in the P+ transition region 1-5 is removed by photolithography and etching, leaving only the field oxide layer 1-9 outside the P+ transition region 1-5, and then a gate oxide layer 1-10 is grown corresponding to the position where the field oxide layer 1-9 is removed.

[0121] Step 7: If Figure 7 As shown, the deposited polysilicon 1-11 covers the field oxide layer 1-9 and the gate oxide layer 1-10 at the same time, and to facilitate subsequent etching, the deposited polysilicon 1-11 also fills the groove on the upper surface of the device processed in step six.

[0122] Step 8: If Figure 8 As shown, the redundant polysilicon 1-11 is removed by photolithography and etching, and only the polysilicon 1-11 in the gate trench 1-8, the upper part of the trench corresponding to the P+ source contact area 1-4, and the polysilicon 1-11 directly above the P+ transition area 1-5 is retained.

[0123] It should be noted that when etching the excess polysilicon 1-11, the polysilicon 1-11 at the top of the gate trench 1-8 and the polysilicon 1-11 at the top of the trench corresponding to the P+ source contact area 1-4 need to be overetched by a few tenths of a micron, so that the polysilicon 1-11 in the gate trench 1-8 and the polysilicon 1-11 just above the P+ source contact area 1-4 are both located below the gate oxide layer 1-10 just above the N+ active area 1-7, thereby ensuring effective isolation between the gate and the source.

[0124] Step 9: If Fig. 9As shown, the ILD isolation layer 1-12 is deposited by chemical vapor deposition to cover the polysilicon 1-11 and the area between the polysilicon 1-11. Specifically, the ILD isolation layer 1-12 is deposited to cover the upper surface of the device after the processing in step eight.

[0125] Step 10: Fig.10 As shown, a notch is first etched on the ILD isolation layer 1-12 above each P+ source contact area 1-4 using a dry photolithography method, and then the ILD isolation layer 1-12 and polysilicon 1-11 below the notch are removed using a wet etching method to form a source through hole, and then Ni alloy is deposited in the source through hole to form a source contact 1-13.

[0126] It should be noted that both sides of the source through hole extend to the two adjacent N-CSL layers 1-3 respectively, and both sides of the source contact 1-13 also cover the two adjacent N-CSL layers 1-3 respectively, so as to ensure the effective conduction of the device by making the source effectively contact with the N+ active area 1-7.

[0127] Step 11: Fig.11 As shown, a mask layer is deposited on the ILD isolation layer 1-12, the ILD isolation layer 1-12 directly above the field oxide layer 1-9 is etched by photolithography to form a gate through hole, and then a Ti alloy is deposited in the gate through hole to form a gate contact 1-14.

[0128] Step 12: Fig.12 As shown, a metal layer is deposited to cover the source contact 1-13 and the gate contact 1-14 at the same time, a glue is applied on the metal layer, and mutually isolated source electrodes 1-15 and gate electrodes 1-17 are formed by photolithography and etching, the source electrode 1-15 is vertically fixed on each source contact 1-13 at the same time, and the gate electrode 1-17 is vertically fixed on the gate contact 1-14. Finally, metal is deposited under the N-type substrate 1-1 to form a drain electrode 1-16, and the preparation is completed.

[0129] Example 4

[0130] This embodiment performs simulation tests on the preparation processes of embodiments 1-3 and the obtained devices, respectively, as follows:

[0131] 1. The applicant conducted simulation tests on the threshold voltage and specific on-resistance of the devices obtained in Examples 1-3, and the test results are as follows: Fig.13 As shown. Among them, the threshold voltage of the device in Example 1 is about 3.1V, and the specific on-resistance is about 2.5mΩ·cm 2 The threshold voltage of the device in Example 2 is about 3.0 V, and the specific on-resistance is about 2.1 mΩ·cm 2 The threshold voltage of the device in Example 3 is about 2.7V, and the specific on-resistance is about 1.8mΩ·cm2 From the data, it can be seen that the device with lower on-resistance can be prepared by the method of the present invention.

[0132] 2. The applicant conducted electric field simulation on the bottom of the gate trench for the devices obtained in Examples 1-3 respectively when a voltage of 1600V was applied to the gate. The specific simulation diagrams and data results are as follows: Figure 14-16 The electric field of the device in Example 1 is about 3.3 MV / cm, the electric field of the device in Example 2 is about 3.0 MV / cm, and the electric field of the device in Example 2 is about 2.9 MV / cm.

[0133] It should be noted that in silicon carbide trench MOS devices, there is usually a problem of gate oxide reliability at the bottom of the gate trench. From the above tests, it can be seen that the deep P+ implantation and rounded corners of the gate trench adopted in the present invention can improve the gate oxide reliability and ensure that there is a lower risk of breakdown at the bottom of the gate trench under an external gate voltage of 1600V.

[0134] 3. When setting the P+ transition region and the P+ source contact region, the applicant adopts the method of not digging a groove and digging a groove respectively, wherein, Fig.17 , 18 As shown, when setting the P+ transition region and the P+ source contact region, the maximum injection energy needs to reach 2.4-2.5 MeV without trenching. However, through the trenching design of the present invention, the maximum injection energy only needs 1.7 MeV, which greatly reduces the cost and damage to the lattice.

[0135] The above description is only a specific implementation mode of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other alternative features that are equivalent or have similar purposes; all the disclosed features, or all the steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A method for preparing a silicon carbide trench gate MOSFET power device, characterized in that: The following steps are involved: Step 1: forming a doped N-Drift region (1-2) and an N-CSL layer (1-3) in sequence on a heavily doped N-type substrate (1-1); Step 2: a P+ transition region (1-5) is arranged around the N-CSL layer (1-3), a plurality of P+ source contact regions (1-4) are evenly arranged on the N-CSL layer (1-3), the plurality of P+ source contact regions (1-4) divide the N-CSL layer (1-3) into a plurality of blocks, and the plurality of P+ source contact regions (1-4) and the plurality of N-CSL layers (1-3) are alternately arranged in the P+ transition region (1-5); Step 3: forming a P-well region (1-6) and an N+ active region (1-7) in sequence directly above each N-CSL layer (1-3) by ion implantation, and then annealing at a high temperature to activate the impurities; Step 4: Etching from the middle of each N+ active region (1-7) downward to the upper part of the N-CSL layer (1-3) to form a gate trench (1-8); Step 5: depositing a field oxide layer (1-9) by chemical vapor deposition to simultaneously cover the P+ transition region (1-5) and the region within the P+ transition region (1-5); Step 6: removing the field oxide layer (1-9) inside the P+ transition region (1-5) and inside the P+ transition region (1-5) by photolithography and etching, and only retaining the field oxide layer (1-9) outside the P+ transition region (1-5), and then growing a gate oxide layer (1-10) corresponding to the position where the field oxide layer (1-9) was removed; Step 7: depositing polysilicon (1-11) to cover the field oxide layer (1-9) and the gate oxide layer (1-10); Step 8: removing the excess polysilicon (1-11) by photolithography and etching, and only retaining the polysilicon (1-11) in the gate trench (1-8), directly above the P+ source contact region (1-4) and directly above the P+ transition region (1-5); Step nine: depositing an ILD isolation layer (1-12) by chemical vapor deposition to simultaneously cover the polysilicon (1-11) and the area between the polysilicon (1-11); Step 10: etching a notch on the ILD isolation layer (1-12) above each P+ source contact region (1-4) by dry photolithography, removing the ILD isolation layer (1-12) and polysilicon (1-11) below the notch by wet etching to form a source through hole, and then depositing Ni alloy in the source through hole to form a source contact (1-13); Step 11: depositing a mask layer on the ILD isolation layer (1-12), etching the ILD isolation layer (1-12) directly above the field oxide layer (1-9) by photolithography to form a gate through hole, and then depositing a Ti alloy in the gate through hole to form a gate contact (1-14); Step 12: deposit a metal layer to cover the source contact (1-13) and the gate contact (1-14), apply glue on the metal layer, and form a mutually isolated source electrode (1-15) and gate electrode (1-17) by photolithography and etching, and finally deposit metal under the N-type substrate (1-1) to form a drain electrode (1-16) to complete the preparation.

2. The method for preparing a silicon carbide trench gate MOSFET power device according to claim 1, wherein in step 1, the N-Drift region (1-2) on the N-type substrate (1-1) is formed by an epitaxial process, the N-CSL layer (1-3) can be formed by an epitaxial process or by doping by high-energy ion implantation, and the doping concentration of the N-type substrate (1-1) is 10 19 ~10 20 cm -3 The doping concentration of N-Drift region (1-2) is 10 14 ~10 16 cm -3 The doping concentration of N-CSL layer (1-3) is 10 15 ~10 17 cm -3 Magnitude.

3. The method for preparing a silicon carbide trench gate MOSFET power device according to claim 1, characterized in that: In step 2, the P+ transition region (1-5) and the P+ source contact region (1-4) are formed by first digging a groove on the N-CSL layer (1-3) and then adopting a high-energy implantation method. The P+ transition region (1-5) is surrounded by the N-CSL layer (1-3) in an end-to-end manner. The width of the P+ transition region (1-5) is 40 to 200 μm, and the width of the P+ source contact region (1-4) is 0.3 to 1-2 μm. The depths of the P+ source contact region (1-4) and the P+ transition region (1-5) are both 2.0 to 2.5 μm.

4. The method for preparing a silicon carbide trench gate MOSFET power device according to claim 1, characterized in that: In step 3, the doping concentration of the P-well region (1-6) is 10 16 ~10 17 cm -3 The doping concentration of the N+ active region (1-7) is 10 18 ~10 20 cm -3 Magnitude.

5. A method for preparing a silicon carbide trench gate MOSFET power device according to any one of claims 1 to 4, characterized in that: In step 4, after etching to obtain the gate trench (1-8), the process further includes sequentially performing a trench surface roughness treatment, a trench fillet treatment, and a sacrificial oxidation treatment on the gate trench (1-8).

6. The method for preparing a silicon carbide trench gate MOSFET power device according to claim 1, characterized in that: In step 4, the gate trench (1-8) has a width of 0.5-1-5 μm and a depth of 0.9-1-5 μm.

7. The method for preparing a silicon carbide trench gate MOSFET power device according to claim 1, characterized in that: In step five, the thickness of the field oxide layer (1-9) located above the P+ transition region (1-5) is 1-2 μm.

8. The method for preparing a silicon carbide trench gate MOSFET power device according to claim 1, characterized in that: In step six, the inner side of the P+ transition zone (1-5) refers to the side of the upper surface of the P+ transition zone (1-5) close to the N-CSL layer (1-3), and the outer side of the P+ transition zone (1-5) refers to the side of the upper surface of the P+ transition zone (1-5) away from the N-CSL layer (1-3), and the area of ​​the inner side is smaller than the area of ​​the outer side.

9. The method for preparing a silicon carbide trench gate MOSFET power device according to claim 1, characterized in that: In step eight, the polysilicon (1-11) in the gate trench (1-8) and the polysilicon (1-11) directly above the P+ source contact region (1-4) are both located below the gate oxide layer (1-10) directly above the N+ active region (1-7).

10. The method for preparing a silicon carbide trench gate MOSFET power device according to claim 1, characterized in that: In step ten, two sides of the source through hole extend to two adjacent N-CSL layers (1-3) respectively, and two sides of the source contact (1-13) also cover the two adjacent N-CSL layers (1-3) respectively.

Images