Super junction MOSFET device with low reverse recovery charge and manufacturing method thereof

Abstract

The invention provides a super-junction MOSFET device with low reverse recovery charges and a manufacturing method thereof. The manufacturing method comprises the steps that an ohmic contact layer is formed on the opposite contact surface of an N-type heavily-doped semiconductor substrate and a metal drain; ohmic contact is formed between the first heavily-doped N + region and the opposite contact surface of the metal source electrode. The opposite contact surfaces of the P-body region and the metal source electrode form Schottky contact; the P-type column regions and the first N-type regions are alternately distributed; the second N-type column region is formed by upward extension of the first N-type region; ohmic contact is formed between the second heavily-doped N + region and the opposite contact surface of the metal source electrode. The P-type heavily-doped buried layer is arranged in the P-body region and is in contact with the first heavily-doped N + region; the first gate oxide layer is located below the gate; the third gate oxide layer is located outside the gate; the second gate oxide layers are located on the two sides of the longitudinal channel P-base region. According to the invention, the technical problem of reverse recovery of an existing super-junction MOSFET device caused by stored charges in the reverse recovery process is successfully optimized.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor power devices, and in particular relates to a super junction MOSFET device with low reverse recovery charge and a manufacturing method thereof. Background Art

[0002] Super junction MOSFET achieves a significant increase in doping concentration by cleverly setting N-type and P-type doping regions in the drift region, breaking through the limitations of traditional silicon materials and changing the relationship between on-resistance Ron and breakdown voltage BV from Ron∝BV to 2.5 Optimize to Ron∝BV 1.32 . This innovative design has enabled super junction MOSFETs to dominate the power MOSFET market in the 500 to 650 volt voltage range. However, while this structure reduces on-resistance, it also brings some problems, such as an increase in the junction area of ​​the PN junction body diode and an increase in reverse recovery charge. During the reverse recovery process, the lateral depletion effect of the P-type and N-type strips accelerates the discharge of minority carriers in the drift region, resulting in a sharp change in dV / dt, which in turn generates large electromagnetic interference (EMI) noise in the application system, which may affect the stability of the system. In addition, the reverse recovery charge and maximum reverse recovery current of the super junction MOSFET are higher than those of the planar gate MOSFET, which limits its performance in certain applications.

[0003] See also Figure 1 , the reverse recovery current change of conventional super junction MOSFET comes from the process of its body diode turning off. When its body diode conducts in the reverse direction, such as Figure 1 As shown in (a), the source and gate are at high potential, the internal parasitic body diode is turned on, and a large number of holes are injected from the source through P+, P-body, and P-type column region into the N-type column region, and electrons are injected from the drain through the N-type substrate and N-type column region into the P-type column region. At this time, a large number of residual minority carriers are stored in the PN junction formed by the P-type column region and the N-type column region. When its body diode changes from the reverse conduction state to the reverse cutoff state, the residual minority carriers accumulated in the PN junction must be released first. During the discharge period, such as Figure 1 As shown in (b), the drain is at a high potential, and the holes accumulated in the N-type column region are extracted to the P+ region and then flow out from the source; the electrons accumulated in the P-type column region are extracted to the N-type substrate and flow out from the drain. This process continues until the excess carriers in the PN junction are completely cleared. Since the contact area between the N-type column region and the P-type column region of the superjunction MOSFET is much larger than that of the traditional VDMOS, the number of carriers injected during reverse conduction is also much larger than that of the traditional VDMOS. The superjunction MOSFET consumes more energy when extracting excess carriers.

[0004] Therefore, it is necessary to provide a super junction MOSFET device with low reverse recovery charge and a manufacturing method thereof to solve the above technical problems. Summary of the invention

[0005] The present invention provides a super junction MOSFET device with low reverse recovery charge, which reduces the reverse recovery charge of the super junction MOSFET device and improves the reverse recovery characteristic of the device.

[0006] To solve the above technical problems, the present invention provides a super junction MOSFET device with low reverse recovery charge, including an ohmic contact layer formed by the relative contact surface of an N-type heavily doped semiconductor substrate and a metal drain; an ohmic contact is formed by the relative contact surface of a first heavily doped N+ region and a metal source; a Schottky contact is formed by the relative contact surface of a P-body region and a metal source; P-type column regions and the first N-type regions are alternately distributed; the second N-type column region is formed by the upward extension of the first N-type region; the second heavily doped N+ region and the relative contact surface of the metal source form an ohmic contact; a P-type heavily doped buried layer is in the P-body region and is in contact with the first heavily doped N+ region; a first gate oxide layer is located below the gate; a third gate oxide layer is located outside the gate; and a second gate oxide layer is located on both sides of a longitudinal channel P-base region.

[0007] Preferably, the first N-type column region and the second N-type column region have the same doping concentration, and the thickness of the second N-type column region is adjustable.

[0008] Preferably, the thickness of the first gate oxide layer and the second gate oxide layer can be adjusted, thereby controlling the turn-on voltage of both the lateral and longitudinal channels of the gate MOS.

[0009] Preferably, the doping concentration of the P-type heavily doped buried layer is higher than that of the P-body region, so as to suppress the conduction of the parasitic NPN transistor inside the super junction MOSFET device.

[0010] The present invention also provides a method for manufacturing a super junction MOSFET device with low reverse recovery charge, comprising the following steps:

[0011] S1, epitaxially growing a thin film with the same doping concentration as the first N-type column region on an N-type heavily doped semiconductor substrate, etching a P-type column region trench on the thin film, and then using multiple epitaxy or filling methods to form a P-type column region and a P-type heavily doped buried layer;

[0012] S2, forming an oxide layer by thermal oxidation growth and depositing polysilicon;

[0013] S3, etching excess polysilicon and oxide layer to expose a P-body region implantation window to form a P-body region by ion implantation or diffusion, and forming a first heavily doped N+ region by ion implantation or diffusion;

[0014] S4, oxidizing to form a field oxide layer, etching a gate electrode window, forming a first gate oxide layer and a second gate oxide layer, and depositing to form a gate;

[0015] S5, etching the field oxide layer to form a second N-type column region epitaxial window, epitaxially forming a second N-type column region and a P-base region, and ion implanting to form a second heavily doped N+ region;

[0016] S6, etching a source window, metallizing and forming a Schottky contact with the P-body region to form a source;

[0017] S7, back metallization forms a drain, completing the manufacture of a super junction MOSFET device with low reverse recovery charge.

[0018] Compared with the related art, the super junction MOSFET device with low reverse recovery charge and the manufacturing method thereof provided by the present invention have the following beneficial effects:

[0019] The present invention successfully optimizes the technical difficulties of reverse recovery of existing super junction MOSFET devices due to stored charge during reverse recovery. Compared with conventional structures, this new super junction MOSFET device significantly reduces the stored charge of the parasitic diode in the body, thereby improving the reverse recovery characteristics of the device, while maintaining the breakdown voltage and on-state current handling capacity of the device. These improvements make the super junction MOSFET of the present invention have significant advantages in application fields such as power adapters, drivers, industrial control and automotive electronics that require high switching speed and power conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of the movement of electrons and holes during reverse recovery of super junction MOSFET in related technology;

[0021] Figure 2 A schematic diagram of a super junction MOSFET with low reverse recovery charge according to the present invention;

[0022] Figure 3 Schematic diagram of reverse conduction IV curves of the super junction MOSFET of the present invention and conventional super junction MOSFET;

[0023] Figure 4 This is a schematic diagram of the current distribution of a conventional super junction MOSFET when it is reverse conducting;

[0024] Figure 5 A schematic diagram of current distribution when the super junction MOSFET of the present invention is reversely conducted;

[0025] Figure 6 It is a simulation diagram of the electron flow / hole flow density distribution when the super junction MOSFET of the present invention and the conventional super junction MOSFET are reversely conducted;

[0026] Figure 7 This is a reverse recovery current simulation comparison diagram of the super junction MOSFET of the present invention and the conventional super junction MOSFET. DETAILED DESCRIPTION

[0027] The present invention will be further described below in conjunction with the accompanying drawings and implementation modes.

[0028] See also Figures 2 to 7 The present invention provides a super junction MOSFET device with low reverse recovery charge, comprising an N-type heavily doped semiconductor substrate 101 and a metal drain 113 whose relative contact surfaces form an ohmic contact layer; a first heavily doped N+ region 106 and a metal source 112 whose relative contact surfaces form an ohmic contact; a P-body region 105 and a metal source 112 whose relative contact surfaces form a Schottky contact; a P-type column region 103 and a first N-type region 102 are alternately distributed; a second N-type column region 109 is formed by the upward extension of the first N-type region 102; an ohmic contact is formed between a second heavily doped N+ region 111 and a metal source 112; a P-type heavily doped buried layer 104 is in the P-body region 105 and in contact with the first heavily doped N+ region 106; a first gate oxide layer 114 is located below a gate 108; a third gate oxide layer 107 is located outside the gate 108; and a second gate oxide layer 115 is located on both sides of a longitudinal channel P-base region 110.

[0029] The parameters of various regions of super junction MOSFET devices with low reverse recovery charge are as follows:

[0030]

[0031] The first N-type column region 102 and the second N-type column region 109 have the same doping concentration, and the thickness of the second N-type column region 109 is adjustable.

[0032] Different doping thicknesses correspond to different lengths of longitudinal conductive channels. When the sum of the thicknesses of the second N-type column region 109, the P-base region 110 and the second heavily doped N+ region 111 is constant, the thicker the second N-type column region 109, the thinner the P-base region 110. The thickness of the P-base region 110 is the length of the conductive channel. The longer the conductive channel, the higher the turn-on voltage.

[0033] The thickness of the first gate oxide layer 114 and the second gate oxide layer 115 can be adjusted to control the turn-on voltage of the lateral and longitudinal channels of the gate MOS.

[0034] Different oxide layer thicknesses correspond to different turn-on voltages. The lower the thickness, the smaller the turn-on voltage. The corresponding turn-on voltage is controlled by adjusting the different thicknesses of the lateral and longitudinal oxide layers.

[0035] The doping concentration of the P-type heavily doped buried layer 104 is much higher than that of the P-body region 105 , and is used to suppress the conduction of the parasitic NPN transistor inside the super junction MOSFET device.

[0036] The P-body region is the base region of the parasitic NPN transistor. Although it is short-circuited with the N+ region, the P-body region cannot be completely short-circuited due to its low doping concentration and large internal resistance, and there is a body voltage drop, so the parasitic NPN transistor is easily turned on. The P-type heavily doped buried layer has a high doping concentration and a small internal resistance, and the corresponding body voltage drop is also small, which inhibits the parasitic NPN transistor from turning on.

[0037] The present invention also provides a method for manufacturing a super junction MOSFET device with low reverse recovery charge, comprising the following steps:

[0038] S1, epitaxially grow a thin film with the same doping concentration as the first N-type column region 102 on the N-type heavily doped semiconductor substrate 101, etch a P-type column region trench on the thin film, and then form a P-type column region 103 and a P-type heavily doped buried layer 104 by multiple epitaxial growth or filling methods;

[0039] S2, forming an oxide layer by thermal oxidation growth and depositing polysilicon;

[0040] S3, etching the excess polysilicon and oxide layer to expose the P-body region implantation window to form the P-body region 105 by ion implantation or diffusion, and forming the first heavily doped N+ region 106 by ion implantation or diffusion;

[0041] S4, oxidizing to form a field oxide layer, etching a gate electrode window, forming a first gate oxide layer 114 and a second gate oxide layer 115, and depositing to form a gate 108;

[0042] S5, etching the field oxide layer to form a second N-type column region epitaxial window, epitaxially forming a second N-type column region 109 and a P-base region 110, and ion implanting to form a second heavily doped N+ region 111;

[0043] S6, etching a source window, metallizing and forming a Schottky contact with the P-body region 105, and forming a source 112;

[0044] S7, back metallization to form a drain 113, completing the manufacture of a super junction MOSFET device with low reverse recovery charge.

[0045] The working principle of the super junction MOSFET with low reverse recovery charge of the present invention is as follows:

[0046] When conducting in the reverse direction, the gate and source of the device are simultaneously connected to the same high potential, and the drain is grounded. The source of the Schottky contact injects holes into the N-type region 102 through the P-body region 105, the P-type heavily doped buried layer 104, and the P-type column region 103, while the drain injects electrons into the lateral channel P-body region 105, the first heavily doped N+ region 106 and the longitudinal channel second N-type column region 109, the P-base region 110, and the second heavily doped N+ region 111 through the N-type heavily doped semiconductor substrate 101 and the N-type region 102. Compared with the body diode of the conventional superjunction MOSFET, on the one hand, the electrons start from the drain, pass through the N-type drift region, and then flow to the source through the lateral and longitudinal channels, which reduces the electron injection of the N-type drift region into the P-type drift region when the conventional superjunction MOSFET is reversely conducted, and reduces the storage of a large number of carriers in the P-type drift region. On the other hand, the reverse biased P-type Schottky diode provides a discharge channel for holes, while suppressing the diode conduction between the N-type drift region and the P-type drift region, reducing the carrier concentration in the drift region, and improving the reverse recovery characteristics of the device.

[0047] Figure 3 It is a schematic diagram of the reverse conduction IV curve of the superjunction MOSFET of the present invention and the conventional superjunction MOSFET. It can be observed from the figure that the voltage drop of the device of the present invention during reverse conduction is higher than that of the conventional superjunction MOSFET. This phenomenon is that the device of the present invention needs to form an electron channel to conduct current, so its turn-on voltage is higher than the PN junction turn-on voltage; secondly, the reverse conduction current is almost entirely electron current, and the reverse conduction curve shows a quasi-unipolar conduction characteristic. For conventional superjunction MOSFET, it belongs to the bipolar conduction mode during reverse conduction, and the reverse current is completely conducted by the parasitic body diode, so that the forward voltage drop of its body diode is relatively low.

[0048] Figure 4 Schematic diagram of the current distribution of a conventional superjunction MOSFET during reverse conduction, specifically, the reverse conduction voltage V DS =-3V, V GS =Current distribution when 0V. Figure 5 Schematic diagram of the current distribution of the super junction MOSFET of the present invention when it is reverse conducting, specifically, the super junction MOSFET of the present invention is at the reverse conduction voltage V DS =-3V, V GS = 0V current distribution. In conventional super junction MOSFET structures, the current path is realized through the internal PN junction. In contrast, the current path of the super junction MOSFET of the present invention mainly flows through the two lateral and longitudinal channel diodes of the MOS and the electron channel of the N-type column region, avoiding the opening of the internal PN junction, reducing the injection of excess carriers, and reducing the reverse recovery charge.

[0049] Figure 6: This is a simulation diagram of the electron flow / hole flow density distribution when the super junction MOSFET of the present invention and the conventional super junction MOSFET are reversely conducted, specifically, the conventional super junction MOSFET and the super junction MOSFET of the present invention are reversely conducted at the voltage V DS =-3V, V GS = Simulation diagram of electron flow / hole flow density distribution when 0V. Figure 6 (a) is a simulation diagram of the electron current density distribution when the super junction MOSFET of the present invention is reversely turned on. It can be seen from the figure that the electron current mainly flows through the N-type column area, and the reverse biased P-type Schottky diode clamps the potential difference between the P-type column area and the N-type column area in the drift region to a potential less than the built-in potential of the P / N junction. Therefore, the conduction of the P / N junction between the P-type column area and the N-type column area in the drift region is limited. At the same time, the voltage of the gate reaches the threshold voltage, and the two horizontal and vertical electron channels are opened. The electrons in the N-type column area also flow along the channel to the source, reducing the storage of electrons and facilitating reverse recovery. Figure 6 (b) is a simulation diagram of the hole flow density distribution when the super junction MOSFET of the present invention is reverse-conducting. It can be seen from the figure that the density of the hole flow is much smaller than the electron flow. Due to the reverse leakage current of the P-type Schottky diode, the hole flow density is much smaller than the electron flow, and the hole flow mainly flows through the P-type column area.

[0050] Figure 6 (c) is a simulation diagram of the electron current density distribution when a conventional superjunction MOSFET is reverse-conducted. When reverse-conducting, the P / N junction between the P-type column region and the N-type column region is turned on, and a large number of electrons are injected into the P-type column region through the N-type column region. The electron and hole densities between the P-type column region and the N-type column region are close, and the P-type column region stores a large number of minority electrons, which is not conducive to the extraction of carriers during reverse recovery. Figure 6 (d) is a simulation diagram of the hole current density distribution during reverse conduction of a conventional superjunction MOSFET. During reverse conduction, the P / N junction between the P-type column region and the N-type column region is turned on, and a large number of holes are injected into the N-type column region through the P-type column region. The electron and hole densities between the P-type column region and the N-type column region are close, and the N-type column region stores a large number of minority holes, which is not conducive to the extraction of carriers during reverse recovery.

[0051] Figure 7 This is a simulation comparison diagram of the reverse recovery current of the super junction MOSFET of the present invention and the conventional super junction MOSFET. Under 500V conditions, two 650V grade MOSFETs were simulated and tested. The results show that the reverse recovery current and reverse recovery charge of the super junction MOSFET of the present invention are significantly reduced compared with the conventional super junction MOSFET.

[0052] The core of the present invention is to improve the reverse recovery characteristics of the super junction MOSFET. On the basis of the original lateral channel, a new longitudinal channel is introduced. As the reverse voltage increases, the lateral and longitudinal electron channels are opened, and the electrons in the N-type column area preferentially flow through the channel to the source, reducing the injection of electrons into the P-type column area, thereby reducing the storage of excess carriers. At the same time, by setting a P-type Schottky diode, the conduction of the internal parasitic body diode is suppressed, and the injection of minority carriers during reverse conduction is reduced. Such an improvement not only reduces the reverse recovery charge, but also maintains the saturation current capability of the new structure.

[0053] A super junction MOSFET device with low reverse recovery charge and a manufacturing method thereof provided by the present invention have the following beneficial effects:

[0054] The present invention successfully optimizes the technical difficulties of reverse recovery of existing super junction MOSFET devices due to stored charge during reverse recovery. Compared with conventional structures, this new super junction MOSFET device significantly reduces the stored charge of the parasitic diode in the body, thereby improving the reverse recovery characteristics of the device, while maintaining the breakdown voltage and on-state current handling capacity of the device. These improvements make the super junction MOSFET of the present invention have significant advantages in application fields such as power adapters, drivers, industrial control and automotive electronics that require high switching speed and power conversion efficiency.

[0055] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A super junction MOSFET device with low reverse recovery charge, characterized in that: The invention comprises the following steps: forming an ohmic contact layer between the relative contact surfaces of an N-type heavily doped semiconductor substrate and a metal drain; forming an ohmic contact between the relative contact surfaces of a first heavily doped N+ region and a metal source; forming a Schottky contact between the relative contact surfaces of a P-body region and a metal source; alternatingly distributing P-type column regions and a first N-type region; forming an upward extension of a second N-type column region; forming an ohmic contact between the relative contact surfaces of a second heavily doped N+ region and a metal source; a P-type heavily doped buried layer in the P-body region and in contact with the first heavily doped N+ region; a first gate oxide layer located below the gate; a third gate oxide layer located outside the gate; and a second gate oxide layer located on both sides of a longitudinal channel P-base region.

2. The super junction MOSFET device with low reverse recovery charge according to claim 1, characterized in that: The first N-type column region and the second N-type column region have the same doping concentration, and the thickness of the second N-type column region is adjustable.

3. The super junction MOSFET device with low reverse recovery charge according to claim 1, characterized in that: The thickness of the first gate oxide layer and the second gate oxide layer can be adjusted, thereby controlling the turn-on voltage of the lateral and longitudinal channels of the gate MOS.

4. The super junction MOSFET device with low reverse recovery charge according to claim 1, characterized in that: The doping concentration of the P-type heavily doped buried layer is higher than that of the P-body region, and is used to suppress the conduction of the parasitic NPN transistor inside the super junction MOSFET device.

5. A method for manufacturing a super junction MOSFET device with low reverse recovery charge according to any one of claims 1 to 4, characterized in that: The steps include: S1, epitaxially growing a thin film with the same doping concentration as the first N-type column region on an N-type heavily doped semiconductor substrate, etching a P-type column region trench on the thin film, and then using multiple epitaxy or filling methods to form a P-type column region and a P-type heavily doped buried layer; S2, forming an oxide layer by thermal oxidation growth and depositing polysilicon; S3, etching excess polysilicon and oxide layer to expose a P-body region implantation window to form a P-body region by ion implantation or diffusion, and forming a first heavily doped N+ region by ion implantation or diffusion; S4, oxidizing to form a field oxide layer, etching a gate electrode window, forming a first gate oxide layer and a second gate oxide layer, and depositing to form a gate; S5, etching the field oxide layer to form a second N-type column region epitaxial window, epitaxially forming a second N-type column region and a P-base region, and ion implanting to form a second heavily doped N+ region; S6, etching a source window, metallizing and forming a Schottky contact with the P-body region to form a source; S7, back metallization forms a drain, completing the manufacture of a super junction MOSFET device with low reverse recovery charge.

Images