Semiconductor structure and forming method of semiconductor structure

Abstract

The invention discloses a semiconductor structure and a forming method of the semiconductor structure, and the structure comprises a substrate which is internally provided with a body region and a drift region which are adjacent to each other, the conduction types of the body region and the drift region are opposite, and the surface of the substrate is exposed out of the surfaces of the body region and the drift region; the gate structure is positioned on a part of the body region and a part of the drift region; the isolation layer is positioned on the surface of the drift region and the side wall surface of the gate structure on the drift region; the dielectric structure is located on the isolation layer, the shielding layers are located in the dielectric structure, the shielding layers are distributed in the direction away from the gate structure, and the thicknesses of the portions, between the shielding layers and the drift region, of the dielectric structure are different; and the plug structure is positioned on the dielectric structure. The performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] Lateral double-diffused metal-oxide semiconductor (LDMOS) is a power switching device widely used in high-voltage integrated circuits, such as AC / DC LED drivers, switching power supplies, motor drivers, etc. For high-power LDMOS, achieving high breakdown voltage (BV) and low on-resistance (Ron,sp) at the same time is an ideal goal. The on-resistance increases rapidly with the increase of high breakdown voltage, which is called Ron,sp∝BV. 2.5 The “silicon limit” relationship results in high power consumption.

[0003] Several technologies have been invented to optimize the trade-off between these two important parameters, such as reduced surface electric field (RESURF), super junction, and lateral doping variation (VLD). For medium and low voltage lateral double diffused metal oxide semiconductors, trench plug (Trench CT) is the mainstream technology in the industry. Since the trench plug technology does not destroy the carrier path on the surface of the wafer, a lower on-resistance can be obtained. However, the surface electric field formed by the trench plug technology has only two peaks at the gate and the trench plug edge, which means that the high voltage cannot be effectively reduced in the drift region.

[0004] Therefore, it is difficult to further optimize the relationship between the breakdown voltage and on-resistance of the lateral double diffused metal oxide semiconductor based on the trench plug technology. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of a lateral double diffused metal oxide semiconductor.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate, wherein the substrate has an adjacent body region and a drift region, the body region and the drift region have opposite conductivity types, and the surface of the substrate exposes the surface of the body region and the surface of the drift region; a gate structure located on a portion of the body region and a portion of the drift region; an isolation layer located on the surface of the drift region and the side wall surface of the gate structure on the drift region; a dielectric structure located on the isolation layer and a plurality of shielding layers located in the dielectric structure, wherein the plurality of shielding layers are distributed in a direction away from the gate structure, and the thickness of the dielectric structure between the plurality of shielding layers and the drift region is different; and a plug structure located on the dielectric structure.

[0007] Optionally, in a direction away from the gate structure, the thickness of the dielectric structure between the plurality of shielding layers and the drift region gradually increases.

[0008] Optionally, the projection area of ​​the plug structure on the drift region includes a first region, several second regions and a third region in a direction away from the gate structure, the first region is adjacent to the gate structure, the distance between the third region and the gate structure is greater than the distance between the second region and the gate structure, and several second regions are located between the first region and the third region.

[0009] Optionally, the plurality of shielding layers include: a first shielding layer located on the first area, and a plurality of second shielding layers located on the plurality of second areas, the first shielding layer is located on the isolation layer, and the plurality of second shielding layers are located in the dielectric structure.

[0010] Optionally, the dielectric structure includes: a first dielectric layer located between the first shielding layer and the second shielding layer, the first dielectric layer also being located on the isolation layer of the second zone and the third zone; a second dielectric layer located between adjacent second shielding layers and on the first dielectric layer; and a third dielectric layer located between the plug structure and the second shielding layer and on the second dielectric layer.

[0011] Optionally, the thickness of the first dielectric layer is less than 1000 angstroms; the thickness of the second dielectric layer is less than 1000 angstroms; and the thickness of the third dielectric layer is less than 1000 angstroms.

[0012] Optionally, the gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer.

[0013] Optionally, the first dielectric layer has a first thickness H1, and the i-th second dielectric layer has a second thickness H 2i The third dielectric layer has a third thickness H3, and the gate dielectric layer has a fourth thickness T OX , the isolation layer has a fifth thickness H S , a first spacing S is provided between one end of the first shielding layer away from the gate structure and the gate dielectric layer, a second spacing Ci is provided in the direction away from the gate structure for the i-th second region, a third spacing A is provided in the direction away from the gate structure, a fourth spacing B is provided between one end of the plug structure away from the gate structure and one end of the isolation layer away from the gate structure, the first spacing S, the second spacing Ci and the third spacing A and the first thickness H1 of the first dielectric layer, the second thickness H2 of the i-th second dielectric layer 2i The third thickness H3 of the third dielectric layer and the fourth thickness T OX , the fifth thickness H of the isolation layer S The relationship between the first spacing S = (H S -TOX )*V5 / (V drop *T OX ); the first second spacing C1 = H1 * V4 / (V drop *H S ); the i-th second spacing C i =H 2(i-1) *V R2 / (V drop *(H 2(i-2) +H 2(i-3) …+H 2(i-i) +H1+H S )), wherein the number of i is greater than or equal to 2; the third spacing A = H3*V R(i-2) / (V drop *(H1+H 2(i-2) +H 2(i-3) …+H 2(i-i) +H S )), where V R1 and V Ri V is the upper and lower plate voltage difference of the second capacitor formed by the second shielding layer, the first dielectric layer, the isolation layer and the drift region, V4 is the upper and lower plate voltage difference of the fourth capacitor formed by the first shielding layer, the isolation layer and the drift region, V5 is the upper and lower plate voltage difference of the capacitor edge formed by the gate layer and the drift region, V drop is the voltage drop.

[0014] Optionally, the isolation layer is also located on the sidewall surface and a portion of the top surface of the gate structure on the drift region; the plug structure is also located on the sidewall and a portion of the top dielectric structure of the gate structure on the drift region.

[0015] Optionally, some of the shielding layers further extend onto the isolation layer on the sidewalls and a portion of the top surface of the gate structure on the drift region.

[0016] Optionally, the voltages loaded on several of the shielding layers are the same; the voltages loaded on several of the shielding layers are the same as the ground voltage.

[0017] Optionally, the material of the isolation layer includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon carbon nitride oxynitride.

[0018] Optionally, the material of the dielectric structure includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon carbon nitride oxynitride.

[0019] Optionally, the material of the shielding layer includes metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0020] Optionally, the conductivity type of the body region is P type, and the conductivity type of the drift region is N type.

[0021] Optionally, it also includes: a drain region located in the drift region, the drain region is adjacent to the isolation layer far away from the gate structure, and the conductivity type of the drain region is the same as the conductivity type of the drift region; a source region located in the body region, the source region is adjacent to the gate structure, and the conductivity type of the source region is the same as the conductivity type of the drift region.

[0022] Optionally, it further includes: a doped region located in the body region, the conductivity type of the doped region is opposite to the conductivity type of the source region, and the doped region is adjacent to the source region.

[0023] Optionally, the material of the plug structure includes metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0024] Optionally, it also includes: a sidewall located on the sidewall of the gate structure; and the isolation layer is also located on the surface of the sidewall.

[0025] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate has an adjacent body region and a drift region, the body region and the drift region have opposite conductivity types, and the surface of the substrate exposes the surface of the body region and the surface of the drift region; forming a gate structure on the substrate, wherein the gate structure is located on part of the body region and part of the drift region; forming an isolation layer on the surface of the drift region and the side wall surface of the gate structure on the drift region; forming a dielectric structure and a plurality of shielding layers located in the dielectric structure on the isolation layer, wherein the plurality of shielding layers are distributed in a direction away from the gate structure, and the thickness of the dielectric structure between the plurality of shielding layers and the drift region is different; and forming a plug structure on the dielectric structure.

[0026] Optionally, in a direction away from the gate structure, the thickness of the dielectric structure between the plurality of shielding layers and the drift region gradually increases.

[0027] Optionally, the projection area of ​​the plug structure on the drift region includes a first region, several second regions and a third region in a direction away from the gate structure, the first region is adjacent to the gate structure, the distance between the third region and the gate structure is greater than the distance between the second region and the gate structure, and several second regions are located between the first region and the third region.

[0028] Optionally, the plurality of shielding layers include: a first shielding layer located on the first zone, and a plurality of second shielding layers located on the plurality of second zones, the first shielding layer being located on the isolation layer, and the plurality of the second shielding layers being located within the dielectric structure; the dielectric structure includes: a first dielectric layer located between the first shielding layer and the second shielding layer, the first dielectric layer also being located on the isolation layer between the second zone and the third zone; a second dielectric layer located between adjacent second shielding layers and on the first dielectric layer; and a third dielectric layer located between the plug structure and the second shielding layer and on the second dielectric layer.

[0029] Optionally, the gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer.

[0030] Optionally, the first dielectric layer has a first thickness H1, and the i-th second dielectric layer has a second thickness H 2i The third dielectric layer has a third thickness H3, and the gate dielectric layer has a fourth thickness T OX , the isolation layer has a fifth thickness H S , a first spacing S is provided between one end of the first shielding layer away from the gate structure and the gate dielectric layer, a second spacing Ci is provided in the direction away from the gate structure for the i-th second region, a third spacing A is provided in the direction away from the gate structure, a fourth spacing B is provided between one end of the plug structure away from the gate structure and one end of the isolation layer away from the gate structure, the first spacing S, the second spacing Ci and the third spacing A and the first thickness H1 of the first dielectric layer, the second thickness H2 of the i-th second dielectric layer 2i The third thickness H3 of the third dielectric layer and the fourth thickness T OX , the fifth thickness H of the isolation layer S The relationship between the first spacing S = (H S -T OX )*V5 / (V drop *T OX ); the first second spacing C1 = H1 * V4 / (V drop *H S ); the i-th second spacing C i =H 2(i-1) *V R2 / (V drop *(H 2(i-2) +H 2(i-3) …+H 2(i-i) +H1+H S )), wherein the number of i is greater than or equal to 2; the third spacing A = H3*V R(i-2) / (V drop *(H1+H 2(i-2) +H 2(i-3) …+H2(i-i) +H S )), where V R1 and V Ri V is the upper and lower plate voltage difference of the second capacitor formed by the second shielding layer, the first dielectric layer, the isolation layer and the drift region, V4 is the upper and lower plate voltage difference of the fourth capacitor formed by the first shielding layer, the isolation layer and the drift region, V5 is the upper and lower plate voltage difference of the capacitor edge formed by the gate layer and the drift region, V drop is the voltage drop.

[0031] Optionally, the isolation layer is also located on the sidewall surface and a portion of the top surface of the gate structure on the drift region; the plug structure is also located on the sidewall and a portion of the top dielectric structure of the gate structure on the drift region.

[0032] Optionally, some of the shielding layers further extend onto the isolation layer on the sidewalls and a portion of the top surface of the gate structure on the drift region.

[0033] Optionally, the conductivity type of the body region is P type, and the conductivity type of the drift region is N type.

[0034] Optionally, after forming the gate structure, it also includes: forming a drain region located in the drift region, the drain region is adjacent to the isolation layer, and the conductivity type of the drain region is the same as the conductivity type of the drift region; forming a source region located in the body region, the source region is adjacent to the gate structure, and the conductivity type of the source region is the same as the conductivity type of the drift region; forming a doped region located in the body region, the conductivity type of the doped region is opposite to the conductivity type of the source region, and the doped region is adjacent to the source region.

[0035] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0036] The technical solution of the present invention forms a dielectric structure and several shielding layers located in the dielectric structure on the isolation layer, wherein the several shielding layers are distributed in a direction away from the gate structure, and the thickness of the dielectric structure between the several shielding layers and the drift region is different. Thus, in the direction away from the gate structure, the shielding layer, the isolation layer and the dielectric structure between the shielding layer and the drift region, and the drift region form capacitor structures of different sizes, that is, several capacitor structures of different sizes are formed between the plug structure and the substrate, and each capacitor structure can form a new electric field peak on the drift region, so that the drift region is evenly depleted, the electric field is more uniform, can withstand higher voltages, and the hot carrier attenuation is weaker.

[0037] Furthermore, in the direction away from the gate structure, the thickness of the dielectric structure between the plurality of shielding layers and the drift region gradually increases. Therefore, the total thickness of the isolation layer and the dielectric structure between the shielding layer and the drift region gradually increases, and the size of the capacitor structure formed by the shielding layer and the drift region and the plug structure and the drift region gradually decreases in the direction away from the gate structure. The voltage difference between the upper and lower plates of each capacitor structure gradually increases in the direction away from the gate structure. When the total voltage remains unchanged, the voltage of the drift region from the drain region to the source region needs to be gradually reduced to ensure the charge consistency, thereby achieving uniform depletion of the drift region, making the electric field more uniform, able to withstand higher voltages, and weaker hot carrier attenuation.

[0038] Furthermore, some of the shielding layers extend to the isolation layer on the sidewall and part of the top surface of the gate structure on the drift region, so that the shielding layers can be easily connected to the external voltage later to load the same voltage, so as to ensure that there is no voltage difference between the relative shielding layers and no capacitor structure is formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a schematic structural diagram of a semiconductor structure in one embodiment;

[0040] Figures 2 to 7 It is a structural schematic diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0041] As the background technology, the performance of the existing lateral double diffused metal oxide semiconductor needs to be improved. Now, it is analyzed and explained in conjunction with specific embodiments.

[0042] Please refer to Figure 1 The semiconductor structure includes: a substrate 100, wherein the substrate 100 has a body region 101 and a drift region 102 adjacent to each other, wherein the body region 101 and the drift region 102 have opposite conductivity types, and the surface of the body region 101 and the drift region 102 are exposed on the surface of the substrate 100; a gate structure 103 located on a portion of the body region 101 and a portion of the drift region 102; a sidewall 104 located on a sidewall of the gate structure 103; and a gate structure 103 located on a surface of the drift region 102 and on the drift region 102. An isolation layer 105 on the side wall surface; a plug structure 109 located on the isolation layer 105, and the plug structure 109 is also located on the side wall of the gate structure 103; a drain region 106 located in the drift region 102 on one side of the isolation layer 105; a source region 107 located in the body region 101 on one side of the gate structure 103; a doped region 108 located in the body region 101, the doped region 108 is adjacent to the source region 107, and the conductivity type of the doped region 108 is opposite to the conductivity type of the source region 107.

[0043] In the semiconductor structure, there is a plug structure 109 on the isolation layer 105, and the semiconductor structure has only two electric field peaks on the surface of the gate structure 103 and the edge of the plug structure 109, which means that the high voltage cannot be effectively dropped in the drift region 102. Therefore, it is difficult to further optimize the relationship between the breakdown voltage and the on-resistance of the lateral double diffused metal oxide semiconductor based on the trench technology.

[0044] In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the semiconductor structure, by forming a dielectric structure and a plurality of shielding layers located in the dielectric structure on an isolation layer, the plurality of shielding layers are distributed in a direction away from the gate structure, and the thickness of the dielectric structure between the plurality of shielding layers and the drift region is different. Thus, in the direction away from the gate structure, the shielding layer, the isolation layer and the dielectric structure between the shielding layer and the drift region, and the drift region constitute capacitor structures of different sizes, that is, a plurality of capacitor structures of different sizes are formed between the plug structure and the substrate, and each capacitor structure can form a new electric field peak on the drift region, so that the drift region is evenly depleted, the electric field is more uniform, can withstand higher voltages, and the hot carrier attenuation is weaker.

[0045] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0046] Figures 2 to 7 It is a structural schematic diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0047] Please refer to Figure 2 A substrate 200 is provided, wherein the substrate 200 has adjacent body regions 201 and drift regions 202 , the body regions 201 and the drift regions 202 have opposite conductivity types, and the surface of the substrate 200 exposes the surfaces of the body regions 201 and the drift regions 202 .

[0048] In this embodiment, the conductivity type of the body region 201 is P type, and the conductivity type of the drift region 202 is N type.

[0049] In this embodiment, the material of the substrate 200 is silicon.

[0050] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0051] Please refer to Figure 3 , a gate structure is formed on the substrate 200 , and the gate structure is located on a portion of the body region 201 and a portion of the drift region 202 .

[0052] In this embodiment, the gate structure includes: a gate dielectric layer 204 and a gate layer 203 located on the gate dielectric layer 204 .

[0053] In this embodiment, the material of the gate dielectric layer 204 includes silicon oxide or a low-K (K is less than 3.9) material; the material of the gate layer 203 includes polysilicon.

[0054] Please continue to refer to Figure 3 , forming a sidewall spacer 220 on the sidewall of the gate structure.

[0055] In this embodiment, the material of the spacer 220 includes silicon nitride.

[0056] Please refer to Figure 4 , an isolation layer 205 is formed on the surface of the drift region 202 and the sidewall surface of the gate structure on the drift region 202 .

[0057] In this embodiment, the isolation layer 205 is also located on the top surface of the gate structure portion on the drift region 202 , and the isolation layer 205 is also located on the surface of the spacer 220 .

[0058] In this embodiment, the method for forming the isolation layer 205 includes: forming an isolation material layer (not shown) on the surface of the substrate 200 , the top surface of the gate structure and the sidewall surface; and removing part of the isolation material layer to form the isolation layer 205 .

[0059] In the present embodiment, the material of the isolation layer 205 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbide nitride.

[0060] In this embodiment, the material of the isolation layer 205 includes silicon oxide.

[0061] Please refer to Figure 5 , forming a drain region 206 located in the drift region 202, the conductivity type of the drain region 206 is the same as the conductivity type of the drift region 202, and the drain region 206 is adjacent to the isolation layer 205; forming a source region 207 located in the body region 201, the source region 207 is adjacent to the gate structure, and the conductivity type of the source region 207 is the same as the conductivity type of the drift region 202.

[0062] In this embodiment, the conductivity type of the source region 207 and the drain region 206 is N type.

[0063] In the present embodiment, the source region 207 and the drain region 206 are formed simultaneously, and the process of forming the source region 207 and the drain region 206 includes an ion implantation process.

[0064] Please continue to refer to Figure 5A doped region 208 is formed in the body region 201 . The doped region 208 is adjacent to the source region 207 . The conductivity type of the doped region 208 is opposite to that of the source region 207 .

[0065] In this embodiment, the conductivity type of the doped region 208 is P type, and the process of forming the doped region 208 includes an ion implantation process.

[0066] Please refer to Figure 6 A dielectric structure and several shielding layers located in the dielectric structure are formed on the isolation layer 205, and the several shielding layers are distributed in a direction away from the gate structure. The thickness of the dielectric structure between the several shielding layers and the drift region 202 is different; a plug structure 215 is formed on the dielectric structure.

[0067] The thickness of the dielectric structure between the plurality of shielding layers and the drift region 202 is different. Thus, in the direction away from the gate structure, the shielding layer, the isolation layer 205 and the dielectric structure between the shielding layer and the drift region 202, and the drift region 202 form capacitor structures of different sizes, that is, a plurality of capacitor structures of different sizes are formed between the plug structure 215 and the substrate 200, each of which can form a new electric field peak on the drift region 202, so that the drift region 202 is uniformly depleted, the electric field is more uniform, can withstand higher voltages, and the hot carrier attenuation is weaker.

[0068] The projection area of ​​the plug structure 215 on the drift region 202 includes a first region I, several second regions II and a third region III in a direction away from the gate structure, the first region I is adjacent to the gate structure, the distance between the third region III and the gate structure is greater than the distance between the second region II and the gate structure, the third region III is farthest from the gate structure, and several second regions II are located between the first region I and the third region III.

[0069] In this embodiment, the plurality of shielding layers include: a first shielding layer 209 located on the first zone I, and a plurality of second shielding layers located on a plurality of second zones II, wherein the first shielding layer 209 is located on the isolation layer 205, and the plurality of second shielding layers are located in the dielectric structure.

[0070] In this embodiment, the dielectric structure includes: a first dielectric layer 210 located between the first shielding layer 209 and the second shielding layer, and the first dielectric layer 210 is also located on the isolation layer 205 of the second zone II and the third zone III; a second dielectric layer located between adjacent second shielding layers and on the first dielectric layer 210; and a third dielectric layer 214 located between the plug structure 215 and the second shielding layer and on the second dielectric layer.

[0071] In this embodiment, the thickness of the first dielectric layer 210 is less than 1000 angstroms; the thickness of the second dielectric layer is less than 1000 angstroms; and the thickness of the third dielectric layer 214 is less than 1000 angstroms.

[0072] It should be noted that the second shielding layer shown in this embodiment includes a first second shielding layer 211 and a second second shielding layer 213 , and the second dielectric layer 212 is located between the first second shielding layer 211 and the second second shielding layer 213 .

[0073] In this embodiment, only the first second dielectric layer 212 is schematically shown. When the number of second shielding layers is greater than 2, the number of the second dielectric layers is also greater than 1, and the second second dielectric layer is located on the second second shielding layer 213 and the first second dielectric layer 212.

[0074] In this embodiment, some of the shielding layers also extend onto the isolation layer 205 on the sidewalls and a portion of the top surface of the gate structure on the drift region 202 .

[0075] Some of the shielding layers also extend onto the isolation layer 205 on the sidewalls and part of the top surface of the gate structure on the drift region 202, so that the shielding layers can be easily connected to the external voltage later to load the same voltage, so as to ensure that there is no voltage difference between the relative shielding layers and no capacitor structure is formed.

[0076] In other embodiments, the shielding layer may be located only on the first region I and the second region II.

[0077] In this embodiment, in a direction away from the gate structure, the thickness of the dielectric structure between the plurality of shielding layers and the drift region 202 gradually increases.

[0078] That is, in the first region I, only the isolation layer 205 is between the first shielding layer 209 and the drift region 202; in the second region II, the first dielectric layer 210 and the isolation layer 205 are between the first layer second shielding layer 211 and the drift region 202, and the second dielectric layer 212, the first dielectric layer 210 and the isolation layer 205 are between the second layer second shielding layer 213 and the drift region 202. In the third region III, the plug structure 215 and the drift region 202 are separated by a dielectric structure and an isolation layer 205, and the dielectric structure includes a third dielectric layer 214, a second dielectric layer 212 and a first dielectric layer 210.

[0079] The first shielding layer 209, the isolation layer 205 and the drift region 202 constitute a first capacitor, the first second shielding layer 211, the first dielectric layer 210 and the isolation layer 205 and the drift region 202 constitute a second capacitor, the second second shielding layer 213, the second dielectric layer 212, the first dielectric layer 210 and the isolation layer 205 and the drift region 202 constitute a third capacitor, the plug structure 215, the dielectric structure and the isolation layer 205 and the drift region 202 constitute a fourth capacitor, the dielectric structure includes a third dielectric layer 214, the second dielectric layer 212 and the first dielectric layer 210, and in the direction away from the gate structure, the sizes of the first capacitor, the second capacitor, the third capacitor and the fourth capacitor gradually increase.

[0080] In this embodiment, the same voltage is applied to a plurality of shielding layers, so there is no voltage difference between two adjacent shielding layers, and a capacitor structure cannot be formed.

[0081] In this embodiment, the voltage loaded on the plurality of shielding layers is the same as the ground voltage.

[0082] In this embodiment, the voltage loaded on the plug structure 215 is the same as the voltage loaded on the plurality of shielding layers, and the voltage loaded on the plug structure 215 is also the same as the ground voltage.

[0083] In the direction away from the gate structure, the thickness of the dielectric structure between the plurality of shielding layers and the drift region 202 gradually increases. Therefore, the total thickness of the isolation layer 205 and the dielectric structure between the shielding layer and the drift region 202 gradually increases, and in the direction away from the gate structure, the size of the capacitor structure formed by the shielding layer and the drift region 202 and the plug structure and the drift region 202 gradually increases. Under the condition that the total voltage loaded on the plug structure 215 remains unchanged, the electric field peak of each capacitor structure gradually decreases in the direction away from the gate structure, and the voltage of the drift region 202 gradually decreases from the drain region 206 to the source region 207, thereby achieving uniform depletion of the drift region 202, making the electric field more uniform, able to withstand higher voltages, and weaker hot carrier attenuation.

[0084] In this embodiment, the plug structure 215 is also located on the sidewalls of the gate structure and a portion of the top dielectric structure on the drift region 202 .

[0085] Please refer to Figure 7 , Figure 7 For Figure 6 Based on the schematic diagram, the first dielectric layer 210 has a first thickness H1, and the i-th second dielectric layer has a second thickness H 2i , the third dielectric layer 214 has a third thickness H3, and the gate dielectric layer 204 has a fourth thickness T OX , the isolation layer 205 has a fifth thickness H S, there is a first spacing S between the end of the first shielding layer 209 away from the gate structure and the gate dielectric layer 204, the i-th second region II has a second spacing Ci in the direction away from the gate structure, the third region III has a third spacing A in the direction away from the gate structure, and there is a fourth spacing B between the end of the plug structure 215 away from the gate structure and the end of the isolation layer 205 away from the gate structure.

[0086] The fourth thickness T of the gate dielectric layer 204 is OX Affected by the process, it is a preset value; a fourth distance B between an end of the plug structure 215 away from the gate structure and an end of the isolation layer 205 away from the gate structure is affected by the process and is a preset value.

[0087] In this embodiment, two second regions II are schematically shown, the second shielding layer includes a first second shielding layer 211 and a second second shielding layer 213, the second dielectric layer includes a first second dielectric layer 212, the first second region II has a second spacing C1 in a direction away from the gate structure, the second second region II has a second spacing C2 in a direction away from the gate structure, and the first second dielectric layer 212 has a second thickness H 21 .

[0088] Assume the breakdown voltage of the device is V R , the voltage drop per micron along the direction from the device gate structure to the drain region 206 is V drop ,So:

[0089] The plug structure 215 and the drift region 202 form a first capacitor, and the voltage difference between the upper and lower plates of the first capacitor V1=V R -B*V drop ;

[0090] The second shielding layer 213, the second dielectric layer 212, the first dielectric layer 210, the isolation layer 205 and the drift region 202 form a second capacitor. The voltage difference between the upper and lower plates of the second capacitor is V R1 =V R -(B+A)*V drop ;

[0091] The first second shielding layer 211, the first dielectric layer 210, the isolation layer 205 and the drift region 202 form a third capacitor. The voltage difference between the upper and lower plates of the third capacitor is V R2 =V R -(C2+A+B)*V drop ;

[0092] The first shielding layer 209, the isolation layer 205 and the drift region 202 form a fourth capacitor. The dielectric structure includes a third dielectric layer 214, a second dielectric layer 212 and a first dielectric layer 210. The voltage difference between the upper and lower plates of the fourth capacitor V4=V R -(C1+C2+A+B)*V drop ;

[0093] The voltage difference between the upper and lower plates of the capacitor formed by the gate layer 203 and the drift region 202 is V5 = V R -(S+C1+C2+A+B)*V drop .

[0094] In the direction away from the gate structure, the sizes of the fourth capacitor, the third capacitor, the second capacitor and the first capacitor gradually decrease. It can be seen that the upper and lower plate voltage differences V5, V4, V R2 、V R1 and V 1、、 The size of gradually increases. When the total voltage remains unchanged, the voltage of the drift region 202 gradually decreases from the drain region 206 to the source region 207 to ensure consistent charges, thereby achieving uniform depletion of the drift region 202, making the electric field more uniform, able to withstand higher voltages, and weaker hot carrier attenuation.

[0095] In this embodiment, the voltage drop V drop =10-40V / um.

[0096] The first spacing S, the second spacing Ci and the third spacing A are related to the first thickness H1 of the first dielectric layer 210, the second thickness H2 of the i-th dielectric layer 210 and the 2i , the third thickness H3 of the third dielectric layer 214 and the fourth thickness T OX , the fifth thickness H of the isolation layer 205 S The relationship between them is:

[0097] The third distance A=H3*V R1 / (V drop *(H1+H 21 +H S ));

[0098] The second second spacing C2=H 21 *V R2 / (V drop *(H1+H S ));

[0099] The first second spacing C1=H1*V4 / (V drop *H S );

[0100] The first spacing S=(HS -T OX )*V5 / (V drop *T OX ).

[0101] It can be seen that when the number of the second zone II is greater than or equal to 2,

[0102] The first second spacing C1=H1*V4 / (V drop *H S );

[0103] The i-th second spacing C i =H 2(i-1) *V R2 / (V drop *(H 2(i-2) +H 2(i-3) …+H 2(i-i) +H1+H S )), where the number of i is greater than or equal to 2;

[0104] The third distance A=H3*V R(i-2) / (V drop *(H1+H 2(i-2) +H 2(i-3) …+H 2(i-i) +H S )).

[0105] In this embodiment, the material of the shielding layer includes metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0106] In this embodiment, the material of the plug structure 215 includes metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0107] In this embodiment, the material of the dielectric structure includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride.

[0108] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 6 ,include:

[0109] A substrate 200, wherein the substrate 200 has a body region 201 and a drift region 202 adjacent to each other, the body region 201 and the drift region 202 have opposite conductivity types, and the surface of the body region 201 and the drift region 202 are exposed on the surface of the substrate 200;

[0110] A gate structure located on a portion of the body region 201 and a portion of the drift region 202;

[0111] An isolation layer 205 located on the surface of the drift region 202 and the sidewall surface of the gate structure on the drift region 202;

[0112] a dielectric structure located on the isolation layer 205 and a plurality of shielding layers located in the dielectric structure, wherein the plurality of shielding layers are distributed in a direction away from the gate structure, and the dielectric structure between the plurality of shielding layers and the drift region 202 has different thicknesses;

[0113] A plug structure 215 is located on the dielectric structure.

[0114] In this embodiment, in a direction away from the gate structure, the thickness of the dielectric structure between the plurality of shielding layers and the drift region 202 gradually increases.

[0115] In this embodiment, the projection area of ​​the plug structure 215 on the drift region 202 includes a first region I, several second regions II and a third region III in a direction away from the gate structure, the first region I is adjacent to the gate structure, the third region III is farthest from the gate structure, and several second regions II are located between the first region I and the third region III.

[0116] In this embodiment, the plurality of shielding layers include: a first shielding layer 209 located on the first zone I, and a plurality of second shielding layers located on a plurality of second zones II, wherein the first shielding layer 209 is located on the isolation layer 205, and the plurality of second shielding layers are located in the dielectric structure.

[0117] In this embodiment, the dielectric structure includes: a first dielectric layer 210 located between the first shielding layer 209 and the second shielding layer, and the first dielectric layer 210 is also located on the isolation layer 205 of the second zone II and the third zone III; a second dielectric layer located between adjacent second shielding layers and on the first dielectric layer 210; and a third dielectric layer 214 located between the plug structure 215 and the second shielding layer and on the second dielectric layer.

[0118] In this embodiment, the thickness of the first dielectric layer 210 is less than 1000 angstroms; the thickness of the second dielectric layer is less than 1000 angstroms; and the thickness of the third dielectric layer 214 is less than 1000 angstroms.

[0119] In this embodiment, the gate structure includes a gate dielectric layer 204 and a gate layer 203 located on the gate dielectric layer 204 .

[0120] In this embodiment, the first dielectric layer 210 has a first thickness H1, and the i-th second dielectric layer has a second thickness H2i , the third dielectric layer 214 has a third thickness H3, and the gate dielectric layer 204 has a fourth thickness T OX , the isolation layer 205 has a fifth thickness H S , a first spacing S is formed between the end of the first shielding layer 209 away from the gate structure and the gate dielectric layer 204, the i-th second region II has a second spacing Ci in the direction away from the gate structure, the third region has a third spacing A in the direction away from the gate structure, a fourth spacing B is formed between the end of the plug structure 215 away from the gate structure and the end of the isolation layer 205 away from the gate structure, the first spacing S, the second spacing Ci and the third spacing A and the first thickness H1 of the first dielectric layer 210, the second thickness H2 of the i-th second dielectric layer 2i , the third thickness H3 of the third dielectric layer 214 and the fourth thickness T OX , the fifth thickness H of the isolation layer 205 S The relationship between is: The first spacing S = (H S -T OX )*V5 / (V drop *T OX ); the first second spacing C1 = H1 * V4 / (V drop *H S ); the i-th second spacing C i =H 2(i-1) *V R2 / (V drop *(H 2(i-2) +H 2(i-3) …+H 2(i-i) +H1+H S )), wherein the number of i is greater than or equal to 2; the third spacing A = H3*V R(i-2) / (V drop *(H1+H 2(i-2) +H 2(i-3) …+H 2(i-i) +H S )), where V R1 and V Ri V is the upper and lower plate voltage difference of the second capacitor formed by the second shielding layer 211, the first dielectric layer 210, the isolation layer 205 and the drift region 202, V4 is the upper and lower plate voltage difference of the fourth capacitor formed by the first shielding layer 209, the isolation layer 205 and the drift region 202, V5 is the upper and lower plate voltage difference of the capacitor edge formed by the gate layer 203 and the drift region 202, V drop is the voltage drop.

[0121] In this embodiment, the isolation layer 205 is also located on the top surface of a portion of the gate structure in the drift region 202 ; the plug structure 215 is also located on the sidewall and a portion of the top dielectric structure of the gate structure in the drift region 202 .

[0122] In this embodiment, some of the shielding layers also extend onto the isolation layer 205 on the sidewalls and a portion of the top surface of the gate structure on the drift region 202 .

[0123] In this embodiment, the voltages loaded on the plurality of shielding layers are the same; the voltages loaded on the plurality of shielding layers are the same as the ground voltage.

[0124] In this embodiment, the material of the isolation layer 205 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride.

[0125] In this embodiment, the material of the dielectric structure includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride.

[0126] In this embodiment, the material of the shielding layer includes metal, and the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0127] In this embodiment, the conductivity type of the body region 201 is P type, and the conductivity type of the drift region 202 is N type.

[0128] In this embodiment, it also includes: a drain region 206 located in the drift region 202, the conductivity type of the drain region 206 is the same as the conductivity type of the drift region 202, and the drain region 206 is adjacent to the isolation layer 205 away from the gate structure; a source region 207 located in the body region 201, the source region 207 is adjacent to the gate structure, and the conductivity type of the source region 207 is the same as the conductivity type of the drift region 202.

[0129] In this embodiment, the doping region 208 is further included in the body region 201 . The conductivity type of the doping region 208 is opposite to that of the source region 207 . The doping region 208 is adjacent to the source region 207 .

[0130] In this embodiment, the material of the plug structure 215 includes metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0131] In this embodiment, it further includes: a sidewall spacer 220 located on the sidewall of the gate structure.

[0132] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate having a body region and a drift region adjacent to each other, the body region and the drift region having opposite conductivity types, and a surface of the substrate exposing surfaces of the body region and the drift region; A gate structure located on a portion of the body region and a portion of the drift region; an isolation layer located on the surface of the drift region; a dielectric structure located on the isolation layer and a plurality of shielding layers located in the dielectric structure, wherein the plurality of shielding layers are distributed in a direction away from the gate structure, and the dielectric structure between the plurality of shielding layers and the drift region has different thicknesses; A plug structure is located on the dielectric structure.

2. The semiconductor structure according to claim 1, wherein: In a direction away from the gate structure, the thickness of the dielectric structure between the plurality of shielding layers and the drift region gradually increases.

3. The semiconductor structure according to claim 2, wherein: The projection area of ​​the plug structure on the drift region includes a first region, several second regions and a third region in a direction away from the gate structure, the first region is adjacent to the gate structure, the distance between the third region and the gate structure is greater than the distance between the second region and the gate structure, and several second regions are located between the first region and the third region.

4. The semiconductor structure according to claim 3, characterized in that The plurality of shielding layers include: a first shielding layer located on the first area, and a plurality of second shielding layers located on the plurality of second areas, the first shielding layer is located on the isolation layer, and the plurality of the second shielding layers are located in the dielectric structure.

5. The semiconductor structure according to claim 4, characterized in that The dielectric structure includes: a first dielectric layer located between the first shielding layer and the second shielding layer, the first dielectric layer also being located on the isolation layer of the second area and the third area; a second dielectric layer located between adjacent second shielding layers and on the first dielectric layer; and a third dielectric layer located between the plug structure and the second shielding layer and on the second dielectric layer.

6. The semiconductor structure according to claim 5, characterized in that The thickness of the first dielectric layer is less than 1000 angstroms; the thickness of the second dielectric layer is less than 1000 angstroms; and the thickness of the third dielectric layer is less than 1000 angstroms.

7. The semiconductor structure according to claim 5, characterized in that The gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer.

8. The semiconductor structure according to claim 7, wherein: The first dielectric layer has a first thickness H1, and the i-th second dielectric layer has a second thickness H 2i The third dielectric layer has a third thickness H3, and the gate dielectric layer has a fourth thickness T OX , the isolation layer has a fifth thickness H S , a first spacing S is provided between one end of the first shielding layer away from the gate structure and the gate dielectric layer, a second spacing Ci is provided in the direction away from the gate structure for the i-th second region, a third spacing A is provided in the direction away from the gate structure, a fourth spacing B is provided between one end of the plug structure away from the gate structure and one end of the isolation layer away from the gate structure, the first spacing S, the second spacing Ci and the third spacing A and the first thickness H1 of the first dielectric layer, the second thickness H2 of the i-th second dielectric layer 2i The third thickness H3 of the third dielectric layer and the fourth thickness T OX , the fifth thickness H of the isolation layer S The relationship between the first spacing S = (H S -T OX )*V5 / (V drop *T OX ); the first second spacing C1 = H1 * V4 / (V drop *H S ); the i-th second spacing C i =H 2(i-1) *V R2 / (V drop *(H 2(i-2) +H 2(i-3) …+H 2(i-i) +H1+H S )), wherein the number of i is greater than or equal to 2; the third spacing A = H3*V R(i-2) / (V drop *(H1+H 2(i-2) +H 2(i-3) …+H 2(i-i) +H S )), where V R1 and V Ri V is the upper and lower plate voltage difference of the second capacitor formed by the second shielding layer, the first dielectric layer, the isolation layer and the drift region, V4 is the upper and lower plate voltage difference of the fourth capacitor formed by the first shielding layer, the isolation layer and the drift region, V5 is the upper and lower plate voltage difference of the capacitor edge formed by the gate layer and the drift region, V drop is the voltage drop.

9. The semiconductor structure according to claim 1, wherein: The isolation layer is also located on the side wall surface and part of the top surface of the gate structure on the drift region; the plug structure is also located on the side wall and part of the top dielectric structure of the gate structure on the drift region.

10. The semiconductor structure according to claim 9, wherein: Some of the shielding layers further extend onto the isolation layer on the sidewall and a portion of the top surface of the gate structure on the drift region.

11. The semiconductor structure according to claim 1, wherein: The voltages loaded on several of the shielding layers are the same; the voltages loaded on several of the shielding layers are the same as the ground voltage.

12. The semiconductor structure according to claim 1, wherein: The material of the isolation layer includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

13. The semiconductor structure according to claim 1, wherein: The material of the dielectric structure includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbide nitride.

14. The semiconductor structure according to claim 1, wherein: The material of the shielding layer includes metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

15. The semiconductor structure according to claim 1, wherein: The conductivity type of the body region is P type, and the conductivity type of the drift region is N type.

16. The semiconductor structure according to claim 15, wherein: Also includes: A drain region located in the drift region, the drain region is adjacent to an isolation layer far away from the gate structure, and the conductivity type of the drain region is the same as the conductivity type of the drift region; a source region located in the body region, the source region is adjacent to the gate structure, and the conductivity type of the source region is the same as the conductivity type of the drift region.

17. The semiconductor structure according to claim 16, wherein: Also includes: The doped region is located in the body region, the conductivity type of the doped region is opposite to the conductivity type of the source region, and the doped region is adjacent to the source region.

18. The semiconductor structure according to claim 1, wherein: The material of the plug structure includes metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

19. The semiconductor structure according to claim 1, wherein: Also includes: A sidewall disposed on a sidewall of the gate structure; The isolation layer is also located on the surface of the side wall.

20. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has a body region and a drift region adjacent to each other, the body region and the drift region have opposite conductivity types, and the surface of the substrate exposes the surface of the body region and the drift region; forming a gate structure on the substrate, wherein the gate structure is located on a portion of the body region and a portion of the drift region; forming an isolation layer on the surface of the drift region and on the sidewall surface of the gate structure on the drift region; forming a dielectric structure and a plurality of shielding layers located in the dielectric structure on the isolation layer, wherein the plurality of shielding layers are distributed in a direction away from the gate structure, and the dielectric structure between the plurality of shielding layers and the drift region has different thicknesses; A plug structure is formed on the dielectric structure.

21. The method for forming a semiconductor structure according to claim 20, wherein: In a direction away from the gate structure, the thickness of the dielectric structure between the plurality of shielding layers and the drift region gradually increases.

22. The method for forming a semiconductor structure according to claim 21, wherein: The projection area of ​​the plug structure on the drift region includes a first region, several second regions and a third region in a direction away from the gate structure, the first region is adjacent to the gate structure, the distance between the third region and the gate structure is greater than the distance between the second region and the gate structure, and several second regions are located between the first region and the third region.

23. The method for forming a semiconductor structure according to claim 22, wherein: The plurality of shielding layers include: a first shielding layer located on the first zone, and a plurality of second shielding layers located on the plurality of second zones, the first shielding layer being located on the isolation layer, and the plurality of second shielding layers being located in the dielectric structure; the dielectric structure includes: a first dielectric layer located between the first shielding layer and the second shielding layer, the first dielectric layer also being located on the isolation layer of the second zone and the third zone; a second dielectric layer located between adjacent second shielding layers and on the first dielectric layer; and a third dielectric layer located between the plug structure and the second shielding layer and on the second dielectric layer.

24. The method for forming a semiconductor structure according to claim 23, wherein: The gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer.

25. The method for forming a semiconductor structure according to claim 24, wherein: The first dielectric layer has a first thickness H1, and the i-th second dielectric layer has a second thickness H 2i The third dielectric layer has a third thickness H3, and the gate dielectric layer has a fourth thickness T OX , the isolation layer has a fifth thickness H S , a first spacing S is provided between one end of the first shielding layer away from the gate structure and the gate dielectric layer, a second spacing Ci is provided in the direction away from the gate structure for the i-th second region, a third spacing A is provided in the direction away from the gate structure, a fourth spacing B is provided between one end of the plug structure away from the gate structure and one end of the isolation layer away from the gate structure, the first spacing S, the second spacing Ci and the third spacing A and the first thickness H1 of the first dielectric layer, the second thickness H2 of the i-th second dielectric layer 2i The third thickness H3 of the third dielectric layer and the fourth thickness T OX , the fifth thickness H of the isolation layer S The relationship between the first spacing S = (H S -T OX )*V5 / (V drop *T OX ); the first second spacing C1 = H1 * V4 / (V drop *H S ); the i-th second spacing C i =H 2(i-1) *V R2 / (V drop *(H 2(i-2) +H 2(i-3) …+H 2(i-i) +H1+H S )), wherein the number of i is greater than or equal to 2; the third spacing A = H3*V R(i-2) / (V drop *(H1+H 2(i-2) +H 2(i-3) …+H 2(i-i) +H S )), where V R1 and V Ri V is the upper and lower plate voltage difference of the second capacitor formed by the second shielding layer, the first dielectric layer, the isolation layer and the drift region, V4 is the upper and lower plate voltage difference of the fourth capacitor formed by the first shielding layer, the isolation layer and the drift region, V5 is the upper and lower plate voltage difference of the capacitor edge formed by the gate layer and the drift region, V drop is the voltage drop.

26. The method for forming a semiconductor structure according to claim 20, wherein: The isolation layer is also located on the side wall surface and part of the top surface of the gate structure on the drift region; the plug structure is also located on the side wall and part of the top dielectric structure of the gate structure on the drift region.

27. The method for forming a semiconductor structure according to claim 26, wherein: Some of the shielding layers further extend onto the isolation layer on the sidewall and a portion of the top surface of the gate structure on the drift region.

28. The method for forming a semiconductor structure according to claim 20, wherein: The conductivity type of the body region is P type, and the conductivity type of the drift region is N type.

29. The method for forming a semiconductor structure according to claim 28, wherein: After forming the gate structure, it also includes: forming a drain region located in the drift region, the drain region is adjacent to the isolation layer, and the conductivity type of the drain region is the same as the conductivity type of the drift region; forming a source region located in the body region, the source region is adjacent to the gate structure, and the conductivity type of the source region is the same as the conductivity type of the drift region; forming a doped region located in the body region, the conductivity type of the doped region is opposite to the conductivity type of the source region, and the doped region is adjacent to the source region.

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