MOSFET device and preparation method thereof

Abstract

The invention discloses an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a preparation method thereof, and the MOSFET device comprises a substrate, an epitaxial layer located above the substrate, a drain electrode located below the substrate, a current expansion region located in the epitaxial layer, a well region located above the current expansion region, a source region located in the well region, and a body region located in the source region, the grooves are formed in the two ends of the epitaxial layer, the gate groove is formed in the center of the epitaxial layer, the gate dielectric layer is located in the grooves and the gate groove, the polycrystalline silicon is located on the surface of the gate dielectric layer, and the passivation layer is located on the upper surface of the epitaxial layer. The trench gate injection region is introduced into the MOSFET device and can be used for modulating an internal electric field of the device, so that gate-oxide breakdown is protected, meanwhile, the effective conduction area of the device can be increased, and the conduction capability of the device is improved. The device structure and the preparation method are simple, the effect is remarkable, high-performance and batch preparation and production of the groove type SiC MOSFET device can be achieved, and the device has huge market potential and wide application prospects.

Description

Technical Field

[0001] The invention relates to the field of semiconductor component preparation, and in particular to a MOSFET device and a preparation method thereof. Background Art

[0002] Silicon Carbide (SiC) power devices can simultaneously achieve excellent performance such as high breakdown voltage, low on-resistance, high switching speed and easy heat dissipation, and have obvious competitiveness in high-efficiency, high-power and high-temperature power electronics technology. Compared with planar gate SiC MOSFET devices, trench gate SiC MOSFET does not have a parasitic junction field effect transistor region (Junction Field Electric Transistor, JFET), the device on-resistance can be significantly reduced, and the unit cell size is further reduced, which can further improve the device power density and reduce system power consumption. The performance advantage is obvious and the application prospects are very broad. However, due to the influence of the electric field concentration effect at the bottom corner of the trench, trench SiC MOSFET devices are very likely to cause premature breakdown or even burnout of the device. In addition, the high electric field in the gate oxide at the bottom of the trench is very likely to cause gate oxide breakdown, resulting in device failure. Therefore, how to modulate the electric field at the bottom of the trench of the trench SiC MOSFET device and reduce the risk of gate oxide breakdown is a difficult and hot issue for trench SiC MOSFET devices. Patent ZL 202110726765.3 discloses a trench SiC MOSFET device that introduces a column area electric field modulation structure, which can effectively alleviate the electric field distribution at the bottom of the trench, eliminate the electric field concentration effect, and shield the electric field strength inside the gate oxide, reduce the electric field strength inside the gate oxide, and avoid gate oxide breakdown, thereby preventing the device from breaking down and burning prematurely and improving device reliability. However, the introduced column area structure will not only cause natural depletion with the original well area of ​​the device, thereby deteriorating the device's conduction capability. At the same time, the column area structure will occupy the chip area, resulting in a reduction in the effective conduction area of ​​the chip, further deteriorating the conduction performance. Summary of the invention

[0003] Purpose of the invention: To provide a MOSFET device and a preparation method to solve the problems of modulating the electric field distribution at the bottom of the trench, protecting the gate oxide, and improving the conduction performance of the trench SiC MOSFET device.

[0004] Technical solution: A MOSFET device proposed in the present invention comprises a substrate, an epitaxial layer located above the substrate, a drain electrode located below the substrate, a current extension region located in the epitaxial layer, a well region located above the current extension region, a source region located in the well region, a body region located in the source region, grooves located at both ends of the epitaxial layer, a gate trench located at the center of the epitaxial layer, a gate dielectric layer located in the groove and the gate trench, polysilicon located on the surface of the gate dielectric layer, and a passivation layer located on the upper surface of the epitaxial layer; An injection region is also provided at the bottom of the groove, a source ohmic contact layer is provided on the upper surfaces of the source region and the body region, a recessed source window is provided in the passivation layer to accommodate the source ohmic contact layer so that the source ohmic contact layer contacts the source region and the body region, a source electrode is provided on the upper surface of the ohmic contact layer, the outer side and the center of the passivation layer are recessed to form a gate window, a gate electrode is provided in the gate window, the lower surface of the gate electrode contacts the polysilicon, a drain ohmic contact layer is provided on the lower surface of the substrate, and the drain ohmic contact layer is located between the substrate and the drain electrode.

[0005] Preferably, a buffer layer is provided between the substrate and the first epitaxial layer.

[0006] Preferably, the substrate, epitaxial layer, current extension region, source region and polysilicon are all of the first doping type.

[0007] Preferably, the well region, the body region and the implantation region are all of the second doping type.

[0008] Preferably, the groove has a depth of 1 to 3 um and a width of 0.5 to 1.5 um, the gate trench has a depth of 0.8 to 1.2 um and a width of 0.5 to 1.5 um, and the depth of the gate trench is equal to or less than the depth of the groove.

[0009] Preferably, the distance between the injection area and the groove boundary is 0-0.5um, the depth of the injection area is 0.3-1um, and the doping concentration is 1e17-1e19cm -3 The depth of the well region is 0.2 to 1 um, and the doping concentration is 1e17 to 1e18 cm -3 The depth of the current extension zone is 0.1-0.5um, and the doping concentration is 1e16-1e17cm -3 .

[0010] Preferably, the gate dielectric layer on the sidewalls of the gate trench and the groove is 30-60 nm thick, and the gate dielectric layer at the bottom is 20-50 nm thicker than the gate dielectric layer on the sidewalls.

[0011] A method for preparing a MOSFET device comprises the following steps:

[0012] S1: providing a substrate of a first doping type, forming an epitaxial layer of the first doping type on the upper surface of the substrate, and a buffer layer being provided between the substrate and the epitaxial layer;

[0013] S2: forming a current extension region of a first doping type in the epitaxial layer, forming a well region of a second doping type in the epitaxial layer, forming a source region of the first doping type in the well region, and forming a body region of the second doping type in the source region;

[0014] S3: forming a groove of a trench gate implantation region structure in the epitaxial layer, and forming an implantation region at the bottom of the groove;

[0015] S4: forming a gate trench in the epitaxial layer obtained after completing step 3;

[0016] S5: forming a gate dielectric layer in the gate trench and the groove, and filling a first doping type of polysilicon on the surface of the gate dielectric layer;

[0017] S6: forming a passivation layer on the surface of the epitaxial layer obtained in step 5, and forming a source window in the passivation layer;

[0018] S7: forming a source ohmic contact layer in the source window;

[0019] S8: forming a gate window in the passivation layer at a position corresponding to the polysilicon region;

[0020] S9: forming a gate electrode in the gate window, and forming a source electrode on the surface of the source ohmic contact layer;

[0021] S10: thinning the bottom of the substrate of the first doping type after completing step 9;

[0022] S11: forming a drain ohmic contact layer on the bottom surface of the thinned substrate obtained in step 10, and forming a drain electrode on the lower surface of the drain ohmic contact layer.

[0023] Preferably, in step S3, a groove of a trench gate implantation region structure is formed in the epitaxial layer, and an implantation region is formed at the bottom of the groove, comprising the following steps:

[0024] S31: forming a hard mask dielectric layer on the surface of the epitaxial layer obtained in step S2, wherein the hard mask dielectric layer is silicon oxide, silicon nitride or polysilicon and has a thickness of 3 to 5 um;

[0025] S32: coating a photoresist on the upper surface of the first dielectric layer, and patterning the photoresist to form a patterned photoresist;

[0026] S33: etching the hard mask dielectric layer using an etching process according to the patterned photoresist to form a patterned hard mask dielectric layer;

[0027] S34: removing the patterned photoresist and retaining the patterned hard mask dielectric layer;

[0028] S35: performing an etching process on the epitaxial layer to form a groove according to the patterned hard mask dielectric layer;

[0029] S36: after completing step S35, a dielectric film layer is deposited on the surface of the structure, the dielectric film layer is silicon nitride, silicon oxide or polysilicon, and has a thickness of 0 to 0.5 um;

[0030] S37: performing a second doping type ion implantation process on the structure after step S36 to form an implantation region;

[0031] S38: removing all dielectric layers in the above steps.

[0032] Preferably, in step 4, forming a gate trench in the epitaxial layer obtained after completing step S3 comprises the following steps:

[0033] S41: After completing step S3, a hard mask dielectric layer is formed on the surface of the epitaxial layer. The hard mask dielectric layer may be silicon oxide, silicon nitride, or polysilicon, and has a thickness of 2 to 4 um.

[0034] S42: coating a photoresist on the upper surface of the hard mask dielectric layer, and patterning the photoresist to form a patterned photoresist;

[0035] S43: etching the hard mask dielectric layer using an etching process according to the patterned photoresist to form a patterned hard mask dielectric layer;

[0036] S44: removing the patterned photoresist and retaining the patterned hard mask dielectric layer;

[0037] S45: performing an etching process on the epitaxial layer according to the patterned hard mask dielectric layer to form a gate trench gate;

[0038] S46: removing the patterned hard mask dielectric layer;

[0039] S47: performing a high temperature treatment process on the gate trench by using a high temperature annealing process.

[0040] Beneficial effects: The present invention optimizes the device structure, and by introducing a groove gate injection region into the trench SiC MOSFET device, it can be used to modulate the internal electric field of the device, thereby protecting the gate oxide from breakdown, and at the same time increasing the effective conduction area of ​​the device and improving the conduction capability of the device. The technical effects of the structure are as follows: 1. The groove gate injection region structure can effectively modulate the internal electric field of the device through the injection region, eliminate the electric field concentration effect at the bottom corner of the groove, shield the electric field strength in the gate oxide, avoid gate oxide breakdown, thereby preventing the device from breaking down and burning prematurely, and improving the reliability of the device; 2. The groove gate injection region structure can add two conduction paths to the device, increase the effective conduction area of ​​the device, and thereby enhance the conduction capability of the device; 3. The injection region of the groove gate injection region structure can maintain a farther distance from the device well region, thereby effectively alleviating the natural depletion effect of the column region electric field modulation structure and the well region, thereby further preventing the deterioration of the conduction performance of the device and enhancing the conduction capability of the device. The device structure and preparation method of the present invention are simple, and the effect is significant. It can realize the preparation and production of high-performance, batch-scale trench SiC MOSFET devices, and has huge market potential and broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic diagram of a process for preparing a MOSFET device according to the present invention;

[0042] Figure 2 A schematic diagram of the cross-sectional structure of a MOSFET device presented by S1 of the present invention;

[0043] Figure 3 A schematic diagram of the cross-sectional structure of a MOSFET device presented by S2 of the present invention;

[0044] Figure 4 A schematic diagram of the cross-sectional structure of a MOSFET device presented by S3 of the present invention;

[0045] Figure 5 It is a schematic diagram of the cross-sectional structure of a MOSFET device presented by S4 of the present invention;

[0046] Figure 6 It is a schematic diagram of the cross-sectional structure of a MOSFET device presented by S5 of the present invention;

[0047] Figure 7 It is a schematic diagram of the cross-sectional structure of a MOSFET device presented by S6 of the present invention;

[0048] Figure 8 It is a schematic diagram of the cross-sectional structure of a MOSFET device presented by S7 of the present invention;

[0049] Fig. 9 It is a schematic diagram of the cross-sectional structure of a MOSFET device presented by S8 of the present invention;

[0050] Fig.10 It is a schematic diagram of the cross-sectional structure of a MOSFET device presented by S9 of the present invention;

[0051] Fig.11 A schematic diagram of the cross-sectional structure of a MOSFET device presented by S10 of the present invention;

[0052] Fig.12 It is a schematic diagram of the cross-sectional structure of a MOSFET device presented by S11 of the present invention;

[0053] Fig.13 It is a schematic diagram of the cross-sectional structure of a MOSFET device presented by S31 of the present invention;

[0054] Fig.14 It is a schematic diagram of the cross-sectional structure of a MOSFET device presented by S32 of the present invention;

[0055] Fig.15 It is a schematic diagram of the cross-sectional structure of a MOSFET device presented by S33 of the present invention;

[0056] Fig.16 It is a schematic diagram of the cross-sectional structure of a MOSFET device presented by S34 of the present invention;

[0057] Fig.17 It is a schematic diagram of the cross-sectional structure of a MOSFET device presented by S35 of the present invention;

[0058] Fig.18 It is a schematic diagram of the cross-sectional structure of a MOSFET device presented by S36 of the present invention;

[0059] Fig.19 It is a schematic diagram of the cross-sectional structure of a MOSFET device presented by S37 of the present invention;

[0060] Fig. 20 It is a schematic diagram of the cross-sectional structure of the MOSFET device presented by S38 of the present invention. DETAILED DESCRIPTION

[0061] according to Fig.12As shown, the present invention provides a MOSFET device comprising: a heavily doped substrate 101 of a first doping type; a lightly doped epitaxial layer 103 of a first doping type, located on the upper surface of the substrate 101; a buffer layer located between the substrate 101 and the epitaxial layer 103; a current extension region 104 of a first doping type, located in the epitaxial layer 103; a well region 105 of a second doping type, located above the current extension region 104; a source region 106 of a first doping type, located in the well region 105; a body region 107 of a second doping type, located in the source region 106; and a well region 105 of a second doping type, located in the epitaxial layer 103. 3; the groove 108 is located at both ends of the epitaxial layer 103; the second doping type injection region 109 is located at the bottom of the groove 108; the gate trench 110 is located at the center of the epitaxial layer 103; the gate dielectric layer 111 is located in the groove 108 and the gate trench 110; the first doping type of polysilicon 112 is filled on the surface of the gate dielectric layer 111 in the gate trench 110 and the groove 108; the passivation layer 113 is located on the surface of the epitaxial layer 103 between the source electrode 117 and the gate electrode 116; the source ohmic contact layer 114 is located on the surface of the source region 106 of the first doping type and the body region 107 of the second doping type;

[0062] The drain ohmic contact layer 118 is located on the lower surface of the substrate 101 ; the gate electrode 116 is located on the upper surface of the polysilicon 112 ; the source electrode 117 is located on the upper surface of the source ohmic contact layer 114 ; and the drain electrode 119 is located on the lower surface of the drain ohmic contact layer 118 .

[0063] The first doping type is N type, and the second doping type is P type. In another preferred embodiment, the first doping type is P type, and the second doping type is N type.

[0064] The depth of the groove 108 is 1-3um, and the width is 0.5-1.5um. The depth of the gate groove 110 is 0.8-1.2um, and the width is 0.5-1.5um. The depth of the gate groove 110 is equal to or less than the depth of the recessed gate. The distance between the injection region 109 and the boundary of the groove 108 is 0-0.5um, the depth of the injection region is 0.3-1um, and the doping concentration is 1e17-1e19cm-3. The depth of the well region 105 is 0.2-1um, and the doping concentration is 1e17-1e18cm-3. The depth of the current extension region 104 is 0.1-0.5um, and the doping concentration is 1e16-1e17cm-3. The thickness of the gate dielectric layer on the sidewall of the gate groove 110 and the groove 108 is 30-60nm, and the gate dielectric layer 111 at the bottom is 20-50nm thicker than the gate dielectric layer 111 on the sidewall.

[0065] The injection region 109 is an electric field modulation structure. When the device is working in the blocking state, due to the presence of the injection region 109 at the bottom of the groove 108, the injection region 109 can shield the internal electric field of the device, and the maximum electric field peak can be adjusted from the bottom corner of the trench gate to the bottom of the injection region, thereby reducing the electric field strength at the bottom of the trench gate to solve the electric field concentration effect at the bottom of the trench gate. The reduction of the electric field strength at the bottom of the trench gate further promotes the reduction of the electric field strength in the gate dielectric layer inside the trench gate, thereby avoiding gate oxide breakdown. More importantly, compared with the columnar electric field modulation region, the structure of the trench gate injection region 109 can add two new current conduction paths, increase the effective current conduction area when the device is turned on, and improve the current carrying capacity. In addition, the trench gate injection region is farther away from the well region than the columnar electric field modulation region, which can reduce the natural depletion effect between the injection region and the well region, and further improve the current carrying capacity. The main function of the current expansion region is to provide more carriers when the device is turned on to improve the device conduction capacity. In addition, the current extension region is located between the well region and the trench gate injection region, which can also help reduce the natural depletion effect between the two.

[0066] like Figure 2-20 As shown, the present invention provides a method for preparing a MOSFET device, which comprises at least the following steps:

[0067] 1) providing a heavily doped substrate 101 of a first doping type, forming a lightly doped epitaxial layer 103 of a first doping type on an upper surface of the substrate 101, and a buffer layer 102 is provided between the substrate 101 and the epitaxial layer 103;

[0068] 2) forming a current extension region 104 of a first doping type in the epitaxial layer 103, forming a well region 105 of a second doping type in the epitaxial layer 103, forming a source region 106 of a first doping type in the well region 105, and forming a body region 107 of a second doping type in the source region 106;

[0069] 3) forming grooves 108 at both ends of the epitaxial layer 103 and forming an implantation region 109 at the bottom of the grooves 108;

[0070] 4) forming a gate trench 110 at the center of the epitaxial layer 103 obtained in step 3;

[0071] 5) forming a gate dielectric layer 111 in the gate trench 110 and the recess 108 , and filling a first doping type polysilicon 112 on the surface of the gate dielectric layer 111 ;

[0072] 6) forming a passivation layer 113 on the surface of the epitaxial layer 103 obtained in step 5, and forming a source window in the passivation layer 113;

[0073] 7) forming a source ohmic contact layer 114 in the source window;

[0074] 8) forming a gate window in the passivation layer 113 at a position corresponding to the polysilicon 112 region;

[0075] 9) forming a gate electrode 116 in the gate window and forming a source electrode 117 on the surface of the source ohmic contact layer 114;

[0076] 10) After completing step 9, thinning the bottom of the heavily doped substrate 101 of the first doping type;

[0077] 11) forming a drain ohmic contact layer 118 on the bottom surface of the thinned substrate 101 obtained in step 10, and forming a drain electrode 119 on the surface of the drain ohmic contact layer 118 .

[0078] In step 3, a groove 108 of a trench gate implantation region structure is formed in the epitaxial layer 103, and an implantation region 109 is formed at the bottom of the groove 108, including the following steps:

[0079] 3-1) After the epitaxial layer 103 of step 2 is formed, a hard mask dielectric layer 120 is formed on the surface of the epitaxial layer 103. The hard mask dielectric layer 120 is silicon oxide, silicon nitride, or polysilicon, and has a thickness of 3 to 5 um;

[0080] The hard mask dielectric layer 120 serves as a barrier layer for etching the epitaxial layer in step 3-4, that is, the epitaxial layer region not covered by the barrier layer will be etched away by the etching process to form a groove.

[0081] 3-2 coating a photoresist 121 on the upper surface of the hard mask dielectric layer 120, and patterning the photoresist 121 by using photolithography processes such as exposure, development and hardening to form a patterned photoresist 121;

[0082] It should be noted that the patterned photoresist 121 means that there is no photoresist in the area corresponding to the groove on the upper surface of the hard mask dielectric layer, and the photoresist still remains in the remaining areas.

[0083] 3-3) etching the hard mask dielectric layer 120 using an etching process according to the patterned photoresist 121 to form a patterned hard mask dielectric layer 120;

[0084] 3-4) removing the patterned photoresist 121 and retaining the patterned hard mask dielectric layer 120;

[0085] 3-5) performing an etching process on the epitaxial layer 103 to form a groove 108 according to the patterned hard mask dielectric layer 120;

[0086] 3-6) After completing step 3-5, a dielectric film layer 122 is deposited and grown on the surface of the structure. The dielectric film layer 122 can be silicon nitride, silicon oxide, or polysilicon, with a thickness of 0 to 0.5 um;

[0087] 3-7) performing a second doping type ion implantation process on the structure after step 3-6 to form an implantation region 109;

[0088] 3-8) Remove all dielectric layers from the above steps.

[0089] It should be noted that the dielectric film layer in step 3-6) has three functions: first, by adjusting the thickness of the dielectric film layer, the distance between the injection area and the recessed gate boundary can be automatically modulated to achieve the purpose of precise size control and bilateral symmetry; second, the dielectric film layer can be used as a buffer layer in the ion implantation process to buffer and reduce the implantation damage of the implanted ions to the recessed gate surface; third, the dielectric film layer is used as a shielding layer in the ion implantation process to adjust the distribution state of the implanted ions at the bottom of the recessed gate to achieve the optimal distribution state of the implanted ions in the implantation area.

[0090] In step 4, a gate trench 110 is formed in the epitaxial layer 103 obtained in step 3, including the following steps:

[0091] 4-1) forming a hard mask dielectric layer 120 on the surface of the epitaxial layer 103 completed in step 3. The hard mask dielectric layer 120 may be silicon oxide, silicon nitride, or polysilicon, and has a thickness of 2 to 4 um;

[0092] It should be noted that the dielectric layer serves as a barrier layer for etching the epitaxial layer in step 4-4, that is, the epitaxial layer 103 region not covered by the barrier layer will be etched away by the etching process to form a gate trench.

[0093] 4-2) coating a photoresist 121 on the upper surface of the hard mask dielectric layer, and patterning the photoresist using photolithography processes such as exposure, development and hardening to form a patterned photoresist 121;

[0094] It should be noted that the so-called patterned photoresist means that there is no photoresist in the area corresponding to the gate trench on the upper surface of the hard mask dielectric layer, and the photoresist 121 is still left in the other areas.

[0095] 4-3) etching the hard mask dielectric layer 120 using an etching process according to the patterned photoresist 121 to form a patterned hard mask dielectric layer 120;

[0096] 4-4) removing the patterned photoresist 121 and retaining the patterned hard mask dielectric layer 120;

[0097] 4-5) performing an etching process on the epitaxial layer 103 according to the patterned hard mask dielectric layer 120 to form a gate trench 110;

[0098] 4-6) removing the patterned hard mask dielectric layer 120;

[0099] 4-7) A high temperature annealing process is used to perform a high temperature treatment process on the gate trench 110. The temperature is 1300-1700°C, the gas composition is one or a combination of two or three of H2, SiH4, and Ar, the gas pressure is 10-30 mTorr, and the treatment time is 10-60 min.

[0100] It should be noted that the high temperature annealing process in step 4-7) performs high temperature treatment on the gate trench 110 and simultaneously performs high temperature treatment on the recess 108 formed in step 3), thereby achieving high temperature treatment of the gate trench and the recess at the same time.

[0101] It should be noted that the high-temperature annealing process for the gate groove 110 and the groove 108 has two main purposes: first, under a high-temperature environment, the gas components in step 4-7 can perform micro-etching on the surface of the gate groove 110 and the groove 108, thereby eliminating the etching damage layer of steps 4-5 and 3-5, and further improving the smoothness of the surface of the gate groove 110 and the groove 108; second, under the action of the micro-etching process, the morphology of the bottom corners of the gate groove 110 and the groove 108 can be modified to make the bottom corners become arc-shaped.

Claims

1. A MOSFET device, characterized in that: The invention comprises a substrate (101), an epitaxial layer (103) located above the substrate, a drain electrode (119) located below the substrate (101), a current extension region (104) located in the epitaxial layer (103), a well region (105) located above the current extension region (104), a source region (106) located in the well region (105), a body region (107) located in the source region (106), grooves (108) located at both ends of the epitaxial layer (103), a gate trench (110) located at the center of the epitaxial layer (103), a gate dielectric layer (111) located in the groove (108) and the gate trench (110), polysilicon (112) located on the surface of the gate dielectric layer (111), and a passivation layer (113) located on the upper surface of the epitaxial layer (103); the bottom of the groove (108) further comprises a silicon substrate (112) located on the surface of the gate dielectric layer (111), and a silicon substrate (113) located on the upper surface of the epitaxial layer (103); An injection region (109) is provided, a source ohmic contact layer (114) is provided on the upper surfaces of the source region (106) and the body region (107), a concave source window is provided on the passivation layer (113) to accommodate the source ohmic contact layer (114) so ​​that the source ohmic contact layer (114) contacts the source region (106) and the body region (107), a source electrode (117) is provided on the upper surface of the ohmic contact layer (114), the outer side and the center of the passivation layer (113) are concave to form a gate window (115), a gate electrode (116) is provided in the gate window (115), the lower surface of the gate electrode (116) contacts the polysilicon (112), a drain ohmic contact layer (118) is provided on the lower surface of the substrate (101), and the drain ohmic contact layer (118) is located between the substrate (101) and the drain electrode (119).

2. The MOSFET device according to claim 1, characterized in that A buffer layer (102) is provided between the substrate (101) and the first epitaxial layer (103).

3. The MOSFET device according to claim 1, characterized in that: The substrate (101), the epitaxial layer (103), the current extension region (104), the source region (106) and the polysilicon (112) are all of the first doping type.

4. The MOSFET device according to claim 1, characterized in that: The well region (105), the body region (107) and the implantation region (109) are all of the second doping type.

5. The MOSFET device according to claim 1, characterized in that: The groove (108) has a depth of 1 to 3 um and a width of 0.5 to 1.5 um, the gate trench (110) has a depth of 0.8 to 1.2 um and a width of 0.5 to 1.5 um, and the depth of the gate trench (110) is equal to or less than the depth of the groove (108).

6. The MOSFET device according to claim 1, characterized in that: The distance between the injection region (109) and the boundary of the groove (108) is 0-0.5 um, the depth of the injection region (109) is 0.3-1 um, and the doping concentration is 1e17-1e19 cm -3 The depth of the well region (105) is 0.2-1 um, and the doping concentration is 1e17-1e18 cm -3 The current extension region (104) has a depth of 0.1 to 0.5 um and a doping concentration of 1e16 to 1e17 cm -3 .

7. The MOSFET device according to claim 1, characterized in that: The gate dielectric layer (111) on the side walls of the gate trench (110) and the groove (108) has a thickness of 30 to 60 nm, and the gate dielectric layer (111) at the bottom is 20 to 50 nm thicker than the gate dielectric layer (111) on the side walls.

8. A method for preparing a MOSFET device according to any one of claims 1 to 7, characterized in that: The following steps are involved: S1: providing a substrate (101) of a first doping type, forming an epitaxial layer (103) of a first doping type on the upper surface of the substrate (101), and a buffer layer (102) is present between the substrate (101) and the epitaxial layer (103); S2: forming a current extension region (104) of a first doping type in the epitaxial layer, forming a well region (105) of a second doping type in the epitaxial layer (103), forming a source region (106) of a first doping type in the well region, and forming a body region (107) of a second doping type in the source region; S3: forming a groove (108) of a trench gate implantation region structure in the epitaxial layer, and forming an implantation region (109) at the bottom of the groove; S4: forming a gate trench (110) in the epitaxial layer obtained after completing step 3; S5: forming a gate dielectric layer in the gate trench (110) and the groove (108), and filling a first doping type of polysilicon (112) on the surface of the gate dielectric layer (111); S6: forming a passivation layer (113) on the surface of the epitaxial layer (103) obtained in step 5, and forming a source window in the passivation layer; S7: forming a source ohmic contact layer (114) in the source window; S8: forming a gate window (115) in the passivation layer (115) at a position corresponding to the polysilicon region; S9: forming a gate electrode (116) in the gate window (115), and forming a source electrode (117) on the surface of the source ohmic contact layer (114); S10: thinning the bottom of the first doping type substrate (101) after completing step 9; S11: forming a drain ohmic contact layer (118) on the bottom surface of the thinned substrate (101) obtained in step 10, and forming a drain electrode (119) on the lower surface of the drain ohmic contact layer (118).

9. The method for preparing a MOSFET device according to claim 8, characterized in that: In the step S3, a groove (108) of a trench gate implantation region structure is formed in the epitaxial layer, and an implantation region (109) is formed at the bottom of the groove, comprising the following steps: S31: forming a hard mask dielectric layer (120) on the surface of the epitaxial layer (103) after completing step S2, wherein the hard mask dielectric layer (120) is silicon oxide, silicon nitride or polysilicon and has a thickness of 3 to 5 um; S32: coating a photoresist on the upper surface of the first dielectric layer (120), and patterning the photoresist (121) to form a patterned photoresist (121); S33: using an etching process according to the patterned photoresist (121), etching the hard mask dielectric layer to form a patterned hard mask dielectric layer (120); S34: removing the patterned photoresist (121) and retaining the patterned hard mask dielectric layer (120); S35: performing an etching process on the epitaxial layer (103) according to the patterned hard mask dielectric layer (120) to form a groove (108); S36: after completing step S35, a dielectric film layer (122) is deposited on the surface of the structure, wherein the dielectric film layer (122) is silicon nitride, silicon oxide or polysilicon, and has a thickness of 0 to 0.5 um; S37: performing an ion implantation process of a second doping type on the structure after completing step S36 to form an implantation region (109); S38: removing all dielectric layers in the above steps.

10. A method for preparing a MOSFET device according to claim 8, characterized in that: In the step 4, a gate trench is formed in the epitaxial layer obtained after completing the step S3, comprising the following steps: S41: After completing the step S3, a hard mask dielectric layer (120) is formed on the surface of the epitaxial layer (103), wherein the hard mask dielectric layer (120) may be silicon oxide, silicon nitride, or polysilicon, and has a thickness of 2 to 4 um; S42: coating a photoresist (121) on the upper surface of the hard mask dielectric layer (120), and patterning the photoresist to form a patterned photoresist (121); S43: etching the hard mask dielectric layer using an etching process according to the patterned photoresist to form a patterned hard mask dielectric layer (120); S44: removing the patterned photoresist (121) and retaining the patterned hard mask dielectric layer (120); S45: performing an etching process on the epitaxial layer (103) according to the patterned hard mask dielectric layer (120) to form a gate trench gate (110); S46: removing the patterned hard mask dielectric layer (120); S47: performing a high temperature treatment process on the gate trench (110) using a high temperature annealing process.

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