Preparation method of vertically stacked semiconductor device and vertically stacked semiconductor device

Abstract

The invention provides a preparation method of a vertically stacked semiconductor device and the vertically stacked semiconductor device. The preparation method comprises the following steps: sequentially arranging a lower laminated structure, a middle layer and an upper laminated structure on a substrate; patterning the lower laminated structure, the middle layer, the upper laminated structure and the upper part of the substrate; forming a sacrifice gate on the substrate, wherein the sacrifice gate extends along a second direction intersected with the first direction so as to be intersected with the fins; forming a gate side wall on the side wall of the sacrificial gate; patterning the lower laminated structure, the middle layer and the upper laminated structure; selectively etching the sacrificial layer and the intermediate layer; filling a dielectric material in a space released by selective etching of the sacrificial layer and the intermediate layer in the fin; forming a lower source / drain layer connected with the exposed side surface of the channel layer in the lower laminated structure and an upper source / drain layer connected with the exposed side surface of the channel layer in the upper laminated structure; and replacing the sacrificial gate and the sacrificial layer with a gate stack.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a vertically stacked semiconductor device and the vertically stacked semiconductor device. Background Art

[0002] With the continuous development of integrated circuit manufacturing process nodes and key technologies, NS-GAA FET (Nano-SheetGate-All-Around Field-Effect Transistor) will replace the existing Fin FET (Fin Field-Effect Transistor) technology at 3nm and below nodes. Furthermore, three-dimensional stacked transistors will become the main technical route after the 1nm node. Among them, three-dimensional stacked transistors include three-dimensional stacked integrated transistors and VFET (Vertical Field-Effect Transistor, vertical channel field effect transistor). Among them, the three-dimensional stacked integrated transistor is 3DS FET, or CFET (Complementary FieldEffect Transistor, complementary field effect transistor).

[0003] The main process methods for realizing 3DS FET include two categories: one is sequential integration, and the other is self-aligned same-time (or single-time) integration. The former process method is simple, but it is limited by performance and resources; the latter process method has high integration and superior performance, but this method is complex and has many process technology challenges. Summary of the invention

[0004] In view of this, the present disclosure provides a method for preparing a vertically stacked semiconductor device and a vertically stacked semiconductor device.

[0005] According to a first aspect of the present disclosure, a method for preparing a vertically stacked semiconductor device is provided, comprising: sequentially arranging a lower stacked structure, an intermediate layer, and an upper stacked structure on a substrate, wherein the lower stacked structure and the upper stacked structure each include an alternately arranged channel layer and a sacrificial layer, wherein the sacrificial layer and the intermediate layer have an etching selectivity relative to the substrate and the channel layer; patterning the lower stacked structure, the intermediate layer, and the upper stacked structure together with the upper portion of the substrate to form a fin extending along a first direction; forming a sacrificial gate extending along a second direction intersecting the first direction on the substrate so as to intersect the fin; forming a gate spacer on the sidewall of the sacrificial gate; patterning the lower stacked structure, the intermediate layer, and the upper stacked structure using the sacrificial gate and the gate spacer as masks, so that the patterned lower stacked structure, the intermediate layer, and the upper stacked structure have side surfaces exposed in the first direction; The sacrificial layer and the intermediate layer are selectively etched through the exposed side surface, wherein, in the selective etching, the etching rate of the intermediate layer is higher than the etching rate of the sacrificial layer, so that when the selective etching is completed, the intermediate layer is removed and the sacrificial layer is retained, and the end of the retained sacrificial layer in the first direction is recessed relative to the channel layer; the dielectric material is filled in the space released by the selective etching of the sacrificial layer and the intermediate layer in the fin, wherein the portion of the dielectric material filled at the end of the sacrificial layer is used as an inner sidewall, and the portion of the dielectric material filled between the lower stack structure and the upper stack structure is used as an isolation layer between devices; a lower source / drain layer connected to the exposed side surface of the channel layer in the lower stack structure and an upper source / drain layer connected to the exposed side surface of the channel layer in the upper stack structure are formed; and the sacrificial gate and the sacrificial layer are replaced by a gate stack.

[0006] According to an embodiment of the present disclosure, the intermediate layer and the sacrificial layer are made of the same material, and have different doping element ratios to each other, so that the etching rate of the intermediate layer is higher than that of the sacrificial layer.

[0007] According to an embodiment of the present disclosure, the preparation method further includes: forming an intermediate dielectric layer covering the upper stacked structure, the upper source / drain layer and the lower source / drain layer; etching the intermediate dielectric layer to form a dielectric layer opening exposing the upper source / drain layer and the lower source / drain layer; disposing a conductive material in the dielectric layer opening to form a contact hole, wherein the contact hole in the intermediate dielectric layer enables the upper drain layer and the lower drain layer to be electrically connected to the data output terminal through the contact hole, and enables: the unpowered lower source layer that is not electrically connected to the power supply to be electrically connected to the ground terminal, and the upper source layer located directly above the unpowered lower source layer is also electrically connected to the ground terminal; or, the upper source layer located directly above the powered lower source layer that is electrically connected to the power supply is electrically connected to the bit line terminal.

[0008] According to an embodiment of the present disclosure, a shallow trench isolation member is provided next to the upper portion of the substrate; a power rail for electrically connecting to a power supply is pre-buried in the shallow trench isolation member; the above-mentioned preparation method further comprises: etching the shallow trench isolation member according to the position of the lower source layer and the position of the power rail to form an isolation member opening exposing the lower source layer and the power rail; filling the isolation member opening with a conductive material, and after filling the conductive material, closing the isolation member opening with a dielectric material, thereby forming a contact hole that electrically connects the lower source layer to the power rail.

[0009] According to an embodiment of the present disclosure, a lower source / drain layer connected to an exposed side surface of a channel layer in a lower stacked structure and an upper source / drain layer connected to an exposed side surface of a channel layer in an upper stacked structure are formed, including: forming a protective sidewall on a substrate for protecting the upper stacked structure; forming a first electrode material layer connected to the lower stacked structure in an unprotected area between the protective sidewall and the substrate; in-situ doping the first electrode material layer to obtain a lower source / drain layer; depositing a dielectric material above the lower source / drain layer to form an inter-device isolation layer that isolates the lower source / drain layer and the upper source / drain layer; removing the protective sidewall exposed outside the inter-device isolation layer; forming a second electrode material layer on the inter-device isolation layer that is connected to the upper stacked structure; in-situ doping the second electrode material layer to form an upper source / drain layer; and activating the lower source / drain layer and the upper source / drain layer.

[0010] According to a second aspect of the present disclosure, a vertically stacked semiconductor device is provided, comprising: a first field effect transistor and a second field effect transistor stacked on a substrate in a vertical direction; and an inter-device isolation layer between the first field effect transistor and the second field effect transistor, wherein the first field effect transistor and the second field effect transistor each comprise: a plurality of channel layers stacked apart from each other in the vertical direction; source / drain layers connected to the channel layers on both sides of the plurality of channel layers in the first direction; a gate stack extending in a second direction intersecting the first direction and surrounding the channel layers; and an inner sidewall between the gate stack and the source / drain layer, wherein the inner sidewalls of each of the first field effect transistor and the second field effect transistor have substantially aligned outer surfaces.

[0011] According to an embodiment of the present disclosure, the inter-device isolation layer is integrated with the adjacent inner sidewall.

[0012] According to an embodiment of the present disclosure, in a first field effect transistor, the gate stack includes a portion on an upper surface of an uppermost channel layer among multiple channel layers in the first field effect transistor, and in a second field effect transistor, the gate stack includes a portion on a lower surface of a lowermost channel layer among multiple channel layers in the second field effect transistor.

[0013] According to an embodiment of the present disclosure, the vertically stacked first field effect transistors and the second field effect transistors are multiple groups, and two groups of vertically stacked field effect transistors among the multiple groups of vertically stacked field effect transistors constitute an inverter structure. In the vertically stacked semiconductor device, the multiple inverter structures are cross-coupled with each other to form an SRAM structure.

[0014] According to an embodiment of the present disclosure, for two groups of vertically stacked field effect transistors used to form an inverter structure, the drain layers of the two groups of vertically stacked field effect transistors are shared, and the shared drain layer is electrically connected to the signal output terminal; in the two groups of vertically stacked field effect transistors, the two source layers of one group of vertically stacked field effect transistors are both electrically connected to the ground terminal, and the two source layers of the other group of vertically stacked field effect transistors are respectively electrically connected to the bit line terminal and the power rail.

[0015] According to an embodiment of the present disclosure, an intermediate layer and a sacrificial layer having etching selectivity relative to the substrate and the channel layer are arranged in the fin, and the etching rate of the intermediate layer is set to be higher than the etching rate of the sacrificial layer. Based on this, the intermediate layer and the sacrificial layer are selectively etched at the same time, until the selective etching is completed, the intermediate layer is removed, and the sacrificial layer is retained, and the end of the retained sacrificial layer in the first direction is recessed relative to the channel layer. Dielectric material is filled in the space released by the selective etching of the sacrificial layer and the intermediate layer in the fin, so as to obtain the isolation layer between devices and the inner sidewall, realize the same-time manufacturing of the isolation layer between devices and the inner sidewall, reduce the process steps, and avoid the isolation layer between devices and The inner sidewall is formed in multiple steps. On this basis, in a vertically stacked semiconductor device obtained based on the same-time manufacturing method of the isolation layer between devices and the inner sidewall, the upper source / drain layer of the field effect transistor located above and the lower source / drain layer of the field effect transistor located below are symmetrical, avoiding the unfavorable result that the volume of the field effect transistor structure located above is greater than the volume of the field effect transistor structure located below in the batch manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0017] Figure 1 The diagram schematically shows a development process of an integrated circuit according to an embodiment of the present disclosure.

[0018] Figure 2 A schematic diagram schematically shows an evolution path of an integrated circuit core transistor structure according to an embodiment of the present disclosure.

[0019] Figure 3 The schematic diagram of the sequential integration process according to the embodiment of the present disclosure is schematically shown.

[0020] Figure 4 The diagram schematically shows a self-aligned same-time integration process according to an embodiment of the present disclosure.

[0021] Figure 5 The flowchart of the method for preparing a vertically stacked semiconductor device according to an embodiment of the present disclosure is schematically shown.

[0022] Figure 6 The schematic diagram of a SRAM integrated circuit according to an embodiment of the present disclosure is schematically shown.

[0023] Figure 7 A schematic diagram of a single-layer SRAM structure according to an embodiment of the present disclosure is schematically shown.

[0024] Fig. 8A The schematic diagram of the layer structure of a vertically stacked semiconductor device according to an embodiment of the present disclosure is schematically shown.

[0025] Figure 8B The diagram schematically shows a top structure in a vertically stacked semiconductor device according to an embodiment of the present disclosure.

[0026] Figure 8C The diagram schematically shows a bottom layer structure in a vertically stacked semiconductor device according to an embodiment of the present disclosure.

[0027] Fig.9A The schematic diagram schematically shows an axial direction of a vertically stacked semiconductor device extending along a first direction according to an embodiment of the present disclosure.

[0028] Fig. 9B The schematic diagram schematically shows an axial direction of a vertically stacked semiconductor device extending along a second direction according to an embodiment of the present disclosure.

[0029] Figure 10A to Figure 10E Schematic diagrams of various axial directions of the layer structure of a vertically stacked semiconductor device according to an embodiment of the present disclosure are schematically shown.

[0030] Figure 11A to Figure 48A , Figure 11B~Figure 48B , Fig.32C , Fig.32D , Fig.48C and Fig.48D A schematic cross-sectional view along the axial direction of a vertically stacked semiconductor device according to an embodiment of the present disclosure is schematically shown.

[0031] Figure 18B' , Figure 22A' to Figure 24A' , Figure 22B'~24B' , Figure 26A' , Figure 32A' , Figure 32B' , Figure 32C' , Figure 32D' , Figure 34A' , Figure 35A' , Figure 45A' , Figure 48A' , Figure 48B' , Figure 48C' and Figure 48D' The cross-sectional view of a semiconductor device in the related art along the axial direction is schematically shown.

[0032] Fig.49 The schematic diagram of the structure of a vertically stacked semiconductor device according to an embodiment of the present disclosure is schematically shown.

[0033] Fig.50 The schematic diagram of the SRAM structure implemented based on vertically stacked semiconductor devices according to an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0034] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0035] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0036] All terms used herein, including technical and scientific terms, have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification, and should not be interpreted in an idealized or overly rigid manner.

[0037] When using expressions such as "at least one of A, B, and C, etc.", it should generally be interpreted as the meaning of the expression generally understood by those skilled in the art. For example, "a system having at least one of A, B, and C" should include but not be limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc. When using expressions such as "at least one of A, B, or C, etc.", it should generally be interpreted as the meaning of the expression generally understood by those skilled in the art. For example, "a system having at least one of A, B, or C" should include but not be limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.

[0038] It should also be noted that the directional terms mentioned in the embodiments, such as "upper", "lower", "front", "back", "left", "right", etc., are only reference directions of the drawings and are not intended to limit the scope of protection of the present disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure.

[0039] In the embodiment of the present disclosure, Figure 1 The technology development route shown is used as an example to demonstrate the development process of integrated circuits. Figure 1 In this paper, Tech Node refers to the semiconductor process node, which can be used to indicate the critical dimension that can be achieved by the process of integrated circuits. Figure 1 From the technology development route shown, it can be seen that the preparation processes of integrated circuits are sorted in descending order according to the size represented by the semiconductor process node, namely Planar 11A (i.e., planar transistor structure), Fin FET 11B, NS-GAA FET 11C, VFET 11D and StackedFET 11E. Among them, the sizes represented by the Tech Node 12A of Planar 11A are 90, 65, 45, 32, 28 and 20 from high to low, in nm; the sizes represented by the Tech Node 12B of Fin FET 11B are 14, 10, 7, 5 and 4 from high to low, in nm; the sizes represented by the Tech Node 12C of NS-GAA FET 11C are 3 and 2 from high to low, in nm; the sizes represented by the Tech Node 12D of VFET 11D and Stacked FET11E are 1 and 0.7 from high to low, in nm.

[0040] Furthermore, if Figure 2 As shown, in the evolution path of the core transistor structure of the integrated circuit, it will develop from Fin FET 201 to NS-GAA FET 202, Forksheet 203, and further to the three-dimensional stacked integrated transistor in a single chip, namely 3DS FET or CFET (Complementary Field Effect Transistor) 204, to obtain higher integration density and overall performance.

[0041] like Figure 3 and Figure 4As shown, the main process methods for realizing 3DS FET include two categories: one is sequential integration process (Sequential 3D), and the other is self-aligned monolithic integration process (Monolithic 3D). Taking two transistors stacked up and down as an example, when the two transistors are made by sequential integration process, the channel materials of the two transistors can be different from each other; when the two transistors are made by self-aligned monolithic integration process, the channel materials of the two transistors can be the same. For example, the operation of the sequential integration process may include: bonding the substrate 301 to the upper part of the bottom device 302 to obtain the middle device 303; based on the bonded substrate in the middle device, manufacturing the top device, thereby obtaining the integrated circuit 304. The self-aligned monolithic process may include growing a polysilicon layer 402 surrounding multiple channel layers directly on the fin structure 401, and then processing it to obtain the integrated circuit 403.

[0042] Based on this, the sequential integration process method is simple, but will be limited by performance and resources; the latter self-aligned same-order integration process method has high integration and superior performance, but this method is complex and has many process technology challenges.

[0043] Specifically, the advantages of sequential integration include: flexible architecture design, channel materials can be adjusted as needed, flexible connection settings between transistors, etc. The disadvantages of sequential integration are mainly reflected in: high resource consumption, limitations of the preparation process, bonding, isolation space between NPs, thermal budget and lithography alignment.

[0044] The advantages of the self-aligned same-order integration process include: low resource consumption, precise process control, such as self-aligned top and bottom devices, and narrow isolation space between NPs, etc. The disadvantages are mainly reflected in: high process difficulty, such as processes with high aspect ratios and interconnections between devices, etc.

[0045] In view of this, the present disclosure provides a method for preparing a vertically stacked semiconductor device, comprising: sequentially arranging a lower stacked structure, an intermediate layer, and an upper stacked structure on a substrate, wherein the lower stacked structure and the upper stacked structure each include an alternately arranged channel layer and a sacrificial layer, wherein the sacrificial layer and the intermediate layer have an etching selectivity relative to the substrate and the channel layer. The lower stacked structure, the intermediate layer, and the upper stacked structure are patterned together with the upper portion of the substrate to form a fin extending along a first direction. A sacrificial gate extending along a second direction intersecting the first direction and intersecting the fin is formed on the substrate. A gate sidewall is formed on the sidewall of the sacrificial gate. Using the sacrificial gate and the gate sidewall as a mask, the lower stacked structure, the intermediate layer, and the upper stacked structure are patterned, so that the patterned lower stacked structure, the intermediate layer, and the upper stacked structure have side surfaces exposed in the first direction. The sacrificial layer and the intermediate layer are selectively etched through the exposed side surface, wherein, in the selective etching, the etching rate of the intermediate layer is higher than the etching rate of the sacrificial layer, so that when the selective etching is completed, the intermediate layer is removed, while the sacrificial layer is retained, and the end of the retained sacrificial layer in the first direction is recessed relative to the channel layer. Dielectric material is filled in the space released by the selective etching of the sacrificial layer and the intermediate layer in the fin, wherein the portion of the dielectric material filled at the end of the sacrificial layer is used as an inner sidewall, and the portion of the dielectric material filled between the lower stack structure and the upper stack structure is used as an isolation layer between devices. A lower source / drain layer connected to the exposed side surface of the channel layer in the lower stack structure and an upper source / drain layer connected to the exposed side surface of the channel layer in the upper stack structure are formed. And the sacrificial gate and the sacrificial layer are replaced by a gate stack.

[0046] Figure 5 The flowchart of the method for preparing a vertically stacked semiconductor device according to an embodiment of the present disclosure is schematically shown.

[0047] like Figure 5 As shown, the method for manufacturing a vertical semiconductor device in this embodiment includes operations S501 to S509.

[0048] In operation S501 , a lower stack structure, an intermediate layer, and an upper stack structure are sequentially disposed on a substrate, wherein the lower stack structure and the upper stack structure each include alternately disposed channel layers and sacrificial layers, wherein the sacrificial layers and the intermediate layer have etching selectivity relative to the substrate and the channel layer.

[0049] In operation S502 , the lower stack structure, the middle layer, and the upper stack structure together with an upper portion of the substrate are patterned to form a fin extending in a first direction.

[0050] In operation S503 , a sacrificial gate extending in a second direction intersecting the first direction to cross the fin is formed on the substrate.

[0051] In operation S504 , a gate spacer is formed on a sidewall of the sacrificial gate.

[0052] In operation S505 , the lower stack structure, the middle layer, and the upper stack structure are patterned using the sacrificial gate and the gate spacer as masks, so that the patterned lower stack structure, the middle layer, and the upper stack structure have side surfaces exposed in the first direction.

[0053] In operation S506, the sacrificial layer and the intermediate layer are selectively etched through the exposed side surface, wherein, in the selective etching, the etching rate of the intermediate layer is higher than the etching rate of the sacrificial layer, so that when the selective etching is completed, the intermediate layer is removed and the sacrificial layer is retained, and the end of the retained sacrificial layer in the first direction is recessed relative to the channel layer.

[0054] In operation S507, a dielectric material is filled in the space released in the fin due to the selective etching of the sacrificial layer and the intermediate layer, wherein a portion of the dielectric material filled at the end of the sacrificial layer is used as an inner sidewall, and a portion of the dielectric material filled between the lower stack structure and the upper stack structure is used as an inter-device isolation layer.

[0055] In operation S508 , a lower source / drain layer connected to an exposed side surface of the channel layer in the lower stack structure and an upper source / drain layer connected to an exposed side surface of the channel layer in the upper stack structure are formed.

[0056] In operation S509 , the sacrificial gate and the sacrificial layer are replaced with a gate stack.

[0057] According to an embodiment of the present disclosure, the vertical semiconductor device prepared by the preparation method of the present disclosure can be used to implement an SRAM structure (Static Random-Access Memory). For example, a first group of field effect transistors and a second group of field effect transistors arranged in a second direction and spaced apart from each other can be provided. The first group of field effect transistors and the second group of field effect transistors each include two vertically stacked semiconductor devices. Each vertically stacked semiconductor device may include vertically stacked field effect transistors. On this basis, based on the two groups of stacked field effect transistors in the first group of field effect transistors and the two groups of stacked field effect transistors in the second group of field effect transistors, the above-mentioned SRAM structure can be implemented.

[0058] The following describes the method for preparing the vertical semiconductor device of the embodiment of the present disclosure by taking the realization of the SRAM structure as an example. It should be understood that the SRAM here is only an example, and those skilled in the art can realize other integrated circuit structures based on the vertical semiconductor device in the embodiment of the present disclosure as required.

[0059] like Figure 6As shown in Figure 1, SRAM is the core unit circuit of integrated circuits, and the continuous reduction of SRAM unit area is the main line of development of integrated circuits. The use of a three-dimensional stacked structure of transistors (3DS-FET or CFET) can greatly reduce the SRAM unit area, reducing the SRAM unit area by more than 30%. Figure 7 and Fig. 8A ,contrast Figure 7 Single-layer SRAM structure and Fig. 8A From the double-layer SRAM structure, we can see that Fig. 8A The area of ​​the realized three-dimensional stacked structure is smaller than Figure 7 The area of ​​the two-dimensional structure in . Further, Fig. 8A The three-dimensional stacked structure in can be divided into a top structure and a bottom structure, where the top structure can be implemented based on NMOS and the bottom structure can be implemented based on PMOS. Figure 8B and Figure 8C They are shown respectively Fig. 8A It should be noted that the dimensions marked in the drawings of the present disclosure are examples and are not intended to limit the actual dimensions of the staggered units in the present disclosure.

[0060] Taking SRAM as an example, combined with Fig. 10A and Fig. 10B Various axial directions of the vertically stacked semiconductor device defined in the embodiment of the present disclosure are shown. Figures 10A to 10E An example is shown Fig. 8A The axial directions of the layer structure of the vertically stacked semiconductor device for realizing SRAM are shown in FIG. XX' axial direction extends along the first direction. Y1-Y1' axial direction, Y2-Y2' axial direction, Y3-Y3' axial direction, and Y4-Y4' axial direction extend along the second direction.

[0061] The following is a cross-sectional view based on various axes during the preparation of a vertical semiconductor device, namely Figure 11A to Figure 48A , Figure 11B~Figure 48B , Fig.32C , Fig.32D , Fig.48C and Fig.48D , to explain the contents of the embodiments of the present disclosure. It should be noted that, in the various figures shown in the present disclosure, when the numbers in the title of each of the multiple figures are the same, the preparation processes corresponding to the multiple figures are the same. When the numbers in the title of each of the multiple figures are the same, but the letters are different, the preparation processes corresponding to the multiple figures are the same, and the axes corresponding to the multiple figures are different. For example, Fig.11A and Fig. 11B These are two axial cross-sectional views of the same preparation process.

[0062] Take a stacked set of field effect transistors as an example. Figure 11A to Figure 12A It is a cross-sectional view along the XX' axis during the process of preparing a vertical semiconductor device. Figure 11B to Figure 12B It is a cross-sectional view along the Y4-Y4' axis during the process of preparing a vertical semiconductor device. Figure 11A to Figure 12A ,as well as Figure 11B to Figure 12B , the material of the substrate SUB may include silicon, etc. The substrate SUB may be subjected to pretreatment operations such as well lithography, ion implantation, annealing and cleaning in sequence. Then, a lower stacked structure, an intermediate layer 103 and an upper stacked structure are sequentially arranged on the pretreated substrate SUB using an epitaxial growth process. The lower stacked structure and the upper stacked structure each include an alternating channel layer 101 and a sacrificial layer 102. Among them, the material of the sacrificial layer 102 and the intermediate layer 103 may be consistent, such as SiGe or Si, etc. The material of the channel layer 101 may be doped silicon, etc. The channel layer 101 located above the intermediate layer 103 and the channel layer 101 located below the intermediate layer 103 may have the same doping elements or different doping elements.

[0063] In the first embodiment of the present disclosure, the material of the channel layer 101 located above the middle layer 103 may be p-type doped silicon; the material of the channel layer 101 located below the middle layer 103 may be n-type doped silicon. In the second embodiment of the present disclosure, the material of the channel layer 101 located above the middle layer 103 may be n-type doped silicon; the material of the channel layer 101 located below the middle layer 103 may be p-type doped silicon. In the third embodiment of the present disclosure, the material of the channel layer 101 located above the middle layer 103 and the material of the channel layer 101 located below the middle layer 103 may both be n-type doped silicon or both be p-type doped silicon.

[0064] Figure 13A to Figure 19A It is a cross-sectional view along the XX' axis during the process of preparing a vertical semiconductor device. Figure 13B to Figure 19B It is a cross-sectional view along the Y4-Y4' axis during the process of preparing a vertical semiconductor device. Figure 13A to Figure 19A ,as well as Figure 13B to Figure 19B. The sidewall 104 can be formed by a sidewall transfer (SIT) process. The material of the sidewall 104 can be silicon nitride or the like. In the embodiment of the present disclosure, a core mold 105 can be formed on the upper stacked structure, and the core mold 105 can be patterned by a photolithography process to obtain a linear pattern extending along the X direction. Among them, the material of the core mold 105 can be polycrystalline silicon or amorphous silicon or the like. The sidewall 104 is formed in the above-mentioned area, and the patterned core mold 105 is removed after the sidewall 104 is formed, so that only the sidewall 104 remains on the stacked structure, thereby completing the preparation of the sidewall 104. On this basis, the upper stacked structure, the middle layer 103, the lower stacked structure and the substrate SUB can be etched according to the pattern of the sidewall 104 using an anisotropic etching process to form a fin extending along the first direction on the substrate SUB and a substrate etching area distributed on both sides of the fin along the first direction.

[0065] In the substrate etching area, a dielectric material 106 is deposited. Then, the dielectric material 106 is etched according to the BPR (Buried Power Rail) pattern to obtain a deep hole whose lower surface is lower than the upper surface of the lower fin formed by the substrate SUB in the fin. A conductive material whose upper surface is not higher than the upper surface of the lower fin is arranged in the deep hole to form a power rail VDD. On this basis, the deep hole filled with the conductive material is sealed with a dielectric material, and after sealing, the dielectric material 106 is etched to be lower than the upper surface of the lower fin or to be the same height as the upper surface of the lower fin to obtain a shallow trench isolation member. The dielectric material in the embodiment of the present disclosure may include silicon dioxide or silicon nitride, etc. On this basis, refer to Figure 18B' It can be seen from the schematic diagram of the method of embedding power rails in the related art that in this embodiment, the shallow trench isolation members on both sides of the fin are embedded with power rails. Compared with this technology, the above-mentioned preparation method of the present disclosure reduces the number of embedded power rails, thereby reducing the area of ​​the horizontal cross section of the vertically stacked semiconductor device prepared by the present disclosure.

[0066] Figure 20A to Figure 24A It is a cross-sectional view along the XX' axis during the process of preparing a vertical semiconductor device. Figure 20B~Figure 24B It is a cross-sectional view along the Y4-Y4' axis during the process of preparing a vertical semiconductor device. Figure 20A to Figure 24A ,as well as Figure 20B~Figure 24B, a sacrificial gate across the fin can be formed on the dielectric material 106 by using processes such as thermal oxidation, chemical vapor deposition or sputtering. The sacrificial gate includes a gate oxide layer 107, a silicon layer 108 and a mask layer 109 from bottom to top, wherein the material of the gate oxide layer 107 can be SiO2 or the like. The material of the silicon layer 108 is amorphous silicon or polycrystalline silicon. The material of the hard mask layer 109 can be oxide, carbide or organic matter or the like. On this basis, a gate sidewall 110 can be formed on the sidewall of the sacrificial gate by a sidewall formation process. The material of the gate sidewall can be SiCNO or the like. The upper stacked structure, the middle layer and the lower stacked structure can be etched according to the pattern of the sacrificial gate and the gate sidewall 110, so that the patterned lower stacked structure, the middle layer and the upper stacked structure have side surfaces exposed in the first direction.

[0067] Since the sacrificial layer 102 and the intermediate layer 103 have etching selectivity relative to the substrate SUB and the channel layer 101, the sacrificial layer 102 and the intermediate layer 103 can be selectively etched through the exposed side surface. In the selective etching, the etching rate of the intermediate layer 103 is higher than the etching rate of the sacrificial layer 102, so that when the selective etching is completed, the intermediate layer 103 is removed, and the sacrificial layer 102 is retained, and the end of the retained sacrificial layer 102 in the first direction is recessed relative to the channel layer 101. In one embodiment of the present disclosure, the intermediate layer and the sacrificial layer have the same material type, and the intermediate layer and the sacrificial layer have different doping element ratios to each other, so that the etching rate of the intermediate layer is higher than the etching rate of the sacrificial layer. Based on this, synchronous etching of the intermediate layer 103 and the sacrificial layer 102 can be achieved. For example, the etching selectivity ratio between the intermediate layer 103 and the sacrificial layer 102 is greater than 5:1. For example, the materials of the sacrificial layer 102 and the intermediate layer 103 are both Ge doped with SiGe. By setting the content of Ge doped in the sacrificial layer 102 to be different from the content of Ge doped in the intermediate layer 103, the above-mentioned selective etching can be achieved, and the etching rate of the intermediate layer is higher than the etching rate of the sacrificial layer. For example, the content of Ge doped in the intermediate layer 103 is set to be higher than the content of Ge doped in the sacrificial layer 102.

[0068] Based on this, after the middle layer 103 is etched, an opening 112 is formed, and the recess of the end of the sacrificial layer 102 in the first horizontal direction relative to the channel layer 101 is used as an opening 111. The dielectric material is filled in the space released in the fin due to the selective etching of the sacrificial layer 102 and the middle layer 103. The portion of the dielectric material filled at the end of the sacrificial layer 102 is used as an inner sidewall 113, and the portion of the dielectric material filled between the lower stack structure and the upper stack structure is used as an inter-device isolation layer 114. Among them, the inner sidewall 113 in the upper stack structure is symmetrical with the inner sidewall 113 in the lower stack structure. On this basis, refer to Figure 22A' to Figure 24A' ,as well as Figure 22B'~24B' It can be seen from the schematically shown method of etching the channel layer 101 in the related art that in this embodiment, the intermediate layer 103 is first completely etched to form an opening 112, and then the upper stacked structure is etched, and the lower stacked structure is not etched in this step. That is, in the related art, the upper stacked structure and the lower stacked structure are etched in different steps. Compared with this technology, the above-mentioned preparation method realizes the same-time manufacturing of the inner side wall 113 and the isolation layer 114 between devices, reduces the steps of the manufacturing process, and avoids the adverse result that the upper field effect transistor and the lower field effect transistor in the vertically stacked semiconductor device are not aligned in the vertical direction due to the separate preparation of the inner side wall 113 and the isolation layer 114 between devices.

[0069] Figure 25A to Figure 28A ,as well as Figure 33A to Figure 35A It is a cross-sectional view along the XX' axis during the process of preparing a vertical semiconductor device. Figure 25B to Figure 28B ,as well as Figure 33B~Figure 35B It is a cross-sectional view along the Y4-Y4' axis during the process of preparing a vertical semiconductor device. Figure 25A to Figure 28A , Figure 33A to Figure 35A , Figure 25B to Figure 28B ,as well as Figure 33B~Figure 35B , forming a lower source / drain layer 117 connected to the exposed side surface of the channel layer 101 in the lower stacked structure and an upper source / drain layer 119 connected to the exposed side surface of the channel layer 101 in the upper stacked structure, including: forming a protective sidewall 116 for protecting the upper stacked structure on the substrate SUB. In the unprotected area between the protective sidewall 116 and the substrate SUB, a first electrode material layer connected to the lower stacked structure is formed. The first electrode material layer is in-situ doped to obtain the lower source / drain layer 117. A dielectric material is deposited above the lower source / drain layer to form an inter-device isolation layer 114 that isolates the lower source / drain layer and the upper source / drain layer. The protective sidewall 116 exposed outside the inter-device isolation layer 114 is removed. A second electrode material layer connected to the upper stacked structure is formed on the inter-device isolation layer 114. The second electrode material layer is in-situ doped to form an upper source / drain layer 119. The lower source / drain layer 117 and the upper source / drain layer 119 are activated. Figure 26A'It can be seen from the setting method of the inner side wall 113 in the related art schematically shown that in the related art, when the inner side wall 113 of the lower stacking structure is set, the inner side wall 113 of the upper stacking structure has not yet been formed. That is, in this embodiment, the inner side wall 113 of the lower stacking structure and the inner side wall 113 of the upper stacking structure are formed in different steps. Compared with this embodiment, the above-mentioned preparation method realizes the same-time manufacturing of the inner side wall 113 and the isolation layer 114 between devices, reduces the steps of the manufacturing process, and avoids the adverse result that the outer side surfaces of the upper field effect transistor and the lower field effect transistor in the vertically stacked semiconductor device are not aligned in the vertical direction due to the separate preparation of the inner side wall 113 and the isolation layer 114 between devices. On this basis, further reference is made to Figure 34A' and Figure 35A' It can be seen that in the related art, since the inner sidewall 113 in the upper stacked structure and the inner sidewall 113 in the lower stacked structure are formed in different steps, the outer side surfaces of the inner sidewall 113 in the upper stacked structure of this embodiment and the inner sidewall 113 in the lower stacked structure are not aligned in the vertical direction, which causes the horizontal area of ​​the upper source / drain layer 119 to be larger than the horizontal area of ​​the lower source / drain layer 117. In the vertically stacked semiconductor device disclosed in the present invention, since the outer side surfaces of the inner sidewall 113 in the upper stacked structure and the inner sidewall 113 in the lower stacked structure are substantially aligned in the vertical direction, the horizontal cross-sectional area of ​​the upper source / drain layer 119 of the vertically stacked semiconductor device disclosed in the present invention is equal to the horizontal cross-sectional area of ​​the lower source / drain layer 117.

[0070] Specifically, a lower source / drain position defining layer 115 in contact with the channel layer 101 is formed on both sides of the channel layer 101 located under the inter-device isolation layer 114, and a protective sidewall 116 is formed on the lower source / drain position defining layer 115 by a sidewall forming process. The material of the lower source / drain position defining layer 115 may include but is not limited to aC (amorphous carbon). The method for forming the lower source / drain position defining layer 115 includes but is not limited to spin coating. For example, after depositing aC, the deposited aC may be planarized and the aC may be etched back to a position not higher than the middle of the inter-device isolation layer 114. The material of the protective sidewall 116 includes but is not limited to SiNx and the like. The protective sidewall 116 is used to protect the channel layer 101 located on the upper part of the inter-device isolation layer to prevent the source / drain from growing at both ends of the channel layer 101 of the upper device during the source / drain growth process of the lower device. In the case where the upper and lower layer devices are of different types, the source / drain materials of the upper and lower layer devices may be different.

[0071] After forming the protective sidewall 116, the lower source / drain position defining layer 115 is removed to expose the sidewall of the channel layer 101 located below the device isolation layer 114, and the source / drain material layer is epitaxially grown and in-situ doped at the position on the exposed sidewall of the channel layer 101, thereby forming a lower source / drain layer 117 connected to the lower stacked structure. Among them, the source / drain material can be SiGe or Si. A dielectric material 118 can be deposited on the lower source / drain layer 117, and the dielectric material 118 can be etched to a position not higher than the device isolation layer 114 so as to electrically isolate the source / drain layers of the upper and lower devices. The protective sidewall 116 can be selectively etched to expose the sidewall of the channel layer 101 located above the device isolation layer 114. On the exposed sidewall of the channel layer 101, the source / drain material is epitaxially grown and in-situ doped, thereby forming a source / drain layer 119 connected to the upper stacked structure. On this basis, the source / drain layer 117 and the source / drain layer 119 are activated to thereby obtain the activated source / drain layer 117 and the source / drain layer 119 .

[0072] In the disclosed embodiment, a shallow trench isolation member is provided next to the upper portion of the substrate SUB. A power rail VDD for electrically connecting to a power supply is pre-buried in the shallow trench isolation member. After depositing the dielectric material 118, the preparation method further includes: etching the shallow trench isolation member according to the position of the lower source layer and the position of the power rail VDD to form an isolation member opening exposing the lower source layer and the power rail VDD. Filling the isolation member opening with a conductive material, and sealing the isolation member opening with a dielectric material after filling the conductive material, thereby forming a contact hole that electrically connects the lower source layer to the power rail.

[0073] For example, taking the four field effect transistors in the first group of field effect transistors and the four field effect transistors in the second group of field effect transistors as an example, Figure 29A to Figure 32A It is a cross-sectional view along the XX' axis during the process of preparing a vertical semiconductor device. Figure 29B to Figure 32B It is a cross-sectional view along the Y2-Y2' axis during the process of preparing a vertical semiconductor device. Fig.32C It is a cross-sectional view along the Y1-Y1' axis during the process of preparing a vertical semiconductor device. Fig.32D It is a cross-sectional view along the Y3-Y3' axis during the process of preparing a vertical semiconductor device.

[0074] On this basis, Figure 29A to Figure 32A , Figure 29B to Figure 32B , Fig.32C and Fig.32D A schematic cross-sectional view of a structure integrating the eight field effect transistors described above is shown.

[0075] Refer to the above Figure 29A to Figure 32A , Figure 29B to Figure 32B , Fig.32C and Fig.32D After the dielectric material 118 is deposited on the lower source / drain layer 117 and the dielectric material 118 is etched to a position not higher than the inter-device isolation layer 114, the preparation method further includes: etching the dielectric material 118 and the dielectric material 106 according to the position of the lower source / drain layer 117 to form an isolation opening 128_1, an isolation opening 128_2 and an isolation opening 128_3. Each of the isolation openings 128_1, 128_2 and 128_3 exposes the power rail and the lower source / drain layer at the same time. Conductive material is deposited in the isolation openings 128_1, 128_2 and 128_3. On this basis, based on the conductive material in the isolation openings 128_1 and 128_3, a contact hole is formed to electrically connect the lower source layer to the power rail. Based on the conductive material in the isolation member opening 128_2, a contact hole connected to the lower drain layer in the first group of field effect transistors or the lower drain layer in the second group of field effect transistors is formed. Figure 32A' , Figure 32B' , Figure 32C' and Figure 32D' It can be seen from the schematic diagram of the power rails VDD in the related art that the number of power rails VDD in this embodiment is greater than that of the power rails VDD in the above-mentioned present disclosure. Therefore, the preparation method of the present disclosure reduces the area of ​​the horizontal cross section of the semiconductor device, so that the area of ​​the horizontal cross section of the vertically stacked semiconductor device of the present disclosure is smaller than the area of ​​the horizontal cross section of the semiconductor device in the related art.

[0076] Figure 36A to Figure 44A ,as well as Figure 36A to Figure 44A It is a cross-sectional view along the XX' axis during the process of preparing a vertical semiconductor device. Figure 36B to Figure 44B ,as well as Figure 36B to Figure 44B It is a cross-sectional view along the Y4-Y4' axis during the process of preparing a vertical semiconductor device. Figure 36A to Figure 44A , Figure 36A to Figure 44A , Figure 36B to Figure 44B ,as well as Figure 36B to Figure 44B , a dielectric material 120 is formed on the substrate SUB and the dielectric material 120 is planarized. The planarization can remove the mask layer 109 in the sacrificial gate and expose the silicon layer 108. The dielectric material 120, the gate sidewall 110 and the silicon layer 108 are etched to the same height. Then, the silicon layer 108 and the sacrificial layer 102 are etched back by an etch-back process, so that a cavity 121_1 exposed by etching is formed at the original position of the silicon layer 108 on the inner side of the gate sidewall 110 and the inner sidewall 113, and a cavity 121_2 exposed by etching is formed at the original position of the sacrificial layer 102.

[0077] A gate stack surrounding the channel layer 101 is sequentially formed on the inner sidewalls of the cavities 121_1 and 121_2. The gate stack includes a gate dielectric layer 122 and a P-type work function layer 123. The material of the gate dielectric layer 122 may be a high-k dielectric material, where K represents a dielectric constant. High-k dielectric materials include HfO2, HfSiO x 、HfON、HfSiON、HfAlO x 、HfLaO x 、Al2O3、ZrO2、ZrSiO x , Ta2O5 or La2O3 or a combination of the above. The material of the P-type work function layer 123 may be titanium nitride or the like. A protective layer 124 is formed on the substrate SUB, and the protective layer 124 is etched until the top surface is located between the top surface and the bottom surface of the inter-device isolation layer 114 to shield the cavity for the lower device, so that the protective layer 124 protects the P-type work function layer 123 located in the cavity below the inter-device isolation layer 114, while exposing the P-type work function layer 123 located in the cavity above the inter-device isolation layer 114.

[0078] The P-type work function layer 123 located above the inter-device isolation layer 114 is etched by using a selective etching process, while the gate dielectric layer 122 located above the inter-device isolation layer 114 is retained. Then, an N-type work function layer 125 is formed around the gate dielectric layer 122 located above the inter-device isolation layer 114. Thus, different gate stacks surrounding the channel layer 101 are formed above and below the inter-device isolation layer 114, respectively. Thus, the channel layer 101, the gate stack, and the source / drain layer 119 located above the inter-device isolation layer 114 constitute an N-type field effect transistor, and the channel layer 101, the gate stack, and the source / drain layer 117 located above the inter-device isolation layer 114 constitute a P-type field effect transistor, thereby obtaining a stacked field effect transistor.

[0079] It should be understood that the above is only one embodiment of the present disclosure, and in the preparation process of other embodiments of the present disclosure, N-type field effect transistors or P-type field effect transistors can be formed as needed by changing the doping type of the source / drain layer and forming a corresponding type of work function layer. For example, the N-type field effect transistor of the upper layer can be formed as a P-type field effect transistor, and / or the P-type field effect transistor of the lower layer can be formed as an N-type field effect transistor.

[0080] After preparing the above-mentioned N-type field effect transistor and P-type field effect transistor, the protective layer 124 is removed to release the cavity below the inter-device isolation layer 114. Then, a conductive material is deposited in all the cavities 121_1 and all the cavities 121_2 to form a conductive layer 126, thereby completing the preparation of the gate structure. The conductive material in the embodiment of the present disclosure may include tungsten, etc. After forming the conductive layer 126, the conductive layer 126 may be planarized, and a dielectric material may be deposited on the planarized conductive layer 126.

[0081] Fig.45A It is a cross-sectional view along the XX' axis during the process of preparing a vertical semiconductor device. Fig.45B It is a cross-sectional view along the Y4-Y4' axis during the process of preparing a vertical semiconductor device. Fig.45A and Fig.45B , a contact hole 127 connected to the source / drain layer 119 can be formed in the dielectric material 120. On this basis, refer to Figure 45A' It can be known that in the related art, the isolation layer 114 between devices and the channel layer 101 adjacent to the isolation layer 114 between devices are in close contact, and thus, the gate stack is not disposed between the isolation layer 114 between devices and the channel layer 101 adjacent to the isolation layer 114 between devices. In the vertical semiconductor device disclosed in the present invention, the gate stack includes a portion located below the lower surface of the bottommost channel layer 101 of the plurality of channel layers 101 in the upper stacked structure, and a portion located below the upper surface of the topmost channel layer 101 of the plurality of channel layers 101 in the lower stacked structure, and thus, the preparation method disclosed in the present invention enables the gate stack to more completely surround the channel layer 101, thereby improving the performance of the prepared semiconductor device.

[0082] Specifically, taking the four field effect transistors in the first group of field effect transistors and the four field effect transistors in the second group of field effect transistors as an example, Figure 46A to Figure 48A It is a cross-sectional view along the XX' axis during the process of preparing a vertical semiconductor device. Figure 46B~Figure 48B It is a cross-sectional view along the Y3-Y3' axis during the process of preparing a vertical semiconductor device. Fig.48C It is a cross-sectional view along the Y1-Y1' axis during the process of preparing a vertical semiconductor device. Fig.48D It is a cross-sectional view along the Y2-Y2' axis during the process of preparing a vertical semiconductor device.

[0083] On this basis, Figure 46A to Figure 48A , Figure 46B~Figure 48B , Fig.48C and Fig.48D FIG. 4 is a schematic cross-sectional view of a structure integrating the eight field effect transistors described above. Figure 46A to Figure 48A , Figure 46B~Figure 48B , Fig.48C and Fig.48D, the preparation method further includes: forming an intermediate dielectric layer covering the upper stacked structure, the upper source / drain layer and the lower source / drain layer. The intermediate dielectric layer can be composed of the above-mentioned dielectric material 120, the above-mentioned dielectric material 118 and the above-mentioned dielectric material 120. The intermediate dielectric layer is etched to form a dielectric layer opening exposing the upper source / drain layer and the lower source / drain layer. A conductive material is arranged in the dielectric layer opening to form a contact hole, wherein the contact hole in the intermediate dielectric layer enables the upper drain layer and the lower drain layer to be electrically connected to the data output terminal through the contact hole, and enables: the unpowered lower source layer that is not electrically connected to the power supply is electrically connected to the ground terminal, and the upper source layer located directly above the unpowered lower source layer is also electrically connected to the ground terminal. Alternatively, the upper source layer located directly above the powered lower source layer that is electrically connected to the power supply is electrically connected to the bit line terminal.

[0084] Specifically, the dielectric material 120 is etched on the upper surface of the dielectric material 120 until the source / drain layer 119 is exposed, thereby forming a dielectric layer opening 129_1, a dielectric layer opening 129_2, and a dielectric layer opening 129_3 located in the dielectric material 120. Among them, the dielectric layer opening 129_21 at Y3-Y3' exposes the conductive material connected to the lower drain layer of the first group of field effect transistors, and the dielectric layer opening 129_22 exposes the conductive material connected to the lower drain layer of the second group of field effect transistors. On this basis, the dielectric layer opening 129_21 is further etched so that the dielectric layer opening 129_21 simultaneously exposes the conductive material connected to the lower drain layer of the first group of field effect transistors and the upper drain layer located on the lower drain layer. And, further etching the dielectric layer opening 129_22, so that the dielectric layer opening 129_22 simultaneously exposes the conductive material connected to the lower drain layer of the second group of field effect transistors and the upper drain layer located on the lower drain layer. Based on this, the dielectric layer opening 129_21 is filled with conductive material to form a contact hole 127_21 that is simultaneously in contact with the lower drain layer and the upper drain layer in the first group of field effect transistors. The dielectric layer opening 129_22 is filled with conductive material to form a contact hole 127_22 that is simultaneously in contact with the lower drain layer and the upper drain layer in the second group of field effect transistors. Among them, the contact hole 127_21 can be electrically connected to the first data output terminal; the contact hole 127_22 can be electrically connected to the second data output terminal.

[0085] Similarly, the dielectric layer opening 129_1 includes a dielectric layer opening 129_11 and a dielectric layer opening 129_12. The dielectric layer opening 129_11 in the Y2-Y2' axial direction exposes the conductive material connected to the lower source layer of the second group of field effect transistors, and the dielectric layer opening 129_12 in the Y2-Y2' axial direction exposes the lower source layer and the upper source layer of the first group of field effect transistors. Based on this, a conductive material is filled in the dielectric layer opening 129_11 to form a contact hole 127_11; a conductive material is filled in the dielectric layer opening 129_12 to form a contact hole 127_12. The contact hole 127_11 can be electrically connected to the first bit line terminal, and the contact hole 127_12 can be electrically connected to the ground terminal.

[0086] Similarly, the dielectric layer opening 129_3 includes a dielectric layer opening 129_31 and a dielectric layer opening 129_32. The dielectric layer opening 129_31 in the Y1-Y1' axis exposes the lower source layer and the upper source layer of the first group of field effect transistors, and the dielectric layer opening 129_32 in the Y1-Y1' axis exposes the conductive material connected to the lower source layer of the second group of field effect transistors. Based on this, a conductive material is filled in the dielectric layer opening 129_31 to form a contact hole 127_31; and a conductive material is filled in the dielectric layer opening 129_32 to form a contact hole 127_32. The contact hole 127_31 can be electrically connected to the ground terminal, and the contact hole 127_32 can be electrically connected to the second bit line terminal complementary to the first bit line terminal. In this way, the vertically stacked semiconductor device of the present disclosure can be obtained. On this basis, refer to Figure 48A' , Figure 48B' , Figure 48C' and Figure 48D' It can be seen that the number of power rails VDD of the semiconductor device in the related art is greater than the number of power rails VDD of the vertically stacked semiconductor device disclosed in the present invention, and the number of contact holes connected to the power rails VDD in the related art is greater than the number of contact holes connected to the power rails in the vertically stacked semiconductor device disclosed in the present invention. Therefore, the preparation method disclosed in the present invention reduces the area of ​​the horizontal cross section of the vertically stacked semiconductor device, so that the area of ​​the horizontal cross section of the vertically stacked semiconductor device disclosed in the present invention is smaller than the area of ​​the horizontal cross section of the semiconductor device in the related art.

[0087] Based on this, the present disclosure provides an intermediate layer 103 and a sacrificial layer 102 with etching selectivity relative to the substrate SUB and the channel layer 101 in the fin, and the etching rate of the intermediate layer 103 is set to be higher than the etching rate of the sacrificial layer 102. Based on this, the intermediate layer 103 and the sacrificial layer 102 are selectively etched at the same time, until the selective etching is completed, the intermediate layer 103 is removed, and the sacrificial layer 102 is retained, and the end of the retained sacrificial layer 102 in the first direction is recessed relative to the channel layer 101. The dielectric material is filled in the space released by the selective etching of the sacrificial layer 102 and the intermediate layer 103 in the fin, so as to obtain the isolation layer 114 between devices and the inner sidewall 113, realize the same-time manufacturing of the isolation layer 114 between devices and the inner sidewall 113, reduce the process steps, and avoid the isolation layer 114 between devices and the inner sidewall 113 being formed in multiple steps. On this basis, in the vertically stacked semiconductor device manufactured by the same manufacturing method of the device isolation layer 114 and the inner sidewall 113, the upper source / drain layer 119 of the field effect transistor located above and the lower source / drain layer 117 of the field effect transistor located below are symmetrical, avoiding the unfavorable result that the volume of the field effect transistor structure located above is larger than the volume of the field effect transistor structure located below in the batch manufacturing. It should be understood that in the embodiment of the present disclosure, the dielectric material includes but is not limited to SiO2, SiN x , SiNO, SiCO, SiCNO, SiCN, ploymer, aC and other media and combinations. The method of filling the medium includes but is not limited to ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), Spin (spin), etc. And, the etching method includes but is not limited to wet etching, RIE (Reactive Ion Etching), RPS (Remote Plasma Source) etching, Chemical Dry Etch, ALE (Atomic Layer Etching), etc. The present disclosure is not limited to this, and the above-mentioned preparation method of the present disclosure can be implemented.

[0088] Fig.49 A schematic diagram of a vertically stacked semiconductor device according to an embodiment of the present disclosure is schematically shown.

[0089] like Fig.49As shown, the vertically stacked semiconductor device 4900 of this embodiment includes: a first field effect transistor 4901 and a second field effect transistor 4902 stacked on a substrate SUB in a vertical direction. And an inter-device isolation layer 114 between the first field effect transistor and the second field effect transistor, wherein the first field effect transistor and the second field effect transistor each include: a plurality of channel layers 101 stacked spaced apart from each other in the vertical direction. A source / drain layer connected to the channel layer 101 on both sides of the plurality of channel layers 101 in the first direction. A gate stack extending in a second direction intersecting the first direction and surrounding the channel layer 101. And an inner sidewall 113 between the gate stack and the source / drain layer, wherein the inner sidewall 113 of each of the first field effect transistor and the second field effect transistor has substantially aligned outer surfaces. In the embodiment of the present disclosure, the first field effect transistor 4901 and the second field effect transistor 4902 correspond to a field effect transistor composed of the above-mentioned upper stacked structure and a field effect transistor composed of the above-mentioned lower stacked structure, respectively. The source / drain layer of the first field effect transistor 4901 is the source / drain layer 119 connected to the upper stack structure. The source / drain layer of the second field effect transistor 4902 is the source / drain layer 117 connected to the lower stack structure. The gate stack surrounding the channel layer 101 corresponds to Fig.49 The gate structure G in the channel layer 101 is surrounded by the gate structure G. Fig.49 not shown in the perspective view).

[0090] According to the embodiment of the present disclosure, since the device isolation layer 114 and the adjacent inner sidewall 113 are manufactured at the same time, in the vertically stacked semiconductor device of the embodiment of the present disclosure, the device isolation layer 114 and the adjacent inner sidewall 113 are integrated.

[0091] According to an embodiment of the present disclosure, in the first field effect transistor, the gate stack includes a portion on the upper surface of the uppermost channel layer 101 among the multiple channel layers 101 in the first field effect transistor, and in the second field effect transistor, the gate stack includes a portion on the lower surface of the lowermost channel layer 101 among the multiple channel layers 101 in the second field effect transistor. Therefore, the preparation method of the present disclosure allows the gate stack to more completely surround the channel layer 101, thereby improving the performance of the prepared semiconductor device.

[0092] According to an embodiment of the present disclosure, the vertically stacked first field effect transistors and the second field effect transistors are multiple groups, and two groups of vertically stacked field effect transistors among the multiple groups of vertically stacked field effect transistors constitute an inverter structure. In the vertically stacked semiconductor device, the multiple inverter structures are cross-coupled with each other to form an SRAM structure.

[0093] According to an embodiment of the present disclosure, for two groups of vertically stacked field effect transistors used to form an inverter structure, the drain layers of the two groups of vertically stacked field effect transistors are shared, and the shared drain layer is electrically connected to the signal output terminal. In the two groups of vertically stacked field effect transistors, the two source layers of one group of vertically stacked field effect transistors are both electrically connected to the ground terminal, and the two source layers of the other group of vertically stacked field effect transistors are respectively electrically connected to the bit line terminal and the power rail.

[0094] Specifically, the following Fig.50 The structure of the vertically stacked semiconductor device of the present disclosure is described for example. Fig.50 The schematic diagram of the SRAM structure implemented based on the vertically stacked semiconductor device according to the embodiment of the present disclosure is schematically shown. Fig.50 In the embodiment of the present disclosure, the extension direction of the X-axis is defined as a first direction, the extension direction of the Y-axis is defined as a second direction intersecting the first direction, and the extension direction of the Z-axis is defined as a vertical direction. In one embodiment of the present disclosure, the first direction and the second direction may be perpendicular to each other in the same horizontal plane. The vertical direction may be a direction perpendicular to the horizontal plane.

[0095] like Fig.50 As shown, the SRAM structure 5000 of this embodiment includes: the first group of field effect transistors and the second group of field effect transistors respectively arranged along a first direction on the upper surface of a substrate SUB, and an intermediate dielectric layer surrounding the substrate SUB, the first group of field effect transistors and the second group of field effect transistors.

[0096] exist Fig.50 Each field effect transistor shown in the figure can be used as a transmission transistor or a pull-up transistor, etc. according to actual needs. Among them, the transmission transistor can be a transistor for transmitting write data from the bit line. The pull-up transistor can include a pull-up transistor and a pull-down transistor. The pull-up transistor can be a transistor for pulling up the node level. The pull-down transistor can be a transistor for pulling down the node level. And, in Fig.50 In order to avoid blocking the SRAM structure 5000, Fig.50 It should be understood that the intermediate dielectric layer in the embodiment of the present disclosure can be arranged in the SRAM structure 5000 according to the requirements.

[0097] Continue to refer Fig.50 ,exist Fig.50 Two substrates SUB arranged along the second horizontal direction are shown. On the two substrates SUB, a plurality of field effect transistors integrated into an integrated structure are respectively arranged. Based on this, for the convenience of description, in this disclosure, Fig.50The plurality of field effect transistors on the lower left substrate SUB are defined as the first group of field effect transistors, and are defined as Fig.50 In the space shown, it is located in front; and Fig.50 The transistor on the upper right substrate is defined as the second group of field effect transistors mentioned above, and its Fig.50 The space shown is located at the rear.

[0098] The following will Fig.50 The field effect transistor shown in the figure is defined as a pull transistor or a transfer transistor to facilitate understanding of the SRAM structure 5000 of the embodiment of the present disclosure. It should be understood that the following is only an example, and those skilled in the art can define the function of the field effect transistor in the SRAM structure 5000 as required.

[0099] Exemplarily, the transistor located at the upper left of the first group of field effect transistors is defined as a transmission transistor AC1; the transistor located at the lower left of the first group of field effect transistors is defined as a pull-down transistor PU1; and the transistor located at the upper right of the first group of field effect transistors is defined as a pull-down transistor PD1. Fig.50 It can be seen that the transmission transistor AC1 and the pull-down transistor PD1 are coupled through a common layer. And, based on the above content, it can be seen that the common layer of the upper layer and the common layer of the lower layer in the first group of field effect transistors are coupled through a connection structure. Based on this, the electrical connection between the transmission transistor AC1, the pull-up transistor PU1 and the pull-down transistor PD1 can be achieved. And, the common layer used for electrical connection between the transmission transistor AC1, the pull-up transistor PU1 and the pull-down transistor PD1 corresponds to the first source / drain layer of the transmission transistor AC1, the pull-up transistor PU1 and the pull-down transistor PD1. Among them, the transmission transistor AC1 can be electrically connected to the bit line end through the source layer contact hole connected to the second source / drain layer on the other side of the gate structure of the transmission transistor AC1, and the transmission transistor AC1 can be electrically connected to the word line end through the gate contact hole connected to its gate structure G. The pull-up transistor PU1 can be electrically connected to the power supply terminal through a source layer contact hole connected to the second source / drain layer on the other side of the gate structure of the pull-up transistor PU1; the pull-down transistor PD1 can be electrically connected to the ground terminal through a source layer contact hole connected to the second source / drain layer on the other side of the gate structure of the pull-down transistor PD1. Based on this, the stacked pull-up transistors in the first group of field effect transistors can be configured as an inverter, the pull-up transistor PU1 can realize the level of the pull-up common layer, and the pull-down transistor PD1 can realize the level of the pull-down common layer.

[0100] Correspondingly, the transistor located at the upper right of the second group of field effect transistors is defined as the transmission transistor AC2; the transistor located at the lower right of the second group of field effect transistors is defined as the pull-up transistor PU2; and the transistor located at the upper left of the first group of field effect transistors is defined as the pull-down transistor PD2. Fig.50 It can be seen that the transmission transistor AC2 and the pull-down transistor PU2 are coupled through a common layer. And, based on the above content, it can be seen that the common layer of the upper layer and the common layer of the lower layer in the second group of field effect transistors are coupled through a connecting structure. Based on this, the electrical connection between the transmission transistor AC2, the pull-up transistor PU2 and the pull-down transistor PD2 can be achieved. And, the common layer used for electrical connection between the transmission transistor AC2, the pull-up transistor PU2 and the pull-down transistor PD2 corresponds to the first source / drain layer of the transmission transistor AC2, the pull-up transistor PU2 and the pull-down transistor PD2 respectively. Among them, the transmission transistor AC2 can be electrically connected to the bit line end through the source layer contact hole connected to the second source / drain layer located on the other side of the gate structure of the transmission transistor AC2, and the transmission transistor AC2 can be electrically connected to the word line end through the gate contact hole connected to its gate structure G. The pull-up transistor PU2 can be electrically connected to the power supply terminal through a source layer contact hole connected to the second source / drain layer on the other side of the gate structure of the pull-up transistor PU2; the pull-down transistor PD2 can be electrically connected to the ground terminal through a source layer contact hole connected to the second source / drain layer on the other side of the gate structure of the pull-down transistor PD2. Based on this, the stacked pull-up transistors in the second group of field effect transistors can be configured as an inverter, the pull-up transistor PU2 can realize the level of the pull-up common layer, and the pull-down transistor PD2 can realize the level of the pull-down common layer.

[0101] In the embodiment of the present disclosure, the gate structures of the pull-up transistor PU1 and the pull-down transistor PD1 can be electrically connected to the common drain layer in the second group of field effect transistors through the contact hole, thereby being electrically connected to the second data output terminal; the gate structures of the pull-up transistor PU2 and the pull-down transistor PD2 can be electrically connected to the common drain layer in the first group of field effect transistors through the contact hole, thereby being electrically connected to the first data output terminal. The gate structures of the transmission transistors AC1 and AC2 can be electrically connected to the word line terminal through the contact hole, thereby realizing the SRAM structure of the present disclosure.

[0102] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. The scope of the present disclosure is defined by the attached claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A method for preparing a vertically stacked semiconductor device, comprising: A lower stacked structure, an intermediate layer and an upper stacked structure are sequentially arranged on a substrate, wherein the lower stacked structure and the upper stacked structure each include a channel layer and a sacrificial layer that are alternately arranged, wherein the sacrificial layer and the intermediate layer have an etching selectivity relative to the substrate and the channel layer; patterning the lower stacked structure, the middle layer, and the upper stacked structure together with an upper portion of the substrate to form a fin extending along a first direction; forming a sacrificial gate on the substrate, the sacrificial gate extending along a second direction intersecting the first direction so as to intersect the fin; forming a gate spacer on the sidewall of the sacrificial gate; Using the sacrificial gate and the gate spacer as masks, patterning the lower stacked structure, the middle layer and the upper stacked structure, so that the patterned lower stacked structure, the middle layer and the upper stacked structure have side surfaces exposed in the first direction; Selectively etching the sacrificial layer and the intermediate layer via the exposed side surface, wherein in the selective etching, the etching rate of the intermediate layer is higher than the etching rate of the sacrificial layer, so that when the selective etching is completed, the intermediate layer is removed, while the sacrificial layer is retained, and an end of the retained sacrificial layer in the first direction is recessed relative to the channel layer; Filling a dielectric material in a space released by selective etching of the sacrificial layer and the intermediate layer in the fin, wherein a portion of the dielectric material filled at the end of the sacrificial layer is used as an inner sidewall, and a portion of the dielectric material filled between the lower stacked structure and the upper stacked structure is used as an inter-device isolation layer; forming a lower source / drain layer in contact with an exposed side surface of the channel layer in the lower stacked structure and an upper source / drain layer in contact with an exposed side surface of the channel layer in the upper stacked structure; and The sacrificial gate and the sacrificial layer are replaced with a gate stack.

2. The method according to claim 1, wherein: The intermediate layer and the sacrificial layer are made of the same material, and the ratio of doping elements between the intermediate layer and the sacrificial layer is different, so that the etching rate of the intermediate layer is higher than the etching rate of the sacrificial layer.

3. The method according to claim 1, wherein: The method further comprises: forming an intermediate dielectric layer covering the upper stacked structure, the upper source / drain layer and the lower source / drain layer; Etching the intermediate dielectric layer to form a dielectric layer opening exposing the upper source / drain layer and the lower source / drain layer; A conductive material is disposed in the dielectric layer opening to form a contact hole, wherein the contact hole in the intermediate dielectric layer enables the upper drain layer and the lower drain layer to be electrically connected to the data output terminal through the contact hole, and enables: the unpowered lower source layer that is not electrically connected to the power supply to be electrically connected to the ground terminal, and the upper source layer directly above the unpowered lower source layer is also electrically connected to the ground terminal; or, the upper source layer directly above the powered lower source layer that is electrically connected to the power supply is electrically connected to the bit line terminal.

4. The method according to claim 3, wherein: A shallow trench isolation member is provided beside the upper portion of the substrate; a power rail for electrically connecting to the power supply is pre-buried in the shallow trench isolation member; The method further comprises: According to the position of the lower source layer and the position of the power rail, the shallow trench isolation member is etched to form an isolation member opening exposing the lower source layer and the power rail; The isolation opening is filled with a conductive material, and after being filled with the conductive material, the isolation opening is sealed with a dielectric material, thereby forming a contact hole that electrically connects the lower source layer to the power rail.

5. The method according to claim 1, wherein: The forming of a lower source / drain layer connected to an exposed side surface of the channel layer in the lower stacked structure and an upper source / drain layer connected to an exposed side surface of the channel layer in the upper stacked structure comprises: forming a protective sidewall on the substrate for protecting the upper stacked structure; forming a first electrode material layer connected to the lower stacked structure in an unprotected area between the protective sidewall and the substrate; In-situ doping the first electrode material layer to obtain the lower source / drain layer; Depositing a dielectric material over the lower source / drain layer to form an inter-device isolation layer isolating the lower source / drain layer from the upper source / drain layer; Removing the protective sidewall exposed outside the isolation layer between the devices; forming a second electrode material layer on the inter-device isolation layer and in contact with the upper stacked structure; In-situ doping the second electrode material layer to form the upper source / drain layer; The lower source / drain layer and the upper source / drain layer are activated.

6. A vertically stacked semiconductor device comprising: a first field effect transistor and a second field effect transistor stacked on the substrate in a vertical direction; as well as an inter-device isolation layer between the first field effect transistor and the second field effect transistor, Wherein, the first field effect transistor and the second field effect transistor each include: a plurality of channel layers stacked and spaced apart from each other in a vertical direction; Source / drain layers connected to the channel layers at both sides of the plurality of channel layers in the first direction; a gate stack extending in a second direction intersecting the first direction and surrounding the channel layer; and an inner sidewall between the gate stack and the source / drain layer, The inner sidewalls of the first field effect transistor and the inner sidewalls of the second field effect transistor have outer side surfaces that are substantially aligned.

7. The vertically stacked semiconductor device according to claim 6, wherein: The inter-device isolation layer is integrated with the adjacent inner sidewall.

8. The vertically stacked semiconductor device according to claim 6, wherein: In the first field effect transistor, the gate stack includes a portion on an upper surface of an uppermost channel layer among the plurality of channel layers in the first field effect transistor, In the second field effect transistor, the gate stack includes a portion on a lower surface of a lowermost channel layer among the plurality of channel layers in the second field effect transistor.

9. The vertically stacked semiconductor device according to claim 6, wherein: There are multiple groups of vertically stacked first field effect transistors and second field effect transistors, and two groups of vertically stacked field effect transistors in the multiple groups of vertically stacked field effect transistors constitute an inverter structure. In the vertically stacked semiconductor device, multiple inverter structures are cross-coupled with each other to form an SRAM structure.

10. The vertical complementary field effect transistor according to claim 9, wherein: For the two groups of vertically stacked field effect transistors used to form the inverter structure, the drain layers of the two groups of vertically stacked field effect transistors are shared, and the shared drain layer is electrically connected to the signal output terminal; in the two groups of vertically stacked field effect transistors, the two source layers of one group of vertically stacked field effect transistors are both electrically connected to the ground terminal, and the two source layers of the other group of vertically stacked field effect transistors are respectively electrically connected to the bit line terminal and the power rail.

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