Display device, method for manufacturing display device, and optical device

Abstract

The present disclosure relates to a display device, and more particularly, to a display device capable of making resonance distances different from each other according to a wavelength of light to be emitted from each pixel while simplifying a process step, a method of manufacturing the display device, and an optical device including the display device. The display device includes: a substrate; a bank disposed on the substrate and defining a plurality of emission areas; a plurality of pixel electrodes disposed in the plurality of emission regions; and at least one step electrode disposed between the pixel electrode of the at least one emission region and the substrate. In each emission region, the number of step electrodes between each pixel electrode and the substrate is different from each other.

Description

[0001] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0100047 filed in the Korean Intellectual Property Office on July 31, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a display device, and more particularly, to a display device capable of making resonance distances different from each other according to the wavelength of light to be emitted from each pixel while simplifying process steps, a method for manufacturing the display device, and an optical device including the display device. Background Art

[0003] An organic light emitting display device includes a light emitting element, for example, an organic light emitting diode, whose brightness is changed by electric current. Summary of the invention

[0004] Aspects of the present disclosure provide a display device capable of making resonance distances different from each other according to the wavelength of light to be emitted from each pixel while simplifying process steps, a method of manufacturing the display device, and an optical device including the display device.

[0005] According to an embodiment of the present disclosure, a display device includes: a substrate; a bank disposed on the substrate and defining a plurality of emission regions; a plurality of pixel electrodes disposed in the plurality of emission regions; and at least one step electrode disposed between the pixel electrode of at least one emission region and the substrate. In each emission region, the number of step electrodes between each pixel electrode and the substrate is different from each other.

[0006] In an embodiment, the number of step electrodes is the number of step electrodes stacked on different layers with an insulating film interposed therebetween in each emission region.

[0007] In an embodiment, the multiple emission regions provide light of different colors.

[0008] In an embodiment, the display device further comprises a power line connected to the at least one step electrode.

[0009] In an embodiment, at least one step electrode is a floating electrode.

[0010] In an embodiment, the display device further comprises a pixel connection electrode connected to the pixel electrode of the at least one emission area.

[0011] In an embodiment, at least one step electrode is connected to the pixel connection electrode.

[0012] In an embodiment, the display device further includes a plurality of color filters disposed to correspond to the plurality of emission areas and to provide light of different colors.

[0013] In an embodiment, each of the plurality of pixel electrodes includes: a reflective electrode disposed on the substrate; and a light-transmitting electrode disposed on the reflective electrode and connected to the reflective electrode through a contact hole of the insulating film.

[0014] In an embodiment, at least one step electrode is disposed between the reflective electrode of at least one emission region and the substrate.

[0015] In an embodiment, in each emission region, the number of step electrodes between each reflective electrode and the substrate is different from each other.

[0016] In an embodiment, in each light emitting region, the thicknesses of each light-transmitting electrode are different from each other.

[0017] In an embodiment, the display device further includes: a common electrode disposed on the plurality of light-transmitting electrodes of the plurality of pixel electrodes; and a light-providing layer disposed between the plurality of light-transmitting electrodes of the plurality of pixel electrodes and the common electrode.

[0018] In an embodiment, in each emission region, the distances between each reflective electrode and the common electrode are different from each other.

[0019] In an embodiment, the at least one step electrode comprises: a first step electrode disposed between the substrate and the reflective electrode; and a second step electrode disposed between the first step electrode and the reflective electrode.

[0020] In an embodiment, the display device also includes: a first pixel connecting electrode, which is arranged on the same layer as the first step electrode on the substrate; and a second pixel connecting electrode, which is arranged on the first pixel connecting electrode so as to be arranged on the same layer as the second step electrode, and is connected to the first pixel connecting electrode and the reflective electrode through a contact hole of the insulating film.

[0021] In an embodiment, the first step electrode is connected to the first pixel connection electrode.

[0022] In an embodiment, the first step electrode is integrated with the first pixel connection electrode.

[0023] In an embodiment, the second step electrode is connected to the second pixel connection electrode.

[0024] In an embodiment, the second step electrode is integrated with the second pixel connection electrode.

[0025] In an embodiment, the second step electrode is connected to the first step electrode through a contact hole of the insulating film.

[0026] In an embodiment, the first step electrode is connected to another first step electrode disposed in another emission region.

[0027] According to an embodiment of the present disclosure, a display device includes: a substrate; a bank disposed on the substrate and defining a plurality of emission regions; a plurality of pixel electrodes disposed in the plurality of emission regions; and at least one step electrode overlapped with the pixel electrode of at least one emission region. The number of step electrodes in each emission region is different from each other.

[0028] In an embodiment, the number of step electrodes is the number of step electrodes stacked on different layers with an insulating film interposed therebetween in each emission region.

[0029] In an embodiment, the multiple emission regions provide light of different colors.

[0030] In an embodiment, the display device further comprises a power line connected to the at least one step electrode.

[0031] In an embodiment, at least one step electrode is a floating electrode.

[0032] In an embodiment, the display device further comprises a pixel connection electrode connected to the pixel electrode of the at least one emission area.

[0033] In an embodiment, at least one step electrode is connected to the pixel connection electrode.

[0034] According to an embodiment of the present disclosure, a method for manufacturing a display device includes the following steps: preparing a substrate; forming a different number of step electrodes in multiple emission regions on the substrate; forming a first insulating film on the step electrodes; and forming a plurality of pixel electrodes on the first insulating film in a manner overlapping with at least one of the step electrodes.

[0035] In an embodiment, the number of step electrodes is the number of step electrodes stacked on different layers with an insulating film interposed therebetween in each emission region.

[0036] In an embodiment, the multiple emission regions provide light of different colors.

[0037] In an embodiment, the step of forming a plurality of pixel electrodes includes: forming a plurality of reflective electrodes on a first insulating film in a manner overlapping with at least one of the step electrodes; forming a second insulating film on the plurality of reflective electrodes; forming a plurality of contact holes in the second insulating film; forming a light-transmitting material layer on the second insulating film in a manner overlapping with and connected to the plurality of reflective electrodes; planarizing the light-transmitting material layer; and forming a plurality of light-transmitting electrodes respectively connected to the plurality of reflective electrodes by patterning the light-transmitting material layer.

[0038] In an embodiment, the step of planarizing the light-transmitting material layer is performed by chemical mechanical polishing.

[0039] In an embodiment, the manufacturing method further includes forming a plurality of pixel connection electrodes, which are respectively connected to the plurality of pixel electrodes and are disposed in a layer different from the pixel electrodes with an insulating film interposed between the pixel electrodes and the pixel connection electrodes.

[0040] In the embodiment, among the step electrode and the plurality of pixel connection electrodes, the step electrode and the pixel connection electrode provided at the same layer are connected to each other.

[0041] According to an embodiment of the present disclosure, an optical device includes: a display device; and an optical path changing member, which is disposed on the display device. The display device includes: a substrate; a levee, which is disposed on the substrate and defines a plurality of emission regions; a plurality of pixel electrodes, which are disposed in the plurality of emission regions; and at least one step electrode, which is disposed between the pixel electrode of at least one emission region and the substrate. In each emission region, the number of step electrodes between each pixel electrode and the substrate is different from each other.

[0042] By using a display device, a manufacturing method of a display device, and an optical device including a display device according to the present disclosure, by stacking step electrodes made of the same material as the material of the pixel connection electrode in different numbers for each pixel, the resonance distance for each pixel can be adjusted to be different from each other. Therefore, it is possible to increase and / or optimize the microcavity (or film resonance) effect on light according to the wavelength of light to be emitted from each pixel and the resonance distance, resonance order, etc. corresponding to the wavelength while simplifying the process steps.

[0043] The effects of the present disclosure are not limited to the above-described effects, and other effects not described here will become apparent to those skilled in the art through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the attached drawings.

[0045] Figure 1 is a schematic perspective view of an electronic device according to an exemplary embodiment.

[0046] Figure 2 is a perspective view illustrating a display device included in an electronic device according to an exemplary embodiment.

[0047] Figure 3 Viewed from the side Figure 2 A cross-sectional view of a display device.

[0048] Figure 4 is a plan view illustrating a display layer of a display device according to an exemplary embodiment.

[0049] Figure 5is a plan view illustrating a display layer of a display device according to an exemplary embodiment.

[0050] Figure 6 is a plan view of a first step electrode, a second step electrode, and a pixel electrode provided in a display area of ​​a display device according to an exemplary embodiment.

[0051] Figure 7 yes Figure 6 Plan view of the first step electrode.

[0052] Figure 8 yes Figure 6 Plan view of the second step electrode.

[0053] Fig. 9 yes Figure 6 A plan view of a pixel electrode.

[0054] Fig.10 It is along Figure 6 1 is a cross-sectional view of a display device according to an exemplary embodiment taken along line II′.

[0055] Fig.11 It is along Figure 6 1 is a cross-sectional view of a display device according to an exemplary embodiment taken along line II′.

[0056] Fig.12 It is along Figure 6 1 is a cross-sectional view of a display device according to an exemplary embodiment taken along line II′.

[0057] Fig.13 It is along Figure 6 1 is a cross-sectional view of a display device according to an exemplary embodiment taken along line II′.

[0058] Fig.14 It is along Figure 6 1 is a cross-sectional view of a display device according to an exemplary embodiment taken along line II′.

[0059] Fig.15 It is along Figure 6 1 is a cross-sectional view of a display device according to an exemplary embodiment taken along line II′.

[0060] Fig.16 yes Fig.15 A plan view of a first-first step electrode, a first pixel connecting electrode, and a first-second step electrode.

[0061] Fig.17 It is along Figure 6 1 is a cross-sectional view of a display device according to an exemplary embodiment taken along line II′.

[0062] Fig.18 It is along Figure 6 1 is a cross-sectional view of a display device according to an exemplary embodiment taken along line II′.

[0063] Fig.19 It is along Figure 6 1 is a cross-sectional view of a display device according to an exemplary embodiment taken along line II′.

[0064] Fig. 20 It is along Figure 6 1 is a cross-sectional view of a display device according to an exemplary embodiment taken along line II′.

[0065] Fig.21 is a cross-sectional view illustrating a structure of a light emitting element according to an exemplary embodiment.

[0066] Fig. 22 , Fig.23 , Fig.24 and Fig.25 is a cross-sectional view illustrating a structure of a light emitting element according to an exemplary embodiment.

[0067] Fig.26 It is shown Fig.24 A cross-sectional view of an example of an organic light emitting diode.

[0068] Fig. 27 It is shown Fig.25 A cross-sectional view of an example of an organic light emitting diode.

[0069] Fig.28 , Fig.29 , Fig.30 , Fig.31 , Fig.32 , Fig.33 , Fig.34 , Fig.35 and Fig.36 are cross-sectional views for describing processes of a method of manufacturing a display device according to an exemplary embodiment.

[0070] Fig.37 is an exploded perspective view illustrating a display device according to an exemplary embodiment.

[0071] Fig.38 It is shown Fig.37 Layout diagram of an example of a display panel shown in .

[0072] Fig.39 is a block diagram illustrating a display device according to an exemplary embodiment.

[0073] Fig.40 is an equivalent circuit diagram of a first pixel according to an exemplary embodiment.

[0074] Fig.41is a layout diagram showing pixels of a display area according to an exemplary embodiment.

[0075] Fig.42 It is shown along Fig.41 A cross-sectional view of an example of a display device taken along line AA′.

[0076] Fig.43 is a perspective view illustrating a head mounted display device according to an exemplary embodiment.

[0077] Fig.44 It is shown Fig.43 An exploded perspective view of an example of a head mounted display device.

[0078] Fig.45 is a perspective view illustrating a head mounted display device according to an exemplary embodiment. DETAILED DESCRIPTION

[0079] The inventive concept will now be described more fully below with reference to the accompanying drawings in which embodiments are shown. However, the inventive concept may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete, and these embodiments will fully convey the scope of the inventive concept to those skilled in the art.

[0080] It will also be understood that when a layer is referred to as being "on" another layer or substrate, the layer may be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals refer to like components throughout the specification. In the drawings, the thickness of layers and regions are exaggerated for clarity.

[0081] Although the terms "first", "second", etc. can be used here to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish an element from another. Therefore, without departing from the teaching of one or more embodiments, the first element discussed below can be referred to as the second element. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. can also be used here to distinguish elements of different categories or sets. For simplicity, the terms "first", "second", etc. can respectively represent "first category (or first set)", "second category (or second set)", etc.

[0082] The features of the various embodiments of the present disclosure may be combined in part or in whole. As will be clearly understood by those skilled in the art, various interactions and operations are technically possible. The various embodiments may be practiced individually or in combination.

[0083] Hereinafter, specific exemplary embodiments will be described with reference to the accompanying drawings.

[0084] Figure 1 is a schematic perspective view of an electronic device 1 according to an exemplary embodiment.

[0085] Reference Figure 1 , the electronic device 1 displays a moving image or a still image. The electronic device 1 may refer to all electronic devices that provide a display screen. For example, a television, a laptop computer, a monitor, a billboard, an Internet of Things (IoT) device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, a game console, a digital camera, a video camera, etc. that provide a display screen may be included in the electronic device 1.

[0086] The electronic device 1 may include a display device 10 (see Figure 2 ). Examples of the display device 10 may include an inorganic light emitting diode display device, an organic light emitting display device, a quantum dot light emitting display device, a plasma display device, a field emission display device, etc. Hereinafter, a case where an organic light emitting diode display device is applied as an example of the display device 10 will be described by way of example, but the present disclosure is not limited thereto, and if applicable, the same technical spirit may be applied to other display devices.

[0087] The shape of the electronic device 1 may be modified in various ways. For example, the electronic device 1 may have a shape such as a rectangular shape with a width greater than a length, a rectangular shape with a length greater than a width, a square shape, a quadrilateral shape with rounded corners (vertices), other polygonal shapes, or a circular shape. The shape of the display area DA of the electronic device 1 may also be similar to the overall shape of the electronic device 1. Figure 1 , the electronic device 1 having a rectangular shape having a large length in the second direction DR2 is shown.

[0088] The electronic device 1 may include a display area DA and a non-display area NDA. The display area DA is an area where a picture can be displayed, and the non-display area NDA is an area where a picture is not displayed. The display area DA may also be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DA may substantially occupy the center of the electronic device 1.

[0089] The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The second display area DA2 and the third display area DA3 may be areas in which components for adding various functions to the electronic device 1 are disposed, and may correspond to component areas.

[0090] Figure 2is a perspective view illustrating a display device 10 included in the electronic device 1 according to an exemplary embodiment.

[0091] Reference Figure 1 and Figure 2 According to an exemplary embodiment, the electronic device 1 may include a display device 10. The display device 10 may provide a screen displayed by the electronic device 1. The display device 10 may have a shape similar to that of the electronic device 1 in a plan view. For example, the display device 10 may have a shape similar to a rectangular shape having short sides in a first direction DR1 and long sides in a second direction DR2. The corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be rounded with a certain curvature, but is not limited thereto, and may also be a right angle. The shape of the display device 10 in a plan view is not limited to a quadrilateral, and may be a shape similar to other polygons, a circle, or an ellipse.

[0092] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , and a touch driver 400 .

[0093] The display panel 100 may include a main area MA and a sub area SBA.

[0094] The main area MA may include a display area DA including pixels displaying an image and a non-display area NDA disposed around the display area DA. The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The display area DA may emit light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining film defining an emission area or an opening area, and a self-luminous element.

[0095] For example, the self-luminous element may include at least one of an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0096] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver (not shown) supplying a gate signal to a gate line and a fan-out line (not shown) connecting the display driver 200 and the display area DA to each other.

[0097] The sub-region SBA may be a region extending from one side of the main region MA. The sub-region SBA may include a flexible material that can be bent, folded, and curled. For example, when the sub-region SBA is bent, the sub-region SBA may overlap with the main region MA in the thickness direction (third direction DR3). The sub-region SBA may include a display driver 200 and a pad portion connected to the circuit board 300. In an exemplary embodiment, the sub-region SBA may be omitted, and the display driver 200 and the pad portion may be disposed in the non-display area NDA.

[0098] The display driver 200 may output a signal and a voltage for driving the display panel 100. The display driver 200 may supply a data voltage to a data line. The display driver 200 may supply a source voltage to a power line and a gate control signal to a gate driver. The display driver 200 may be formed as an integrated circuit (IC) and mounted on the display panel 100 in a chip on glass (COG) manner, a chip on plastic (COP) manner, or an ultrasonic bonding manner. As an example, the display driver 200 may be disposed in a sub-region SBA and may overlap with the main region MA in a thickness direction by bending of the sub-region SBA. As another example, the display driver 200 may be mounted on a circuit board 300.

[0099] The circuit board 300 may be attached to the pad portion of the display panel 100 using an anisotropic conductive film (ACF). Leads of the circuit board 300 may be electrically connected to the pad portion of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0100] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be connected to the touch sensing unit of the display panel 100. The touch driver 400 may supply a touch drive signal to a plurality of touch electrodes of the touch sensing unit and sense the amount of change in capacitance between the plurality of touch electrodes. For example, the touch drive signal may be a pulse signal having a predetermined frequency. The touch driver 400 may determine whether an input has occurred based on the amount of change in capacitance between the plurality of touch electrodes and calculate the input coordinates. The touch driver 400 may be formed as an integrated circuit (IC).

[0101] Figure 3 Viewed from the side Figure 2 10 is a cross-sectional view of a display device 10.

[0102] Reference Figure 3 , the display panel 100 may include a display layer DU and a color filter layer CFL. The display layer DU may include a substrate SUB, a transistor layer TRL, a light emitting element layer EMTL, and an encapsulation layer ENC.

[0103] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, and curled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. In an exemplary embodiment, the substrate SUB may include a glass material or a metal material. In an exemplary embodiment, the substrate SUB may be a silicon substrate, a germanium substrate, or a silicon germanium substrate.

[0104] The transistor layer TRL may be disposed on the substrate SUB, but it is understood that Fig.10 As shown in , at least a portion of the substrate SUB may also be interpreted as being included in the transistor layer TRL. The transistor layer TRL may include a plurality of transistors constituting a pixel circuit of a pixel. The transistor layer TRL may also include a gate line, a data line, a power line, a gate control line, a fan-out line connecting the display driver 200 and the data line to each other, and a lead connecting the display driver 200 and the pad portion to each other. Each of the transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when a gate driver is formed on one side of a non-display area NDA of the display panel 100, the gate driver may include a transistor.

[0105] The transistor layer TRL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The transistor, gate line, data line, and power line of each pixel of the transistor layer TRL may be disposed in the display area DA. The gate control line and fan-out line of the transistor layer TRL may be disposed in the non-display area NDA. The lead line of the transistor layer TRL may be disposed in the sub-area SBA.

[0106] The light emitting element layer EMTL may be disposed on the transistor layer TRL. The light emitting element layer EMTL may include a plurality of light emitting elements and a pixel defining film defining a pixel, each light emitting element including a first electrode, a second electrode and a light emitting layer to emit light. The plurality of light emitting elements of the light emitting element layer EMTL may be disposed in the display area DA.

[0107] In an exemplary embodiment, the light emitting layer may be an organic light emitting layer including an organic material. The light emitting layer may include a hole transport layer, an organic light emitting layer, and an electron transport layer. When the first electrode receives a voltage through the transistor of the transistor layer TRL and the second electrode receives a cathode voltage, holes and electrons may move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and may be combined with each other in the organic light emitting layer to emit light.

[0108] In an exemplary embodiment, the light emitting element may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0109] The encapsulation layer ENC may cover the upper surface and the side surface of the light emitting element layer EMTL and may protect the light emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic film and at least one organic film for encapsulating the light emitting element layer EMTL.

[0110] Despite Figure 3 Although not shown in the figure, in an exemplary embodiment, a touch layer may also be provided on the encapsulation layer ENC. The touch layer may include a plurality of touch electrodes for sensing the touch of a user in a capacitive manner and a touch line connecting the plurality of touch electrodes and a touch driver to each other. For example, the touch layer may sense the touch of a user in a mutual capacitance manner or a self-capacitance manner. In an exemplary embodiment, the touch layer may be provided on a separate substrate provided on the display layer DU. In this case, the substrate supporting the touch layer may be a base member of the encapsulated display layer DU.

[0111] The color filter layer CFL may be disposed on the encapsulation layer ENC. The color filter layer CFL may include a plurality of color filters each corresponding to a plurality of emission regions. Each of the color filters may selectively transmit light of a specific wavelength and block or absorb light of other wavelengths. The color filter layer CFL may absorb some of the light introduced from the outside of the display device 10 to reduce reflected light caused by external light. Therefore, the color filter layer CFL may prevent color distortion caused by external light reflection.

[0112] Since the color filter layer CFL is directly disposed on the encapsulation layer ENC, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively small.

[0113] In some exemplary embodiments, the display device 10 may further include an optical device 500. The optical device 500 may be disposed in the second display area DA2 or the third display area DA3. The optical device 500 may emit or receive light in an infrared band, an ultraviolet band, and a visible light band. For example, the optical device 500 may be an optical sensor (such as a proximity sensor, an illumination sensor), a camera sensor, or an image sensor that senses light incident on the display device 10.

[0114] At the same time, when the sub-area SBA is bent, as Figure 3 As shown in FIG. 8 , a protection layer 800 may also be disposed on the bent portion of the sub-area SBA.

[0115] Figure 4 is a plan view illustrating a display layer DU of a display device 10 according to an exemplary embodiment.

[0116] Reference Figure 4 , the display layer DU may include a display area DA and a non-display area NDA.

[0117] The display area DA may be disposed at the center of the display panel 100. A plurality of pixels PX, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of power lines VL may be disposed in the display area DA. Each of the plurality of pixels PX may be defined as a minimum unit emitting light.

[0118] The plurality of gate lines GL may supply the plurality of pixels PX with gate signals received from the gate driver 210. The plurality of gate lines GL may extend in a first direction DR1 and may be spaced apart from each other in a second direction DR2 crossing the first direction DR1.

[0119] The plurality of data lines DL may supply the plurality of pixels PX with data voltages received from the display driver 200. The plurality of data lines DL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0120] The plurality of power lines VL may supply a source voltage received from the display driver 200 to the plurality of pixels PX. Here, the source voltage may be at least one of a driving voltage, an initialization voltage, a reference voltage, and a common voltage. The plurality of power lines VL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0121] The non-display area NDA may surround the display area DA. The gate driver 210, the fan-out line FOL, and the gate control line (or control scan line) GCL may be disposed in the non-display area NDA. The gate driver 210 may generate a plurality of gate signals based on the gate control signal, and may sequentially supply the plurality of gate signals to the plurality of gate lines GL according to a set order.

[0122] The fan-out line FOL may extend from the display driver 200 to the display area DA. The fan-out line FOL may supply a data voltage received from the display driver 200 to the plurality of data lines DL.

[0123] The gate control line GCL may extend from the display driver 200 to the gate driver 210. The gate control line GCL may supply the gate driver 210 with a gate control signal received from the display driver 200.

[0124] The sub area SBA may include the display driver 200 , the pad area PA, and first and second touch pad areas TPA1 and TPA2 .

[0125] The display driver 200 may output signals and voltages for driving the display panel 100 to the fan-out lines FOL. The display driver 200 may supply data voltages to the data lines DL through the fan-out lines FOL. The data voltages may be supplied to a plurality of pixels PX, and the brightness of the plurality of pixels PX may be controlled. The display driver 200 may supply gate control signals to the gate driver 210 through the gate control lines GCL.

[0126] The pad area PA, the first touch pad area TPA1, and the second touch pad area TPA2 may be disposed at an edge of the sub-area SBA. The pad area PA, the first touch pad area TPA1, and the second touch pad area TPA2 may be electrically connected to the circuit board 300 using a material such as an anisotropic conductive film or a self-assembled anisotropic conductive paste (SAP).

[0127] The pad area PA may include a plurality of display pad portions DP. The plurality of display pad portions DP may be connected to a graphic system through a circuit board 300. The plurality of display pad portions DP may be connected to the circuit board 300 to receive digital video data, and may supply the digital video data to the display driver 200.

[0128] Figure 5 is a plan view illustrating a display layer DU of a display device 10 according to an exemplary embodiment.

[0129] Reference Figure 5 , the external power lines EVDL and EVSL may be disposed in the non-display area NDA of the display layer DU. The external power lines EVDL and EVSL may include, for example, an external driving voltage line EVDL and an external common voltage line EVSL.

[0130] The external drive voltage line EVDL may be connected to the power line VL of the display area DA. For example, the external drive voltage line EVDL may be connected to the drive voltage line VDL of the display area DA. In other words, the drive voltage line VDL of the display area DA may extend to the non-display area NDA to be connected to the external drive voltage line EVDL. The external drive voltage line EVDL may transmit a drive voltage. The drive voltage from the external drive voltage line EVDL may be supplied to the drive voltage line VDL of the display area DA, and the drive voltage from the drive voltage line VDL may be supplied to the pixel PX. The external drive voltage line EVDL may be disposed in the non-display area NDA to surround the display area DA and the external common voltage line EVSL. The external drive voltage line EVDL may have a ring shape surrounding the display area DA and the external common voltage line EVSL.

[0131] The external common voltage line EVSL may be connected to the power line VL of the display area DA. For example, the external common voltage line EVSL may be connected to the common voltage line VSL of the display area DA. In other words, the common voltage line VSL of the display area DA may extend to the non-display area NDA to be connected to the external common voltage line EVSL. The external common voltage line EVSL may transmit a common voltage. The common voltage from the external common voltage line EVSL may be provided to the common voltage line VSL of the display area DA, and the common voltage from the common voltage line VSL may be provided to the pixel PX. The external common voltage line EVSL may be disposed in the non-display area NDA to surround the display area DA. The external common voltage line EVSL may have a ring shape surrounding the display area DA.

[0132] Figure 6 1 is a plan view of a first step electrode, a second step electrode STE2, and a pixel electrode disposed in a display area DA of a display device 10 according to an exemplary embodiment. Figure 7 yes Figure 6 Plan view of the first step electrode. Figure 8 yes Figure 6 FIG. 1 is a plan view of a second step electrode STE2. Fig. 9 yes Figure 6 A plan view of a pixel electrode. Fig.10 It is along Figure 6 1 is a cross-sectional view of a display device 10 according to an exemplary embodiment taken along line II′.

[0133] like Figure 6 and Fig. 9 As shown in FIG. 1 , one unit pixel UPX may include a first pixel electrode PE1 , a second pixel electrode PE2 , and a third pixel electrode PE3 disposed adjacent to each other.

[0134] The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be disposed adjacent to each other. For example, the first pixel electrode PE1 and the second pixel electrode PE2 may be disposed adjacent to each other in the first direction DR1, the second pixel electrode PE2 and the third pixel electrode PE3 may be disposed adjacent to each other in the second direction DR2, and the third pixel electrode PE3 and the first pixel electrode PE1 may be disposed adjacent to each other in the second direction DR2.

[0135] A portion of the first pixel electrode PE1 (e.g., an edge of the first pixel electrode PE1), a portion of the second pixel electrode PE2 (e.g., an edge of the second pixel electrode PE2), and a portion of the third pixel electrode PE3 (e.g., an edge of the third pixel electrode PE3) may be formed by a bank PDL (see FIG. 1 ) to be described later. Fig.10In other words, a portion of the first pixel electrode PE1 (e.g., an edge of the first pixel electrode PE1), a portion of the second pixel electrode PE2 (e.g., an edge of the second pixel electrode PE2), and a portion of the third pixel electrode PE3 (e.g., an edge of the third pixel electrode PE3) may overlap with the bank PDL.

[0136] The bank PDL may include a plurality of opening areas (hereinafter, referred to as emission areas) therethrough, and such emission areas EA1, EA2, and EA3 may be provided to correspond to the above-mentioned pixel electrodes PE1, PE2, and PE3, respectively. For example, the first emission area EA1 of the bank PDL may overlap with an area of ​​the first pixel electrode PE1 except for an edge of the first pixel electrode PE1, the second emission area EA2 of the bank PDL may overlap with an area of ​​the second pixel electrode PE2 except for an edge of the second pixel electrode PE2, and the third emission area EA3 of the bank PDL may overlap with an area of ​​the third pixel electrode PE3 except for an edge of the third pixel electrode PE3.

[0137] One unit pixel UPX may include a first pixel PX1, a second pixel PX2, and a third pixel PX3 providing light of different colors. The first pixel electrode PE1 may be a component included in the first pixel PX1, the second pixel electrode PE2 may be a component included in the second pixel PX2, and the third pixel electrode PE3 may be a component included in the third pixel PX3.

[0138] The first pixel PX1 may provide light through the first emission area EA1, the second pixel PX2 may provide light through the second emission area EA2, and the third pixel PX3 may provide light through the third emission area EA3.

[0139] Reference Fig.10 , the display device 10 may include a transistor layer TRL, a light emitting element layer EMTL, an encapsulation layer ENC, and a color filter layer CFL.

[0140] The substrate SUB may be, for example, a silicon substrate, a germanium substrate, or a silicon germanium substrate. The substrate SUB may be a substrate doped with first type impurities. Figure 3 The substrate SUB shown in FIG. Fig.10 As shown in , at least a portion of the substrate SUB may be included in the transistor layer TRL.

[0141] The well region W may be disposed on the substrate SUB (or inside the substrate SUB). The well region W may be a region doped with second type impurities. The second type impurities may be different from the first type impurities described above. For example, when the first type impurities are p-type impurities, the second type impurities may be n-type impurities. On the other hand, when the first type impurities are n-type impurities, the second type impurities may be p-type impurities.

[0142] The source region S, drain region D and channel region CH of the transistor TR may be arranged in the well region W. For example, the source region S (or source electrode) and drain region D (or drain electrode) of the transistor TR may be arranged in the well region W. Each of the source region S and the drain region D may be a region doped with the above-mentioned first type impurities. The gate electrode G of the transistor TR may overlap with the well region W and intersect with the well region W. In a plan view, the well region W intersecting with the gate electrode G may be defined as two regions, the source region S may be arranged in any one of the two regions, and the drain region D may be arranged in the other of the two regions. In other words, in the well region W, the source region S and the drain region D may be respectively arranged on both sides of the gate electrode G and the gate electrode G is placed between the source region S and the drain region D. The channel region CH of the transistor may be arranged in the region of the well region W overlapping with the gate electrode G.

[0143] Meanwhile, the source region S may include a first low-concentration impurity region having a relatively lower impurity concentration than other portions of the source region S. In other words, a portion of the source region S may include impurities having a lower concentration than other portions of the source region S. The drain region D may include a second low-concentration impurity region having a relatively lower impurity concentration than other portions of the drain region D. In other words, a portion of the drain region D may include impurities having a lower concentration than other portions of the drain region D.

[0144] The first low-concentration impurity region and the second low-concentration impurity region may be disposed close to the channel region CH of the transistor TR. For example, the first low-concentration impurity region may be disposed close to the channel region CH to overlap with the first spacer disposed on one side of the gate electrode G, and the second low-concentration impurity region may be disposed close to the channel region CH to overlap with the second spacer disposed on the other side of the gate electrode G. In this way, the distance between the high-concentration impurity region of the source region S and the high-concentration impurity region of the drain region D may be increased by the first low-concentration impurity region and the second low-concentration impurity region, and as the distance increases, the length of the channel region CH may eventually increase. Therefore, punch-through and hot carrier phenomena caused by a short channel may be prevented.

[0145] The first interlayer insulating film VA1 may be disposed on the substrate SUB. Here, the first interlayer insulating film VA1 may include a plurality of insulating films sequentially stacked along the third direction DR3. Metal layers may be disposed between the corresponding insulating films. These metal layers may include, for example, capacitor electrodes, the gate lines and data lines described above, and the like.

[0146] The first pixel connection electrode PCE1, the first-first step electrode STE1-1, and the first-second step electrode STE1-2 may be disposed on the first interlayer insulating film VA1. The first pixel connection electrode PCE1, the first-first step electrode STE1-1, and the first-second step electrode STE1-2 may be disposed on the same layer. The first pixel connection electrode PCE1, the first-first step electrode STE1-1, and the first-second step electrode STE1-2 may be made of the same material.

[0147] The first pixel connection electrode PCE1 may be disposed on the first interlayer insulating film VA1 to overlap the bank PDL and may be connected to the source region S of the transistor TR through a contact hole penetrating the insulating film and the plurality of metal layers of the first interlayer insulating film VA1.

[0148] The first-second step electrode STE1-2 may be disposed on the first interlayer insulating film VA1 to overlap the third emission area EA3. Figure 7 As shown in , the first-second step electrode STE1-2 may be connected to the power line VL. For example, the first-second step electrode STE1-2 may be connected to the common voltage line VSL (and / or the external common voltage line EVSL) described above. The first-second step electrode STE1-2 and the common voltage line VSL (and / or the external common voltage line EVSL) may be formed integrally with each other. The first-second step electrode STE1-2 may be disposed at the same layer as the common voltage line VSL (and / or the external common voltage line EVSL). The first-second step electrode STE1-2 may be made of the same material as the common voltage line VSL (and / or the external common voltage line EVSL). The first-second step electrode STE1-2 may have a quadrilateral shape.

[0149] The first-first step electrode STE1-1 may be disposed on the first interlayer insulating film VA1 to overlap the second emission area EA2. Figure 7As shown in , the first-first step electrode STE1-1 may be in a floating state. However, the present disclosure is not limited thereto, and the first-first step electrode STE1-1 may be connected to the power line VL. For example, the first-first step electrode STE1-1 may be connected to the common voltage line VSL (and / or the external common voltage line EVSL). The first-first step electrode STE1-1 and the common voltage line VSL (and / or the external common voltage line EVSL) may be formed integrally with each other. The first-first step electrode STE1-1 may be disposed on the same layer as the common voltage line VSL (and / or the external common voltage line EVSL). The first-first step electrode STE1-1 may be made of the same material as the common voltage line VSL (and / or the external common voltage line EVSL). The first-first step electrode STE1-1 may have a quadrilateral shape.

[0150] Meanwhile, the first pixel connection electrode PCE1, the first-first step electrode STE1-1, the first-second step electrode STE1-2, the common voltage line VSL and the external common voltage line EVSL may all be disposed on the same layer. In addition, the first pixel connection electrode PCE1, the first-first step electrode STE1-1, the first-second step electrode STE1-2, the common voltage line VSL and the external common voltage line EVSL may all be made of the same material.

[0151] A second interlayer insulating film VA2 may be disposed on the first pixel connection electrode PCE1 , the first-first step electrode STE1 - 1 , and the first-second step electrode STE1 - 2 .

[0152] The second pixel connection electrode PCE2 and the second step electrode STE2 may be disposed on the second interlayer insulating film VA2 .

[0153] The second pixel connection electrode PCE2 may be disposed on the second interlayer insulating film VA2 to overlap the first pixel connection electrode PCE1. The second pixel connection electrode PCE2 may be connected to the first pixel connection electrode PCE1 through a fourth contact hole CT4 penetrating the second interlayer insulating film VA2.

[0154] The second step electrode STE2 may be disposed on the second interlayer insulating film VA2 to overlap with the third emission region EA3. For example, the second step electrode STE2 may overlap with the first-second step electrode STE1-2 in the third emission region EA3. The second step electrode STE2 may overlap with the entire first-second step electrode STE1-2. In this case, the area of ​​the second step electrode STE2 and the area of ​​the first-second step electrode STE1-2 may be the same as each other. However, the present disclosure is not limited thereto, and the area of ​​the second step electrode STE2 and the area of ​​the first-second step electrode STE1-2 may be different from each other. The area of ​​the step electrode may be defined by the size of the step electrode in the first direction DR1 and the size of the step electrode in the second direction DR2.

[0155] The second step electrode STE2 may be maintained in a floating state. However, the present disclosure is not limited thereto, and the second step electrode STE2 may be connected to the power line VL. For example, the second step electrode STE2 may be connected to the driving voltage line VDL (or the external driving voltage line EVDL) described above. The second step electrode STE2 and the driving voltage line VDL (or the external driving voltage line EVDL) may be formed integrally with each other. The second step electrode STE2 may be disposed on the same layer as the driving voltage line VDL (or the external driving voltage line EVDL). The second step electrode STE2 may be made of the same material as the driving voltage line VDL (or the external driving voltage line EVDL). The second step electrode STE2 may have a quadrilateral shape.

[0156] Meanwhile, the second pixel connection electrode PCE2, the second step electrode STE2, the driving voltage line VDL and the external driving voltage line EVDL may all be arranged in the same layer. In addition, the second pixel connection electrode PCE2, the second step electrode STE2, the driving voltage line VDL and the external driving voltage line EVDL may all be made of the same material.

[0157] A third interlayer insulating film VA3 may be disposed on the second pixel connection electrode PCE2 and the second step electrode STE2 .

[0158] The light emitting element layer EMTL may be disposed on the third interlayer insulating film VA3. The light emitting element layer EMTL may include, for example, a first light emitting element ED1, a second light emitting element ED2, and a third light emitting element ED3 disposed in different emission regions. For example, the first light emitting element ED1 of the light emitting element layer EMTL may be disposed in the first emission region EA1, the second light emitting element ED2 of the light emitting element layer EMTL may be disposed in the second emission region EA2, and the third light emitting element ED3 of the light emitting element layer EMTL may be disposed in the third emission region EA3.

[0159] Each of the first light emitting element ED1 , the second light emitting element ED2 , and the third light emitting element ED3 may provide white light.

[0160] The first light emitting element ED1 may include a first pixel electrode PE1 (or a first anode electrode), a light-providing layer EL, and a common electrode CE, which are stacked in the third direction DR3 .

[0161] The second light emitting element ED2 may include a second pixel electrode PE2 (or a second anode electrode), a light-providing layer EL, and a common electrode CE, which are stacked in the third direction DR3 .

[0162] The third light emitting element ED3 may include a third pixel electrode PE3 (or a third anode electrode), a light-providing layer EL, and a common electrode CE stacked in the third direction DR3.

[0163] Here, the light-supply layer EL and the common electrode CE may be common layers commonly used for the respective light emitting elements ED1, ED2, and ED3. In other words, the plurality of light emitting elements ED1, ED2, and ED3 of the light emitting element layer EMTL may share the light-supply layer EL and the common electrode CE with each other.

[0164] The light providing layer EL may include a plurality of light emitting layers providing light of different colors, and the plurality of light emitting layers may be stacked along a third direction DR3. The plurality of light emitting layers may include, for example, a red light emitting layer, a green light emitting layer, and a blue light emitting layer stacked in the third direction DR3. Different lights from the plurality of light emitting layers may be mixed with each other to generate white light. At the same time, the light providing layer EL may further include a charge generating layer. The charge generating layer may be disposed between adjacent light emitting layers. In this way, the light providing layer EL may have a series structure including a plurality of light emitting layers and a charge generating layer.

[0165] The first pixel electrode PE1 , the second pixel electrode PE2 , and the third pixel electrode PE3 may be connected to corresponding source regions S of corresponding transistors TR through the first pixel connection electrode PCE1 , the second pixel connection electrode PCE2 , and the metal connection layer ME.

[0166] The second pixel electrode PE2 may overlap the second emission area EA2. In addition, the second pixel electrode PE2 may overlap the first-first step electrode STE1-1 in the second emission area EA2.

[0167] The third pixel electrode PE3 may overlap the third emission area EA3. In addition, the third pixel electrode PE3 may overlap the first-second step electrode STE1-2 and the second step electrode STE2 in the third emission area EA3.

[0168] Each of the pixel electrodes PE1, PE2 and PE3 may include a reflective electrode and a light-transmitting electrode. Fig.10As shown in , the first pixel electrode PE1 may include a first reflective electrode RE1 and a first light-transmitting electrode TE1 connected to each other through a fifth contact hole CT5 of a fourth interlayer insulating film VA4. The second pixel electrode PE2 may include a second reflective electrode RE2 and a second light-transmitting electrode TE2 connected to each other through a fifth contact hole CT5 of the fourth interlayer insulating film VA4. The third pixel electrode PE3 may include a third reflective electrode RE3 and a third light-transmitting electrode TE3 connected to each other through a fifth contact hole CT5 of the fourth interlayer insulating film VA4.

[0169] The reflective electrodes RE1, RE2, and RE3 may be disposed on the third interlayer insulating film VA3 to overlap with the emission regions EA1, EA2, and EA3, respectively. For example, the first reflective electrode RE1 may be disposed on the third interlayer insulating film VA3 to overlap with the first emission region EA1, the second reflective electrode RE2 may be disposed on the third interlayer insulating film VA3 to overlap with the second emission region EA2, and the third reflective electrode RE3 may be disposed on the third interlayer insulating film VA3 to overlap with the third emission region EA3.

[0170] Each of the reflective electrodes RE1, RE2 and RE3 may be connected to the corresponding second pixel connection electrode PCE2 through the corresponding contact holes CT1, CT2 and CT3 penetrating the third interlayer insulating film VA3. For example, the first reflective electrode RE1 may be connected to the second pixel connection electrode PCE2 disposed below the first reflective electrode RE1 through the first contact hole CT1 penetrating the third interlayer insulating film VA3. The second reflective electrode RE2 may be connected to the second pixel connection electrode PCE2 disposed below the second reflective electrode RE2 through the second contact hole CT2 penetrating the third interlayer insulating film VA3. The third reflective electrode RE3 may be connected to the second pixel connection electrode PCE2 disposed below the third reflective electrode RE3 through the third contact hole CT3 penetrating the third interlayer insulating film VA3.

[0171] The second reflective electrode RE2 may overlap the second emission area EA2. The second reflective electrode RE2 may overlap the first-first step electrode STE1-1 in the second emission area EA2.

[0172] The third reflective electrode RE3 may overlap the third emission area EA3. The third reflective electrode RE3 may overlap the first-second step electrode STE1-2 and the second step electrode STE2 in the third emission area EA3.

[0173] like Fig.10As shown in the figure, the number of step electrodes arranged in each emission area EA1, EA2 and EA3 of a unit pixel UPX (for example, the number of stacked step electrodes overlapping with the respective emission areas EA1, EA2 and EA3 in the third direction DR3) is different from each other, so for each pixel, the distance between the reflective electrodes RE1, RE2 and RE3 and the common electrode CE can be different from each other.

[0174] For example, the step electrode may not be provided in the first emission region EA1 (for example, the number of step electrodes in the first emission region EA1 may be 0), one step electrode STE1-1 may be provided in the second emission region EA2, and two step electrodes STE1-2 and STE2 may be provided in the third emission region EA3. Specifically, the step electrode may not be provided between the first reflective electrode RE1 and the first interlayer insulating film VA1 (for example, the uppermost insulating film of the first interlayer insulating film VA1) in the first emission region EA1, one step electrode STE1-1 may be provided between the second reflective electrode RE2 and the first interlayer insulating film VA1 (for example, the uppermost insulating film of the first interlayer insulating film VA1) in the second emission region EA2, and two step electrodes STE1-2 and STE2 may be provided between the third reflective electrode RE3 and the first interlayer insulating film VA1 (for example, the uppermost insulating film of the first interlayer insulating film VA1) in the third emission region EA3 to overlap each other in the third direction DR3. In other words, there may be no step electrode overlapping the first reflective electrode RE1 between the first reflective electrode RE1 of the first emission area EA1 and the first interlayer insulating film VA1 (for example, the uppermost insulating film of the first interlayer insulating film VA1). There may be one step electrode STE1-1 overlapping the second reflective electrode RE2 in the third direction DR3 between the second reflective electrode RE2 of the second emission area EA2 and the first interlayer insulating film VA1 (for example, the uppermost insulating film of the first interlayer insulating film VA1). There may be two step electrodes STE1-2 and STE2 overlapping the third reflective electrode RE3 in the third direction DR3 between the third reflective electrode RE3 of the third emission area EA3 and the first interlayer insulating film VA1 (for example, the uppermost insulating film of the first interlayer insulating film VA1). Here, the uppermost insulating film of the first interlayer insulating film VA1 may refer to an insulating film that is farthest from the substrate SUB in the third direction DR3 among a plurality of insulating films included in the first interlayer insulating film VA1. In other words, the uppermost insulating film of the first interlayer insulating film VA1 may be an insulating film closest to the second interlayer insulating film VA2 in the third direction DR3 among the insulating films of the first interlayer insulating film VA1 .

[0175] Since the number of stacked step electrodes disposed under the respective reflective electrodes RE1, RE2, and RE3 of one unit pixel UPX is different from each other as described above, the distances between the first interlayer insulating film VA1 (e.g., the uppermost insulating film of the first interlayer insulating film VA1) and the respective reflective electrodes RE1, RE2, and RE3 may be different from each other. For example, the distance d1 (hereinafter, referred to as the first distance) between the first interlayer insulating film VA1 (e.g., the uppermost insulating film of the first interlayer insulating film VA1) and the first reflective electrode RE1, the distance d2 (hereinafter, referred to as the second distance) between the first interlayer insulating film VA1 (e.g., the uppermost insulating film of the first interlayer insulating film VA1) and the second reflective electrode RE2, and the distance d3 (hereinafter, referred to as the third distance) between the first interlayer insulating film VA1 (e.g., the uppermost insulating film of the first interlayer insulating film VA1) and the third reflective electrode RE3 may be defined by Relational Expression 1.

[0176] <Relational expression 1>

[0177] d1 <d2<d3

[0178] That is, the second distance d2 is greater than the first distance d1 and less than the third distance d3 as defined in relational expression 1. In other words, as the number of stacked step electrodes overlapping the reflective electrode in the third direction DR3 increases, the distance between the reflective electrode and the uppermost insulating film of the first interlayer insulating film VA1 may increase.

[0179] In addition, since the number of stacked step electrodes disposed under each of the reflective electrodes RE1, RE2, and RE3 of one unit pixel UPX is different from each other as described above, the distances between each of the reflective electrodes RE1, RE2, and RE3 and the common electrode CE may be different from each other. For example, as the number of stacked step electrodes stacked with the reflective electrode in the third direction DR3 increases, the distance between the reflective electrode and the common electrode CE may decrease. For example, the distance rd1 between the first reflective electrode RE1 and the common electrode CE (hereinafter, referred to as the first distance), the distance rd2 between the second reflective electrode RE2 and the common electrode CE (hereinafter, referred to as the second distance), and the distance rd3 between the third reflective electrode RE3 and the common electrode CE (hereinafter, referred to as the third distance) may be defined by relational expression 2.

[0180] <Relational expression 2>

[0181] rd1>rd2>rd3

[0182] That is, as defined in relational expression 2, the second distance rd2 is smaller than the first distance rd1 and larger than the third distance rd3. This is because the distance between the reflective electrode and the uppermost insulating film of the first interlayer insulating film VA1 increases as the number of stacked step electrodes overlapping the reflective electrode in the third direction DR3 increases. For example, the first reflective electrode RE1 among the reflective electrodes RE1, RE2, and RE3 disposed in one unit pixel UPX may be disposed closest to the first interlayer insulating film VA1 in the third direction DR3 (e.g., the uppermost insulating film of the first interlayer insulating film VA1), and the third reflective electrode RE3 among the reflective electrodes RE1, RE2, and RE3 disposed in one unit pixel UPX may be disposed farthest from the first interlayer insulating film VA1 in the third direction DR3 (e.g., the uppermost insulating film of the first interlayer insulating film VA1). At the same time, the second reflective electrode RE2 may be disposed at a level higher than the first reflective electrode RE1 and lower than the third reflective electrode RE3 in the third direction DR3.

[0183] Meanwhile, the distance between each of the reflective electrodes RE1, RE2 and RE3 and the common electrode CE may refer to, for example, a size in the third direction DR3. In this case, the distance between each of the reflective electrodes RE1, RE2 and RE3 and the common electrode CE may be the distance between the lowest part of the common electrode CE and the corresponding reflective electrode in the corresponding emission area in the third direction DR3. For example, the distance between the first reflective electrode RE1 and the common electrode CE may be defined as the distance between the lowest part of the common electrode CE and the first reflective electrode RE1 in the first emission area EA1 in the third direction DR3. Similarly, the distance between the second reflective electrode RE2 and the common electrode CE may be defined as the distance between the lowest part of the common electrode CE and the second reflective electrode RE2 in the second emission area EA2 in the third direction DR3. Similarly, the distance between the third reflective electrode RE3 and the common electrode CE may be defined as the distance between the lowest part of the common electrode CE and the third reflective electrode RE3 in the third emission area EA3 in the third direction DR3.

[0184] The distances between the common electrode CE and the respective reflective electrodes RE1, RE2, and RE3 described above may be defined as resonance distances. For example, the distance between the first reflective electrode RE1 and the common electrode CE may be defined as a first resonance distance rd1, the distance between the second reflective electrode RE2 and the common electrode CE may be defined as a second resonance distance rd2, and the distance between the third reflective electrode RE3 and the common electrode CE may be defined as a third resonance distance rd3.

[0185] In an exemplary embodiment, since the number of stacked step electrodes for each pixel is different from each other, the resonance distances rd1, rd2, and rd3 between the reflective electrode and the common electrode CE for each pixel can be adjusted to be different from each other. Therefore, the microcavity (or film resonance) effect on light can be increased and / or optimized according to the wavelength of light to be emitted from each pixel and the resonance distance corresponding to the wavelength, the resonance order, etc. For example, the light of the first color, the light of the second color, and the light of the third color can be appropriately amplified in the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively. As an example, the light of the first color emitted by the first emission area EA1 can be red light corresponding to the first color filter CF1 to be described later, the light of the second color emitted by the second emission area EA2 can be green light corresponding to the second color filter CF2 to be described later, and the light of the third color emitted by the third emission area EA3 can be blue light corresponding to the third color filter CF3 to be described later. In other words, the resonance distance rd2 of the second emission area EA2 from which green light is emitted may be smaller than the resonance distance rd1 of the first emission area EA1 from which red light is emitted, and greater than the resonance distance rd3 of the third emission area EA3 from which blue light is emitted.

[0186] In an exemplary embodiment, the reflective electrodes RE1, RE2, and RE3 may be a metal layer including a metal such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound or mixture thereof. In an exemplary embodiment, the reflective electrodes RE1, RE2, and RE3 may further include a metal oxide layer (e.g., a transparent conductive oxide layer) located above and / or below the metal layer. As an example, each of the reflective electrodes RE1, RE2, and RE3 may have indium tin oxide (ITO) / Ag, Ag / ITO, ITO / Mg, or ITO / MgF 2 A double-layer structure or a triple-layer structure such as ITO / Ag / ITO.

[0187] A fourth interlayer insulating film VA4 may be disposed on each of the reflective electrodes RE1, RE2, and RE3. The fourth interlayer insulating film VA4 may include an inorganic film.

[0188] The first light transparent electrode TE1 , the second light transparent electrode TE2 , and the third light transparent electrode TE3 may be disposed on the fourth interlayer insulating film VA4 .

[0189] The first light-transmitting electrode TE1 may be disposed on the fourth interlayer insulating film VA4 to overlap with the first emission region EA1. The first light-transmitting electrode TE1 may overlap with the first reflective electrode RE1 in the first emission region EA1. The first light-transmitting electrode TE1 may be connected to the first reflective electrode RE1 through a fifth contact hole CT5 penetrating the fourth interlayer insulating film VA4.

[0190] The second light-transmitting electrode TE2 may be disposed on the fourth interlayer insulating film VA4 to overlap with the second emission region EA2. The second light-transmitting electrode TE2 may overlap with the second reflective electrode RE2 and the first-first step electrode STE1-1 in the second emission region EA2. The second light-transmitting electrode TE2 may be connected to the second reflective electrode RE2 through a fifth contact hole CT5 penetrating the fourth interlayer insulating film VA4.

[0191] The third light-transmitting electrode TE3 may be disposed on the fourth interlayer insulating film VA4 to overlap with the third emission region EA3. The third light-transmitting electrode TE3 may overlap with the third reflective electrode RE3, the second step electrode STE2, and the first-second step electrode STE1-2 in the third emission region EA3. The third light-transmitting electrode TE3 may be connected to the third reflective electrode RE3 through a fifth contact hole CT5 penetrating the fourth interlayer insulating film VA4.

[0192] The respective light-transmitting electrodes TE1, TE2, and TE3 described above may have different thicknesses. For example, as the number of stacked step electrodes stacked with the reflective electrode in the third direction DR3 increases, the light-transmitting electrode connected to the reflective electrode may have a thinner thickness. For example, the thickness of the first light-transmitting electrode TE1 (hereinafter, referred to as the first thickness T1), the thickness of the second light-transmitting electrode TE2 (hereinafter, referred to as the second thickness T2), and the thickness of the third light-transmitting electrode TE3 (hereinafter, referred to as the third thickness T3) may be defined by relational expression 3.

[0193] <Relational expression 3>

[0194] T1>T2>T3

[0195] That is, as defined in relational expression 3, the second thickness T2 is less than the first thickness T1 and greater than the third thickness T3. In other words, the thickness of the light-transmitting electrode may be proportional to the distance between the reflective electrode connected to the light-transmitting electrode and the common electrode CE. Here, the thickness of each of the light-transmitting electrodes TE1, TE2, and TE3 may refer to, for example, the size of each of the light-transmitting electrodes TE1, TE2, and TE3 in the third direction DR3 in the corresponding emission region. In other words, the thickness of each of the light-transmitting electrodes TE1, TE2, and TE3 may be the size of each of the light-transmitting electrodes measured in the third direction DR3. For example, the first thickness T1 may be the size of the first light-transmitting electrode TE1 in the first emission region EA1 in the third direction DR3, the second thickness T2 may be the size of the second light-transmitting electrode TE2 in the second emission region EA2 in the third direction DR3, and the third thickness T3 may be the size of the third light-transmitting electrode TE3 in the third emission region EA3 in the third direction DR3.

[0196] The light-transmitting electrodes TE1, TE2, and TE3 may include a transparent conductive material. For example, the light-transmitting electrodes TE1, TE2, and TE3 may include a transparent conductive oxide (TCO). As an example, the light-transmitting electrodes TE1, TE2, and TE3 may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), aluminum zinc oxide (AZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium tin zinc oxide (ITZO), tungsten oxide (W x O x ), titanium oxide (TiO 2 ) and at least one of magnesium oxide (MgO) or other transparent conductive materials.

[0197] A bank PDL (or a pixel defining layer) may be disposed on the first light transparent electrode TE1 , the second light transparent electrode TE2 , and the third light transparent electrode TE3 .

[0198] The bank PDL may define the respective emission regions of the respective pixels PX1, PX2, and PX3 (e.g., the first emission region EA1 of the first pixel PX1, the second emission region EA2 of the second pixel PX2, and the third emission region EA3 of the third pixel PX3). To this end, the bank PDL may be provided to expose, for example, a partial region of the first light-transmitting electrode TE1, a partial region of the second light-transmitting electrode TE2, and a partial region of the third light-transmitting electrode TE3 on the fourth interlayer insulating film VA4. The bank PDL may cover the edge of the first light-transmitting electrode TE1, the edge of the second light-transmitting electrode TE2, and the edge of the third light-transmitting electrode TE3. The bank PDL may be formed as an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0199] The light-providing layer EL may be disposed on the respective light-transmitting electrodes TE1, TE2, and TE3 and the bank PDL. For example, the light-providing layer EL may be disposed on the first light-transmitting electrode TE1, the second light-transmitting electrode TE2, the third light-transmitting electrode TE3, and the bank PDL.

[0200] The light-providing layer EL may include a plurality of light-emitting units (see Figure 21 to Figure 27 ). For example, the light-providing layer EL may include a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit stacked in the third direction DR3. Each light-emitting unit may provide light of different wavelengths. For example, the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit may emit light of different colors. For example, the light-providing layer EL may have a series structure in which a plurality of light-emitting units providing light of different colors are stacked in a vertical direction (e.g., the third direction DR3).

[0201] The first light emitting unit may be disposed on each light-transmitting electrode. The first light emitting unit may include a first light emitting layer, a hole transport layer, an organic material layer, and an electron transport layer.

[0202] The second light emitting unit may be disposed on the first light emitting unit. The second light emitting unit may include a second light emitting layer, a hole transport layer, an organic material layer, and an electron transport layer.

[0203] The third light emitting unit may be disposed on the second light emitting unit. The third light emitting unit may include a third light emitting layer, a hole transport layer, an organic material layer, and an electron transport layer.

[0204] Each of the light emitting elements ED1, ED2, and ED3 can provide white light by mixing light of a first color (e.g., blue light) from a first light emitting unit, light of a second color (e.g., red light) from a second light emitting unit, and light of a third color (e.g., green light) from a third light emitting unit. For example, each of the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 can provide white light.

[0205] In addition, in addition to the light-emitting unit described above, the light-providing layer EL may further include at least one charge generating layer. For example, the charge generating layer may be disposed between the light-emitting units adjacent to each other in the third direction DR3. The charge generating layer may include, for example, a first charge generating layer and a second charge generating layer stacked in the third direction DR3. In this case, the first charge generating layer may be disposed between the first light-emitting unit and the second light-emitting unit, and the second charge generating layer may be disposed between the second light-emitting unit and the third light-emitting unit.

[0206] At the same time, each charge generation layer may include a negative charge generation layer and a positive charge generation layer. For example, the first charge generation layer may include a first negative charge generation layer and a first positive charge generation layer stacked in the third direction DR3, and the second charge generation layer may include a second negative charge generation layer and a second positive charge generation layer stacked in the third direction DR3.

[0207] The common electrode CE may be disposed on the light-providing layer EL. For example, the common electrode CE may be disposed on the light-providing layer EL to overlap with the first light-transmitting electrode TE1, the second light-transmitting electrode TE2, the third light-transmitting electrode TE3, the first emission region EA1, the second emission region EA2, the third emission region EA3, and the dike PDL. In the top emission structure, the common electrode CE may be made of a transparent conductive material (TCO) (such as ITO or IZO) through which light can be transmitted, or a semi-transmitting conductive material (such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag)). When the common electrode CE is made of a semi-transmitting conductive material, the emission efficiency may be improved by a microcavity.

[0208] The cap layer CPL may be disposed on the common electrode CE. The cap layer CPL may include an inorganic insulating material. In an exemplary embodiment, the cap layer CPL may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0209] The encapsulation layer ENC may be disposed on the cap layer CPL. The encapsulation layer ENC may cover the upper surface and the side surface of the light emitting element layer EMTL, and may protect the light emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic film and at least one organic film for encapsulating the light emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic film TFE1 or TFE3 to prevent oxygen or moisture from penetrating into the light emitting element layer EMTL. In addition, the encapsulation layer ENC may include at least one organic film to protect the light emitting element layer EMTL from foreign matter such as dust. For example, the encapsulation layer ENC may include a first encapsulation inorganic film TFE1, an encapsulation organic film TFE2, and a second encapsulation inorganic film TFE3.

[0210] The first encapsulation inorganic film TFE1 may be disposed on the cap layer CPL, the encapsulation organic film TFE2 may be disposed on the first encapsulation inorganic film TFE1, and the second encapsulation inorganic film TFE3 may be disposed on the encapsulation organic film TFE2. The first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 may be formed as a multilayer film in which one or more inorganic films of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The encapsulation organic film TFE2 may be an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0211] The display device 10 may include a plurality of color filters CF1, CF2, and CF3 disposed on the emission areas EA1, EA2, and EA3. The plurality of color filters CF1, CF2, and CF3 may be disposed to correspond to the emission areas EA1, EA2, and EA3, respectively. For example, the color filters CF1, CF2, and CF3 may be disposed on the encapsulation layer ENC to correspond to the emission areas EA1, EA2, and EA3, respectively.

[0212] The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 that are arranged to correspond to different emission areas EA1, EA2, and EA3, respectively. The color filters CF1, CF2, and CF3 may include a colorant (such as a dye or a pigment) that absorbs light of a wavelength band other than light of a specific wavelength band, and may be arranged to correspond to the color of the light emitted from the emission areas EA1, EA2, and EA3. For example, the first color filter CF1 may be a red color filter that is arranged to overlap with the first emission area EA1 and through which only red light is transmitted. The second color filter CF2 may be a green color filter that is arranged to overlap with the second emission area EA2 and through which only green light is transmitted, and the third color filter CF3 may be a blue color filter that is arranged to overlap with the third emission area EA3 and through which only blue light is transmitted.

[0213] A plurality of color filters CF1, CF2, and CF3 may be arranged to partially overlap with other adjacent color filters CF1, CF2, and CF3. Different color filters CF1, CF2, and CF3 may overlap with each other on the encapsulation layer ENC in an area that does not overlap with the emission areas EA1, EA2, and EA3. In the display device 10, the color filters CF1, CF2, and CF3 are arranged to overlap with each other, so that the intensity of the reflected light caused by the external light can be reduced. In addition, by adjusting the arrangement, shape, area, etc. of the color filters CF1, CF2, and CF3 in the plan view, the color sense of the reflected light caused by the external light can be controlled. However, the present disclosure is not limited thereto. A plurality of color filters CF1, CF2, and CF3 may be spaced apart from other adjacent color filters CF1, CF2, and CF3 on the encapsulation layer ENC.

[0214] Meanwhile, although not shown, the display device 10 according to the exemplary embodiment may further include a light blocking layer disposed between adjacent color filters (e.g., between the first color filter CF1 and the second color filter CF2 and between the second color filter CF2 and the third color filter CF3) on the encapsulation layer ENC. The light blocking layer may include a plurality of holes disposed to overlap with the emission areas EA1, EA2, and EA3, respectively. For example, the first hole may be disposed to overlap with the first emission area EA1. The second hole may be disposed to overlap with the second emission area EA2, and the third hole may be disposed to overlap with the third emission area EA3. The area or size of each of the holes of the light blocking layer may be larger than the area or size of each of the emission areas EA1, EA2, and EA3 defined by the embankment PDL. The holes of the light blocking layer are formed to be larger than the emission areas EA1, EA2, and EA3, so that the user can view the light emitted from each emission area EA1, EA2, and EA3 not only from the front (front) of the display device 10 but also from the side of the display device 10.

[0215] The light blocking layer may include a light absorbing material. For example, the light blocking layer may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but the present disclosure is not limited thereto. The light blocking layer may prevent color mixing caused by penetration of visible light between the first emission area to the third emission area EA1, EA2, and EA3 to improve the color gamut of the display device 10.

[0216] An overcoat layer OC may be disposed on the color filters CF1, CF2, and CF3 to flatten the upper ends of the color filters CF1, CF2, and CF3. The overcoat layer OC may be a colorless light-transmitting layer having no color in the visible light band. For example, the overcoat layer OC may include a colorless light-transmitting organic material such as an acrylic resin.

[0217] Fig.11 It is along Figure 6 1 is a cross-sectional view of a display device 10 according to an exemplary embodiment taken along line II′.

[0218] Fig.11 The display device 10 is different from the above-described display device in terms of the shape of at least one step electrode. Fig.10 The display device 10 is different from that of FIG. 1 , and this difference will be mainly described below.

[0219] like Fig.11As shown in , the first-first step electrode STE1-1 may be connected to the first pixel connection electrode PCE1 connected to the second pixel electrode PE2 (hereinafter, referred to as the first pixel connection electrode PCE1 of the second pixel PX2). In other words, the first-first step electrode STE1-1 may be connected to the first pixel connection electrode PCE1 of the second pixel PX2. Therefore, the first-first step electrode STE1-1 may receive a voltage (hereinafter, referred to as a pixel voltage) from the transistor of the second pixel PX2 through the first pixel connection electrode PCE1 of the second pixel PX2.

[0220] The first-first step electrode STE1-1 may be integrally formed with the first pixel connection electrode PCE1 of the second pixel PX2. In this case, the structure including the first-first step electrode STE1-1 and the first pixel connection electrode PCE1 of the second pixel PX2 may correspond to a shape in which, for example, the first pixel connection electrode PCE1 of the second pixel PX2 further extends to the second emission area EA2.

[0221] The first-second step electrode STE1-2 may be integrally formed with the first pixel connection electrode PCE1 of the third pixel PX3. In this case, the structure including the first-second step electrode STE1-2 and the first pixel connection electrode PCE1 of the third pixel PX3 may correspond to a shape in which, for example, the first pixel connection electrode PCE1 of the third pixel PX3 further extends to the third emission area EA3.

[0222] The second step electrode STE2 may be integrally formed with the second pixel connection electrode PCE2 of the third pixel PX3. In this case, the structure including the second step electrode STE2 and the second pixel connection electrode PCE2 of the third pixel PX3 may correspond to a shape in which, for example, the second pixel connection electrode PCE2 of the third pixel PX3 further extends to the third emission area EA3.

[0223] The common voltage described above may not be applied to Fig.11 The first-first step electrode STE1-1 and the first-second step electrode STE1-2 in the embodiment. For example, Fig.11 The first-first step electrode STE1-1 and the first-second step electrode STE1-2 may not be connected to the common voltage line VSL and / or the external common voltage line EVSL. In other words, when any step electrode is connected to the pixel connection electrode, the step electrode is not connected to the power line described above.

[0224] The driving voltage described above may not be applied to Fig.11 The second step electrode STE2 in the embodiment. For example, Fig.11The second step electrode STE2 in the embodiment may not be connected to the driving voltage line VDL and / or the external driving voltage line EVDL. In other words, when any step electrode is connected to the pixel connection electrode, the step electrode is not connected to the above-described power line.

[0225] Fig.12 It is along Figure 6 1 is a cross-sectional view of a display device 10 according to an exemplary embodiment taken along line II′.

[0226] Fig.12 The display device 10 is different from the above-described display device in terms of the shape of at least one step electrode. Fig.10 The display device 10 is different from that of FIG. 1 , and this difference will be mainly described below.

[0227] like Fig.12 As shown in FIG. 1 , the first-first step electrode STE1-1 may have the same Fig.10 The structure of the first-first step electrode STE1-1 is the same as that of the first-first step electrode STE1-1.

[0228] In addition, if Fig.12 As shown in FIG. 1 , the first-second step electrodes STE1-2 and the second step electrode STE2 may have the same structure as described above. Fig.11 The first-second step electrodes STE1-2 and the second step electrode STE2 have the same structure.

[0229] Fig.13 It is along Figure 6 1 is a cross-sectional view of a display device 10 according to an exemplary embodiment taken along line II′.

[0230] Fig.13 The display device 10 is different from the above-described display device in terms of the shape of at least one step electrode. Fig.10 The display device 10 is different from that of FIG. 1 , and this difference will be mainly described below.

[0231] like Fig.13 As shown in FIG. 1 , the first-first step electrode STE1-1 may have the same Fig.11 The structure of the first-first step electrode STE1-1 is the same as that of the first-first step electrode STE1-1.

[0232] In addition, if Fig.13 As shown in FIG. 1 , the first-second step electrodes STE1-2 and the second step electrode STE2 may have the same structure as described above. Fig.10 The first-second step electrodes STE1-2 and the second step electrode STE2 have the same structure.

[0233] Fig.14 It is along Figure 61 is a cross-sectional view of a display device 10 according to an exemplary embodiment taken along line II′.

[0234] Fig.14 The display device 10 is different from the above-described display device in terms of the shape of at least one step electrode. Fig.10 The display device 10 is different from that of FIG. 1 , and this difference will be mainly described below.

[0235] like Fig.14 As shown in FIG. 1 , the first-first step electrode STE1-1 and the first-second step electrode STE1-2 may have the same structure as described above. Fig.11 The structures of the first-first step electrode STE1-1 and the first-second step electrode STE1-2 are the same.

[0236] In addition, if Fig.14 As shown in FIG. 1 , the second step electrode STE2 may have the same Fig.10 The structure of the second step electrode STE2 is the same as that of the second step electrode STE2.

[0237] Fig.15 It is along Figure 6 1 is a cross-sectional view of a display device 10 according to an exemplary embodiment taken along line II′. Fig.16 yes Fig.15 1-1, the first pixel connection electrode PCE1, and the first-second step electrode STE1-2.

[0238] Fig.15 The display device 10 is different from the above-described display device in terms of the shape of at least one step electrode. Fig.10 The display device 10 is different from that of FIG. 1 , and this difference will be mainly described below.

[0239] like Fig.15 As shown in , the first-first step electrode STE1-1 and the first-second step electrode STE1-2 may be connected to each other. Fig.16As shown in , the first-first step electrode STE1-1 and the first-second step electrode STE1-2 may be formed integrally with each other. In this case, for example, the connection electrode CNE connecting the first-first step electrode STE1-1 and the first-second step electrode STE1-2 to each other may connect the first-first step electrode STE1-1 and the first-second step electrode STE1-2 to each other while bypassing the first pixel connection electrode PCE1 provided between the first-first step electrode STE1-1 and the first-second step electrode STE1-2 so as not to be short-circuited with the first pixel connection electrode PCE1. As an example, the connection electrode CNE may have a curved shape surrounding a portion of the first pixel connection electrode PCE1 of the third pixel PX3. For example, the connection electrode CNE may have a U-shape.

[0240] Fig.15 and Fig.16 The first-first step electrode STE1-1, the connection electrode CNE, and the first-second step electrode STE1-2 may be formed integrally with each other.

[0241] Fig.15 and Fig.16 The structure including the first-first step electrode STE1-1, the connection electrode CNE, and the first-second step electrode STE1-2 may be connected to, for example, the common voltage line VSL described above and / or the external common voltage line EVSL.

[0242] Fig.15 The second step electrode STE2 may have the same structure as described above. Fig.10 The structure of the second step electrode STE2 is the same as that of the second step electrode STE2.

[0243] Fig.17 It is along Figure 6 1 is a cross-sectional view of a display device 10 according to an exemplary embodiment taken along line II′.

[0244] Fig.17 The display device 10 is different from the above-described display device in terms of the shape of at least one step electrode. Fig.10 The display device 10 is different from that of FIG. 1 , and this difference will be mainly described below.

[0245] like Fig.17 As shown in FIG. 1 , the first-first step electrode STE1-1 and the first-second step electrode STE1-2 may be formed by Fig.15 and Fig.16 The connection electrodes CNE shown in FIG. 1 are connected to each other.

[0246] In addition, if Fig.17As shown in FIG. 1 , the first-first step electrode STE1 - 1 may be integrally formed with the first pixel connection electrode PCE1 of the second pixel PX2 .

[0247] Fig.18 It is along Figure 6 1 is a cross-sectional view of a display device 10 according to an exemplary embodiment taken along line II′.

[0248] Fig.18 The display device 10 is different from the above-described display device in terms of the shape of at least one step electrode. Fig.10 The display device 10 is different from that of FIG. 1 , and this difference will be mainly described below.

[0249] Fig.18 The first-first step electrode STE1-1 may have the same structure as described above. Fig.10 The structure of the first-first step electrode STE1-1 is the same as that of the first-first step electrode STE1-1.

[0250] like Fig.18 As shown in FIG. 1 , the first-second step electrode STE1-2 and the second step electrode STE2 may be connected to each other. For example, the second step electrode STE2 may be connected to the first-second step electrode STE1-2 through a sixth contact hole CT6 penetrating the second interlayer insulating film VA2.

[0251] Fig.19 It is along Figure 6 1 is a cross-sectional view of a display device 10 according to an exemplary embodiment taken along line II′.

[0252] Fig.19 The display device 10 is different from the above-described display device in terms of the shape of at least one step electrode. Fig.10 The display device 10 is different from that of FIG. 1 , and this difference will be mainly described below.

[0253] Fig.19 The first-first step electrode STE1-1 may have the same structure as described above. Fig.10 The structure of the first-first step electrode STE1-1 is the same as that of the first-first step electrode STE1-1.

[0254] like Fig.19 As shown in , the first-second step electrode STE1-2 and the second step electrode STE2 may be connected to each other. For example, the second step electrode STE2 may be connected to the first-second step electrode STE1-2 through the sixth contact hole CT6 penetrating the second interlayer insulating film VA2. In this case, the first-second step electrode STE1-2 may be formed integrally with the first pixel connection electrode PCE1 of the third pixel PX3.

[0255] Fig. 20 It is along Figure 61 is a cross-sectional view of a display device 10 according to an exemplary embodiment taken along line II′.

[0256] Fig. 20 The display device 10 is different from the above-described display device in terms of the shape of at least one step electrode. Fig.10 The display device 10 is different from that of FIG. 1 , and this difference will be mainly described below.

[0257] Fig. 20 The first-first step electrode STE1-1 may have the same structure as described above. Fig.10 The structure of the first-first step electrode STE1-1 is the same as that of the first-first step electrode STE1-1.

[0258] like Fig. 20 As shown in , the first-second step electrode STE1-2 and the second step electrode STE2 may be connected to each other. For example, the second step electrode STE2 may be connected to the first-second step electrode STE1-2 through the sixth contact hole CT6 penetrating the second interlayer insulating film VA2. In this case, the first-second step electrode STE1-2 may be integrally formed with the first pixel connection electrode PCE1 of the third pixel PX3, and the second step electrode STE2 may be integrally formed with the second pixel connection electrode PCE2 of the third pixel PX3.

[0259] At the same time, the following will refer to Figure 21 to Figure 27 Describe the light emitting element (e.g. Fig.10 other structures of ED1, ED2 and ED3).

[0260] Fig.21 is a cross-sectional view illustrating a structure of a light emitting element according to an exemplary embodiment. Figure 22 to Figure 25 is a cross-sectional view illustrating a structure of a light emitting element according to an exemplary embodiment.

[0261] Reference Fig.21 According to an exemplary embodiment, a light emitting element (e.g., an organic light emitting diode) may include the pixel electrode 201 described above, a common electrode 205, and a light providing layer 203 between the pixel electrode 201 and the common electrode 205. Here, the pixel electrode 201 may be one of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 described above. In addition, the common electrode 205 may be the common electrode CE described above. In addition, the light providing layer 203 may be the light providing layer EL described above. In this case, the pixel electrode 201 may include the reflective electrode and the light-transmitting electrode described above.

[0262] The pixel electrode 201 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). The pixel electrode 201 may be a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound or mixture thereof. For example, the pixel electrode 201 may have a three-layer structure of ITO / Ag / ITO.

[0263] The common electrode 205 may be disposed on the light-providing layer 203. The common electrode 205 may include a metal, an alloy, a conductive compound, or any combination thereof having a low work function. For example, the common electrode 205 may include lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), ytterbium (Yb), silver-ytterbium (Ag-Yb), ITO, IZO, or any combination thereof. The common electrode 205 may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode.

[0264] The light-providing layer 203 may include a high molecular organic material or a low molecular organic material that emits light of a predetermined color. In addition to various organic materials, the light-providing layer 203 may also include a metal-containing compound such as an organic metal compound, an inorganic material such as a quantum dot, and the like.

[0265] In an exemplary embodiment, the light-providing layer 203 may include a light-emitting layer and a first functional layer and a second functional layer respectively disposed below and above the light-emitting layer. The first functional layer may include, for example, a hole transport layer (HTL) or a hole transport layer and a hole injection layer (HIL). The second functional layer is a component disposed on the light-emitting layer and is optional. For example, the light-providing layer 203 may include or may not include the second functional layer. The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0266] In an exemplary embodiment, the light-providing layer 203 may include two or more light-emitting units sequentially stacked between the pixel electrode 201 and the common electrode 205 and a charge generation layer CGL disposed between the two light-emitting units. When the light-providing layer 203 includes the light-emitting unit and the charge generation layer, the light-emitting element (e.g., an organic light-emitting diode) may be a series light-emitting element. The light-emitting element (e.g., an organic light-emitting diode) may improve color purity and light-emitting efficiency by having a stacked structure of a plurality of light-emitting units.

[0267] One light-emitting unit may include a light-emitting layer and a first functional layer and a second functional layer disposed below and above the light-emitting layer, respectively. The charge generation layer CGL may include a negative charge generation layer and a positive charge generation layer. The luminous efficiency of an organic light-emitting diode as a tandem light-emitting element having a plurality of light-emitting layers may be further improved by the negative charge generation layer and the positive charge generation layer.

[0268] The negative charge generation layer may be an n-type charge generation layer. The negative charge generation layer may supply electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material. The positive charge generation layer may be a p-type charge generation layer. The positive charge generation layer may provide holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material.

[0269] In an exemplary embodiment, if Fig. 22 As shown in , the light-emitting element (e.g., an organic light-emitting diode) may include a first light-emitting unit EU1 and a second light-emitting unit EU2 stacked sequentially, the first light-emitting unit EU1 including a first light-emitting layer EL1, and the second light-emitting unit EU2 including a second light-emitting layer EL2. The charge generation layer CGL may be disposed between the first light-emitting unit EU1 and the second light-emitting unit EU2. For example, the light-emitting element (e.g., an organic light-emitting diode) may include a pixel electrode 201, a first light-emitting layer EL1, a charge generation layer CGL, a second light-emitting layer EL2, and a common electrode 205 stacked sequentially. The first functional layer and the second functional layer may be disposed below and above the first light-emitting layer EL1, respectively. The first functional layer and the second functional layer may be disposed below and above the second light-emitting layer EL2, respectively. The first light-emitting layer EL1 may be a blue light-emitting layer, and the second light-emitting layer EL2 may be a yellow light-emitting layer.

[0270] In an exemplary embodiment, if Fig.23As shown in , the light emitting element (e.g., an organic light emitting diode) may include a first light emitting unit EU1, a third light emitting unit EU3, and a second light emitting unit EU2, the first light emitting unit EU1 including a first light emitting layer EL1, the third light emitting unit EU3 including a first light emitting layer EL1, and the second light emitting unit EU2 including a second light emitting layer EL2. The first charge generation layer CGL1 may be disposed between the first light emitting unit EU1 and the second light emitting unit EU2, and the second charge generation layer CGL2 may be disposed between the second light emitting unit EU2 and the third light emitting unit EU3. For example, the light emitting element (e.g., an organic light emitting diode) may include a pixel electrode 201, a first light emitting layer EL1, a first charge generation layer CGL1, a second light emitting layer EL2, a second charge generation layer CGL2, a first light emitting layer EL1, and a common electrode 205 stacked sequentially. The first functional layer and the second functional layer may be disposed below and above the first light emitting layer EL1, respectively. The first functional layer and the second functional layer may be disposed below and above the second light emitting layer EL2, respectively. The first light emitting layer EL1 may be a blue light emitting layer, and the second light emitting layer EL2 may be a yellow light emitting layer.

[0271] In an exemplary embodiment, in a light emitting element (e.g., an organic light emitting diode), in addition to the second light emitting layer EL2, the second light emitting unit EU2 may further include a third light emitting layer EL3 and / or a fourth light emitting layer EL4 directly contacting the second light emitting layer EL2 below and / or above the second light emitting layer EL2. Here, the phrase "direct contact" may mean that no other layer is provided between the second light emitting layer EL2 and the third light emitting layer EL3 and / or between the second light emitting layer EL2 and the fourth light emitting layer EL4. The third light emitting layer EL3 may be a red light emitting layer, and the fourth light emitting layer EL4 may be a green light emitting layer.

[0272] For example, Fig.24 As shown in , the light emitting element (e.g., an organic light emitting diode) may include a pixel electrode 201, a first light emitting layer EL1, a first charge generating layer CGL1, a third light emitting layer EL3, a second light emitting layer EL2, a second charge generating layer CGL2, a first light emitting layer EL1, and a common electrode 205 stacked sequentially. Alternatively, as Fig.25 As shown in the figure, the light-emitting element (e.g., an organic light-emitting diode) may include a pixel electrode 201, a first light-emitting layer EL1, a first charge generation layer CGL1, a third light-emitting layer EL3, a second light-emitting layer EL2, a fourth light-emitting layer EL4, a second charge generation layer CGL2, a first light-emitting layer EL1 and a common electrode 205 stacked sequentially.

[0273] Fig.26 It is shown Fig.24 A cross-sectional view of an example of an organic light emitting diode. Fig. 27 It is shown Fig.25A cross-sectional view of an example of an organic light emitting diode.

[0274] Reference Fig.26 , the light emitting element (e.g., an organic light emitting diode) may include a first light emitting unit EU1, a second light emitting unit EU2, and a third light emitting unit EU3 stacked sequentially. The first charge generation layer CGL1 may be disposed between the first light emitting unit EU1 and the second light emitting unit EU2, and the second charge generation layer CGL2 may be disposed between the second light emitting unit EU2 and the third light emitting unit EU3. Each of the first charge generation layer CGL1 and the second charge generation layer CGL2 may include a negative charge generation layer nCGL and a positive charge generation layer pCGL.

[0275] The first light emitting unit EU1 may include a blue light emitting layer BEML. The first light emitting unit EU1 may further include a hole injection layer HIL and a hole transport layer HTL between the pixel electrode 201 and the blue light emitting layer BEML. In an exemplary embodiment, a p-doped layer may be further included between the hole injection layer HIL and the hole transport layer HTL. The p-doped layer may be formed by doping the hole injection layer HIL with a p-type doping material. In an exemplary embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may be further included between the blue light emitting layer BEML and the hole transport layer HTL. The blue light auxiliary layer may improve the emission efficiency of the blue light emitting layer BEML. The blue light auxiliary layer may improve the emission efficiency of the blue light emitting layer BEML by adjusting the hole charge balance. The electron blocking layer may prevent electrons from being injected into the hole transport layer HTL. The buffer layer may compensate for the resonance distance according to the wavelength of light emitted from the light emitting layer.

[0276] The second light emitting unit EU2 may include a yellow light emitting layer YEML and a red light emitting layer REML directly contacting the yellow light emitting layer YEML below the yellow light emitting layer YEML. The second light emitting unit EU2 may further include a hole transport layer HTL between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red light emitting layer REML, and may further include an electron transport layer ETL between the yellow light emitting layer YEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0277] The third light-emitting unit EU3 may include a blue light-emitting layer BEML. The third light-emitting unit EU3 may also include a hole transport layer HTL between the positive charge generation layer pCGL of the second charge generation layer CGL2 and the blue light-emitting layer BEML. The third light-emitting unit EU3 may also include an electron transport layer ETL and an electron injection layer EIL between the blue light-emitting layer BEML and the common electrode 205. The electron transport layer ETL may be a single layer or a multilayer. In an exemplary embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may be further included between the blue light-emitting layer BEML and the hole transport layer HTL. At least one of a hole blocking layer and a buffer layer may also be included between the blue light-emitting layer BEML and the electron transport layer ETL. The hole blocking layer may prevent holes from being injected into the electron transport layer ETL.

[0278] Fig. 27 The light emitting element (eg, organic light emitting diode) shown in Fig.26 The light emitting element (eg, organic light emitting diode) shown in FIG. 1 is different from that in the stacked structure of the second light emitting unit EU2 and is similar to that in other configurations. Fig.26 The light emitting element (eg, organic light emitting diode) shown in FIG. Fig. 27 , the second light emitting unit EU2 may include a yellow light emitting layer YEML, a red light emitting layer REML directly contacting the yellow light emitting layer YEML below the yellow light emitting layer YEML, and a green light emitting layer GEML directly contacting the yellow light emitting layer YEML above the yellow light emitting layer YEML. The second light emitting unit EU2 may further include a hole transport layer HTL between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red light emitting layer REML, and may further include an electron transport layer ETL between the green light emitting layer GEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0279] Figures 28 to 36 1 and 2 are cross-sectional views for describing processes of a method of manufacturing the display device 10 according to an exemplary embodiment.

[0280] First, if Fig.28 As shown in , a substrate SUB having a first interlayer insulating film VA1 formed thereon may be prepared. Thereafter, a first pixel connection electrode PCE1, a first-first step electrode STE1-1, and a first-second step electrode STE1-2 may be formed on the first interlayer insulating film VA1. The first pixel connection electrode PCE1, the first-first step electrode STE1-1, and the first-second step electrode STE1-2 may be simultaneously formed using the same material.

[0281] Afterwards, if Fig.29As shown in, a second interlayer insulating film VA2 may be formed on the entire surface of a substrate SUB on which a first pixel connection electrode PCE1, a first-first step electrode STE1-1, and a first-second step electrode STE1-2 are formed. Next, a fourth contact hole CT4 penetrating the second interlayer insulating film VA2 may be formed. The first pixel connection electrode PCE1 of each pixel PX1, PX2, and PX3 may be exposed through the fourth contact hole CT4 of the second interlayer insulating film VA2. Subsequently, a second pixel connection electrode PCE2 and a second step electrode STE2 may be formed on the second interlayer insulating film VA2. The second pixel connection electrode PCE2 and the second step electrode STE2 may be formed simultaneously using the same material. In this case, the second pixel connection electrode PCE2 may be connected to the first pixel connection electrode PCE1 through the fourth contact hole CT4.

[0282] Next, if Fig.30 As shown in , a third interlayer insulating film VA3 may be formed on the entire surface of the substrate SUB on which the second pixel connection electrode PCE2 and the second step electrode STE2 are formed. Thereafter, a first contact hole CT1, a second contact hole CT2, and a third contact hole CT3 penetrating the third interlayer insulating film VA3 may be formed. The second pixel connection electrode PCE2 of the first pixel PX1 may be exposed through the first contact hole CT1 of the third interlayer insulating film VA3, the second pixel connection electrode PCE2 of the second pixel PX2 may be exposed through the second contact hole CT2 of the third interlayer insulating film VA3, and the second pixel connection electrode PCE2 of the third pixel PX3 may be exposed through the third contact hole CT3 of the third interlayer insulating film VA3. Subsequently, a first reflective electrode RE1, a second reflective electrode RE2, and a third reflective electrode RE3 may be formed on the third interlayer insulating film VA3. The first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 may be formed simultaneously using the same material. In this case, the first reflective electrode RE1 can be connected to the second pixel connection electrode PCE2 of the first pixel PX1 through the first contact hole CT1 of the third interlayer insulating film VA3, the second reflective electrode RE2 can be connected to the second pixel connection electrode PCE2 of the second pixel PX2 through the second contact hole CT2 of the third interlayer insulating film VA3, and the third reflective electrode RE3 can be connected to the second pixel connection electrode PCE2 of the third pixel PX3 through the third contact hole CT3 of the third interlayer insulating film VA3.

[0283] At the same time, if Fig.30As shown in, there may be no step electrode overlapping the first reflective electrode RE1 between the first reflective electrode RE1 and the first interlayer insulating film VA1 (for example, the uppermost insulating film of the first interlayer insulating film VA1), there may be a step electrode STE1-1 overlapping the second reflective electrode RE2 in the third direction DR3 between the second reflective electrode RE2 and the first interlayer insulating film VA1 (for example, the uppermost insulating film of the first interlayer insulating film VA1), and there may be two step electrodes STE1-2 and STE2 overlapping the third reflective electrode RE3 in the third direction DR3 between the third reflective electrode RE3 and the first interlayer insulating film VA1 (for example, the uppermost insulating film of the first interlayer insulating film VA1).

[0284] Since the numbers of stacked step electrodes disposed under the respective reflective electrodes RE1, RE2, and RE3 are different from each other as described above, the distances between the first interlayer insulating film VA1 (e.g., the uppermost insulating film of the first interlayer insulating film VA1) and the respective reflective electrodes RE1, RE2, and RE3 may be different from each other. Fig.30 As shown in, a distance d1 between the first interlayer insulating film VA1 (e.g., the uppermost insulating film of the first interlayer insulating film VA1) and the first reflective electrode RE1, a distance d2 between the first interlayer insulating film VA1 (e.g., the uppermost insulating film of the first interlayer insulating film VA1) and the second reflective electrode RE2, and a distance d3 between the first interlayer insulating film VA1 (e.g., the uppermost insulating film of the first interlayer insulating film VA1) and the third reflective electrode RE3 may be different from each other.

[0285] Next, if Fig.31 As shown in , a fourth interlayer insulating film VA4 may be formed on the entire surface of the substrate SUB on which the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 are formed. Thereafter, a fifth contact hole CT5 penetrating the fourth interlayer insulating film VA4 may be formed. The fifth contact hole CT5 may expose the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3, respectively. Next, a light-transmitting material layer TEM may be formed on the entire surface of the substrate SUB on which the fourth interlayer insulating film VA4 is formed. The light-transmitting material layer TEM may contact the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 through the fifth contact hole CT5. At this time, the light-transmitting material layer TEM may have a step due to a pattern (e.g., the first-first step electrode STE1-1, the first-second step electrode STE1-2, and the second step electrode STE2) disposed thereunder.

[0286] Then, if Fig.32As shown in , the light-transmitting material layer TEM can be planarized. The planarization process can be performed based on the lowest step portion of the light-transmitting material layer TEM. At the same time, the planarization process can be performed by chemical mechanical polishing (CMP). Through the planarization process, as Fig.32 As in the example shown in , the upper surface of the light-transmitting material layer TEM may be substantially parallel to the lower surface of the substrate SUB. Therefore, the thickness T1 of the light-transmitting material layer TEM overlapped with the first reflective electrode RE1 in the first emission area EA1, the thickness T2 of the light-transmitting material layer TEM overlapped with the second reflective electrode RE2 in the second emission area EA2, and the thickness T3 of the light-transmitting material layer TEM overlapped with the third reflective electrode RE3 in the third emission area EA3 may be different from each other.

[0287] Then, if Fig.33 As shown in , the light-transmitting material layer TEM may be patterned by photolithography and etching processes. By patterning the light-transmitting material layer TEM, a first light-transmitting electrode TE1, a second light-transmitting electrode TE2, and a third light-transmitting electrode TE3 separated from each other may be formed on the fourth interlayer insulating film VA4. The first light-transmitting electrode TE1 may be connected to the first reflective electrode RE1 through the fifth contact hole CT5 of the fourth interlayer insulating film VA4, the second light-transmitting electrode TE2 may be connected to the second reflective electrode RE2 through the fifth contact hole CT5 of the fourth interlayer insulating film VA4, and the third light-transmitting electrode TE3 may be connected to the third reflective electrode RE3 through the fifth contact hole CT5 of the fourth interlayer insulating film VA4. Therefore, a first pixel electrode PE1 including the first light-transmitting electrode TE1 and the first reflective electrode RE1, a second pixel electrode PE2 including the second light-transmitting electrode TE2 and the second reflective electrode RE2, and a third pixel electrode PE3 including the third light-transmitting electrode TE3 and the third reflective electrode RE3 may be formed.

[0288] Afterwards, if Fig.34 As shown in , a bank PDL defining the first, second, and third emission regions EA1, EA2, and EA3 may be formed on the first, second, and third light-transmitting electrodes TE1, TE2, and TE3.

[0289] Then, if Fig.35 As shown in , a light-providing layer EL may be formed on the first reflective electrode RE1 , the second reflective electrode RE2 , the third reflective electrode RE3 , and the bank PDL.

[0290] Next, if Fig.36As shown in , a common electrode CE may be formed on the light providing layer EL. In this case, the arrangement heights of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 are different from each other due to the step electrodes STE1-1, STE1-2, and STE2 described above, while the upper surface of the first light-transmitting electrode TE1, the upper surface of the second light-transmitting electrode TE2, and the upper surface of the third light-transmitting electrode TE3 are arranged at the same height by the planarization process of the light-transmitting material layer TEM described above. Therefore, the resonance distance rd1 between the common electrode CE and the first reflective electrode RE1, the resonance distance rd2 between the common electrode CE and the second reflective electrode RE2, and the resonance distance rd3 between the common electrode CE and the third reflective electrode RE3 may be different from each other.

[0291] On the other hand, although not shown, the display device 10 may be manufactured by forming the cap layer CPL, the encapsulation layer ENC, and the color filter layer CFL described above.

[0292] Fig.37 is an exploded perspective view illustrating a display device 10A according to an exemplary embodiment. Fig.38 It is shown Fig.37 Layout diagram of an example of a display panel 100A shown in FIG. Fig.39 is a block diagram illustrating a display device 10A according to an exemplary embodiment.

[0293] Reference Fig.37 and Fig.38 , the display device 10A according to the exemplary embodiment is a device for displaying a moving image or a still image. The display device 10A according to the exemplary embodiment can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). As an example, the display device 10A can be applied as a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device. Alternatively, the display device 10A can be applied to a smart watch, a watch phone, or a head-mounted display (HMD) for realizing virtual reality and augmented reality.

[0294] A display device 10A according to an exemplary embodiment includes a display panel 100A, a heat dissipation layer 200A, a circuit board 300A, and a driving circuit 400A.

[0295] The display panel 100A may have a shape similar to a quadrilateral shape in a plan view. For example, the display panel 100A may have a shape similar to a quadrilateral shape having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1 in a plan view. In the display panel 100A, the corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be rounded with a predetermined curvature or may be a right angle. The shape of the display panel 100A in a plan view is not limited to a quadrilateral, and may be a shape similar to other polygonal shapes, a circular shape, or an elliptical shape. The shape of the display device 10A in a plan view may follow the shape of the display panel 100A in a plan view, but exemplary embodiments of the present disclosure are not limited thereto.

[0296] like Fig.39 As shown in , the display panel 100A may include a display area DAA where an image is displayed and a non-display area NDA where no image is displayed.

[0297] The display area DAA includes a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines ECL, and a plurality of data lines DL.

[0298] Each of the plurality of pixels PX includes a light emitting element that emits light. The plurality of pixels PX may be arranged in a matrix form in a first direction DR1 and a second direction DR2. A plurality of scan lines SL and a plurality of emission control lines ECL may extend in the first direction DR1 and may be arranged in the second direction DR2. A plurality of data lines DL may extend in the second direction DR2 and may be arranged in the first direction DR1.

[0299] The plurality of scan lines SL include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines EBL. The plurality of emission control lines ECL include a plurality of first emission control lines ECL1 and a plurality of second emission control lines ECL2.

[0300] The plurality of unit pixels UPX include a plurality of pixels PX1, PX2 and PX3, for example, Figure 6 The plurality of pixels PX1, PX2 and PX3 may include Fig.40 The plurality of pixel transistors shown in FIG. 1 and FIG. 2 may be formed by a semiconductor process and may be disposed on a semiconductor substrate SSUB (see FIG. 2 ). Fig.42 For example, a plurality of pixel transistors may be formed as a complementary metal oxide semiconductor (CMOS).

[0301] Each of the plurality of pixels PX1, PX2, and PX3 may be connected to any one of the plurality of write scan lines GWL, any one of the plurality of control scan lines GCL, any one of the plurality of bias scan lines EBL, any one of the plurality of first emission control lines ECL1, any one of the plurality of second emission control lines ECL2, and any one of the plurality of data lines DL. Each of the plurality of pixels PX1, PX2, and PX3 may receive a data voltage of the data line DL according to a write scan signal of the write scan line GWL, and cause the light emitting element to emit light according to the data voltage.

[0302] The non-display area NDA includes a scan driving area SDA, a data driving area DDA and a pad area PDA. Fig.38 .

[0303] The scan driving area SDA may be an area in which the scan driver 610 and the emission driver 620 are disposed. Fig.38 6 shows that the scan driver 610 is disposed on the left side of the display area DAA and the emission driver 620 is disposed on the right side of the display area DAA, but the exemplary embodiments of the present disclosure are not limited thereto. For example, the scan driver 610 and the emission driver 620 may be disposed on both the left and right sides of the display area DAA.

[0304] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors may be formed by a semiconductor process and may be formed on a semiconductor substrate SSUB (see Fig.42 ). For example, a plurality of scanning transistors and a plurality of light emitting transistors may be formed as CMOS.

[0305] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing controller TC. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS of the timing controller TC, and sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal according to the scan timing control signal SCS, and sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal according to the scan timing control signal SCS, and sequentially output the bias scan signal to the bias scan line EBL.

[0306] The emission driver 620 includes a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 may receive an emission timing control signal ECS from the timing controller TC. The first emission control driver 621 may generate a first emission control signal according to the emission timing control signal ECS, and sequentially output the first emission control signal to the first emission control line ECL1. The second emission control driver 622 may generate a second emission control signal according to the emission timing control signal ECS, and sequentially output the second emission control signal to the second emission control line ECL2.

[0307] The data driving area DDA may be an area in which the data driver 700 is disposed. The data driver 700 may include a plurality of data transistors, which may be formed by a semiconductor process and may be formed on a semiconductor substrate SSUB (see Fig.42 For example, a plurality of data transistors may be formed as CMOS.

[0308] The data driver 700 may receive the digital video data DATA and the data timing control signal DCS from the timing controller TC. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS, and outputs the converted analog data voltage to the data line DL. In this case, the pixels PX1, PX2, and PX3 may be selected by the write scan signal of the scan driver 610, and the data voltage may be supplied to the selected pixels PX1, PX2, and PX3.

[0309] The pad area PDA includes a plurality of pads PD arranged in the first direction DR1. Each of the plurality of pads PD may be exposed without being covered by the cover layer CVL (see Fig.42 ) and a polarizing plate (not shown).

[0310] The heat dissipation layer 200A may overlap the display panel 100A in the third direction DR3 which is the thickness direction of the display panel 100A. The heat dissipation layer 200A may be provided on one surface (e.g., the rear surface) of the display panel 100A. The heat dissipation layer 200A is used to dissipate heat generated from the display panel 100A. The heat dissipation layer 200A may include a material having high thermal conductivity, such as graphite, silver (Ag), copper (Cu), or aluminum (Al).

[0311] The circuit board 300A may be electrically connected to the plurality of pads PD of the pad area PDA of the display panel 100A using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300A may be a flexible printed circuit board or a flexible film having a flexible material. Fig.37100A has been shown not to be bent, but the circuit board 300A may be bent. In this case, one end of the circuit board 300A may be disposed on the rear surface of the display panel 100A. The one end of the circuit board 300A may be an end opposite to the other end of the circuit board 300A connected to the plurality of pads PD of the pad area PDA of the display panel 100A using a conductive adhesive member.

[0312] The timing controller TC may receive digital video data DATA and a timing signal from the outside. The timing controller TC may generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100A according to the timing signal. The timing controller TC may output the scan timing control signal SCS to the scan driver 610 and the emission timing control signal ECS to the emission driver 620. The timing controller TC may output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0313] The power supply unit 500A may generate a plurality of panel driving voltages according to an external source voltage. For example, the power supply unit 500A may generate a first driving voltage VSS, a second driving voltage VDD, a third driving voltage VINT, and a reference voltage VREF, and supply the first driving voltage VSS, the second driving voltage VDD, the third driving voltage VINT, and the reference voltage VREF to the display panel 100. Fig.40 A first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT are described.

[0314] Each of the timing controller TC and the power supply unit 500A may be formed as an integrated circuit (IC) and attached to one surface of the circuit board 300A. The scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing controller TC may be supplied to the display panel 100A through the circuit board 300A. The first driving voltage VSS, the second driving voltage VDD, the third driving voltage VINT, and the reference voltage VREF of the power supply unit 500A may be supplied to the display panel 100A through the circuit board 300A.

[0315] Fig.40 is an equivalent circuit diagram of a first pixel PX1 according to an exemplary embodiment.

[0316] Reference Fig.40, the first pixel PX1 may be connected to the write scan line GWL, the control scan line GCL, the bias scan line EBL, the first emission control line ECL1, the second emission control line ECL2, and the data line DL. In addition, the first pixel PX1 may be connected to a first drive voltage line VSL, a second drive voltage line VDL, and a third drive voltage line VIL, the first drive voltage line VSL being applied with a first drive voltage VSS corresponding to a low potential voltage, the second drive voltage line VDL being applied with a second drive voltage VDD corresponding to a high potential voltage, and the third drive voltage line VIL being applied with a third drive voltage VINT corresponding to an initialization voltage. That is, the first drive voltage line VSL may be a low potential voltage line, the second drive voltage line VDL may be a high potential voltage line, and the third drive voltage line VIL may be an initialization voltage line. In this case, the first drive voltage VSS may be a voltage lower than the third drive voltage VINT. The second drive voltage VDD may be a voltage higher than the third drive voltage VINT.

[0317] The first pixel PX1 includes a plurality of transistors T1 to T6 , a light emitting element ED, a first capacitor C1 , and a second capacitor C2 .

[0318] The light emitting element ED emits light according to the driving current Ids flowing through the channel of the first transistor T1. The amount of light emitted from the light emitting element ED may be proportional to the driving current Ids. The light emitting element ED may be disposed between the fourth transistor T4 and the first driving voltage line VSL. The first electrode of the light emitting element ED may be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light emitting element ED may be connected to the first driving voltage line VSL. The first electrode of the light emitting element ED may be an anode electrode, and the second electrode of the light emitting element ED may be a cathode electrode. The light emitting element ED may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer disposed between the first electrode and the second electrode, but exemplary embodiments of the present disclosure are not limited thereto. For example, the light emitting element ED may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode, and in this case, the light emitting element ED may be a micro light emitting diode.

[0319] The first transistor T1 may be a driving transistor that controls a source-drain current Ids (hereinafter, referred to as a "driving current") flowing between a source electrode and a drain electrode according to a voltage applied to its gate electrode. The first transistor T1 includes a gate electrode connected to a first node N1, a source electrode connected to a drain electrode of the sixth transistor T6, and a drain electrode connected to a second node N2.

[0320] The second transistor T2 may be disposed between one electrode of the first capacitor C1 and the data line DL. The second transistor T2 is turned on by a write scan signal of the write scan line GWL to connect one electrode of the first capacitor C1 to the data line DL. Therefore, a data voltage of the data line DL may be applied to one electrode of the first capacitor C1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor C1.

[0321] The third transistor T3 may be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal of the control scan line GCL to connect the first node N1 to the second node N2. To this end, the gate electrode and the drain electrode of the first transistor T1 are connected to each other, so that the first transistor T1 can operate like a diode. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0322] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emission control signal of the first emission control line ECL1 to connect the second node N2 to the third node N3. To this end, the driving current Ids of the first transistor T1 may be supplied to the light emitting element ED. The fourth transistor T4 includes a gate electrode connected to the first emission control line ECL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0323] The fifth transistor T5 may be disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line EBL to connect the third node N3 to the third driving voltage line VIL. To this end, the third driving voltage VINT of the third driving voltage line VIL may be applied to the first electrode of the light emitting element ED. The fifth transistor T5 includes a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0324] The sixth transistor T6 may be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by the second emission control signal of the second emission control line ECL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. To this end, the second drive voltage VDD of the second drive voltage line VDL may be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line ECL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0325] The first capacitor C1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor C1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0326] The second capacitor C2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor C2 includes one electrode connected to the gate electrode of the first transistor T1 and the other electrode connected to the second driving voltage line VDL.

[0327] The first node N1 is a contact point between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor C1, and the one electrode of the second capacitor C2. The second node N2 is a contact point between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a contact point between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light emitting element ED.

[0328] Each of the first transistor T1 to the sixth transistor T6 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first transistor T1 to the sixth transistor T6 may be a P-type MOSFET, but the exemplary embodiments of the present disclosure are not limited thereto. Each of the first transistor T1 to the sixth transistor T6 may be an N-type MOSFET. Alternatively, some of the first transistor T1 to the sixth transistor T6 may be a P-type MOSFET, and the other transistors of the first transistor T1 to the sixth transistor T6 may be an N-type MOSFET.

[0329] exist Fig.40 It has been shown in FIG. 1 that the first pixel PX1 includes six transistors T1 to T6 and two capacitors C1 and C2, but it will be noted that the equivalent circuit diagram of the first pixel PX1 is not limited to Fig.40 For example, the number of transistors and capacitors of the first pixel PX1 is not limited to Fig.40 The number of transistors and capacitors shown in .

[0330] In addition, the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 can be compared with the reference Fig.40 The equivalent circuit diagram of the first pixel PX1 described is substantially the same. Therefore, the description of the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 is omitted in the present disclosure.

[0331] Fig.41 is a layout diagram showing pixels of a display area according to an exemplary embodiment.

[0332] Reference Fig.41 , each of the plurality of unit pixels UPX may include a first emission area EA1 as an emission area of ​​a first pixel PX1, a second emission area EA2 as an emission area of ​​a second pixel PX2, and a third emission area EA3 as an emission area of ​​a third pixel PX3.

[0333] Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a quadrilateral shape in a plan view, such as a rectangular shape, a square shape, or a diamond shape. For example, the first emission area EA1 may have a rectangular shape having a short side in the first direction DR1 and a long side in the second direction DR2 in a plan view. In addition, each of the second emission area EA2 and the third emission area EA3 may have a rectangular shape having a long side in the first direction DR1 and a short side in the second direction DR2 in a plan view.

[0334] The length of the first emission region EA1 in the first direction DR1 may be smaller than the length of the second emission region EA2 in the first direction DR1 and smaller than the length of the third emission region EA3 in the first direction DR1. The length of the second emission region EA2 in the first direction DR1 and the length of the third emission region EA3 in the first direction DR1 may be substantially the same as each other.

[0335] The length of the first emission region EA1 in the second direction DR2 may be greater than the sum of the lengths of the second emission region EA2 and the third emission region EA3 in the second direction DR2. The length of the second emission region EA2 in the second direction DR2 may be greater than the length of the third emission region EA3 in the second direction DR2.

[0336] exist Fig.41 It has been shown that each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 has a quadrilateral shape in a plan view, but the exemplary embodiments of the present disclosure are not limited thereto. For example, each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a polygonal shape other than a quadrilateral shape, a circular shape, or an elliptical shape in a plan view.

[0337] In each of the plurality of unit pixels UPX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the first direction DR1. In addition, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. In addition, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the second direction DR2. The area of ​​the first emission region EA1, the area of ​​the second emission region EA2, and the area of ​​the third emission region EA3 may be different from each other.

[0338] The first emission area EA1 may emit light of a first color, the second emission area EA2 may emit light of a second color, and the third emission area EA3 may emit light of a third color. Here, the light of the first color may be light of a red wavelength band, the light of the second color may be light of a green wavelength band, and the light of the third color may be light of a blue wavelength band. For example, the blue wavelength band may refer to a main peak wavelength of light included in a wavelength range of about 370nm to 460nm, the green wavelength band may refer to a main peak wavelength of light included in a wavelength range of about 480nm to 560nm, and the red wavelength band may refer to a main peak wavelength of light included in a wavelength range of about 600nm to 750nm.

[0339] exist Fig.41 It has been shown in FIG. 5 that each of the plurality of unit pixels UPX includes three emission areas EA1, EA2, and EA3, but exemplary embodiments of the present disclosure are not limited thereto. That is, each of the plurality of unit pixels UPX may also include four emission areas.

[0340] In addition, the arrangement of the emission regions of the plurality of unit pixels UPX is not limited to Fig.41 For example, the emission regions of the plurality of unit pixels UPX may be arranged in a stripe structure in which the emission regions are arranged in the first direction DR1, in which the emission regions have a diamond arrangement, or in which the emission regions have a diamond arrangement. structure or a hexagonal structure in which an emission region having a hexagonal shape in a plan view is arranged.

[0341] Fig.42 It is shown along Fig.41 A cross-sectional view of an example of a display device taken along line AA′.

[0342] Reference Fig.42 , the display panel 100 includes a semiconductor backplane SBP, a light emitting element backplane EBP, a light emitting element layer EMTL, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL and a polarizing plate.

[0343] The semiconductor backplane SBP may include a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating films covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR, respectively. Fig.40 The first transistor T1 to the sixth transistor T6 are described.

[0344] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate or a silicon germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type of impurity. A plurality of well regions may be provided in the upper surface of the semiconductor substrate SSUB. The plurality of well regions may be regions doped with a second type of impurity. The second type of impurity may be different from the first type of impurity described above. For example, when the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. Alternatively, when the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0345] Each of the plurality of well regions includes a source region S corresponding to a source electrode of the pixel transistor PTR, a drain region D corresponding to a drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region S and the drain region D.

[0346] Each of the source region S and the drain region D may be a region doped with first type impurities. The gate electrode GE of the pixel transistor PTR may overlap the well region in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region S may be disposed on one side of the gate electrode GE, and the drain region S may be disposed on the other side of the gate electrode GE.

[0347] Each of the plurality of well regions further includes a first low-concentration impurity region disposed between the channel region CH and the source region S and a second low-concentration impurity region disposed between the channel region CH and the drain region D. The first low-concentration impurity region may have an impurity concentration lower than that of the source region S. The second low-concentration impurity region may have an impurity concentration lower than that of the drain region D. The distance between the source region S and the drain region D may be increased by the first low-concentration impurity region and the second low-concentration impurity region. Therefore, the length of the channel region CH of each of the pixel transistors PTR may be increased, and therefore, punch-through and hot carrier phenomena caused by a short channel may be prevented.

[0348] The first semiconductor insulating film SINS1 may be disposed on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 may be formed as a silicon nitride (SiN)-based inorganic film or a silicon oxide (SiO x ) type inorganic film, but the exemplary embodiments of the present disclosure are not limited thereto.

[0349] The second semiconductor insulating film SINS2 may be provided on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 may be formed of silicon oxide (SiO x ) type inorganic film, but the exemplary embodiments of the present disclosure are not limited thereto.

[0350] A plurality of contact terminals CTE may be disposed on the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE may be connected to any one of the gate electrode GE, the source region S, and the drain region D of each of the pixel transistors PTR through a hole penetrating the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0351] The third semiconductor insulating film SINS3 may be disposed on a side surface of each of the plurality of contact terminals CTE. The upper surface of each of the plurality of contact terminals CTE may be exposed without being covered by the third semiconductor insulating film SINS3. The third semiconductor insulating film SINS3 may be formed of silicon oxide (SiO x ) type inorganic film, but the exemplary embodiments of the present disclosure are not limited thereto.

[0352] The semiconductor substrate SSUB may be replaced with a glass substrate or a polymer resin substrate (such as a polyimide substrate). In this case, the thin film transistor may be disposed on the glass substrate or the polymer resin substrate. The glass substrate may be a rigid substrate that is not bent, and the polymer resin substrate may be a flexible substrate that can be bent.

[0353] The light emitting element back plate EBP includes first to eighth metal layers ML1 to ML8, reflective electrodes RL1 to RL4, a plurality of via holes VIA1 to VIA10, and a step layer STPL. In addition, the light emitting element back plate EBP includes a plurality of interlayer insulating films INS1 to INS10 disposed between the first to eighth metal layers ML1 to ML8.

[0354] The first metal layer ML1 to the eighth metal layer ML8 are used to realize the Fig.40The circuit of the first pixel PX1 shown in FIG. That is, only the first transistor T1 to the sixth transistor T6 are formed in the semiconductor backplane SBP, and the connection between the first transistor T1 to the sixth transistor T6 and the formation of the first capacitor C1 and the second capacitor C2 are performed through the first metal layer ML1 to the eighth metal layer ML8. In addition, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light emitting element ED is also performed through the first metal layer ML1 to the eighth metal layer ML8.

[0355] The first interlayer insulating film INS1 may be disposed on the semiconductor backplane SBP. Each of the first vias VIA1 may penetrate the first interlayer insulating film INS1 to be connected to the contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first metal layers ML1 may be disposed on the first interlayer insulating film INS1 and connected to the first vias VIA1.

[0356] The second interlayer insulating film INS2 may be disposed on the first interlayer insulating film INS1 and the first metal layer ML1. Each of the second via holes VIA2 may penetrate the second interlayer insulating film INS2 to be connected to the exposed first metal layer ML1. Each of the second metal layers ML2 may be disposed on the second interlayer insulating film INS2 and connected to the second via holes VIA2.

[0357] The third interlayer insulating film INS3 may be disposed on the second interlayer insulating film INS2 and the second metal layer ML2. Each of the third via holes VIA3 may penetrate the third interlayer insulating film INS3 to be connected to the exposed second metal layer ML2. Each of the third metal layers ML3 may be disposed on the third interlayer insulating film INS3 and connected to the third via holes VIA3.

[0358] The fourth interlayer insulating film INS4 may be disposed on the third interlayer insulating film INS3 and the third metal layer ML3. Each of the fourth via holes VIA4 may penetrate the fourth interlayer insulating film INS4 to be connected to the exposed third metal layer ML3. Each of the fourth metal layers ML4 may be disposed on the fourth interlayer insulating film INS4 and connected to the fourth via holes VIA4.

[0359] The fifth interlayer insulating film INS5 may be disposed on the fourth interlayer insulating film INS4 and the fourth metal layer ML4. Each of the fifth via holes VIA5 may penetrate the fifth interlayer insulating film INS5 to be connected to the exposed fourth metal layer ML4. Each of the fifth metal layers ML5 may be disposed on the fifth interlayer insulating film INS5 and connected to the fifth via holes VIA5.

[0360] The sixth interlayer insulating film INS6 may be disposed on the fifth interlayer insulating film INS5 and the fifth metal layer ML5. Each of the sixth via holes VIA6 may penetrate the sixth interlayer insulating film INS6 to be connected to the exposed fifth metal layer ML5. Each of the sixth metal layers ML6 may be disposed on the sixth interlayer insulating film INS6 and connected to the sixth via holes VIA6.

[0361] The seventh interlayer insulating film INS7 may be disposed on the sixth interlayer insulating film INS6 and the sixth metal layer ML6. Each of the seventh via holes VIA7 may penetrate the seventh interlayer insulating film INS7 to be connected to the exposed sixth metal layer ML6. Each of the seventh metal layers ML7 may be disposed on the seventh interlayer insulating film INS7 and connected to the seventh via hole VIA7.

[0362] The eighth interlayer insulating film INS8 may be disposed on the seventh interlayer insulating film INS7 and the seventh metal layer ML7. Each of the eighth via holes VIA8 may penetrate the eighth interlayer insulating film INS8 to be connected to the exposed seventh metal layer ML7. Each of the eighth metal layers ML8 may be disposed on the eighth interlayer insulating film INS8 and connected to the eighth via holes VIA8.

[0363] The first metal layer ML1 to the eighth metal layer ML8 and the first via hole VIA1 to the eighth via hole VIA8 may be made of substantially the same material. Each of the first metal layer ML1 to the eighth metal layer ML8 and the first via hole VIA1 to the eighth via hole VIA8 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy thereof. The first via hole VIA1 to the eighth via hole VIA8 may be made of substantially the same material. The first interlayer insulating film INS1 to the eighth interlayer insulating film INS8 may be formed of silicon oxide (SiO x ) type inorganic film, but the exemplary embodiments of the present disclosure are not limited thereto.

[0364] Each of the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be greater than each of the thickness of the first via VIA1, the thickness of the second via VIA2, the thickness of the third via VIA3, the thickness of the fourth via VIA4, the thickness of the fifth via VIA5, and the thickness of the sixth via VIA6. Each of the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be greater than the thickness of the first metal layer ML1. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be substantially the same as each other. For example, the thickness of the first metal layer ML1 may be about 1000 Å. Each of the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be approximately And each of the thickness of the first via hole VIA1, the thickness of the second via hole VIA2, the thickness of the third via hole VIA3, the thickness of the fourth via hole VIA4, the thickness of the fifth via hole VIA5, and the thickness of the sixth via hole VIA6 may be about 1000 Å.

[0365] Each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than each of the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6. Each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than each of the thickness of the seventh via VIA7 and the thickness of the eighth via VIA8. Each of the thickness of the seventh via VIA7 and the thickness of the eighth via VIA8 may be greater than each of the thickness of the first via VIA1, the thickness of the second via VIA2, the thickness of the third via VIA3, the thickness of the fourth via VIA4, the thickness of the fifth via VIA5, and the thickness of the sixth via VIA6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be substantially the same as each other. For example, each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be approximately Each of the thickness of the seventh via hole VIA7 and the thickness of the eighth via hole VIA8 may be approximately

[0366] The ninth interlayer insulating film INS9 may be disposed on the eighth interlayer insulating film INS8 and the eighth metal layer ML8. The ninth interlayer insulating film INS9 may be formed of silicon oxide (SiO x ) type inorganic film, but the exemplary embodiments of the present disclosure are not limited thereto.

[0367] Each of the ninth via holes VIA9 may penetrate the ninth interlayer insulating film INS9 to be connected to the exposed eighth metal layer ML8. Each of the ninth via holes VIA9 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. The thickness of the ninth via hole VIA9 may be about

[0368] Each of the first reflective electrodes RL1 may be disposed on the ninth interlayer insulating film INS9 and connected to the ninth via hole VIA9. Each of the first reflective electrodes RL1 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0369] Each of the second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. Each of the second reflective electrodes RL2 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, each of the second reflective electrodes RL2 may be made of titanium nitride (TiN).

[0370] In the first pixel PX1, the step layer STPL may be disposed on the second reflective electrode RL2. The step layer STPL may not be disposed in each of the second pixel PX2 and the third pixel PX3. The thickness of the step layer STPL may be set in consideration of the wavelength of the light of the first color and the distance from the first light emitting layer of the first pixel PX1 to the fourth reflective electrode RL4, so as to facilitate reflection of the light of the first color emitted from the first light emitting layer of the first pixel PX1. The step layer STPL may be formed as a silicon nitride (SiN)-based inorganic film or a silicon oxide (SiO x ) type inorganic film, but the exemplary embodiments of the present disclosure are not limited thereto. The thickness of the step layer STPL may be about

[0371] In the first pixel PX1, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2 and the step layer STPL. In the second pixel PX2 and the third pixel PX3, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2. Each of the third reflective electrodes RL3 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0372] At least one of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3 may be omitted.

[0373] Each of the fourth reflective electrodes RL4 may be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 may be a layer that reflects light from the first to third intermediate layers IL1, IL2, and IL3. The fourth reflective electrode RL4 may include a metal having a high reflectivity to facilitate reflecting light. Each of the fourth reflective electrodes RL4 may be made of aluminum (Al), a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy (which is an alloy of silver (Ag), palladium (Pd), and copper (Cu)), and a stacked structure of an APC alloy and ITO (ITO / APC / ITO), but exemplary embodiments of the present disclosure are not limited thereto. The thickness of each of the fourth reflective electrodes RL4 may be about 1000 Å.

[0374] The tenth interlayer insulating film INS10 may be disposed on the ninth interlayer insulating film INS9 and the fourth reflective electrode RL4. The tenth interlayer insulating film INS10 may be formed of silicon oxide (SiO x ) type inorganic film, but the exemplary embodiments of the present disclosure are not limited thereto.

[0375] Each of the tenth via holes VIA10 may penetrate the tenth interlayer insulating film INS10 to be connected to the exposed fourth reflective electrode RL4. Each of the tenth via holes VIA10 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. Due to the step layer STPL, the thickness of the tenth via hole VIA10 in the first pixel PX1 may be less than the thickness of the tenth via hole VIA10 in each of the second pixel PX2 and the third pixel PX3. For example, the thickness of the tenth via hole VIA10 in the first pixel PX1 may be about And the thickness of the tenth via hole VIA10 in each of the second pixel PX2 and the third pixel PX3 may be about 1000 Å.

[0376] The light emitting element layer EMTL may be disposed on the light emitting element backplane EBP. The light emitting element layer EMTL may include a light emitting element, a pixel defining film PDL, and a plurality of trenches TRC, each of the light emitting elements including a first electrode AND, an intermediate layer IL, and a second electrode CAT.

[0377] The first electrode AND of each of the light emitting elements may be disposed on the tenth interlayer insulating film INS10 and connected to the tenth via hole VIA10. The first electrode AND of each of the light emitting elements may be connected to the drain region D or the source region S of the pixel transistor PTR through the tenth via hole VIA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth via holes VIA1 to VIA9, the first to eighth metal layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each of the light emitting elements may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, the first electrode AND of each of the light emitting elements may be made of titanium nitride (TiN).

[0378] The pixel defining film PDL may be disposed on a partial region of the first electrode AND of each of the light emitting elements. The pixel defining film PDL may cover an edge of the first electrode AND of each of the light emitting elements. The pixel defining film PDL is used to separate the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0379] The first emission area EA1 may be defined as an area in the first pixel PX1 where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked to emit light. The second emission area EA2 may be defined as an area in the second pixel PX2 where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked to emit light. The third emission area EA3 may be defined as an area in the third pixel PX3 where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked to emit light.

[0380] The pixel definition film PDL may include first to third pixel definition films PDL1, PDL2, and PDL3. The first pixel definition film PDL1 may be disposed on the edge of the first electrode AND of each of the light emitting elements, the second pixel definition film PDL2 may be disposed on the first pixel definition film PDL1, and the third pixel definition film PDL3 may be disposed on the second pixel definition film PDL2. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 may be formed of silicon oxide (SiO x) type inorganic film, but the exemplary embodiments of the present disclosure are not limited thereto. The thickness of the first pixel defining film PDL1, the thickness of the second pixel defining film PDL2, and the thickness of the third pixel defining film PDL3 may each be about

[0381] Each of the plurality of trenches TRC may penetrate the first, second, and third pixel defining films PDL1, PDL2, and PDL3. In each of the plurality of trenches TRC, the tenth interlayer insulating film INS10 may have a shape in which a portion thereof forms a trench.

[0382] At least one trench TRC may be provided between pixels PX1, PX2, and PX3 adjacent to each other. Fig.42 It has been shown in FIG. 5 that two trenches TRC are provided between the pixels PX1 , PX2 , and PX3 adjacent to each other, but exemplary embodiments of the present disclosure are not limited thereto.

[0383] The intermediate layer IL may include a first intermediate layer IL1 , a second intermediate layer IL2 , and a third intermediate layer IL3 .

[0384] The intermediate layer IL may have a series structure including a plurality of intermediate layers IL1, IL2, and IL3 emitting different lights. For example, the intermediate layer IL may include a first intermediate layer IL1 emitting light of a first color, a second intermediate layer IL2 emitting light of a third color, and a third intermediate layer IL3 emitting light of a second color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be sequentially stacked.

[0385] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic light emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic light emitting layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic light emitting layer emitting light of a second color, and a third electron transport layer are sequentially stacked.

[0386] A first charge generation layer for supplying charges to the second intermediate layer IL2 and electrons to the first intermediate layer IL1 may be disposed between the first intermediate layer IL1 and the second intermediate layer IL2. A second charge generation layer for supplying charges to the third intermediate layer IL3 and electrons to the second intermediate layer IL2 may be disposed between the second intermediate layer IL2 and the third intermediate layer IL3.

[0387] The first intermediate layer IL1 may be disposed on the first electrode AND and the pixel defining film PDL, and may be disposed on the bottom surface of each of the grooves TRC. Due to the groove TRC, the first intermediate layer IL1 may be disconnected between mutually adjacent pixels PX1, PX2, and PX3. The second intermediate layer IL2 may be disposed on the first intermediate layer IL1. Due to the groove TRC, the second intermediate layer IL2 may be disconnected between mutually adjacent pixels PX1, PX2, and PX3. The third intermediate layer IL3 may be disposed on the second intermediate layer IL2. Due to the groove TRC, the third intermediate layer IL3 may be disconnected between mutually adjacent pixels PX1, PX2, and PX3. That is, each of the plurality of grooves TRC may be a structure for disconnecting the first to third intermediate layers IL1, IL2, and IL3 of the light emitting element layer EMTL between mutually adjacent pixels PX1, PX2, and PX3.

[0388] In order to stably disconnect the first to third intermediate layers IL1, IL2, and IL3 of the light emitting element layer EMTL between the adjacent pixels PX1, PX2, and PX3, the height of each of the plurality of grooves TRC may be greater than the height of the pixel defining film PDL. The height of each of the plurality of grooves TRC refers to the length of each of the plurality of grooves TRC in the third direction DR3. The height of the pixel defining film PDL refers to the length of the pixel defining film PDL in the third direction DR3.

[0389] In order to disconnect the first to third intermediate layers IL1, IL2 and IL3 of the light emitting element layer EMTL between adjacent pixels PX1, PX2 and PX3, other structures may exist instead of the trench TRC. For example, instead of the trench TRC, a partition wall having an inverted tapered shape may be provided on the pixel defining film PDL.

[0390] The number of the intermediate layers IL1, IL2 and IL3 emitting different light is not limited to Fig.42 . For example, the intermediate layer IL may include two intermediate layers. In this case, any one of the two intermediate layers may be substantially the same as the first intermediate layer IL1, and the other of the two intermediate layers may include a second hole transport layer, a second organic light emitting layer, a third organic light emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to any one intermediate layer and supplying charges to the other intermediate layer may be provided between the two intermediate layers.

[0391] exist Fig.42It has been shown that the first to third intermediate layers IL1, IL2 and IL3 are all arranged in the first emission area EA1, the second emission area EA2 and the third emission area EA3, but the exemplary embodiments of the present disclosure are not limited to this. For example, the first intermediate layer IL1 may be arranged in the first emission area EA1, and may not be arranged in the second emission area EA2 and the third emission area EA3. In addition, the second intermediate layer IL2 may be arranged in the second emission area EA2, and may not be arranged in the first emission area EA1 and the third emission area EA3. In addition, the third intermediate layer IL3 may be arranged in the third emission area EA3, and may not be arranged in the first emission area EA1 and the second emission area EA2. In this case, the first to third color filters CF1, CF2 and CF3 of the optical layer OPL may be omitted.

[0392] The second electrode CAT may be disposed on the third intermediate layer IL3. The second electrode CAT may be disposed on the third intermediate layer IL3 in each of the plurality of grooves TRC. The second electrode CAT may be made of a transparent conductive material (TCO) (such as ITO or IZO) through which light can be transmitted, or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag)). When the second electrode CAT is made of a semi-transmissive conductive material, the emission efficiency of each of the first to third pixels PX1, PX2, and PX3 may be improved through a microcavity.

[0393] The encapsulation layer TFE may be disposed on the light emitting element layer EMTL. The encapsulation layer TFE may include at least one inorganic film TFE1 or TFE3 to prevent oxygen or moisture from penetrating into the light emitting element layer EMTL. In addition, the encapsulation layer TFE may include at least one organic film to protect the light emitting element layer EMTL from foreign matter such as dust. For example, the encapsulation layer TFE may include a first encapsulation inorganic film TFE1, an encapsulation organic film TFE2, and a second encapsulation inorganic film TFE3.

[0394] The first encapsulation inorganic film TFE1 may be disposed on the second electrode CAT, the encapsulation organic film TFE2 may be disposed on the first encapsulation inorganic film TFE1, and the second encapsulation inorganic film TFE3 may be disposed on the encapsulation organic film TFE2. The first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 may be formed as a silicon nitride (SiN x ) layer, silicon oxynitride (SiON) layer, silicon oxide (SiO x ) layer, titanium oxide (TiO x ) layer and aluminum oxide (AlO x) layers. The encapsulating organic film TFE2 may be made of a monomer. Alternatively, the encapsulating organic film TFE2 may be an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0395] The adhesive layer ADL may be a layer for bonding the encapsulation layer TFE and the optical layer OPL to each other. The adhesive layer ADL may be a double-sided adhesive member. In addition, the adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive or a transparent adhesive resin.

[0396] The optical layer OPL includes a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a filling layer FIL. The plurality of color filters CF1, CF2, and CF3 may include first to third color filters CF1, CF2, and CF3. The first to third color filters CF1, CF2, and CF3 may be disposed on the adhesive layer ADL.

[0397] The first color filter CF1 may overlap the first emission area EA1 of the first pixel PX1. The first color filter CF1 may transmit light of the first color (i.e., light of the blue wavelength band). The blue wavelength band may be about 370nm to 460nm. Therefore, the first color filter CF1 may transmit light of the first color among the light emitted from the first emission area EA1.

[0398] The second color filter CF2 may overlap the second emission area EA2 of the second pixel PX2. The second color filter CF2 may transmit light of the second color (i.e., light of the green wavelength band). The green wavelength band may be approximately 480 nm to 560 nm. Therefore, the second color filter CF2 may transmit light of the second color among the light emitted from the second emission area EA2.

[0399] The third color filter CF3 may overlap the third emission area EA3 of the third pixel PX3. The third color filter CF3 may transmit light of the third color (i.e., light of the red wavelength band). The red wavelength band may be approximately 600nm to 750nm. Therefore, the third color filter CF3 may transmit light of the third color among the light emitted from the third emission area EA3.

[0400] Each of the plurality of lenses LNS may be disposed on each of the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the plurality of lenses LNS may be a structure for increasing the ratio of light guided to the front surface of the display device 10A. Each of the plurality of lenses LNS may have a cross-sectional shape convex in an upward direction.

[0401] The filling layer FIL may be disposed on the plurality of lenses LNS. The filling layer FIL may have a predetermined refractive index so that light travels in a third direction DR3 at an interface between the plurality of lenses LNS and the filling layer FIL. In addition, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0402] The cover layer CVL may be disposed on the filling layer FIL. The cover layer CVL may be a glass substrate or a polymer resin such as resin. When the cover layer CVL is a glass substrate, the cover layer CVL may be attached to the filling layer FIL. In this case, the filling layer FIL may be used to adhere the cover layer CVL. When the cover layer CVL is a glass substrate, the cover layer CVL may be used as a packaging substrate. When the cover layer CVL is a polymer resin such as resin, the cover layer CVL may be directly applied to the filling layer FIL.

[0403] The polarizing plate may be disposed on one surface of the cover layer CVL. The polarizing plate may be a structure for preventing visibility degradation caused by external light reflection. The polarizing plate may include a linear polarizing plate and a phase delay film. For example, the phase delay film may be a λ / 4 plate (quarter wave plate), but the exemplary embodiments of the present disclosure are not limited thereto. However, when visibility degradation caused by external light reflection is sufficiently improved by the first to third color filters CF1, CF2, and CF3, the polarizing plate may be omitted.

[0404] Fig.43 is a perspective view showing a head mounted display device 1000 according to an exemplary embodiment. Fig.44 It is a commentary Fig.43 1 is an exploded perspective view of an example of a head mounted display device 1000.

[0405] Reference Fig.43 and Fig.44 According to an exemplary embodiment, a head-mounted display device 1000 as an optical device includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, optical path changing members 1210, 1220, 1510 and 1520, a head-mounted band 1300, an intermediate frame 1400, a control circuit board 1600 and a connector (not shown).

[0406] The optical path changing member may include a first eyepiece 1210 , a second eyepiece 1220 , a first optical member 1510 , and a second optical member 1520 .

[0407] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Each of the first display device 10_1 and the second display device 10_2 is connected to the reference Figures 37 to 42 The display devices 10A described are substantially the same, and thus descriptions of the first display device 10_1 and the second display device 10_2 are omitted.

[0408] The first optical member 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0409] The middle frame 1400 may be disposed between the first display device 10_1 and the control circuit board 1600, and between the second display device 10_2 and the control circuit board 1600. The middle frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0410] The control circuit board 1600 may be disposed between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA, and transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 through the connector.

[0411] The control circuit board 1600 may transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1 and transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 1600 may transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0412] The display device housing 1100 is used to accommodate the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, the control circuit board 1600 and the connector. The housing cover 1200 is provided to cover one open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 and a second eyepiece 1220, the first eyepiece 1210 is provided on the left eye of the user, and the second eyepiece 1220 is provided on the right eye of the user. Fig.43 and Fig.4412 has shown that the first eyepiece 1210 and the second eyepiece 1220 are separately provided, but exemplary embodiments of the present disclosure are not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one eyepiece.

[0413] The first eyepiece 1210 may be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 10_2 and the second optical member 1520. Therefore, the user may view the image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and view the image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0414] The head-mounted strap 1300 is used to fix the display device housing 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 can be maintained in a state where they are respectively disposed on the left eye and the right eye of the user. When the display device housing 1200 is implemented to have a light weight and a small size, the head-mounted display device 1000 may include a Fig.45 , rather than a headband 1300, is shown in FIG.

[0415] In addition, the head mounted display device 1000 may further include a battery for power supply, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a wireless fidelity (WiFi) module, or a Bluetooth module.

[0416] Fig.45 is a perspective view illustrating a head mounted display device 1000_1 according to an exemplary embodiment.

[0417] Reference Fig.45 The head mounted display device 1000_1 as an optical device according to an exemplary embodiment may be a glasses type display device in which the display device housing 1200_1 is implemented as a light-weight and small-sized display device. The head mounted display device 1000_1 according to an exemplary embodiment may include a display device 10-3, a left-eye lens 1010, a right-eye lens 1020, a support frame 1030, glasses frame legs 1040 and 1050, an optical member 1060, an optical path changing member 1070, and a display device housing 1200_1.

[0418] The display device housing 1200_1 may house the display device 10_3, the optical member 1060, and the optical path changing member 1070. The image displayed on the display device 10_3 may be enlarged by the optical member 1060, the optical path may be changed by the optical path changing member 1070, and supplied to the right eye of the user through the right eye lens 1020. For this reason, the user may view an augmented reality image in which a virtual image displayed on the display device 10_3 seen through his / her right eye and a real image seen through the right eye lens 1020 are combined with each other.

[0419] exist Fig.45 1030, but the exemplary embodiments of the present disclosure are not limited thereto. For example, the display device housing 1200_1 may be disposed at the left end of the support frame 1030, and in this case, the image of the display device 10_3 may be supplied to the left eye of the user. Alternatively, the display device housing 1200_1 may be disposed at both the left and right ends of the support frame 1030, and in this case, the user may view the image displayed on the display device 10_3 through both his / her left eye and right eye.

[0420] It will be understood by those skilled in the art that the present disclosure may be implemented in other specific forms without changing the technical spirit or basic features of the present disclosure. Therefore, it will be understood that the exemplary embodiments described above are illustrative rather than restrictive in all aspects. It will be understood that the scope of the present disclosure is defined by the claims rather than the detailed description described above, and all modifications and changes derived from the claims and their equivalents fall within the scope of the present disclosure.

Claims

1. A display device, comprising: substrate; a bank disposed on the substrate and defining a plurality of emission regions; A plurality of pixel electrodes are arranged in the plurality of emission regions; as well as at least one step electrode, disposed between the pixel electrode of at least one emission region and the substrate, Wherein, in each emission area, the number of step electrodes between each pixel electrode and the substrate is different from each other.

2. The display device according to claim 1, wherein: The number of step electrodes is the number of step electrodes stacked on different layers with insulating films interposed therebetween in each emission region.

3. The display device according to claim 1, wherein: The multiple emission regions provide light of different colors. 4 . The display device according to claim 1 , further comprising a power line connected to the at least one step electrode.

5. The display device according to claim 1, wherein: The at least one step electrode is a floating electrode. 6 . The display device according to claim 1 , further comprising a pixel connection electrode connected to the pixel electrode of the at least one emission region.

7. The display device according to claim 6, wherein: The at least one step electrode is connected to the pixel connection electrode. 8 . The display device of claim 1 , further comprising a plurality of color filters disposed to correspond to the plurality of emission regions and providing light of different colors.

9. The display device according to claim 1, wherein: Each pixel electrode of the plurality of pixel electrodes comprises: a reflective electrode, disposed on the substrate; and The light-transmitting electrode is disposed on the reflective electrode and connected to the reflective electrode through a contact hole of the insulating film.

10. The display device according to claim 9, wherein: The at least one step electrode is disposed between the reflective electrode of the at least one emitting region and the substrate.

11. The display device according to claim 10, wherein: In each emission region, the number of step electrodes between each reflection electrode and the substrate is different from each other.

12. The display device according to claim 9, wherein: In each light emitting region, the thickness of each light-transmitting electrode is different from each other.

13. The display device according to claim 9, further comprising: A common electrode, disposed on the plurality of light-transmitting electrodes of the plurality of pixel electrodes; as well as The light-providing layer is disposed between the plurality of light-transmitting electrodes of the plurality of pixel electrodes and the common electrode.

14. The display device according to claim 13, wherein: In each emission region, the distances between each reflective electrode and the common electrode are different from each other.

15. The display device according to claim 9, wherein: The at least one step electrode comprises: A first step electrode is arranged between the substrate and the reflective electrode; The second step electrode is arranged between the first step electrode and the reflective electrode.

16. The display device according to claim 15, further comprising: A first pixel connection electrode is arranged on the same layer as the first step electrode on the substrate; as well as The second pixel connection electrode is disposed on the first pixel connection electrode to be disposed on the same layer as the second step electrode, and is connected to the first pixel connection electrode and the reflective electrode through a contact hole of the insulating film.

17. The display device according to claim 16, wherein: The first step electrode is connected to the first pixel connection electrode.

18. The display device according to claim 17, wherein: The first step electrode is integrated with the first pixel connecting electrode.

19. The display device according to claim 16, wherein: The second step electrode is connected to the second pixel connection electrode.

20. The display device according to claim 19, wherein: The second step electrode is integrated with the second pixel connecting electrode.

21. The display device according to claim 16, wherein: The second step electrode is connected to the first step electrode through a contact hole of the insulating film.

22. The display device according to claim 16, wherein: The first step electrode is connected to another first step electrode provided in another emission region.

23. A display device, comprising: substrate; a bank disposed on the substrate and defining a plurality of emission regions; A plurality of pixel electrodes are arranged in the plurality of emission regions; as well as At least one step electrode overlaps with at least one pixel electrode of the emission area, The number of step electrodes in each emission region is different from each other.

24. The display device according to claim 23, wherein: The number of step electrodes is the number of step electrodes stacked on different layers with insulating films interposed therebetween in each emission region.

25. The display device according to claim 23, wherein: The multiple emission regions provide light of different colors. 26 . The display device according to claim 23 , further comprising a power line connected to the at least one step electrode.

27. The display device according to claim 23, wherein: The at least one step electrode is a floating electrode.

28. The display device according to claim 23, further comprising a pixel connection electrode connected to the pixel electrode of the at least one emission region.

29. The display device according to claim 28, wherein: The at least one step electrode is connected to the pixel connection electrode.

30. A method for manufacturing a display device, the method comprising the following steps: Prepare the substrate; forming different numbers of step electrodes in a plurality of emission regions on the substrate; forming a first insulating film on the step electrode; as well as A plurality of pixel electrodes are formed on the first insulating film so as to overlap with at least one of the step electrodes.

31. The manufacturing method according to claim 30, wherein: The number of step electrodes is the number of step electrodes stacked on different layers with insulating films interposed therebetween in each emission region.

32. The manufacturing method according to claim 30, wherein: The multiple emission regions provide light of different colors.

33. The manufacturing method according to claim 30, wherein: The step of forming the plurality of pixel electrodes comprises: forming a plurality of reflective electrodes on the first insulating film in a manner overlapping with the at least one step electrode among the step electrodes; forming a second insulating film on the plurality of reflective electrodes; forming a plurality of contact holes in the second insulating film; forming a light-transmitting material layer on the second insulating film in a manner overlapping with and connected to the plurality of reflective electrodes; planarizing the light-transmitting material layer; and A plurality of light-transmitting electrodes respectively connected to the plurality of reflective electrodes are formed by patterning the light-transmitting material layer.

34. The manufacturing method according to claim 33, wherein: The step of planarizing the light-transmitting material layer is performed by chemical mechanical polishing.

35. The manufacturing method according to claim 30 further comprises forming a plurality of pixel connection electrodes, wherein the plurality of pixel connection electrodes are respectively connected to the plurality of pixel electrodes and are arranged in a layer different from the pixel electrodes and an insulating film is placed between the pixel electrodes and the pixel connection electrodes.

36. The manufacturing method according to claim 35, wherein: Among the step electrode and the plurality of pixel connection electrodes, the step electrode and the pixel connection electrode provided in the same layer are connected to each other.

37. An optical device, comprising: Display device; as well as an optical path changing member, arranged on the display device, Wherein, the display device comprises: substrate; a bank disposed on the substrate and defining a plurality of emission regions; a plurality of pixel electrodes disposed in the plurality of emission regions; and at least one step electrode is disposed between the pixel electrode of at least one emission area and the substrate, and In each emission area, the number of step electrodes between each pixel electrode and the substrate is different from each other.

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