Display device

Abstract

The present disclosure relates to a display device, and more particularly, to a display device capable of improving the holding force of a spacer. The display device may include a substrate, a transistor on the substrate, a first electrode connected to the transistor, and a spacer disposed on the first electrode, where the spacer overlaps a connection portion between the transistor and the first electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0100095 filed in the Korean Intellectual Property Office on July 31, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device capable of improving a holding force of a spacer. Background Art

[0004] A head mounted display (HMD) is an image display device that is worn on the user's head in the form of glasses or a helmet and focuses at a short distance in front of the user's eyes. The head mounted display can be used for virtual reality (VR) or augmented reality (AR) devices.

[0005] A head-mounted display uses multiple lenses to magnify and display an image displayed on a small display device. Therefore, the display device applied to the head-mounted display needs to provide a high-resolution image, for example, an image with a resolution of 3000 pixels per inch (PPI) or higher. For this reason, an organic light-emitting diode on silicon (OLEDoS), which is a high-resolution, small organic light-emitting display device, is used as a display device applied to a head-mounted display. OLEDoS is a device that displays an image by disposing an organic light-emitting diode (OLED) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is disposed. Summary of the invention

[0006] Aspects of the present disclosure provide a display device capable of improving a holding force of a spacer.

[0007] However, the aspects of the present disclosure are not limited to those described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art by referring to the detailed description of the present disclosure given below.

[0008] Various benefits of the present disclosure will be apparent to those skilled in the art from the following description.

[0009] According to an embodiment of the present disclosure, a display device includes a substrate, a transistor on the substrate, a first electrode connected to the transistor, and a spacer disposed on the first electrode, wherein the spacer overlaps a connection portion between the transistor and the first electrode.

[0010] In an implementation, the display device may further include an insulating layer between the transistor and the first electrode, wherein the connection portion extends through a contact hole in the insulating layer.

[0011] In an implementation, the spacer may overlap the contact hole.

[0012] In an implementation, the first electrode may be disposed in the contact hole.

[0013] In an implementation, the spacer may surround the first electrode in a plan view and overlap a connection portion between the transistor and the first electrode.

[0014] In an embodiment, the spacer may include a first sub-spacer disposed between the first electrodes of adjacent rows and a second sub-spacer disposed between adjacent first sub-spacers and overlapping a connection portion between the transistor and the first electrode.

[0015] In an embodiment, the first sub-spacer may extend in a row direction, and wherein the second sub-spacer extends in a column direction crossing the row direction.

[0016] In an implementation, the second sub-spacer may be connected to an adjacent first sub-spacer.

[0017] In an implementation, the second sub-spacer and the first sub-spacer may be integrally formed.

[0018] In an implementation, the first sub-spacer may have a zigzag form.

[0019] In an embodiment, a plurality of second sub-spacers may be disposed between adjacent first sub-spacers.

[0020] In an implementation, the first electrode may be disposed in a region surrounded and defined by adjacent first sub-spacers and adjacent second sub-spacers.

[0021] In an implementation, the display device may further include a pixel defining layer disposed between the first electrode and the spacer.

[0022] In an embodiment, the connection portion may extend through a contact hole in the insulating layer between the transistor and the first electrode, wherein a top surface of the pixel defining layer is at the same distance from the substrate in an overlapping region and a non-overlapping region with the contact hole.

[0023] In an implementation, the pixel defining layer may have a groove surrounding the first electrode.

[0024] In embodiments, the spacer may surround the trench.

[0025] In an implementation, the spacer and the pixel defining layer may be integrally formed.

[0026] In an implementation, the display device may further include a partition wall disposed on the pixel defining layer.

[0027] In an implementation, the partition wall may include a lower layer on the pixel defining layer, and an upper layer on the lower layer.

[0028] In an implementation, the display device may further include a heating electrode on the spacer.

[0029] In an implementation, the heating electrode may be disposed in a contact hole extending through the spacer and the pixel defining layer.

[0030] In an implementation, the spacer may have a black color.

[0031] In an embodiment, the display device may further include an intermediate layer on the first electrode, and a second electrode on the intermediate layer.

[0032] According to the display device according to the present disclosure, the holding force of the spacer can be improved.

[0033] In addition, a difference in reflectivity between a region where a contact hole is placed and a region where no contact hole is placed is minimized, thereby improving image quality.

[0034] Also, since the spacer has a black color, external light reflection can be minimized, thereby improving image quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0036] Figure 1 is an exploded perspective view showing a display device according to an embodiment;

[0037] Figure 2 It is shown Figure 1 An example layout diagram of a display panel shown in FIG.

[0038] Figure 3 is a block diagram showing a display device according to an embodiment;

[0039] Figure 4 is an equivalent circuit diagram of a first pixel according to an embodiment;

[0040] Figure 5 is a layout diagram showing pixels of a display area according to an embodiment;

[0041] Figure 6 is shown along Figure 5 A cross-sectional view of an example of a display device taken along line AA';

[0042] Figure 7 is a perspective view showing a head mounted display device according to an embodiment;

[0043] Figure 8 It is shown Figure 7 An exploded perspective view of an example of a head mounted display device;

[0044] Fig. 9 is a perspective view showing a head mounted display device according to an embodiment;

[0045] Fig.10 is a plan view of a display device according to an embodiment;

[0046] Fig.11 yes Fig.10 an enlarged view of part A;

[0047] Fig.12 is along Fig.11 A cross-sectional view of the display device taken along line II';

[0048] Fig.13 is a plan view of a display device according to an embodiment;

[0049] Fig.14 yes Fig.13 an enlarged view of part B;

[0050] Fig.15 is along Fig.14 A cross-sectional view of the display device taken along line II-II';

[0051] Fig.16 is a plan view of a display device according to an embodiment;

[0052] Fig.17 yes Fig.16 an enlarged view of part C;

[0053] Fig.18 is along Fig.17 A cross-sectional view of the display device taken along line III-III'; and

[0054] Fig.19 is a cross-sectional view of a display device according to an embodiment. DETAILED DESCRIPTION

[0055] The features of the present disclosure and methods for implementing them will become apparent through the description of exemplary embodiments with reference to the accompanying drawings hereinafter. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but can be implemented in various different ways. Exemplary embodiments are provided to make the disclosure of the present disclosure thorough and to fully convey the scope of the present disclosure to those skilled in the art. The scope of the present disclosure is limited only by the claims.

[0056] As used herein, the phrase "element A on element B" means that element A may be directly disposed on element B and / or element A may be indirectly disposed on element B via another element C. Throughout the description, the same reference numerals represent the same elements. The figures, dimensions, proportions, angles, and numbers of elements given in the drawings are illustrative only and not limiting.

[0057] Ordinal terms such as first, second, etc. are used to arbitrarily distinguish between elements, and do not necessarily indicate the time or other priority of such elements. These terms are only used to distinguish one element from another element. Accordingly, as used herein, the first element and the second element are interchangeable within the technical scope of the present disclosure. As used herein, element A and element B "overlap" is intended to mean that one element partially or completely covers another element, and the two elements may or may not directly contact.

[0058] The features of the various exemplary embodiments of the present disclosure may be combined in part or in whole. As will be clearly understood by those skilled in the art, various interactions and operations are technically possible. The various exemplary embodiments can be practiced individually or in combination.

[0059] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0060] Figure 1 is an exploded perspective view showing a display device according to an embodiment. Figure 2 It is shown Figure 1 Layout diagram of an example of a display panel shown in . Figure 3 is a block diagram showing a display device according to an embodiment.

[0061] Reference Figure 1 and Figure 2 , the display device 10 according to the embodiment is a device for displaying a moving image or a still image. The display device 10 according to the exemplary embodiment may be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs). For example, the display device 10 may be applied to a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device. Alternatively, the display device 10 may be applied to a smart watch, a watch phone, and a head-mounted display (HMD) for realizing virtual reality and augmented reality.

[0062] The display device 10 according to the embodiment includes a display panel 100 , a heat dissipation layer 200 , a circuit board 300 , a timing control circuit 400 , and a power supply circuit 500 .

[0063] The display panel 100 may be formed in a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. In the display panel 100, corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be rounded to have a predetermined curvature or may be formed as a right angle. The planar shape of the display panel 100 is not limited to a quadrilateral, and may be formed similarly to other polygons, circles, or ellipses. The planar shape of the display device 10 may follow the planar shape of the display panel 100, but embodiments of the present specification are not limited thereto.

[0064] like Figure 2 As shown in , the display panel 100 includes a display area DAA where an image is displayed and a non-display area NDA where no image is displayed.

[0065] The display area DAA includes a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0066] Each of the plurality of pixels PX includes a light emitting element that emits light. The plurality of pixels PX may be arranged in a matrix form in a first direction DR1 and a second direction DR2. A plurality of scan lines SL and a plurality of emission control lines EL may extend in the first direction DR1 and may be arranged in the second direction DR2. A plurality of data lines DL may extend in the second direction DR2 and may be arranged in the first direction DR1.

[0067] The plurality of scan lines SL include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines EBL. The plurality of emission control lines EL include a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0068] Each of the plurality of unit pixels UPX (see Figure 5 ) includes a plurality of pixels PX1, PX2 and PX3 (see Figure 6 ). The plurality of pixels PX1, PX2 and PX3 may include Figure 4 The plurality of pixel transistors shown in the figure may be formed by a semiconductor process and may be disposed on a semiconductor substrate ( Figure 6 For example, a plurality of pixel transistors may be formed by a complementary metal oxide semiconductor (CMOS).

[0069] Each of the plurality of pixels PX1, PX2, and PX3 may be connected to any one of the plurality of write scan lines GWL, any one of the plurality of control scan lines GCL, any one of the plurality of bias scan lines EBL, any one of the plurality of first emission control lines EL1, any one of the plurality of second emission control lines EL2, and any one of the plurality of data lines DL. Each of the plurality of pixels PX1, PX2, and PX3 may receive a data voltage of the data line DL according to a write scan signal of the write scan line GWL, and may emit light from the light emitting element according to the data voltage.

[0070] The non-display area NDA includes a scan driving area SDA, a data driving area DDA, and a pad area PDA.

[0071] The scan driving area SDA may be an area in which the scan driver 610 and the emission driver 620 are disposed. Figure 2 , the scan driver 610 is shown to be disposed on the left side of the display area DAA, and the emission driver 620 is disposed on the right side of the display area DAA, but the embodiments of the present specification are not limited thereto. For example, the scan driver 610 and the emission driver 620 may be disposed on both the left and right sides of the display area DAA.

[0072] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors may be formed by a semiconductor process and may be formed on a semiconductor substrate ( Figure 6 For example, a plurality of scanning transistors and a plurality of light emitting transistors may be formed by CMOS.

[0073] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS of the timing control circuit 400 and sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal according to the scan timing control signal SCS and sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal according to the scan timing control signal SCS and sequentially output the bias scan signal to the bias scan line EBL.

[0074] The emission driver 620 includes a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 may receive an emission timing control signal ECS from the timing control circuit 400. The first emission control driver 621 may generate a first emission control signal according to the emission timing control signal ECS and sequentially output the first emission control signal to the first emission control line EL1. The second emission control driver 622 may generate a second emission control signal according to the emission timing control signal ECS and sequentially output the second emission control signal to the second emission control line EL2.

[0075] The data driving area DDA may be an area in which the data driver 700 is disposed. The data driver 700 may include a plurality of data transistors, and the plurality of data transistors may be formed by a semiconductor process and may be formed on a semiconductor substrate ( Figure 6 For example, a plurality of data transistors may be formed of CMOS.

[0076] The data driver 700 may receive the digital video data DATA and the data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the converted analog data voltage to the data line DL. In this case, the pixels PX1, PX2, and PX3 may be selected by the write scan signal of the scan driver 610, and the converted analog data voltage may be supplied to the selected pixels PX1, PX2, and PX3.

[0077] The pad area PDA includes a plurality of pads PD arranged in the first direction DR1. Each of the plurality of pads PD may be exposed without being covered by the cover layer ( Figure 6 The CVL in the embodiment of the present invention and the polarizing plate (not shown) are covered.

[0078] The heat dissipation layer 200 may overlap the display panel 100 in the third direction DR3 which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be provided on one surface (e.g., the rear surface) of the display panel 100. The heat dissipation layer 200 serves to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a layer having high thermal conductivity including a metal material such as graphite, or silver (Ag), copper (Cu), or aluminum (Al).

[0079] The circuit board 300 may be electrically connected to the plurality of pads PD of the pad area PDA of the display panel 100 by using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be a flexible printed circuit board having a flexible material or a flexible film. Figure 1The circuit board 300 is depicted in an unfolded state, but the circuit board 300 may be bendable. In the bent state, one end of the circuit board 300 may be disposed on the rear surface of the display panel 100. The one end of the circuit board 300 may be an opposite end of the other end of the circuit board 300 connected to the plurality of pads PD of the pad area PDA of the display panel 100 by using a conductive adhesive member.

[0080] The timing control circuit 400 may receive digital video data DATA and a timing signal from the outside. The timing control circuit 400 may generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 according to the timing signal. The timing control circuit 400 may output the scan timing control signal SCS to the scan driver 610 and the emission timing control signal ECS to the emission driver 620. The timing control circuit 400 may output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0081] The power supply circuit 500 may generate a plurality of panel driving voltages according to an external power supply voltage. For example, the power supply circuit 500 may generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT and supply them to the display panel 100. Figure 4 A first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT are described.

[0082] Each of the timing control circuit 400 and the power supply circuit 500 may be formed as an integrated circuit (IC) and attached to one surface of the circuit board 300. The scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 may be supplied to the display panel 100 through the circuit board 300. The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 may be supplied to the display panel 100 through the circuit board 300.

[0083] Figure 4 is an equivalent circuit diagram of a first pixel according to an embodiment.

[0084] Reference Figure 4, the first pixel PX1 may be connected to the write scan line GWL, the control scan line GCL, the bias scan line EBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. In addition, the first pixel PX1 may be connected to a first drive voltage line VSL to which a first drive voltage VSS corresponding to a low potential voltage is applied, a second drive voltage line VDL to which a second drive voltage VDD corresponding to a high potential voltage is applied, and a third drive voltage line VIL to which a third drive voltage VINT corresponding to an initialization voltage is applied. That is, the first drive voltage line VSL may be a low potential voltage line, the second drive voltage line VDL may be a high potential voltage line, and the third drive voltage line VIL may be an initialization voltage line. In this case, the first drive voltage VSS may be a voltage lower than the third drive voltage VINT. The second drive voltage VDD may be a voltage higher than the third drive voltage VINT.

[0085] The first pixel PX1 includes a plurality of transistors T1 to T6 , a light emitting element ED, a first capacitor C1 , and a second capacitor C2 .

[0086] The light emitting element ED emits light according to the driving current Ids flowing through the channel of the first transistor T1. The amount of light emitted from the light emitting element ED may be proportional to the driving current Ids. The light emitting element ED may be disposed between the fourth transistor T4 and the first driving voltage line VSL. The first electrode of the light emitting element ED may be connected to the drain electrode of the fourth transistor T4, and the second electrode thereof may be connected to the first driving voltage line VSL. The first electrode of the light emitting element ED may be an anode electrode, and the second electrode of the light emitting element ED may be a cathode electrode. The light emitting element ED may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer disposed between the first electrode and the second electrode, but the embodiments of the present specification are not limited thereto. For example, the light emitting element ED may be an inorganic light emitting device including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. In this case, the light emitting element ED may be a micro light emitting diode.

[0087] The first transistor T1 may be a driving transistor that controls a source-drain current Ids (hereinafter referred to as a "driving current") flowing between a source electrode and a drain electrode according to a voltage applied to a gate electrode. The first transistor T1 includes a gate electrode connected to a first node N1, a source electrode connected to a drain electrode of a sixth transistor T6, and a drain electrode connected to a second node N2.

[0088] The second transistor T2 may be disposed between one electrode of the first capacitor C1 and the data line DL. The second transistor T2 is turned on by a write scan signal of the write scan line GWL, and connects one electrode of the first capacitor C1 to the data line DL. Accordingly, a data voltage of the data line DL may be applied to one electrode of the first capacitor C1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor C1.

[0089] The third transistor T3 may be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal of the control scan line GCL, and connects the first node N1 to the second node N2. Accordingly, since the gate electrode and the drain electrode of the first transistor T1 are connected, the first transistor T1 may operate like a diode. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0090] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emission control signal of the first emission control line EL1, and connects the second node N2 to the third node N3. Accordingly, the driving current Ids of the first transistor T1 may be supplied to the light emitting element ED. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0091] The fifth transistor T5 may be disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line EBL, and connects the third node N3 to the third driving voltage line VIL. Accordingly, the third driving voltage VINT of the third driving voltage line VIL may be applied to the first electrode of the light emitting element ED. The fifth transistor T5 includes a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0092] The sixth transistor T6 may be disposed between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 is turned on by the second emission control signal of the second emission control line EL2, and connects the source electrode of the first transistor T1 to the second driving voltage line VDL. Accordingly, the second driving voltage VDD of the second driving voltage line VDL may be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0093] The first capacitor C1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor C1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0094] The second capacitor C2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor C2 includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second driving voltage line VDL.

[0095] The first node N1 is a contact point of the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor C1, and one electrode of the second capacitor C2. The second node N2 is a contact point of the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a contact point of the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light emitting element ED.

[0096] Each of the first transistor T1 to the sixth transistor T6 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first transistor T1 to the sixth transistor T6 may be a P-type MOSFET, but the embodiments of the present specification are not limited thereto. Each of the first transistor T1 to the sixth transistor T6 may be an N-type MOSFET. Alternatively, some of the first transistor T1 to the sixth transistor T6 may be a P-type MOSFET, and the remaining transistors may be an N-type MOSFET.

[0097] exist Figure 4 FIG. 4 shows that the first pixel PX1 includes six transistors T1 to T6 and two capacitors C1 and C2, but it should be noted that the equivalent circuit diagram of the first pixel PX1 is not limited to Figure 4 For example, the number of transistors and capacitors of the first pixel PX1 is not limited to Figure 4 The quantity shown in .

[0098] In addition, the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 can be compared with the reference Figure 4 The equivalent circuit diagram of the first pixel PX1 described above is substantially the same. Therefore, description of the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 is omitted in this specification.

[0099] Figure 5 is a diagram showing a layout of pixels of a display area according to an embodiment.

[0100] Reference Figure 5, each of the plurality of pixels PX includes a first light emitting area EA1 as a light emitting area of ​​a first pixel PX1, a second light emitting area EA2 as a light emitting area of ​​a second pixel PX2, and a third light emitting area EA3 as a light emitting area of ​​a third pixel PX3.

[0101] Each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may have a quadrilateral plane shape, such as a rectangle, a square, or a rhombus. For example, the first light emitting area EA1 may have a rectangular plane shape having a short side in the first direction DR1 and a long side in the second direction DR2. In addition, each of the second light emitting area EA2 and the third light emitting area EA3 may have a rectangular plane shape having a long side in the first direction DR1 and a short side in the second direction DR2.

[0102] The length of the first light emitting area EA1 in the first direction DR1 may be smaller than the length of the second light emitting area EA2 and the length of the third light emitting area EA3 in the first direction DR1.

[0103] The length of the first light emitting area EA1 in the second direction DR2 may be greater than the sum of the lengths of the second light emitting area EA2 and the third light emitting area EA3 in the second direction DR2.

[0104] exist Figure 5 In the embodiment of the present invention, each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 has a quadrilateral plane shape. However, this is an exemplary embodiment of the present specification, not a limitation of the inventive concept. For example, each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may have a polygonal, circular, or elliptical plane shape other than a quadrilateral shape.

[0105] In each of the plurality of pixels PX, the first light emitting region EA1 and the second light emitting region EA2 may be adjacent to each other in the first direction DR1. In addition, the first light emitting region EA1 and the third light emitting region EA3 may be adjacent to each other in the first direction DR1. In addition, the second light emitting region EA2 and the third light emitting region EA3 may be adjacent to each other in the second direction DR2. The area of ​​the first light emitting region EA1, the area of ​​the second light emitting region EA2, and the area of ​​the third light emitting region EA3 may be different.

[0106] The first light emitting area EA1 emits light of a first color, the second light emitting area EA2 emits light of a second color, and the third light emitting area EA3 emits light of a third color. Here, the light of the first color may be light in a blue wavelength band, the light of the second color may be light in a green wavelength band, and the light of the third color may be light in a red wavelength band. For example, the blue wavelength band may indicate that the main peak wavelength of the light is included in a wavelength band of about 370nm to 460nm, the green wavelength band may indicate that the main peak wavelength of the light is included in a wavelength band of about 480nm to 560nm, and the red wavelength band may indicate that the main peak wavelength of the light is included in a wavelength band of about 600nm to 750nm.

[0107] Figure 5 The embodiment of the present invention depicts that each of the plurality of pixels PX includes three emission areas EA1, EA2, and EA3, but the present specification is not limited thereto. For example, each of the plurality of pixels PX may also include four emission areas.

[0108] In addition, the arrangement of the light emitting regions of the plurality of pixels PX is not limited to Figure 5 For example, the light emitting regions of the plurality of pixels PX may be arranged in a stripe structure in which the light emitting regions are arranged in the first direction DR1, in which the light emitting regions have a diamond arrangement, or in which the light emitting regions have a diamond arrangement. structure, or a hexagonal structure in which light emitting regions having a hexagonal planar shape are arranged.

[0109] Figure 6 is shown along Figure 5 A cross-sectional view of an example of a display device taken along line AA′.

[0110] Reference Figure 6 , the display panel 100 includes a semiconductor backplane SBP, a light emitting element backplane EBP, a light emitting element layer EMTL, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL and a polarizing plate.

[0111] The semiconductor backplane SBP includes a semiconductor substrate SSUB, the semiconductor substrate SSUB includes a plurality of pixel transistors TRS, a plurality of semiconductor insulating layers covering the plurality of pixel transistors TRS, and a plurality of contact terminals CTE respectively electrically connected to the plurality of pixel transistors TRS. Figure 4 The first transistor T1 to the sixth transistor T6 are described.

[0112] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type of impurity. A plurality of well regions WA may be provided on the upper surface of the semiconductor substrate SSUB. The plurality of well regions WA may be regions doped with a second type of impurity. The second type of impurity may be different from the first type of impurity described above. For example, when the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. Alternatively, when the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0113] Each of the plurality of well regions WA includes a source region SA corresponding to a source electrode of the pixel transistor TRS, a drain region DA corresponding to a drain electrode of the pixel transistor TRS, and a channel region CH disposed between the source region SA and the drain region DA.

[0114] Each of the source region SA and the drain region DA may be a region doped with first type impurities. The gate electrode GE of the pixel transistor TRS may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be disposed on one side of the gate electrode GE, and the drain region DA may be disposed on the other side of the gate electrode GE.

[0115] Each of the plurality of well regions WA further includes a first low-concentration impurity region disposed between the channel region CH and the source region SA, and a second low-concentration impurity region disposed between the channel region CH and the drain region DA. The first low-concentration impurity region may be a region having an impurity concentration lower than that of the source region SA. The second low-concentration impurity region may be a region having an impurity concentration lower than that of the drain region DA. The distance between the source region SA and the drain region DA may be increased by the first low-concentration impurity region and the second low-concentration impurity region. Therefore, since the length of the channel region CH of each of the plurality of pixel transistors TRS may be increased, punch-through and hot carrier phenomena caused by a short channel may be prevented.

[0116] The first semiconductor insulating layer SINS1 may be disposed on the semiconductor substrate SSUB. The first semiconductor insulating layer SINS1 may be formed of silicon carbon nitride (SiCN) or silicon oxide (SiO x )-based inorganic film, but the embodiments of the present specification are not limited thereto.

[0117] The second semiconductor insulating layer SINS2 may be disposed on the first semiconductor insulating layer SINS1. The second semiconductor insulating layer SINS2 may be formed of silicon oxide (SiO x )-based inorganic film, but the embodiments of the present specification are not limited thereto.

[0118] A plurality of contact terminals CTE may be disposed on the second semiconductor insulating layer SINS2. Each of the plurality of contact terminals CTE may be connected to any one of the gate electrode GE, the source region SA, and the drain region DA of each of the plurality of pixel transistors TRS through a hole penetrating the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2. The plurality of contact terminals CTE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of them.

[0119] The third semiconductor insulating layer SINS3 may be disposed on a side surface of each of the plurality of contact terminals CTE. The upper surface of each of the plurality of contact terminals CTE may be exposed without being covered by the third semiconductor insulating layer SINS3. The third semiconductor insulating layer SINS3 may be formed of silicon oxide (SiO x )-based inorganic film, but the embodiments of the present specification are not limited thereto.

[0120] The semiconductor substrate SSUB may be replaced by a glass substrate or a polymer resin substrate such as polyimide. In this case, the pixel transistor may be disposed on the glass substrate or the polymer resin substrate. The glass substrate may be a rigid substrate that is not bent, and the polymer resin substrate may be a flexible substrate that can be bent or folded.

[0121] The light emitting element back plate EBP includes first to eighth metal layers ML1 to ML8, reflective electrodes RL1 to RL4, a plurality of vias VA1 to VA10, and a step layer STPL. In addition, the light emitting element back plate EBP includes a plurality of interlayer insulating layers INS1 to INS10 disposed between the first to eighth metal layers ML1 to ML8.

[0122] The first metal layer ML1 to the eighth metal layer ML8 are used to realize the Figure 4 The circuit of the first pixel PX1 shown in FIG. That is, only the first transistor T1 to the sixth transistor T6 are formed on the semiconductor backplane SBP, and the first transistor T1 to the sixth transistor T6 are connected to the first capacitor C1 and the second capacitor C2 through the first metal layer ML1 to the eighth metal layer ML8. In addition, the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light emitting element ED are also connected through the first metal layer ML1 to the eighth metal layer ML8.

[0123] The first interlayer insulating layer INS1 may be disposed on the semiconductor backplane SBP. Each of the plurality of first vias VA1 may penetrate the first interlayer insulating layer INS1 and be connected to the contact terminal CTE exposed from the semiconductor backplane SBP. Each of the plurality of first metal layers ML1 may be disposed on the first interlayer insulating layer INS1 and may be connected to the first vias VA1.

[0124] The second interlayer insulating layer INS2 may be disposed on the first interlayer insulating layer INS1 and the plurality of first metal layers ML1. Each of the plurality of second vias VA2 may be connected to the first metal layer ML1 exposed by penetrating the second interlayer insulating layer INS2. Each of the plurality of second metal layers ML2 may be disposed on the second interlayer insulating layer INS2 and may be connected to the second vias VA2.

[0125] The third interlayer insulating layer INS3 may be disposed on the second interlayer insulating layer INS2 and the plurality of second metal layers ML2. Each of the plurality of third vias VA3 may be connected to the second metal layer ML2 exposed by penetrating the third interlayer insulating layer INS3. Each of the plurality of third metal layers ML3 may be disposed on the third interlayer insulating layer INS3 and may be connected to the third vias VA3.

[0126] The fourth interlayer insulating layer INS4 may be disposed on the third interlayer insulating layer INS3 and the plurality of third metal layers ML3. Each of the plurality of fourth vias VA4 may be connected to the third metal layer ML3 exposed by penetrating the fourth interlayer insulating layer INS4. Each of the plurality of fourth metal layers ML4 may be disposed on the fourth interlayer insulating layer INS4 and may be connected to the fourth vias VA4.

[0127] The fifth interlayer insulating layer INS5 may be disposed on the fourth interlayer insulating layer INS4 and the plurality of fourth metal layers ML4. Each of the plurality of fifth vias VA5 may be connected to the fourth metal layer ML4 exposed by penetrating the fifth interlayer insulating layer INS5. Each of the plurality of fifth metal layers ML5 may be disposed on the fifth interlayer insulating layer INS5 and may be connected to the fifth vias VA5.

[0128] The sixth interlayer insulating layer INS6 may be disposed on the fifth interlayer insulating layer INS5 and the plurality of fifth metal layers ML5. Each of the plurality of sixth vias VA6 may be connected to the fifth metal layer ML5 exposed by penetrating the sixth interlayer insulating layer INS6. Each of the plurality of sixth metal layers ML6 may be disposed on the sixth interlayer insulating layer INS6 and may be connected to the sixth via VA6.

[0129] The seventh interlayer insulating layer INS7 may be disposed on the sixth interlayer insulating layer INS6 and the plurality of sixth metal layers ML6. Each of the plurality of seventh vias VA7 may be connected to the sixth metal layer ML6 exposed by penetrating the seventh interlayer insulating layer INS7. Each of the plurality of seventh metal layers ML7 may be disposed on the seventh interlayer insulating layer INS7 and may be connected to the seventh via VA7.

[0130] The eighth interlayer insulating layer INS8 may be disposed on the seventh interlayer insulating layer INS7 and the plurality of seventh metal layers ML7. Each of the plurality of eighth vias VA8 may be connected to the seventh metal layer ML7 exposed by penetrating the eighth interlayer insulating layer INS8. Each of the plurality of eighth metal layers ML8 may be disposed on the eighth interlayer insulating layer INS8 and may be connected to the eighth via VA8.

[0131] The first metal layer ML1 to the eighth metal layer ML8 and the first through hole VA1 to the eighth through hole VA8 may be formed of substantially the same material. The first metal layer ML1 to the eighth metal layer ML8 and the first through hole VA1 to the eighth through hole VA8 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy containing any one of them. The first through hole VA1 to the eighth through hole VA8 may be formed of substantially the same material. The first interlayer insulating layer INS1 to the eighth interlayer insulating layer INS8 may be formed of silicon oxide (SiO x )-based inorganic film, but the embodiments of the present specification are not limited thereto.

[0132] The thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be respectively greater than the thickness (i.e., depth) of the first through hole VA1, the thickness of the second through hole VA2, the thickness of the third through hole VA3, the thickness of the fourth through hole VA4, the thickness of the fifth through hole VA5, and the thickness of the sixth through hole VA6. Each of the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be greater than the thickness of the first metal layer ML1. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be substantially the same. For example, the thickness of the first metal layer ML1 may be approximately The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be approximately And the thickness of the first through hole VA1, the thickness of the second through hole VA2, the thickness of the third through hole VA3, the thickness of the fourth through hole VA4, the thickness of the fifth through hole VA5 and the thickness of the sixth through hole VA6 may be

[0133] Each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than each of the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6. Each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than each of the thickness of the seventh through hole VA7 and the thickness of the eighth through hole VA8. Each of the thickness of the seventh through hole VA7 and the thickness of the eighth through hole VA8 may be greater than each of the thickness of the first through hole VA1, the thickness of the second through hole VA2, the thickness of the third through hole VA3, the thickness of the fourth through hole VA4, the thickness of the fifth through hole VA5, and the thickness of the sixth through hole VA6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be substantially the same. For example, each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be approximately Each of the thickness of the seventh through hole VA7 and the thickness of the eighth through hole VA8 may be approximately

[0134] The ninth interlayer insulating layer INS9 may be disposed on the eighth interlayer insulating layer INS8 and the eighth metal layer ML8. The ninth interlayer insulating layer INS9 may be formed of silicon oxide (SiO x )-based inorganic film, but the embodiments of the present specification are not limited thereto.

[0135] Each of the plurality of ninth vias VA9 may be connected to the eighth metal layer ML8 exposed by penetrating the ninth interlayer insulating layer INS9. The ninth via VA9 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of them. The thickness of the ninth via VA9 may be about 1000 Å.

[0136] Each of the plurality of first reflective electrodes RL1 may be disposed on the ninth interlayer insulating layer INS9 and may be connected to the ninth via hole VA9. The first reflective electrode RL1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one thereof.

[0137] Each of the plurality of second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. The second reflective electrode RL2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of them. Alternatively, the second reflective electrode RL2 may be formed of a compound including any one of the above-mentioned metal materials. For example, the second reflective electrode RL2 may be formed of titanium nitride (TiN).

[0138] In the first pixel PX1, the step layer STPL may be disposed on the second reflective electrode RL2. The step layer STPL may not be disposed in each of the second pixel PX2 and the third pixel PX3. The thickness of the step layer STPL may be set in consideration of the wavelength of the light of the first color and the distance from the first intermediate layer IL1 to the fourth reflective electrode RL4 to facilitate reflection of the light of the first color emitted from the first intermediate layer IL1 of the first pixel PX1. The step layer STPL may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x )-based inorganic film is formed, but the embodiments of the present specification are not limited thereto. The thickness of the step layer STPL may be about

[0139] In the first pixel PX1, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2 and the step layer STPL. In the second pixel PX2 and the third pixel PX3, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of them.

[0140] At least one of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3 may be omitted.

[0141] Each of the plurality of fourth reflective electrodes RL4 may be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 may be a layer that reflects light from the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3. The fourth reflective electrode RL4 may include a metal having a high reflectivity to facilitate reflecting light. The fourth reflective electrode RL4 may be formed of aluminum (Al), a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy that is an alloy of silver (Ag), palladium (Pd), and copper (Cu), and a stacked structure of an APC alloy and ITO (ITO / APC / ITO), but the embodiments of the present specification are not limited thereto. The thickness of each of the fourth reflective electrodes RL4 may be approximately 1000 Å.

[0142] The tenth interlayer insulating layer INS10 may be disposed on the ninth interlayer insulating layer INS9 and the fourth reflective electrode RL4. The tenth interlayer insulating layer INS10 may be formed of silicon oxide (SiO x )-based inorganic film, but the embodiments of the present specification are not limited thereto.

[0143] Each of the plurality of tenth through holes VA10 may be connected to the first electrode AND exposed by extending through the tenth interlayer insulating layer INS10. The tenth through hole VA10 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one thereof. Due to the step layer STPL, the thickness of the tenth through hole VA10 in the first pixel PX1 may be less than the thickness of the tenth through hole VA10 in each of the second pixel PX2 and the third pixel PX3. For example, the thickness of the tenth through hole VA10 in the first pixel PX1 may be approximately And the thickness of the tenth through hole VA10 in each of the second pixel PX2 and the third pixel PX3 may be approximately

[0144] The light emitting element layer EMTL may be disposed on the light emitting element back plate EBP. The light emitting element layer EMTL may include light emitting elements ED each including a first electrode AND, an intermediate layer IL, and a second electrode CAT, a pixel defining layer PDL, and a plurality of trenches TRC.

[0145] The first electrode AND of each of the plurality of light emitting elements ED may be disposed on the tenth interlayer insulating layer INS10 and may be connected to the tenth through hole VA10. The first electrode AND of each of the plurality of light emitting elements ED may be connected to the drain area DA or the source area SA of the pixel transistor TRS through the tenth through hole VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth through holes VA1 to VA9, the first to eighth metal layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each of the plurality of light emitting elements ED may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of them. Alternatively, the first electrode AND of each of the plurality of light emitting elements ED may be formed of a compound including any one of the above-mentioned metal materials. For example, the first electrode AND of each of the plurality of light emitting elements ED may be formed of titanium nitride (TiN).

[0146] The pixel defining layer PDL may be disposed on a partial region of the first electrode AND of each of the plurality of light emitting elements ED. The pixel defining layer PDL may cover an edge of the first electrode AND of each of the plurality of light emitting elements ED. The pixel defining layer PDL is used to separate the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3.

[0147] The first light emitting area EA1 may be defined as an area where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the first pixel PX1 to emit light. The second light emitting area EA2 may be defined as an area where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the second pixel PX2 to emit light. The third light emitting area EA3 may be defined as an area where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the third pixel PX3 to emit light.

[0148] The pixel defining layer PDL may include a first pixel defining layer PDL1, a second pixel defining layer PDL2, and a third pixel defining layer PDL3. The first pixel defining layer PDL1 may be disposed on an edge of the first electrode AND of each of the plurality of light emitting elements ED, the second pixel defining layer PDL2 may be disposed on the first pixel defining layer PDL1, and the third pixel defining layer PDL3 may be disposed on the second pixel defining layer PDL2. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may be formed of silicon oxide (SiO x )-based inorganic film, but the embodiments of the present specification are not limited thereto. Each of the thickness of the first pixel defining layer PDL1, the thickness of the second pixel defining layer PDL2, and the thickness of the third pixel defining layer PDL3 may be approximately

[0149] Each of the plurality of trenches TRC may penetrate the first pixel defining layer PDL1 , the second pixel defining layer PDL2 , and the third pixel defining layer PDL3 . Each of the plurality of trenches TRC may partially extend into the tenth interlayer insulating layer INS10 .

[0150] At least one trench TRC may be provided between pixels PX1, PX2, and PX3 adjacent to each other. Figure 6 In the embodiment, two trenches TRC are provided between pixels PX1 and PX2 adjacent to each other and between pixels PX2 and PX3 (and between pixel PX3 and the next pixel PX1, although not explicitly shown). However, the present specification is not limited thereto.

[0151] The intermediate layer IL may include a first intermediate layer IL1 , a second intermediate layer IL2 , and a third intermediate layer IL3 .

[0152] The intermediate layer IL may have a tandem structure including a plurality of intermediate layers IL1, IL2, and IL3 emitting light of different colors. For example, the intermediate layer IL may include a first intermediate layer IL1 emitting light of a first color, a second intermediate layer IL2 emitting light of a third color, and a third intermediate layer IL3 emitting light of a second color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be sequentially stacked.

[0153] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic light emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic light emitting layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic light emitting layer emitting light of a second color, and a third electron transport layer are sequentially stacked.

[0154] A first charge generation layer for supplying charges to the second intermediate layer IL2 and electrons to the first intermediate layer IL1 may be provided between the first intermediate layer IL1 and the second intermediate layer IL2. A second charge generation layer for supplying charges to the third intermediate layer IL3 and electrons to the second intermediate layer IL2 may be provided between the second intermediate layer IL2 and the third intermediate layer IL3.

[0155] The first intermediate layer IL1 may be disposed on the first electrode AND and the first pixel defining layer PDL1, and may be disposed on the bottom surface of each of the plurality of grooves TRC. Due to the groove TRC, the first intermediate layer IL1 may be disconnected between the pixels PX1, PX2, and PX3 adjacent to each other. The second intermediate layer IL2 may be disposed on the first intermediate layer IL1. Due to the groove TRC, the second intermediate layer IL2 may be disconnected between the pixels PX1, PX2, and PX3 adjacent to each other. The third intermediate layer IL3 may be disposed on the second intermediate layer IL2. Due to the groove TRC, the third intermediate layer IL3 may be disconnected between the pixels PX1, PX2, and PX3 adjacent to each other. That is, each of the plurality of grooves TRC may be a structure for disconnecting the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 of the light emitting element layer EMTL between the pixels PX1, PX2, and PX3 adjacent to each other.

[0156] In order to stably disconnect the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 of the light emitting element layer EMTL between the pixels PX1, PX2, and PX3 adjacent to each other, the depth of each of the plurality of grooves TRC may be greater than the thickness of the pixel defining layer PDL. The depth of each of the plurality of grooves TRC indicates the length of each of the plurality of grooves TRC in the third direction DR3. The thickness of the pixel defining layer PDL indicates the length of the pixel defining layer PDL in the third direction DR3.

[0157] In order to disconnect the first intermediate layer IL1, the second intermediate layer IL2 and the third intermediate layer IL3 of the light emitting element layer EMTL between the adjacent pixels PX1, PX2 and PX3, other structures may exist instead of the trench TRC. For example, instead of the trench TRC, a partition wall having an inverted tapered shape may be provided on the pixel defining layer PDL.

[0158] The number of intermediate layers IL1, IL2, and IL3 emitting light of different colors is not limited to Figure 6 . For example, the intermediate layer IL may include two intermediate layers. In this case, one of the two intermediate layers may be substantially the same as the first intermediate layer IL1, and the other thereof may include a second hole transport layer, a second organic light emitting layer, a third organic light emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to one intermediate layer and supplying charges to the other intermediate layer may be provided between the two intermediate layers.

[0159] In addition, Figure 6 , it is shown that the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 are all disposed in the first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3, but the embodiments of the present specification are not limited thereto. For example, the first intermediate layer IL1 may be disposed in the first light-emitting area EA1 and may not be disposed in the second light-emitting area EA2 and the third light-emitting area EA3. In addition, the second intermediate layer IL2 may be disposed in the second light-emitting area EA2 and may not be disposed in the first light-emitting area EA1 and the third light-emitting area EA3. In addition, the third intermediate layer IL3 may be disposed in the third light-emitting area EA3 and may not be disposed in the first light-emitting area EA1 and the second light-emitting area EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be omitted.

[0160] The second electrode CAT may be disposed on the third intermediate layer IL3. The second electrode CAT may be disposed on the third intermediate layer IL3 in each of the plurality of trenches TRC. The second electrode CAT may be made of a transparent conductive material (TCO) capable of transmitting light, such as ITO or IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode CAT is formed of a semi-transmissive conductive material, light emitting efficiency may be increased in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 through a microcavity.

[0161] The encapsulation layer TFE may be disposed on the light emitting element layer EMTL. The encapsulation layer TFE may include one or more inorganic films to prevent oxygen or moisture from penetrating into the light emitting element layer EMTL. In addition, the encapsulation layer TFE may include at least one organic film to protect the light emitting element layer EMTL from foreign matter such as dust. For example, the encapsulation layer TFE may include a first encapsulation inorganic layer TFE1, an encapsulation organic layer TFE2, and a second encapsulation inorganic layer TFE3.

[0162] The first encapsulation inorganic layer TFE1 may be disposed on the second electrode CAT, the encapsulation organic layer TFE2 may be disposed on the first encapsulation inorganic layer TFE1, and the second encapsulation inorganic layer TFE3 may be disposed on the encapsulation organic layer TFE2. The first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE3 may be formed in which silicon nitride layers (SiN x ), silicon oxynitride layer (SiON), silicon oxide layer (SiO x ), titanium oxide layer (TiO x ) and aluminum oxide layer (AlO x ) in a multilayer of one or more inorganic layers. The encapsulating organic layer TFE2 may be a monomer. In addition, the encapsulating organic layer TFE2 may be an organic layer made of acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0163] The adhesive layer ADL may be a layer for attaching the encapsulation layer TFE to the optical layer OPL. The adhesive layer ADL may be a double-sided adhesive member. In addition, the adhesive layer ADL may also be a transparent adhesive member such as a transparent adhesive or a transparent adhesive resin.

[0164] The optical layer OPL includes a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a filling layer FIL. The plurality of color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on the adhesive layer ADL.

[0165] The first color filter CF1 may overlap the first light emitting area EA1 of the first pixel PX1. The first color filter CF1 may transmit light of the first color, that is, light in a blue wavelength band. The blue wavelength band may be approximately 370 nm to 460 nm. Therefore, the first color filter CF1 may transmit light of the first color among the light emitted from the first light emitting area EA1.

[0166] The second color filter CF2 may overlap with the second light emitting area EA2 of the second pixel PX2. The second color filter CF2 may transmit light of the second color, that is, light in the green wavelength band. The green wavelength band may be approximately 480nm to 560nm. Therefore, the second color filter CF2 may transmit light of the second color among the light emitted from the second light emitting area EA2.

[0167] The third color filter CF3 may overlap with the third light emitting area EA3 of the third pixel PX3. The third color filter CF3 may transmit light of a third color, that is, light in a red wavelength band. The red wavelength band may be approximately 600 nm to 750 nm. Therefore, the third color filter CF3 may transmit light of a third color among the light emitted from the third light emitting area EA3.

[0168] Each of the plurality of lenses LNS may be disposed on each of the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the plurality of lenses LNS may be a structure for increasing the proportion of light guided to the front of the display device 10. Each of the plurality of lenses LNS may have a cross-sectional shape convex in an upward direction.

[0169] The filling layer FIL may be disposed on the plurality of lenses LNS. The filling layer FIL may have a predetermined refractive index so that light travels in the third direction DR3 at the interface between the plurality of lenses LNS and the filling layer FIL. In addition, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0170] The cover layer CVL may be disposed on the filling layer FIL. The cover layer CVL may be a glass substrate or a polymer such as a resin. When the cover layer CVL is a glass substrate, the cover layer CVL may be attached to the filling layer FIL. In this case, the filling layer FIL may be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, the cover layer CVL may be used as a packaging substrate. When the cover layer CVL is a polymer such as a resin, the cover layer CVL may be directly applied to the filling layer FIL.

[0171] A polarizing plate may be provided on one surface of the cover layer CVL. The polarizing plate may be a structure for preventing degradation in visibility due to reflection of external light. The polarizing plate may include a linear polarizing plate and a phase delay film. For example, the phase delay film may be a λ / 4 (quarter wavelength) plate, but the embodiments of the present specification are not limited thereto. However, when degradation in visibility due to reflection of external light is sufficiently improved by the first color filter CF1, the second color filter CF2, and the third color filter CF3, the polarizing plate may also be omitted.

[0172] Figure 7 is a perspective view showing a head mounted display device according to an embodiment. Figure 8 It is shown Figure 7 An exploded perspective view of an example of a head mounted display device.

[0173] Reference Figure 7 and Figure 8 According to an embodiment, a head-mounted display device 1000 as an optical device includes a first display device 10_1, a second display device 10_2, an image generator 1100, an image generator cover 1200, a first eyepiece lens 1210, a second eyepiece lens 1220, a head mounting band 1300, an intermediate frame 1400, a first optical component 1510, a second optical component 1520, a control circuit board 1600 and a connector.

[0174] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Figures 1 to 6 The display devices 10 described are substantially the same, and thus descriptions of the first display device 10_1 and the second display device 10_2 are omitted.

[0175] The first optical member 1510 may be disposed between the first display device 10_1 and the first eyepiece lens 1210. The second optical member 1520 may be disposed between the second display device 10_2 and the second eyepiece lens 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0176] The middle frame 1400 may be disposed between the first display device 10_1 and the control circuit board 1600, and may be disposed between the second display device 10_2 and the control circuit board 1600. The middle frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0177] The control circuit board 1600 may be disposed between the middle frame 1400 and the image generator 1100. The control circuit board 1600 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA, and may transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 through a connector.

[0178] The control circuit board 1600 may transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and may transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 1600 may transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0179] The image generator 1100 is used to accommodate the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, the control circuit board 1600, and the connector. The image generator cover 1200 is provided to cover an open surface of the image generator 1100. The image generator cover 1200 may include a first eyepiece lens 1210 for the left eye of the user and a second eyepiece lens 1220 for the right eye of the user. Although Figure 7 and Figure 8 The first eyepiece lens 1210 and the second eyepiece lens 1220 are depicted as being separately provided, but this is not a limitation of the present specification. For example, the first eyepiece lens 1210 and the second eyepiece lens 1220 may be integrated into one long eyepiece.

[0180] The first eyepiece lens 1210 may be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece lens 1220 may be aligned with the second display device 10_2 and the second optical member 1520. Therefore, the user may observe the image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first eyepiece lens 1210, and may observe the image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second eyepiece lens 1220.

[0181] The head mounting band 1300 is used to fix the image generator 1100 to the user's head so that the first eyepiece lens 1210 and the second eyepiece lens 1220 of the image generator cover 1200 are respectively disposed on the left eye and the right eye of the user. When the image generator 1100 is implemented in a light weight and a small size, the head mounted display device 1000 may include a Fig. 9The eyeglass frame shown in FIG. 1 is used to replace the head mounting strap 1300.

[0182] In addition, the head mounted display device 1000 may further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0183] Fig. 9 is a perspective view showing a head mounted display device according to an embodiment.

[0184] Reference Fig. 9 The head mounted display device 1000_1 according to the embodiment may be a glasses type display device in which the image generator 1200_1 is implemented in a lightweight and small housing. The head mounted display device 1000_1 according to the embodiment may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, glasses frame legs 1040 and 1050, an optical member 1060, an optical path conversion member 1070, and an image generator 1200_1.

[0185] The image generator 1200_1 may accommodate a display device and an optical component. More specifically, the image generator 1200_1 may include a display device 10_3, an optical member 1060, and an optical path conversion member 1070. Since the image displayed on the display device 10_3 is magnified by the optical member 1060 and its optical path is converted by the optical path conversion member 1070, the image may be provided to the right eye of the user through the right eye lens 1020. Accordingly, the user may observe an augmented reality image in which a virtual image displayed on the display device 10_3 and a real image viewed through the right eye lens 1020 are combined through the right eye.

[0186] exist Fig. 9 1030, but the embodiments of the present specification are not limited thereto. For example, the image generator 1200_1 may be disposed at the left distal end of the support frame 1030, and in this case, the image of the display device 10_3 may be provided to the left eye of the user. Alternatively, the image generator 1200_1 may be disposed at both the left distal end and the right distal end of the support frame 1030. In this case, the user may observe the image displayed on the display device 10_3 through both the left eye and the right eye of the user.

[0187] Fig.10 is a plan view of a display device according to an embodiment, Fig.11 yes Fig.10 is an enlarged view of part A of Fig.12 is along Fig.11 A cross-sectional view of the display device taken along line II'.

[0188] like Figures 10 to 12 As shown in , the display device 10 may include a substrate SSUB, a transistor TR, an insulating layer INS, an anode electrode AND (eg, a first electrode), a pixel defining layer PDL, a spacer SPC, an intermediate layer LPL, and a cathode electrode CAT (eg, a second electrode).

[0189] like Fig.12 As shown in , the transistor TR may be disposed on the substrate SSUB. The transistor TR may include a gate electrode G, a source electrode S, and a drain electrode D. The source electrode S and the drain electrode D may be disposed in a well region W of the substrate SSUB. Fig.12 The transistor TR shown in FIG. 1 may be, for example, the transistor Figure 4 The fourth transistor T4.

[0190] like Fig.12 As shown in , the anode electrode AND may be connected to the transistor TR through a contact hole CT extending through the insulating layer INS. For example, the anode electrode AND may be connected to the drain electrode D of the transistor TR through the contact hole CT of the insulating layer INS. A portion of the anode electrode AND may be disposed within the contact hole CT of the insulating layer INS. Here, the insulating layer INS may be an interlayer insulating layer INS disposed between the substrate SSUB and the anode electrode AND. For example, Fig.12 The insulating layer INS can be the above Figure 6 In addition, Fig.12 The contact hole CT can be Figure 6 The tenth through hole VA10.

[0191] like Fig.10 and Fig.11 As shown in , a plurality of first (anode) electrodes AND may be provided. In other words, the display device 10 may include a plurality of anode electrodes AND. According to an embodiment, the plurality of anode electrodes AND may be arranged along a plurality of rows and a plurality of columns. Fig.10 4 , a plurality of anode electrodes AND arranged along four rows RW1 , RW2 , RW3 , and RW4 and five columns CL1 , CL2 , CL3 , CL4 , and CL5 are illustrated.

[0192] like Fig.12 As shown in , the pixel defining layer PDL may be disposed on the anode electrode AND. Fig.10 and Fig.11As shown in , the pixel defining layer PDL may define the light emitting area EA of the pixel. To this end, the pixel defining layer PDL may be configured, for example, to expose a portion of the anode electrode AND on the insulating layer INS. The pixel defining layer PDL may cover the edge of the anode electrode AND. The pixel defining layer PDL may be formed as an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0193] like Fig.12 As shown in , the spacer SPC may be disposed on the pixel defining layer PDL.

[0194] like Fig.10 and Fig.11 As shown in FIG. 1 , from a plan view, the spacer SPC may surround the anode electrode AND and the trench TRC, which will be described later. Fig.10 As shown in , the spacer SPC may define a spacer region 111 surrounded by the spacer SPC, and from a plan view, the above-mentioned anode electrode AND and the trench TRC may be disposed in the spacer region 111. At this time, at least a portion of the spacer SPC may overlap with a connection portion between the above-mentioned anode electrode AND and the transistor TR (e.g., a contact hole CT of the insulating layer INS).

[0195] The spacer SPC may have a black color so that reflection of external light may be minimized. For example, a surface of the spacer SPC may be coated with a black dye or the like.

[0196] like Fig.10 and Fig.11 As shown in FIG, the spacer SPC may include a first sub-spacer SS1 and a second sub-spacer SS2.

[0197] like Fig.10 As shown in , the first sub-spacer SS1 may be disposed between the anode electrodes AND in adjacent rows. For example, the first sub-spacer SS1 may be disposed between the anode electrode AND of the first row RW1 and the anode electrode AND of the second row RW2. In addition, the first sub-spacer SS1 may be disposed between the anode electrode AND in the second row RW2 and the anode electrode AND in the third row RW3. In addition, the first sub-spacer SS1 may be disposed between the anode electrode AND in the third row RW3 and the anode electrode AND in the fourth row RW4.

[0198] The first sub-spacer SS1 may extend generally in a row direction (eg, a first direction DR1 ).

[0199] The first sub-spacer SS1 may have a zigzag shape extending generally in the first direction DR1.

[0200] The second subspacer SS2 may be disposed between adjacent first subspacers SS1. For example, the first subspacer SS1 disposed between the anode electrode AND of the first row RW1 and the anode electrode AND of the second row RW2 is referred to as a first-first subspacer, and the first subspacer SS1 disposed between the anode electrode AND of the second row RW2 and the anode electrode AND of the third row RW3 is referred to as a first-second subspacer, and the second subspacer SS2 may be disposed between the first-first subspacer and the first-second subspacer.

[0201] The second sub-spacer SS2 may extend in a direction different from that of the first sub-spacer SS1. Fig.10 As shown in , the second sub-spacer SS2 may extend in a column direction (eg, second direction DR2). The second sub-spacer SS2 may have a linear shape.

[0202] The second sub-spacer SS2 may be disposed between the anode electrodes AND adjacent in the first direction DR1. For example, the second sub-spacer SS2 may be disposed between the anode electrodes AND adjacent to each other in the same row in the row direction (e.g., the first direction DR1). For example, the second sub-spacer SS2 may be disposed between the anode electrodes AND adjacently disposed in the first direction DR1 in the second row RW2.

[0203] The second sub-spacer SS2 may connect adjacent first sub-spacers SS1. In an implementation, the second sub-spacer SS2 and the first sub-spacer SS1 may be integrally or continuously formed.

[0204] A region surrounded and defined by the first and second sub-spacers SS1 and SS2 may be the above-mentioned spacer region 111. For example, a region surrounded by the first and second sub-spacers SS1 and SS2 disposed adjacent to each other may be defined as the spacer region 111.

[0205] At least a portion of the second sub-spacer SS2 may overlap the contact hole CT described above. For example, the second sub-spacer SS2 may extend into the spacer region 111, and the extended portion of the second sub-spacer SS2 may overlap the contact hole CT.

[0206] At the same time, Fig.12 As shown in FIG. 1 , after forming the spacer SPC, a trench TRC penetrating the pixel defining layer PDL and the insulating layer INS may be formed. Fig.10 As shown in , the trench TRC may surround the anode electrode AND from a plan view. At this time, the trench TRC may be provided between the anode electrode AND and the spacer SPC from a plan view.

[0207] The trench TRC may define a separation region 222 , and the anode electrode AND may be disposed within the separation region 222 .

[0208] like Fig.12 As shown in , the intermediate layer LPL may be disposed on the pixel defining layer PDL, on the spacer SPC, and in the groove TRC. The intermediate layer LPL may be conformally formed at the base of the groove TRC to have substantially the same thickness as on the spacer SPC and the pixel defining layer PDL, and may not fill the groove TRC.

[0209] The middle layer LPL may include a plurality of light emitting units. For example, the middle layer LPL may include a first light emitting unit, a second light emitting unit, and a third light emitting unit stacked in the third direction DR3. The respective light emitting units may provide light of different wavelengths. For example, the first light emitting unit, the second light emitting unit, and the third light emitting unit may emit light of different colors. For example, the middle layer LPL may have a series structure in which a plurality of light emitting units providing light of different colors are stacked in a vertical direction (e.g., in the third direction DR3).

[0210] The first light emitting unit may be disposed on the anode electrode AND. The first light emitting unit may include a first light emitting layer, a hole transport layer, an organic material layer, and an electron transport layer.

[0211] The second light emitting unit may be disposed on the first light emitting unit. The second light emitting unit may include a second light emitting layer, a hole transport layer, an organic material layer, and an electron transport layer.

[0212] The third light emitting unit may be disposed on the second light emitting unit. The third light emitting unit may include a third light emitting layer, a hole transport layer, an organic material layer, and an electron transport layer.

[0213] The light emitting element may provide white light by mixing light of a first color (e.g., blue) from a first light emitting unit, light of a second color (e.g., red) from a second light emitting unit, and light of a third color (e.g., green) from a third light emitting unit. For example, the light emitting element may emit white light.

[0214] In addition, in addition to the above-mentioned light-emitting units, the intermediate layer LPL may further include at least one charge generation layer. For example, the charge generation layer may be disposed between light-emitting units adjacent to each other in the third direction DR3. The charge generation layer may include, for example, a first charge generation layer and a second charge generation layer stacked in the third direction DR3. In this case, the first charge generation layer may be disposed between the first light-emitting unit and the second light-emitting unit, and the second charge generation layer may be disposed between the second light-emitting unit and the third light-emitting unit.

[0215] At the same time, each charge generation layer may include a negative charge generation layer and a positive charge generation layer. For example, the first charge generation layer may include a first negative charge generation layer and a first positive charge generation layer stacked in the third direction DR3, and the second charge generation layer may include a second negative charge generation layer and a second positive charge generation layer stacked in the third direction DR3.

[0216] like Fig.12 As shown in , the middle layer LPL can be disconnected by a trench TRC extending through the pixel defining layer PDL and the insulating layer INS. Fig.10 and Fig.12 As shown in , the groove TRC may extend through the pixel defining layer PDL and the insulating layer INS to surround the anode electrode AND, and the intermediate layer LPL may be separated into a plurality of anode electrode units (or a plurality of pixel units) by the groove TRC for distinction. Accordingly, the intermediate layer LPL of each separation region 222 may be physically separated from other islands of the intermediate layer LPL.

[0217] like Fig.12 As shown in , the cathode electrode CAT may be disposed on the intermediate layer LPL. For example, the cathode electrode CAT may be disposed on the intermediate layer LPL to overlap with the anode electrode AND, the light emitting area EA, the pixel defining layer PDL, the spacer SPC, and the groove TRC. In the top emission structure, the cathode electrode CAT may be formed of a transparent conductive material (TCO) capable of transmitting light (such as ITO or IZO), or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag)). When the cathode electrode CAT is formed of a semi-transmissive conductive material, the luminous efficiency can be increased by a microcavity.

[0218] According to the display device 10 of the embodiment, since the insulating layer INS and the metal layer are planarized by a chemical mechanical polishing (CMP) process, the pixel defining layer PDL formed by the chemical mechanical polishing process may also be planarized. Fig.12As shown in , the portion of the pixel defining layer PDL on the contact hole CT connecting the drain electrode D of the transistor TR to the anode electrode AND and the portion of the pixel defining layer PDL in which the contact hole CT is not provided can be flattened without steps. Accordingly, in the area overlapping with the contact hole CT (hereinafter, the overlapping area) and in the area not overlapping with the contact hole CT (hereinafter, the non-overlapping area), the top layer of the pixel defining layer PDL may be at the same distance from the substrate SSUB in the third direction DR3, that is, at the same height. In the above-mentioned overlapping area and non-overlapping area, the spacer SPC on the pixel defining layer PDL may be at the same distance from the substrate SSUB, that is, at the same height. Here, since the height of the pixel defining layer PDL is constant, the spacer SPC may have a substantially constant thickness in the overlapping area and the non-overlapping area. Therefore, even if the spacer SPC is arranged on the pixel defining layer PDL to overlap with the contact hole CT, the spacer SPC may be at the same height in all parts. In other words, since the entire portion of the spacer SPC may have the same height even in the case of overlap between the spacer SPC and the contact hole CT, the role of the spacer supporting the mask may be normally performed.

[0219] In this way, the spacer SPC can be placed not only in the non-overlapping region described above, but also in the overlapping region including the contact hole CT, and as a result, the spacer SPC can overlap more with the mask (e.g., fine metal mask) placed on top of the spacer SPC. In other words, the supporting area and supporting force of the spacer SPC relative to the mask can be increased, so the sagging of the mask can be minimized.

[0220] In addition, the spacer SPC may include the first and second sub-spacers SS1 and SS2 connected to each other in the first and second directions DR1 and DR2 , and thus tearing of the spacer SPC, etc. can be prevented.

[0221] At the same time, since the region in which the anode electrode AND is provided with the contact hole CT (hereinafter, referred to as the first region; for example, Fig.10 In the region between the second row RW2 and the third row RW3) and in which the contact hole CT is not provided (hereinafter, referred to as the second region; for example, in Fig.10The first region and the second region are placed between the contact holes CT and the contact holes CT to form different shapes in a plan view, so the amount of light reflected from the first region and the second region may vary. This difference in reflected light may cause color difference between the first region and the second region and deteriorate the image quality. For example, although the anode electrodes AND connected to the contact holes CT are densely placed in the first region, the anode electrodes AND are less densely positioned in the second region. In other words, the anode electrodes AND occupy a greater proportion of the first region than the second region. Accordingly, the reflectivity in the first region may be higher than the reflectivity in the second region. However, since the spacer SPC according to the embodiment is arranged on the pixel defining layer PDL to cover both the first region and the second region, any color difference problem caused by the difference in reflectivity between the first region and the second region may be solved.

[0222] Fig.13 is a plan view of a display device according to an embodiment, Fig.14 yes Fig.13 is an enlarged view of part B, and Fig.15 is along Fig.14 A cross-sectional view of the display device taken along line II-II'.

[0223] Figures 13 to 15 The display device 10 and Figures 10 to 12 The display device 10 is different in that Figures 13 to 15 The display device 10 includes a partition wall PRT instead of the above-mentioned trench TRC, and this difference will be mainly described as follows.

[0224] At the same time, Fig.15 As shown in FIG. 1 , after forming the spacer SPC, a partition wall PRT may be formed on the pixel defining layer PDL. Fig.13 As shown in , the partition wall PRT may surround the anode electrode AND in a plan view. At this time, the partition wall PRT may be disposed between the anode electrode AND and the spacer SPC in a plan view.

[0225] The partition wall PRT may define a separation region 222, and the anode electrode AND may be disposed within the separation region 222. Fig.14 As shown in FIG. 1 , the separation region 222 may form a boundary along an edge region of the anode electrode AND.

[0226] The partition wall PRT may include a lower layer LL and an upper layer UL.

[0227] The lower layer LL may be disposed on the pixel defining layer PDL, and the upper layer UL may be disposed on the lower layer LL.

[0228] At least one side of the upper layer UL may protrude (or extend) further than the lower layer LL in at least one of the first direction DR1 and the second direction DR2 so as not to be supported by the lower layer LL. In other words, at least one side of the upper layer UL may extend beyond the edge of the lower layer LL in the first direction DR1 and the second direction DR2, thereby forming a tip TP. Specifically, the lower layer LL may support the upper layer UL in the third direction DR3, and the upper layer UL may form a tip TP on the lower layer LL that extends beyond the edge of the lower layer LL in a direction intersecting the third direction DR3 (for example, at least one of the first direction DR1 and the second direction DR2). The tip TP is not supported by the lower layer LL. Accordingly, a virtual extension line extending along one side of the lower layer LL may intersect with the upper layer UL. For example, from a plan view, the area of ​​the upper layer UL may be larger than the area of ​​the top surface of the lower layer LL. Here, the area of ​​the upper layer UL may mean, for example, an area defined by the size of the upper layer UL in a plane defined by the first direction DR1 and the second direction DR2, and the area of ​​the top surface of the lower layer LL may mean an area defined by the size of the top surface of the lower layer LL in a plane defined by the first direction DR1 and the second direction DR2. Accordingly, the tip TP of the upper layer UL may not contact the lower layer LL. Due to the tip TP of the upper layer UL, an undercut may occur on the lower side of the tip TP when the partition wall PRT is formed. Accordingly, at least one side of the partition wall PRT may have an overhang structure.

[0229] like Fig.15 As shown in , the middle layer LPL can be disconnected by the partition wall PRT on the pixel definition layer PDL. Fig.13 As shown in , the partition wall PRT can be set on the pixel definition layer PDL to surround the anode electrode AND, and the intermediate layer LPL can be separated into multiple anode electrode units (or multiple pixel units) by the partition wall PRT for distinction. Accordingly, the intermediate layer LPL of each separation area 222 can be physically separated.

[0230] like Fig.15 As shown in , the intermediate layer LPL may be disposed on the pixel defining layer PDL, the spacer SPC, and the partition wall PRT.

[0231] Fig.16 is a plan view of a display device according to an embodiment, Fig.17 yes Fig.16 is an enlarged view of part C of Fig.18 is along Fig.17 A cross-sectional view of the display device taken along line III-III'.

[0232] Figures 16 to 18 The display device and Figures 10 to 12 The display device 10 is different in that Figures 16 to 18The display device includes a heating electrode 777 instead of the above-mentioned groove TRC, and this difference will be mainly described as follows.

[0233] like Fig.18 As shown in FIG. 7 , after the spacer SPC is formed, a heating electrode 777 may be formed on the spacer SPC. At the same time, the heating electrode 777 may also be disposed in a contact hole 701 penetrating the spacer SPC and the pixel defining layer PDL.

[0234] like Fig.16 As shown in , the heating electrode 777 may be disposed along the spacer SPC. In other words, the heating electrode 777 may be disposed on the spacer SPC to overlap with the first sub-spacer SS1 and the second sub-spacer SS2 of the spacer SPC. From a plan view, the heating electrode 777 may be completely covered by the spacer SPC.

[0235] like Fig.16 As shown in FIG. , in a plan view, a heating electrode 777 may be formed around the anode electrode AND. Fig.16 In an embodiment, the heater electrode 777 may surround most of the anode electrode AND but have an opening 333 connecting between adjacent spacer regions 111 .

[0236] The heating electrode 777 may be connected to a power supply circuit through the contact hole 701 described above. The power supply circuit may apply a voltage (or current) to the heating electrode 777. The heating electrode 777 may be heated to a high temperature by the voltage (or current) applied to the heating electrode 777, and the intermediate layer LPL may be disconnected by the heated heating electrode 777. For example, in the manufacturing process sequence, the intermediate layer LPL may be formed after the heating electrode 777 is set. When a voltage (or current) is applied to the heating electrode 777, a portion of the intermediate layer LPL around the heating electrode 777 may be removed. In other words, the intermediate layer LPL may be removed by the heat of the heating electrode 777. For example, a portion of the intermediate layer LPL on the heating electrode 777 may be removed. Then, the intermediate layer LPL may be separated into a plurality of anode electrode units (or a plurality of pixel units) for distinction. Accordingly, the intermediate layers LPL of the spacer region 111 may be physically separated from each other.

[0237] Fig.19 is a cross-sectional view of a display device according to an embodiment.

[0238] Fig.19 The display device and Fig.12 The display device 10 is different in that the pixel defining layer PDL and the spacer SPC are formed integrally. Fig.19 The following description of the implementation of will focus on this difference.

[0239] like Fig.19As shown in , the pixel defining layer PDL and the spacer SPC may be formed integrally. In other words, the pixel defining layer PDL and the spacer SPC may be made of the same material. The structure including the pixel defining layer PDL and the spacer SPC may be manufactured by using, for example, a halftone exposure method.

[0240] Although not shown, Fig.15 and Fig.18 In other words, in Fig.15 and Fig.18 In an embodiment, the pixel defining layer PDL and the spacer SPC may be made of the same material.

[0241] Those skilled in the art to which the present disclosure belongs will be able to understand that the present disclosure can be implemented in other specific forms without changing the technical spirit or essential features of the present disclosure. Therefore, it should be understood that the above exemplary embodiments are illustrative rather than restrictive in all aspects. It should be understood that the scope of the present disclosure is defined by the claims, rather than the above detailed description, and all modifications and changes derived from the claims and their equivalents fall within the scope of the present disclosure.

Claims

1. A display device, comprising: substrate; a transistor, the transistor being on the substrate; a first electrode connected to the transistor; as well as a spacer, the spacer being disposed on the first electrode, The spacer overlaps a connection portion between the transistor and the first electrode.

2. The display device according to claim 1, further comprising: an insulating layer, the insulating layer being between the transistor and the first electrode, Wherein, the connecting portion extends through a contact hole in the insulating layer.

3. The display device according to claim 2, wherein: The spacer overlaps the contact hole.

4. The display device according to claim 3, wherein: The first electrode is disposed in the contact hole.

5. The display device according to claim 1, wherein: The spacer surrounds the first electrode in a plan view.

6. The display device according to claim 1, wherein: The spacer comprises: a first sub-spacer disposed between the first electrodes of adjacent rows; and A second sub-spacer is provided between adjacent first sub-spacers and overlaps the connection portion between the transistor and the first electrode.

7. The display device according to claim 6, wherein: The first sub-spacer extends in a row direction, and The second sub-spacer extends in a column direction crossing the row direction.

8. The display device according to claim 6, wherein: The second sub-spacer is connected to the adjacent first sub-spacer.

9. The display device according to claim 8, wherein: The second sub-spacer and the first sub-spacer are integrally formed.

10. The display device according to claim 6, wherein: The first sub-spacer has a sawtooth form.

11. The display device according to claim 6, wherein: A plurality of the second sub-spacers are disposed between adjacent first sub-spacers.

12. The display device according to claim 11, wherein: The first electrode is disposed in a region surrounded and defined by adjacent first sub-spacers and adjacent second sub-spacers.

13. The display device according to claim 1, further comprising: A pixel defining layer is disposed between the first electrode and the spacer.

14. The display device according to claim 13, wherein: The connection portion extends between the transistor and the first electrode through a contact hole in the insulating layer, and Wherein, a top surface of the pixel defining layer is at the same distance from the substrate in an overlapping region and a non-overlapping region with the contact hole.

15. The display device according to claim 13, wherein: The pixel defining layer has a groove surrounding the first electrode.

16. The display device according to claim 15, wherein: The spacer surrounds the groove.

17. The display device according to claim 13, wherein: The spacer and the pixel defining layer are integrally formed.

18. The display device according to claim 13, further comprising: A partition wall is disposed on the pixel defining layer.

19. The display device according to claim 18, wherein: The partition wall comprises: a lower layer on the pixel defining layer; and An upper layer, the upper layer is on the lower layer.

20. The display device according to claim 13, further comprising: A heating electrode is provided on the spacer.

21. The display device according to claim 20, wherein: The heating electrode is disposed in a contact hole extending through the spacer and the pixel defining layer.

22. The display device according to claim 1, wherein: The spacer has a black color.

23. The display device according to claim 1, further comprising: an intermediate layer, the intermediate layer being on the first electrode; as well as A second electrode is disposed on the intermediate layer.

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