Wafer-level packaging structure of heterogeneous chip and preparation method of wafer-level packaging structure

Abstract

The invention provides a wafer-level packaging structure of a heterogeneous chip and a preparation method of the wafer-level packaging structure. According to the preparation method, the first chip is inversely stacked on the second chip, and the electrodes of the first chip and the second chip are led out through the metal interconnection layer. The occupation rate of the area of the mainboard is reduced, the integration density is improved, a glass carrier plate does not need to be prepared, the preparation cost is reduced, the process efficiency is improved, and the process effects of 2.5 D packaging and 3D packaging are achieved on the basis of 2D packaging. Besides, under the condition that the first chip is inverted, an opening of the cavity in the first chip is covered by the bonding area in the metal interconnection layer, and sealing is achieved through the plastic packaging adhesive layer. Therefore, an expensive dry film does not need to be used for covering the opening of the cavity in the process of preparing the first chip, the preparation cost is further reduced, and the process efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a wafer-level packaging structure of a heterogeneous chip and a preparation method thereof. Background Art

[0002] As Moore's Law slows down, traditional packaging technology cannot meet the growing data transmission volume and performance requirements, so heterogeneous stacking packaging technology (Heterogeneous Integration, HI) is born. Heterogeneous chip stacking technology is a technology that integrates two or more different chips through packaging, 3D stacking and other technologies, aiming to improve the integration, performance and size optimization of the product. Especially in the range of mobile devices such as mobile phones and tablets, heterogeneous chip stacking technology can meet their high-density packaging requirements and enhance their cost advantages.

[0003] Existing heterogeneous stacking packaging technologies are mainly divided into 2D packaging, 2.5D packaging and 3D packaging. 2D packaging technology is the most basic packaging method. It solders multiple chips face down to the substrate, and the interconnection between chips is mainly achieved through wiring on the substrate. 2D packaging has the advantages of simple process, high flexibility and low cost, but the chip occupies too large an area and the motherboard utilization rate is low. 2.5D packaging and 3D packaging are to stack and package multiple chips through dielectric layers, which can greatly improve the motherboard utilization rate and achieve higher density interconnection. However, the process of 2.5D packaging and 3D packaging is relatively complicated, and the dielectric layer between chips generally uses a glass carrier, which is too expensive. Therefore, for the packaging of communication chips and wafer-level packaging (Wafer Level Chip Scale Packaging, WLCSP) chips in mobile devices, the cost of using 2.5D packaging and 3D packaging is too high, and the process efficiency is low, while the use of 2D packaging cannot meet the higher integration density requirements.

[0004] Therefore, there is an urgent need for a new chip packaging structure that can achieve a balance between integration density and process cost. Summary of the invention

[0005] The object of the present invention is to provide a wafer-level packaging structure of a heterogeneous chip and a preparation method thereof, so as to solve the technical problem of how to balance low-cost packaging and high-density integration of filters and WLCSP chips.

[0006] In order to solve the above technical problems, the present invention provides a method for preparing a wafer-level packaging structure of a heterogeneous chip, comprising:

[0007] A first chip and a second chip are provided; wherein the first chip comprises a first substrate and a support layer and a functional layer located on the first substrate, and the support layer encloses a plurality of cavities, and the functional layer is located in the cavities;

[0008] Forming a metal interconnection layer on the surface of the second chip, wherein the surface of the metal interconnection layer has a bonding area;

[0009] placing the first chip upside down on the bonding area, so that a side of the support layer away from the first substrate is in contact with the bonding area, and the bonding area covers the opening of the cavity;

[0010] A plastic sealant is used to seal the contact surface between the support layer and the bonding area, so as to at least seal the cavity.

[0011] Optionally, in the method for preparing the wafer-level packaging structure of the heterogeneous chip, the process of forming a metal interconnection layer on the surface of the second chip includes:

[0012] forming a first metal wiring layer; the first metal wiring layer covers a portion of the surface of the second chip;

[0013] forming a first dielectric layer; the first dielectric layer covers a portion of the second chip and a portion of the surface of the first metal wiring layer; and exposes the remaining portion of the second chip and the remaining portion of the surface of the first metal wiring layer;

[0014] forming a second metal wiring layer; the second metal wiring layer covers a portion of the surface of the first dielectric layer and is connected to the exposed remaining portion of the surface of the second chip;

[0015] A second dielectric layer is formed; the second dielectric layer covers a portion of the second metal wiring layer and a portion of the first dielectric layer; and the remaining portion of the second metal wiring layer, the remaining portion of the first dielectric layer and the remaining portion of the first metal wiring layer are exposed; wherein the surface of the exposed remaining portion of the first dielectric layer and the portion of the first metal wiring layer is the bonding area;

[0016] Furthermore, the metal interconnection layer includes the first metal wiring layer, the second metal wiring layer, the first dielectric layer and the second dielectric layer.

[0017] Optionally, in the method for preparing the wafer-level packaging structure of the heterogeneous chip, before inverting the first chip on the bonding area, the method for preparing the wafer-level packaging structure of the heterogeneous chip further includes:

[0018] A plurality of metal balls are formed; and each of the metal balls is respectively connected to the exposed second metal wiring layer and a portion of the first metal wiring layer.

[0019] Optionally, in the method for preparing the wafer-level packaging structure of heterogeneous chips, the process of preparing the first chip includes:

[0020] providing the first substrate;

[0021] forming the functional layer on the first substrate; and forming a plurality of first metal pads on the side of the functional layer;

[0022] forming a support material layer on the functional layer, the first metal pad and the exposed first substrate;

[0023] Removing part of the support material layer to form the support layer; wherein the support layer at least exposes the functional layer and the first metal pad;

[0024] A conductive column is formed on the exposed first metal pad, and the conductive column protrudes from the supporting layer.

[0025] Optionally, in the preparation method of the wafer-level packaging structure of the heterogeneous chip, in the bonding area, the exposed portion of the first metal wiring layer corresponds to the position of the conductive column; and after the first chip is inverted on the bonding area, the conductive column is connected to the exposed portion of the first metal wiring layer, so that the first metal pad, the conductive column, part of the first metal wiring layer and part of the metal balls are connected in sequence.

[0026] Optionally, in the method for preparing the wafer-level packaging structure of the heterogeneous chip, the thickness of the support layer is greater than the thickness of the functional layer and the first metal pad, and the thickness of the support layer ranges from 4 microns to 89 microns.

[0027] Optionally, in the method for preparing the wafer-level packaging structure of the heterogeneous chip, a protective layer and a plurality of second metal pads are formed on the surface of the second chip, and the protective layer exposes the plurality of second metal pads; and,

[0028] During the process of preparing the metal interconnection layer, the second metal pad is located on the surface of the portion of the second chip exposed by the first dielectric layer, and the second metal pad is sequentially connected to the second metal wiring layer and a portion of the metal balls.

[0029] Optionally, in the method for preparing the wafer-level packaging structure of the heterogeneous chip, the material of the first dielectric layer and the second dielectric layer includes PI or BCB.

[0030] Based on the same inventive concept, the present invention also provides a wafer-level packaging structure of heterogeneous chips, including: a first chip, a second chip, a metal interconnection layer and a plastic encapsulation layer; wherein,

[0031] The first chip includes a first substrate and a support layer and a functional layer located on the first substrate, wherein the support layer encloses a plurality of cavities, and the functional layer is located in the cavities;

[0032] The metal interconnection layer is located on the surface of the second chip, and the surface of the metal interconnection layer has a bonding area; the first chip is inverted on the bonding area, so that the side of the support layer away from the first substrate is in contact with the bonding area, and the bonding area covers the opening of the cavity;

[0033] The plastic sealing layer is located on the contact surface between the support layer and the bonding area to at least seal the cavity.

[0034] Optionally, in the wafer-level packaging structure of the heterogeneous chip, the metal interconnect layer includes a first metal wiring layer, a first dielectric layer, a second metal wiring layer and a second dielectric layer;

[0035] The first metal wiring layer covers a portion of the surface of the second chip;

[0036] The first dielectric layer covers a portion of the surface of the second chip and a portion of the surface of the first metal wiring layer; and exposes the remaining portion of the surface of the second chip and the remaining portion of the surface of the first metal wiring layer;

[0037] The second metal wiring layer covers a portion of the surface of the first dielectric layer and is connected to the exposed remaining portion of the surface of the second chip;

[0038] The second dielectric layer covers part of the second metal wiring layer and part of the first dielectric layer; and exposes the remaining part of the second metal wiring layer, the remaining part of the first dielectric layer and the remaining part of the first metal wiring layer; wherein the surface of the exposed remaining part of the first dielectric layer and part of the first metal wiring layer is the bonding area.

[0039] Optionally, in the wafer-level packaging structure of the heterogeneous chip, the material of the first dielectric layer and the second dielectric layer includes PI or BCB.

[0040] Optionally, in the wafer-level packaging structure of the heterogeneous chip, the wafer-level packaging structure of the heterogeneous chip also includes a plurality of metal balls; and each of the metal balls is respectively connected to the exposed second metal wiring layer and a portion of the first metal wiring layer.

[0041] Optionally, in the wafer-level packaging structure of the heterogeneous chip, the first chip further includes a plurality of first metal pads; the first metal pads are located on the side of the functional layer, and a conductive column is further formed on the first metal pad, and the conductive column penetrates and protrudes from the support layer; and,

[0042] In the bonding area, the exposed portion of the first metal wiring layer corresponds to the position of the conductive pillar, so that when the first chip is inverted on the bonding area, the conductive pillar is connected to the exposed portion of the first metal wiring layer and part of the metal balls in sequence.

[0043] Optionally, in the wafer-level packaging structure of the heterogeneous chip, the thickness of the support layer is greater than the thickness of the functional layer and the first metal pad, and the thickness of the support layer ranges from 4 microns to 89 microns.

[0044] Optionally, in the wafer-level packaging structure of the heterogeneous chip, a protective layer and a plurality of second metal pads are formed on the surface of the second chip, and the protective layer exposes the second metal pads; and the exposed second metal pads are connected to part of the second metal wiring layer and part of the metal balls in sequence.

[0045] In summary, the present invention provides a wafer-level packaging structure of a heterogeneous chip and a preparation method thereof. Compared with the prior art, the preparation method stacks the first chip upside down on the second chip, and uses a metal interconnection layer to respectively realize the electrode lead-out of the two. Not only does it reduce the occupancy rate of the mainboard area and improve the integration density, but it also does not need to prepare a glass carrier, reduces the preparation cost, and improves the process efficiency, thereby achieving the process effects of 2.5D packaging and 3D packaging on the basis of 2D packaging. In addition, when the first chip is inverted, the opening of the cavity in the first chip is covered by the bonding area in the metal interconnection layer, and is sealed by the plastic sealing layer. Therefore, there is no need to use an expensive dry film to cover the opening of the cavity during the preparation of the first chip, which further reduces the preparation cost and improves the process efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Those skilled in the art will appreciate that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0047] Figure 1 It is a flow chart of a method for preparing a wafer-level packaging structure of a heterogeneous chip in an embodiment of the present invention.

[0048] Figure 2 It is a process flow chart of preparing the first chip in an embodiment of the present invention.

[0049] Figure 3 to Figure 7 It is a schematic diagram of the semiconductor structure of each step of preparing the first chip in an embodiment of the present invention.

[0050] Figure 8 It is a process flow chart of preparing a metal interconnection layer in an embodiment of the present invention.

[0051] Figures 9 to 14 It is a schematic diagram of the semiconductor structure of each step of preparing the metal interconnection layer in an embodiment of the present invention.

[0052] Fig.15 Schematic diagram of the structure of forming metal balls in an embodiment of the present invention.

[0053] Fig.16 It is a schematic diagram of a structure in which a first chip is inverted on a second chip in an embodiment of the present invention.

[0054] Fig.17 Schematic diagram of the position of the plastic sealing layer in the embodiment of the present invention.

[0055] And, in the attached drawings:

[0056] 100 - first substrate; 101 - first metal pad; 102 - functional layer; 103 - support material layer; 104 - support layer; 105 - second patterned photoresist layer; 106 - first electroplating layer; 107 - second electroplating layer;

[0057] 200 - second substrate; 201 - second metal pad; 202 - protective layer;

[0058] 300 - first metal wiring layer; 301 - first dielectric layer; 302 - second metal wiring layer; 303 - second dielectric layer;

[0059] 400- plastic sealing layer;

[0060] A-bonding area; B-metal bump; C-cavity; D-metal under the ball; T-metal ball. DETAILED DESCRIPTION

[0061] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different proportions are used. It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0062] See also Figure 1 This embodiment provides a method for preparing a wafer-level packaging structure of a heterogeneous chip, comprising:

[0063] Step 1 S10: providing a first chip and a second chip; wherein the first chip comprises a first substrate and a support layer and a functional layer located on the first substrate, and the support layer encloses a plurality of cavities, and the functional layer is located in the cavities;

[0064] Step 2 S20: forming a metal interconnection layer on the surface of the second chip, wherein the surface of the metal interconnection layer has a bonding area;

[0065] Step three S30: placing the first chip upside down on the bonding area, so that a side of the support layer away from the first substrate is in contact with the bonding area, and the bonding area covers the opening of the cavity;

[0066] Step 4 S40: Use plastic sealant to seal the contact surface between the support layer and the bonding area, so as to at least seal the cavity.

[0067] Based on this, the preparation method provided in this embodiment stacks the first chip upside down on the second chip, and uses the metal interconnect layer to respectively realize the electrode lead-out of the two. Not only does it reduce the occupancy rate of the mainboard area and improve the integration density, but it also does not need to prepare a glass carrier, which reduces the preparation cost and improves the process efficiency, thereby achieving the process effects of 2.5D packaging and 3D packaging on the basis of 2D packaging. In addition, when the first chip is inverted, the opening of the cavity in the first chip is covered by the bonding area in the metal interconnect layer and is sealed by the plastic sealing layer. Therefore, there is no need to use expensive dry film to cover the opening of the cavity during the preparation of the first chip, which further reduces the preparation cost and improves the process efficiency.

[0068] The following combination Figures 1 to 17 The preparation method of the wafer-level packaging structure of the heterogeneous chip provided in this embodiment is specifically described.

[0069] Step 1 S10: Please refer to Figures 2 to 7 , providing a first chip and a second chip; wherein the first chip includes a first substrate 100 and a support layer 104 and a functional layer 102 located on the first substrate 100, and the support layer 104 surrounds a plurality of cavities C, and the functional layer 102 is located in the cavity C.

[0070] It should be noted that the first chip and the second chip provided in this embodiment are two different types of chips for implementing heterogeneous packaging. And illustratively, the first chip is a wafer-level packaged surface acoustic wave filter (WLP-SAW Filter), and the second chip is a WLCSP packaged chip including a power chip, a Bluetooth chip, an audio amplifier, etc.

[0071] For further information, see Figure 2 , the preparation process of the first chip includes:

[0072] Sub-step 1 S100: Please refer to Figure 3 , providing the first substrate 100.

[0073] The first substrate 100 is a piezoelectric substrate, and its material includes but is not limited to lithium tantalate (LT), lithium niobate (LN), aluminum nitride (AlN), lead zirconate titanate piezoelectric ceramics (PZT) or zinc oxide (ZnO) and the like.

[0074] Sub-step 2 S101: Please refer to Figure 3 , forming the functional layer 102 on the first substrate 100 ; and forming a plurality of first metal pads 101 on the side of the functional layer 102 .

[0075] The functional layer 102 is a forked electrode. The forked electrode is the main functional device of the filter, which converts the electrical signal at the input end into a surface acoustic wave through the piezoelectric effect, and converts the acoustic signal back into an electrical signal at the output end, thereby realizing the filtering function. The first metal pad 101 is located on the side of the functional layer 102, and is used to realize the transmission of electrical signals. Preferably, the first metal pad 101 and the functional layer 102 can be prepared synchronously using the same material. For example, the first metal pad 101 and the functional layer 102 are formed by sputtering, electroplating and other processes. And the materials of the first metal pad 101 and the functional layer 102 include but are not limited to gold, silver, aluminum, copper, tungsten, titanium, nickel or other metal alloys.

[0076] Sub-step 3 S102: Please refer to Figure 4 , forming a support material layer 103 on the functional layer 102 , the first metal pad 101 and the exposed first substrate 100 .

[0077] Sub-step 4 S103: Please refer to Figure 5 , partially removing the support material layer 103 to form the support layer 104 ; and the support layer 104 at least exposes the functional layer 102 and the first metal pad 101 .

[0078] It should be noted that the functional layer 102 has very high requirements for the environment. When there are polluted particles or air disturbances, the functional layer 102 will be disturbed, causing the filter frequency band to shift, thereby affecting the device performance. Therefore, it is necessary to place the functional layer 102 in a closed and stable environment to improve the stability and reliability of the device.

[0079] Specifically, Figure 4As shown, a layer of the support material layer 103 is formed on the functional layer 102, the first metal pad 101 and the exposed first substrate 100 by a deposition process. Then, a first patterned photoresist layer (not shown) is formed on the support material layer 103 to expose a portion of the support material layer 103 located on the functional layer 102 and the first metal pad 101, and a portion of the support material layer 103 on the first substrate 100 that is in contact with the functional layer 102. Finally, as shown Figure 5 As shown, the first patterned photoresist layer is used as a barrier to etch away the exposed portion of the support material layer 103 to form the support layer 104. And, after forming the support layer 104, the first patterned photoresist layer is cleaned and removed. Optionally, in other examples, the support layer 104 may be formed on the first substrate 100 first, and then the functional layer 102 and the first metal pad 101 may be formed, which is not specifically limited in this embodiment.

[0080] Please continue reading Figure 5 , the support layer 104 surrounds the functional layer 102 and the peripheral part of the first substrate 100, and forms the cavity C, so that the functional layer 102 is placed in a stable environment of the cavity C. In the existing process, a layer of dry film is formed at the opening of the cavity C to close the opening of the cavity C and ensure that the functional layer 102 is in a sealed cavity. However, the preparation cost of the dry film is too high and the process is complicated. Therefore, the preparation method provided in this embodiment eliminates the step of forming a dry film during the preparation of the first chip, and uses the first dielectric layer on the second chip to cover the cavity C (please refer to the following for details), thereby improving the process preparation efficiency and reducing the preparation cost.

[0081] Preferably, the thickness of the support layer 104 ranges from 4 microns to 89 microns.

[0082] Sub-step 5 S104: Please refer to Figure 6 and Figure 7 , a conductive column is formed on the exposed portion of the first metal pad 101 , and the conductive column protrudes from the support layer 104 .

[0083] As can be seen from the above, the first metal pad 101 is used to realize electrode extraction. Therefore, it is necessary to form the conductive column to facilitate electrical connection in subsequent processes. Figure 6As shown, a second patterned photoresist layer 105 is first formed on the semiconductor structure. The second patterned photoresist layer 105 exposes the first metal pad 101 exposed by the support layer 104 and covers the rest of the structure. Then, the conductive column is formed by electroplating, sputtering, etc. using the second patterned photoresist layer 105 as a barrier. Preferably, as Figure 7 As shown, a first electroplating process is used to first form a first electroplating layer 106 on the surface of the exposed first metal pad 101, and the material of the first electroplating layer 106 includes but is not limited to conductive metals such as copper and gold. A second electroplating process is then used to form a second electroplating layer 107 on the first electroplating layer 106, and the material of the second electroplating layer 107 includes but is not limited to welding metals such as tin and tin-silver alloy. Among them, the first electroplating layer 106 and the second electroplating layer 107 constitute the conductive column. It can be understood that the conductive column contains two conductive materials, which can not only simultaneously utilize the advantages of the two materials to achieve efficient electrode extraction, but also reduce the process preparation cost. Preferably, the conductive column protrudes from the support layer 104 to facilitate subsequent bonding connection with the second chip.

[0084] Furthermore, after forming the conductive pillars, the second patterned photoresist layer 105 is cleaned and removed. The wafer is cut using a cutting process to form Figure 7 A single filter is shown.

[0085] Step 2 S20: Please refer to Figures 8 to 15 A metal interconnection layer is formed on the surface of the second chip, and the surface of the metal interconnection layer has a bonding area A.

[0086] It should be noted that the preparation method provided in this embodiment is based on the 2D packaging process, the first chip is stacked on the second chip, and the metal interconnection layer is used to achieve the connection between the two and the electrode lead-out. There is no need to use expensive glass carriers like 2.5D packaging and 3D packaging, which not only reduces process costs and improves process efficiency, but also uses vertical stacking to increase chip integration density and improve motherboard utilization.

[0087] Based on this, see Figure 8 , the preparation process of the metal interconnection layer includes:

[0088] Sub-step 1 S200: Please refer to Fig. 9 and Fig.10 , forming a first metal wiring layer 300; the first metal wiring layer 300 covers a portion of the surface of the second chip.

[0089] The second chip is a WLCSP packaged chip, and this embodiment does not limit the specific type of the second chip. Optionally, the second chip includes a second substrate 200, a second metal pad 201 and a protective layer 202. The second substrate 200 is only a general term for the main device structure of the second chip, which is the chip body, including but not limited to a base, various well regions, an isolation structure, and various device layers. The second metal pad 201 is located on the surface of the second substrate 200 for electrode extraction. The protective layer 202 covers the surface of the second substrate 200, and the second metal pad 201 is exposed by etching. The material of the protective layer 202 includes but is not limited to silicon nitride to avoid the influence of the external environment on the second substrate 200, and also plays a role of electrical isolation to ensure the stability of the electrode extraction at the second metal pad 201.

[0090] Furthermore, since the first chip will be stacked on the second chip, in order to realize the electrode extraction of the first chip, it is necessary to form the first metal wiring layer 300 on the protective layer 202. And the position of the first metal wiring layer 300 corresponds to the position of the first chip on the second chip after subsequent stacking to ensure accurate connection.

[0091] Optionally, the preparation process of the first metal wiring layer 300 includes but is not limited to: firstly forming a third patterned photoresist layer (not shown) on the surface of the protective layer 202 and the exposed second metal pad 201, and the third patterned photoresist layer exposes a portion of the protective layer 202. Then, a sputtering or electroplating process is used to form a metal material on the exposed surface of the protective layer 202. Finally, the third patterned photoresist layer is cleaned and removed, and the metal material located on the protective layer 202 constitutes the first metal wiring layer 300.

[0092] Sub-step 2 S201: Please refer to Fig.11 , forming a first dielectric layer 301; the first dielectric layer 301 covers a portion of the surface of the second chip and a portion of the first metal wiring layer 300; and exposes the remaining portion of the second chip and the remaining portion of the surface of the first metal wiring layer 300.

[0093] Furthermore, the first dielectric layer 301 is used as an isolation dielectric layer in the metal interconnect structure, and its material is preferably an inorganic or organic polymer, such as polyimide (PI) or benzocyclobutene (BCB). Such a material has good tensile strength, that is, good elasticity, and can well adapt to the ductility of metal.

[0094] The surface of the portion of the second chip exposed by the first dielectric layer 301 corresponds to the second metal pad 201, so that the electrode of the second chip can be led out through the second metal pad 201. In addition, the first dielectric layer 301 also exposes a portion of the first metal wiring layer 300, so that the electrical connection and electrode lead-out of the first chip can be realized through the first metal wiring layer 300 later.

[0095] Optionally, the process of forming the first dielectric layer 301 includes but is not limited to: first forming a fourth patterned photoresist layer (not shown) on the second chip to shield the partial area of ​​the first dielectric layer 301 to be exposed. Then forming the first dielectric layer 301 by using the fourth patterned photoresist layer as a barrier deposition. Finally, cleaning and removing the fourth patterned photoresist layer. Alternatively, directly forming the first dielectric material layer on the second chip, and then using an etching process to remove the remaining second chip and the remaining first metal wiring layer 300 on the surface of the first dielectric material layer, the remaining first dielectric material layer is the first dielectric layer 301.

[0096] Sub-step 3 S202: Please refer to Fig.12 , forming a second metal wiring layer 302; the second metal wiring layer 302 covers a portion of the surface of the first dielectric layer 301 and is connected to the exposed surface of the remaining portion of the second chip.

[0097] The second metal wiring layer 302 is used to lead out the electrode of the second chip, and the second metal pad 201 is formed on the surface of the part of the second chip connected to the second metal wiring layer 302. And, the second metal wiring layer 302 and the second metal pad 201 can be connected through a metal bump B. That is, before or after the second metal wiring layer 302 is formed, the metal bump B is formed on the second metal pad 201 to facilitate the connection between the two. Preferably, the surface of the part of the first metal wiring layer 300 exposed through the first dielectric layer 301 is also provided with the metal bump B to facilitate the subsequent electrical connection with the metal ball. Further, in order to avoid interference, the second metal wiring layer 302 is spaced apart from the first metal wiring layer 300.

[0098] Optionally, the process of forming the second metal wiring layer 302 includes but is not limited to: firstly forming a fifth patterned photoresist layer (not shown) on the surface of the first dielectric layer 301, the exposed part of the first metal wiring layer 300 and the exposed second metal pad 201 or metal bump B, and the fifth patterned photoresist layer exposes a part of the first dielectric layer 301. Then, a sputtering or electroplating process is used to form a metal material on the surface of the exposed first dielectric layer 301. Finally, the fifth patterned photoresist layer is cleaned and removed, and the metal material located on the first dielectric layer 301 constitutes the second metal wiring layer 302.

[0099] Sub-step 4 S203: Please refer to Fig.13 and Fig.14 , forming a second dielectric layer 303; the second dielectric layer 303 covers a portion of the second metal wiring layer 302 and a portion of the first dielectric layer 301; and exposes the remaining portion of the second metal wiring layer 302, the remaining portion of the first dielectric layer 301 and the remaining portion of the first metal wiring layer 300; wherein the surface of the exposed remaining portion of the first dielectric layer 301 and a portion of the first metal wiring layer 300 is the bonding area A.

[0100] Preferably, the second dielectric layer 303 also serves as an isolation dielectric layer in the metal interconnect structure, and its material can be the same as that of the first dielectric layer 301. The preparation process of the second dielectric layer 303 can also refer to the preparation process of the first dielectric layer 301, and this embodiment will not be repeated here.

[0101] like Fig.13 As shown, the part of the second metal wiring layer 302 exposed by the second dielectric layer 303 is used to lead out the second chip through the second metal pad 201 and the second metal wiring layer 302; and the part of the first metal wiring layer 300 exposed by the second dielectric layer 303 is used to lead out the first chip through the first metal wiring layer 300. In addition, the remaining part of the first dielectric layer 301 and the surface of the first metal wiring layer 300 exposed by the second dielectric layer 303 are used as the bonding area A for subsequent connection to the first chip. Preferably, as Fig.14 As shown, in order to facilitate subsequent connection with the metal ball, an under-ball metal D is formed on the surface of the second metal wiring layer 302 exposed through the second dielectric layer 303. Similarly, in order to facilitate the lead-out of the first metal wiring layer 300, an under-ball metal D is also formed on the metal protrusion B located on the first metal wiring layer 300. However, in order to achieve connection with the first chip, the first metal wiring layer 300 retains a partially exposed area for connection with the conductive column.

[0102] As can be seen from the above, the metal interconnection layer includes the first metal wiring layer 300, the second metal wiring layer 302, the first dielectric layer 301 and the second dielectric layer 303. It should be noted that this embodiment does not limit the specific distribution of metal wirings in the metal interconnection layer, and the above is only an example structure.

[0103] For further information, see Fig.15 After forming the metal interconnection layer, the preparation process further includes: forming metal balls T on each of the under-ball metals D. The metal balls T are used for electrical connection of each chip pin and are preferably solder balls.

[0104] Step 3 S30: Please refer to Figures 13 to 16 , the first chip is placed upside down on the bonding area A, so that the side of the support layer 104 away from the first substrate 100 is in contact with the bonding area A, and the bonding area A covers the opening of the cavity C.

[0105] like Fig.13 and Fig.16 As shown, the exposed part of the first metal wiring layer 300 in the bonding area A is exposed through the first dielectric layer 301. In other words, the first dielectric layer 301 has a through groove, and the through groove exposes the first metal wiring layer 300. And the position of the through groove corresponds to the conductive column, so when the first chip is inverted on the bonding area A, the conductive column protruding from the support layer 104 can be inserted into the through groove and connected with the first metal wiring layer 300. Based on this, the first chip can be connected to the first metal pad 101, the conductive column, the first metal wiring layer 300, the metal bump B located on the first metal wiring layer 300, the under-ball metal D and the metal ball T in sequence to achieve electrode extraction. Similarly, the second chip can be connected to the second metal pad 201, the metal bump B, the second metal wiring layer 302, the under-ball metal D located on the second metal wiring layer 302 and the metal ball T in sequence to achieve electrode extraction.

[0106] It can be understood that the process of placing the first chip upside down on the bonding area A of the second chip in this embodiment is similar to the stacking form in 2.5D packaging and 3D packaging. Compared with the existing 2D packaging process in which the chips are distributed side by side, this stacking method can greatly reduce the occupancy rate of the mainboard area and improve the integration of the chip. In addition, this embodiment does not use the glass carrier required for 2.5D packaging and 3D packaging, nor does it prepare the through silicon via (TSV) with complex process. Instead, the metal interconnect layer is used to lead out the electrodes of the first chip and the second chip respectively, and the metal ball T is used for subsequent connection. This lead method belongs to the 2D packaging process, and its routing design is more flexible, and the process difficulty is low, which is conducive to improving the preparation efficiency. Therefore, the preparation method provided in this embodiment takes into account the advantages of 2D packaging, 2.5D packaging and 3D packaging, which can not only reduce the preparation cost and process difficulty, but also improve the motherboard utilization rate and integration density.

[0107] Furthermore, it can be seen from the above that the first chip, as a surface wave filter, needs to prepare a cavity C with good sealing performance to accommodate the functional layer 102, so as to ensure the filter performance. In the process of preparing the first chip, the preparation method provided in this embodiment eliminates the dry film preparation link, but uses the inverted distribution form of the first chip to make the bonding area A cover the cavity C. That is, the surface of the exposed first dielectric layer 301 is used to replace the dry film to cover the opening of the cavity C. Not only does it meet the structural requirements of closing the opening of the cavity C, but it also saves the preparation cost of the dry film, effectively reducing the overall preparation cost of the device.

[0108] Step 4 S40: Please refer to Fig.13 , Fig.16 and Fig.17 A plastic sealant is used to seal the contact surface between the support layer 104 and the bonding area A, so as to at least seal the cavity C.

[0109] Based on the inversion of the first chip, the conductive column can be inserted into the through groove in the first dielectric layer 301, and the support layer 104 can be close to or abut against the second dielectric layer 303. However, simple stacking cannot ensure the connection stability of the first chip relative to the second chip, nor can it meet the high sealing requirements of the cavity C. Therefore, the preparation method provided in this embodiment is to dot the plastic sealant between the contact surface of the support layer 104 and the bonding area A to form a plastic sealant layer 400, thereby achieving a stable connection between the first chip and the second chip, and improving the sealing effect of the cavity C. It should be noted that, based on the first chip and the second chip illustrated in this embodiment, in actual application, there is no need to perform comprehensive secondary plastic sealing. Therefore, the cavity C sealed by the plastic sealant layer 400 will not be greatly disturbed, and the covering of the first dielectric layer 301 is sufficient to ensure the stability of the environment in the cavity C.

[0110] Based on the same concept, this embodiment also provides a wafer-level packaging structure of heterogeneous chips. Figure 5 , Figure 7 , Fig.13 and Fig.17 The wafer-level packaging structure of the heterogeneous chip includes: a first chip, a second chip, a metal interconnection layer, a plastic encapsulation layer 400 and a plurality of metal balls T. Preferably, the wafer-level packaging structure of the heterogeneous chip is prepared by the above-mentioned preparation method.

[0111] Specifically, the first chip includes a first substrate 100, a first metal pad 101, a functional layer 102, a support layer 104 and a conductive column. The first metal pad 101 and the functional layer 102 are respectively located on the first substrate 100, and the first metal pad 101 is located on one side of the functional layer 102. The support layer 104 surrounds the functional area 102 and forms a plurality of cavities C so that the functional area 102 is located in the cavity C. In addition, the support layer 104 also exposes a portion of the first metal pad 101, and the conductive column penetrates the support layer 104 and is connected to the exposed portion of the first metal pad 101. Preferably, the conductive column is composed of a first electroplating layer 106 and a second electroplating layer 107 of different materials, so as to realize the electrode extraction of the first chip. Further, the conductive column protrudes from the support layer 104, and the thickness of the support layer 104 is greater than the thickness of the functional layer 102 and the first metal pad 101. Optionally, the thickness of the support layer 104 ranges from 4 microns to 89 microns.

[0112] The metal interconnection layer is located on the surface of the second chip, and the surface of the metal interconnection layer has a bonding area A. The first chip is inverted on the bonding area A, so that the side of the support layer 104 away from the first substrate 100 is connected to the bonding area A, and the bonding area A covers the openings of each cavity C. Preferably, the metal interconnection layer includes a first metal wiring layer 300, a first dielectric layer 301, a second metal wiring layer 302 and a second dielectric layer 303. Fig.17 As shown, the first metal wiring layer 300 covers part of the surface of the second chip. The first dielectric layer 301 covers part of the surface of the second chip and part of the first metal wiring layer 300, and exposes the remaining part of the second chip and the remaining part of the first metal wiring layer 300. The second metal wiring layer 302 covers part of the surface of the first dielectric layer 301, and is connected to the exposed remaining part of the surface of the second chip. The second dielectric layer 303 covers part of the second metal wiring layer 302 and part of the first dielectric layer 301, and exposes the remaining part of the second metal wiring layer 302, the remaining part of the first dielectric layer 301, and the remaining part of the first metal wiring layer 300. The exposed remaining part of the first dielectric layer 301 and the surface of the first metal wiring layer 300 are the bonding area A. Preferably, the material of the first dielectric layer 301 and the second dielectric layer 303 includes PI or BCB.

[0113] Preferably, the conductive pillar corresponds to the position of the exposed part of the first metal wiring layer 300, so that when the first chip is inverted on the bonding area A, the conductive pillar is sequentially connected with the exposed part of the first metal wiring layer 300 and part of the metal balls T to realize the electrode lead-out of the first chip. And the second chip includes a second substrate 200 and a protective layer 202 and a plurality of second metal pads 201 formed on the second substrate 200. The protective layer 202 exposes the second metal pad 201, and the exposed second metal pad 201 is sequentially connected with part of the second metal wiring layer 302 and part of the metal balls T to realize the electrode lead-out of the second chip.

[0114] The plastic encapsulation layer 400 is located at the contact surface between the support layer 104 and the bonding area A, and between the support layer 104 and the second dielectric layer 303. On the one hand, a stable connection between the first chip and the second chip is achieved, and on the other hand, the sealing effect of the cavity C is improved to ensure stable performance of the filter.

[0115] In summary, the wafer-level packaging structure of the heterogeneous chip provided in this embodiment and the preparation method thereof are to stack the first chip upside down on the second chip, and use the metal interconnection layer to respectively realize the electrode lead-out of the two. Not only does it reduce the occupancy rate of the mainboard area and improve the integration density, but it also does not need to prepare a glass carrier, which reduces the preparation cost and improves the process efficiency, thereby achieving the process effects of 2.5D packaging and 3D packaging on the basis of 2D packaging. In addition, when the first chip is inverted, the opening of the cavity C in the first chip is covered by the bonding area A in the metal interconnection layer, and is sealed by the plastic sealing layer 400. Therefore, there is no need to use an expensive dry film to cover the opening of the cavity C during the preparation of the first chip, which further reduces the preparation cost and improves the process efficiency.

[0116] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A method for preparing a wafer-level packaging structure of a heterogeneous chip, characterized in that: include: A first chip and a second chip are provided; wherein the first chip comprises a first substrate and a support layer and a functional layer located on the first substrate, and the support layer encloses a plurality of cavities, and the functional layer is located in the cavities; Forming a metal interconnection layer on the surface of the second chip, wherein the surface of the metal interconnection layer has a bonding area; placing the first chip upside down on the bonding area, so that a side of the support layer away from the first substrate is in contact with the bonding area, and the bonding area covers the opening of the cavity; A plastic sealant is used to seal the contact surface between the support layer and the bonding area, so as to at least seal the cavity.

2. The method for preparing a wafer-level packaging structure of a heterogeneous chip according to claim 1, characterized in that: The process of forming a metal interconnection layer on the surface of the second chip includes: forming a first metal wiring layer; the first metal wiring layer covers a portion of the surface of the second chip; forming a first dielectric layer; the first dielectric layer covers a portion of the second chip and a portion of the surface of the first metal wiring layer; and exposes the remaining portion of the second chip and the remaining portion of the surface of the first metal wiring layer; forming a second metal wiring layer; the second metal wiring layer covers a portion of the surface of the first dielectric layer and is connected to the exposed remaining portion of the surface of the second chip; A second dielectric layer is formed; the second dielectric layer covers a portion of the second metal wiring layer and a portion of the first dielectric layer; and the remaining portion of the second metal wiring layer, the remaining portion of the first dielectric layer and the remaining portion of the first metal wiring layer are exposed; wherein the surface of the exposed remaining portion of the first dielectric layer and the portion of the first metal wiring layer is the bonding area; Furthermore, the metal interconnection layer includes the first metal wiring layer, the second metal wiring layer, the first dielectric layer and the second dielectric layer.

3. The method for preparing a wafer-level packaging structure of a heterogeneous chip according to claim 2, characterized in that: Before placing the first chip upside down on the bonding area, the method for preparing the wafer-level packaging structure of the heterogeneous chip further includes: A plurality of metal balls are formed; and each of the metal balls is respectively connected to the exposed second metal wiring layer and a portion of the first metal wiring layer.

4. The method for preparing a wafer-level packaging structure of a heterogeneous chip according to claim 3, characterized in that: The process of preparing the first chip includes: providing the first substrate; forming the functional layer on the first substrate; and forming a plurality of first metal pads on the side of the functional layer; forming a support material layer on the functional layer, the first metal pad and the exposed first substrate; Removing part of the support material layer to form the support layer; wherein the support layer at least exposes the functional layer and the first metal pad; A conductive column is formed on the exposed first metal pad, and the conductive column protrudes from the supporting layer.

5. The method for preparing a wafer-level packaging structure of a heterogeneous chip according to claim 4, characterized in that: In the bonding area, the exposed portion of the first metal wiring layer corresponds to the position of the conductive column; and after the first chip is inverted on the bonding area, the conductive column is connected to the exposed portion of the first metal wiring layer, so that the first metal pad, the conductive column, part of the first metal wiring layer and part of the metal balls are connected in sequence.

6. The method for preparing a wafer-level packaging structure of a heterogeneous chip according to claim 1 or 4, characterized in that: The thickness of the support layer is greater than the thickness of the functional layer and the first metal pad, and the thickness of the support layer ranges from 4 micrometers to 89 micrometers.

7. The method for preparing a wafer-level packaging structure of a heterogeneous chip according to claim 3, characterized in that: A protective layer and a plurality of second metal pads are formed on the surface of the second chip, and the protective layer exposes the plurality of second metal pads; and, During the process of preparing the metal interconnection layer, the second metal pad is located on the surface of the portion of the second chip exposed by the first dielectric layer, and the second metal pad is sequentially connected to the second metal wiring layer and a portion of the metal balls.

8. The method for preparing a wafer-level packaging structure of a heterogeneous chip according to claim 2, characterized in that: The material of the first dielectric layer and the second dielectric layer includes PI or BCB.

9. A wafer-level packaging structure of a heterogeneous chip, characterized in that: include: A first chip, a second chip, a metal interconnection layer and a plastic encapsulation layer; wherein, The first chip includes a first substrate and a support layer and a functional layer located on the first substrate, wherein the support layer encloses a plurality of cavities, and the functional layer is located in the cavities; The metal interconnection layer is located on the surface of the second chip, and the surface of the metal interconnection layer has a bonding area; the first chip is inverted on the bonding area, so that the side of the support layer away from the first substrate is in contact with the bonding area, and the bonding area covers the opening of the cavity; The plastic sealing layer is located on the contact surface between the support layer and the bonding area to at least seal the cavity.

10. The wafer-level packaging structure of heterogeneous chips according to claim 9, characterized in that: The metal interconnection layer includes a first metal wiring layer, a first dielectric layer, a second metal wiring layer, and a second dielectric layer; The first metal wiring layer covers a portion of the surface of the second chip; The first dielectric layer covers a portion of the surface of the second chip and a portion of the surface of the first metal wiring layer; and exposes the remaining portion of the surface of the second chip and the remaining portion of the surface of the first metal wiring layer; The second metal wiring layer covers a portion of the surface of the first dielectric layer and is connected to the exposed remaining portion of the surface of the second chip; The second dielectric layer covers part of the second metal wiring layer and part of the first dielectric layer; and exposes the remaining part of the second metal wiring layer, the remaining part of the first dielectric layer and the remaining part of the first metal wiring layer; wherein the surface of the exposed remaining part of the first dielectric layer and part of the first metal wiring layer is the bonding area.

11. The wafer-level packaging structure of heterogeneous chips according to claim 9, characterized in that: The material of the first dielectric layer and the second dielectric layer includes PI or BCB.

12. The wafer-level packaging structure of heterogeneous chips according to claim 9, characterized in that: The wafer-level packaging structure of the heterogeneous chip also includes a plurality of metal balls; and each of the metal balls is respectively connected to the exposed second metal wiring layer and a portion of the first metal wiring layer.

13. The wafer-level packaging structure of heterogeneous chips according to claim 12, characterized in that: The first chip further includes a plurality of first metal pads; the first metal pads are located at the side of the functional layer, and a conductive column is formed on the first metal pad, and the conductive column penetrates and protrudes from the support layer; as well as, In the bonding area, the exposed portion of the first metal wiring layer corresponds to the position of the conductive pillar, so that when the first chip is inverted on the bonding area, the conductive pillar is connected to the exposed portion of the first metal wiring layer and part of the metal balls in sequence.

14. The wafer-level packaging structure of heterogeneous chips according to claim 9 or 13, characterized in that: The thickness of the support layer is greater than the thickness of the functional layer and the first metal pad, and the thickness of the support layer ranges from 4 micrometers to 89 micrometers.

15. The wafer-level packaging structure of heterogeneous chips according to claim 12, characterized in that: A protection layer and a plurality of second metal pads are formed on the surface of the second chip, and the protection layer exposes the second metal pads; and the exposed second metal pads are sequentially connected to a portion of the second metal wiring layer and a portion of the metal balls.

Images