Manufacturing process

Abstract

The invention provides a manufacturing process. The manufacturing process comprises the following steps of S1, stacking at least one dielectric layer on a substrate; s2, coating a photoresist layer on the dielectric layer, exposing and developing the photoresist layer in the processing area, forming a processing area upper groove on the photoresist layer, etching the dielectric layer below the processing area upper groove to form a processing area lower groove, the processing area lower groove being not in contact with the substrate, and the width of the processing area lower groove being greater than that of the processing area upper groove; s3, metal sputtering or evaporation is carried out, a metal layer I is formed at the bottom of the processing area lower groove, and the height of the processing area lower groove is larger than that of the metal layer I; and S4, removing the metal layer II, and finally removing the photoresist layer. According to the process, the problem that the edge of the sputtered metal is tilted is effectively solved, and the appearance yield is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a manufacturing process. Background Art

[0002] Existing metal sputtering process technology, such as Figure 1 Specifically, photoresist is used → photoresist coating → alignment → IR inversion → full exposure → development to form a positive trapezoidal morphology → metal sputtering; the bottom corner of this morphology will be connected to the bottom sputtered metal during the sputtering operation, so when the metal is lifted off, the metal at the bottom edge will be torn up, causing the edge of the sputtered metal to warp up, affecting the appearance yield, and the subsequent lead metal connecting through the bump position is prone to cause device failure defects. Summary of the invention

[0003] In view of the above-mentioned problems, the present invention proposes a process technology, which has the characteristics of no warping of metal edges, good appearance and good yield.

[0004] The technical solution of the present invention is achieved in this way:

[0005] A manufacturing process comprises the following steps:

[0006] S1: at least one dielectric layer is stacked on the substrate;

[0007] S2: coating a photoresist layer on the dielectric layer, exposing and developing the photoresist layer in the process area to form an upper groove in the process area on the photoresist layer, and then etching the dielectric layer below the upper groove in the process area to form a lower groove in the process area, wherein the lower groove in the process area does not contact the substrate, and the width of the lower groove in the process area is greater than the width of the upper groove in the process area;

[0008] S3: performing metal sputtering or evaporation to form a metal layer I at the bottom of the lower groove of the process area, and a metal layer II on the photoresist layer, wherein the height of the lower groove of the process area is greater than the height of the metal layer I;

[0009] S4: remove the metal layer II, and finally remove the photoresist layer.

[0010] Preferably, the method further comprises step S5: etching away the dielectric layer remaining from the last etching next to the metal layer II.

[0011] Preferably, the dielectric layer includes a first InGaP layer, a first GaAs layer, a second InGaP layer and a second GaAs layer stacked in sequence from bottom to top. The lower groove of the process area in step S2 is formed by etching the second GaAs layer, or etching the second GaAs layer and the second InGaP layer, or etching the second GaAs layer, the second InGaP layer and the first GaAs layer.

[0012] Alternatively, the dielectric layer includes a SiN layer and a TiW layer stacked in sequence from bottom to top. The lower groove of the process area in step S2 is formed by etching the TiW layer. After removing the photoresist layer, the remaining TiW layer is also removed.

[0013] Preferably, the upper groove of the process area is a rectangular groove or a trapezoidal groove that is smaller at the top and larger at the bottom; and the lower groove of the process area is a rectangular groove.

[0014] Preferably, the photoresist layer is a positive photoresist layer or a negative photoresist layer.

[0015] Preferably, the substrate is a single crystal silicon substrate, a gallium arsenide substrate, a gallium nitride substrate, an indium phosphide substrate or a silicon carbide substrate.

[0016] Preferably, the metal layer I is a TaN layer, a TiW layer or an Au layer.

[0017] The beneficial effects of the present invention are as follows: the lower groove of the process area in the present invention is specifically used for the molding of the metal layer I, and the height of the lower groove of the process area is greater than the height of the metal layer I. During the process of sputtering or evaporating metal, the metal layer I in the lower groove of the process area and the metal layer II on the photoresist layer will be disconnected and will not be connected together. Therefore, when the metal layer II is removed, the metal layer I will not be torn up by the metal layer II, and the edge of the metal layer I will not be caused to curl up, which will not affect the appearance yield of the metal layer I. There will be no subsequent device failure caused by the lead metal passing through the bump position. In addition, the process of the present invention can utilize the existing structure, without the addition of additional masks, and without increasing production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 The figure is a process diagram of the existing metal sputtering process;

[0020] Figure 2 is a process diagram of Example 2;

[0021] Figure 3 is a process diagram of Example 3;

[0022] Figure 4 This is a process flow chart of Example 4. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] Example 1

[0025] A manufacturing process comprises the following steps:

[0026] S1: at least one dielectric layer is stacked on the substrate;

[0027] S2: coating a photoresist layer on the dielectric layer, exposing and developing the photoresist layer in the process area to form an upper groove in the process area on the photoresist layer, and then etching the dielectric layer below the upper groove in the process area to form a lower groove in the process area, wherein the lower groove in the process area does not contact the substrate, and the width of the lower groove in the process area is greater than the width of the upper groove in the process area;

[0028] S3: performing metal sputtering or evaporation to form a metal layer I at the bottom of the lower groove of the process area, and a metal layer II on the photoresist layer, wherein the height of the lower groove of the process area is greater than the height of the metal layer I;

[0029] S4: removing the metal layer II, and finally removing the photoresist layer;

[0030] S5: Etch away the dielectric layer remaining from the last etching next to the metal layer II.

[0031] As a preferred technical solution, the substrate is a single crystal silicon substrate, a gallium arsenide substrate, a gallium nitride substrate, an indium phosphide substrate or a silicon carbide substrate, which is selected according to actual needs, but is not limited to the above materials.

[0032] The dielectric layer can be one layer, two layers, three layers, four layers or more layers, and the number of layers is selected according to actual needs. When the dielectric layer is one layer, half or three quarters of the dielectric layer can be etched to form a groove under the process area.

[0033] The material of the dielectric layer can be InGaP, GaAs, SiN or TiW, etc., which can be selected according to actual needs, but is not limited to the above materials.

[0034] The photoresist layer can be a positive photoresist layer or a negative photoresist layer, which can be selected according to actual needs.

[0035] The upper groove of the process area can be a rectangular groove or a trapezoidal groove that is smaller at the top and larger at the bottom, etc., which can be selected according to actual needs and is not limited to the above two shapes.

[0036] The lower groove of the process area can be a rectangular groove, which can be selected according to actual needs and is not limited to a rectangular groove.

[0037] The metal layer I is a TaN layer, a TiW layer or an Au layer, which is selected according to actual needs, but is not limited to the above materials.

[0038] Example 2

[0039] Reference Figure 2 The difference between this embodiment and embodiment 1 is that the dielectric layer includes a first InGaP layer, a first GaAs layer, a second InGaP layer and a second GaAs layer stacked in sequence from bottom to top.

[0040] The groove under the process area in step S2 is formed by etching the second GaAs layer, or etching the second GaAs layer and the second InGaP layer, or etching the second GaAs layer, the second InGaP layer and the first GaAs layer.

[0041] The upper groove of the process area is a trapezoidal groove that is smaller at the top and larger at the bottom.

[0042] Example 3

[0043] Reference Figure 3 The difference between this embodiment and embodiment 2 is that the upper groove of the process area is a rectangular groove.

[0044] Example 4

[0045] Reference Figure 4 The difference between this embodiment and embodiment 1 is that the dielectric layer includes a SiN layer and a TiW layer stacked in sequence from bottom to top.

[0046] The groove under the process area in step S2 is formed by etching the TiW layer. After removing the photoresist layer, the remaining TiW layer is also removed.

[0047] The lower groove of the process area in the present invention is specifically used for the molding of the metal layer I, and the height of the lower groove of the process area is greater than the height of the metal layer I. In the process of sputtering or evaporating metal, the metal layer I in the lower groove of the process area and the metal layer II on the photoresist layer will be disconnected and will not be connected together. Therefore, when the metal layer II is removed, the metal layer I will not be torn up by the metal layer II, and the edge of the metal layer I will not be caused to curl up, which will not affect the appearance yield of the metal layer I. There will be no subsequent device failure caused by the lead metal passing through the bump position. In addition, the process of the present invention can utilize the existing structure, without adding additional masks, and does not increase production costs.

[0048] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A process technology, characterized in that: The following steps are involved: S1: at least one dielectric layer is stacked on the substrate; S2: coating a photoresist layer on the dielectric layer, exposing and developing the photoresist layer in the process area to form an upper groove in the process area on the photoresist layer, and then etching the dielectric layer below the upper groove in the process area to form a lower groove in the process area, wherein the lower groove in the process area does not contact the substrate, and the width of the lower groove in the process area is greater than the width of the upper groove in the process area; S3: performing metal sputtering or evaporation to form a metal layer I at the bottom of the lower groove of the process area, and a metal layer II on the photoresist layer, wherein the height of the lower groove of the process area is greater than the height of the metal layer I; S4: remove the metal layer II, and finally remove the photoresist layer.

2. The process as claimed in claim 1, characterized in that: The dielectric layer includes, from bottom to top, a first InGaP layer, a first GaAs layer, a second InGaP layer and a second GaAs layer which are stacked in sequence.

3. The process as claimed in claim 1, characterized in that: The dielectric layer includes a SiN layer and a TiW layer stacked in sequence from bottom to top.

4. The process as claimed in claim 2, characterized in that: In step S2, the groove under the process area is formed by etching the second GaAs layer, or by etching the second GaAs layer and the second InGaP layer.

5. The process as claimed in claim 2, characterized in that: In step S2, the groove under the process area is formed by etching the second GaAs layer, the second InGaP layer and the first GaAs layer.

6. The process as claimed in claim 3, characterized in that: In step S2, the groove under the process area is formed by etching the TiW layer.

7. The process as claimed in claim 6, characterized in that: After removing the photoresist layer, the remaining TiW layer is also removed.

8. The process as claimed in claim 1, wherein: The upper groove of the process area is a rectangular groove or a trapezoidal groove that is smaller at the top and larger at the bottom; the lower groove of the process area is a rectangular groove.

9. The process as claimed in claim 1, wherein: The photoresist layer is a positive photoresist layer or a negative photoresist layer.

10. The process as claimed in claim 1, wherein: The substrate is a single crystal silicon substrate, a gallium arsenide substrate, a gallium nitride substrate, an indium phosphide substrate or a silicon carbide substrate; the metal layer I is a TaN layer, a TiW layer or an Au layer.

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