Baud rate detection method, Baud rate detection device and serial port communication system

Abstract

The invention provides a Baud rate detection method, a Baud rate detection device and a serial communication system, which can automatically perform edge detection, pulse width capture and signal waveform judgment on serial communication signals, and adopt continuous'at least one low-level pulse width + at least one high-level pulse width 'to calculate the Baud rate so as to eliminate slope errors. Furthermore, the target frame header data can be automatically analyzed to obtain the pulse number threshold and the ratio of the low-level pulse width to the high-level pulse width, so that the operation is simplified, and the efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of serial communication, and in particular to a baud rate detection method and a baud rate detection device, and a serial communication system. Background Art

[0002] In the fields of industrial measurement, automatic control, communication, system testing, etc., people often use serial communication (also called serial communication) to complete data transmission between communicating parties (such as a host and a terminal or two device systems, etc.). This communication method is a communication method that transmits the data to be transmitted bit by bit from low to high (that is, one bit at a time) on a transmission line. It has the advantages of simple structure and low communication cost.

[0003] When the two parties communicate in serial communication, especially asynchronous serial communication, there is no synchronous clock, so the two parties must agree on and comply with the same baud rate, so as to achieve the correct transmission and reception of data or instructions. Among them, the baud rate refers to the data bit transmission rate during the serial communication process, which refers to the number of bits transmitted per second (bit / s). Asynchronous serial communication protocols are, for example, Universal Asynchronous Receiver / Transmitter (UART).

[0004] When the two communicating parties agree on the baud rate, as long as the duration of each bit sent by the sender (i.e. the inverse of the baud rate) is accurate, the receiver can normally parse the data accurately. However, in actual applications, there may be problems with the baud rate mismatch due to clock accuracy errors or data interference, which may cause communication interruption or failure between the two parties.

[0005] Therefore, it is necessary to accurately detect the baud rate of serial communication. Summary of the invention

[0006] The object of the present invention is to provide a baud rate detection method and a baud rate detection device, and a serial port communication system, which can obtain the accurate baud rate of serial port communication.

[0007] To achieve the above object, the present invention provides a baud rate detection method, which comprises the following steps:

[0008] S1, determining the pulse number threshold of the signal waveform of the target frame header data of the serial communication protocol;

[0009] S2, performing edge detection on the corresponding serial communication signal to capture the low level pulse width and high level pulse width of the serial communication signal;

[0010] S3, when the number of captured pulses reaches the pulse number threshold, judging whether the captured signal waveform is the signal waveform of the target frame header data according to the captured low-level pulse width and high-level pulse width;

[0011] If yes, then S4 is executed to select at least one continuous low-level pulse width and at least one high-level pulse width from all captured low-level pulse widths and high-level pulse widths to calculate the baud rate.

[0012] Optionally, in step S1, corresponding target frame header data is received and parsed to obtain the pulse width ratio between pulses in the signal waveform corresponding to the target frame header data and the pulse number threshold, wherein the signal waveform has at least one low-level pulse and at least one high-level pulse, and the pulse width of each pulse is at least 1 bit.

[0013] Optionally, in step S1, the step of parsing the target frame header data includes: parsing the target frame header data into a corresponding binary sequence; taking the value of the total number of data frame signal flips of the binary sequence minus 1 as the pulse number threshold; recording the number of bits of each high level and low level in the binary sequence, wherein the ratio of the number of high level bits to the number of low level bits is the pulse width ratio between the corresponding high level pulses and the low level pulses.

[0014] Optionally, in step S1, at least one of the pulse number threshold and the pulse width ratio between pulses in the signal waveform of the target frame header data is directly configured by configuring a register or modifying a code parameter.

[0015] Optionally, in step S2, while capturing the low-level pulse width and the high-level pulse width of the serial communication signal, timing is also performed and the captured pulses are counted, and the capture is terminated when the count within a specified time threshold reaches the pulse number threshold, or the capture is terminated when the timing exceeds the time threshold.

[0016] Optionally, in step S3, the ratio between the captured high-level pulse width and the low-level pulse width is compared with a corresponding ratio threshold value, and if the comparison result is within an allowable range, it is determined that the captured signal waveform is the signal waveform of the target frame header data; if the comparison result exceeds the allowable range, it is determined that the captured signal waveform is not the signal waveform of the target frame header data;

[0017] Alternatively, in step S3, the time ratio between two adjacent falling edges and two adjacent rising edges in the captured signal waveform is compared with a corresponding proportional threshold; if the comparison result is within an allowable range, the captured signal waveform is determined to be the signal waveform of the target frame header data; if the comparison result exceeds the allowable range, the captured signal waveform is determined not to be the signal waveform of the target frame header data.

[0018] Optionally, in step S4, the sum of the pulse widths of a low pulse and a high pulse and the total number of bits are calculated, and the sum of the pulse widths is divided by the total number of bits to obtain a time width of one bit, and then the baud rate is calculated.

[0019] Optionally, the baud rate detection method further comprises, after step S4:

[0020] Step S5, comparing the baud rate with an ideal baud rate;

[0021] Step S6, judging whether the baud rate is abnormal according to the comparison result, or adaptively adjusting the baud rate according to the comparison result.

[0022] Based on the same inventive concept, the present invention also provides a baud rate detection device, which comprises:

[0023] A pre-configuration module, used to determine a pulse number threshold of a signal waveform of target frame header data of a serial communication protocol;

[0024] A capture and analysis module, used for performing edge detection on the corresponding serial communication signal to capture the low level pulse width and high level pulse width of the serial communication signal;

[0025] A judging module, used for judging whether the signal waveform captured by the capture and analysis module is the signal waveform of the target frame header data according to the captured low-level pulse width and high-level pulse width when the number of pulses captured by the capture and analysis module reaches the pulse number threshold;

[0026] The baud rate calculation module is used to select at least one continuous low-level pulse width and at least one high-level pulse width from all low-level pulse widths and high-level pulse widths captured by the capture analysis module to calculate the baud rate after the judgment module determines that the captured signal waveform is the signal waveform of the target frame header data.

[0027] Optionally, the pre-configuration module is used to receive and parse the corresponding target frame header data, obtain the pulse width ratio between each pulse in the signal waveform corresponding to the target frame header data and the pulse number threshold, the signal waveform has at least one low-level pulse and at least one high-level pulse, and the pulse width of each pulse is at least 1 bit;

[0028] Alternatively, the pre-configuration module is used to directly configure at least one of the pulse number threshold and the pulse width ratio between each pulse in the signal waveform by configuring a register or modifying a code parameter.

[0029] Optionally, the capture and analysis module further includes at least one of the following circuits:

[0030] An edge detection circuit, used for detecting the rising edge and the falling edge of the serial communication signal to generate a rising edge trigger signal and a falling edge trigger signal;

[0031] A capture circuit, connected to the edge detection circuit, for capturing the low level pulse width and the high level pulse width of the serial communication signal according to the rising edge trigger signal and the falling edge trigger signal;

[0032] A counting circuit, used for counting the pulses captured by the capture circuit while the capture circuit captures the low level pulse width and the high level pulse width of the serial communication signal;

[0033] A timing circuit, used for timing while the capture circuit captures the low level pulse width and the high level pulse width of the serial communication signal;

[0034] The storage register is used to store the low level pulse width and the high level pulse width captured by the capture circuit.

[0035] Optionally, the baud rate detection device further includes:

[0036] An interrupt module, used for ending the capture of the capture circuit when the count of the counting circuit reaches the pulse number threshold within a specified time threshold, or when the timing of the timing circuit exceeds the time threshold, or when a specified capture interrupt condition is triggered;

[0037] A CPU, wherein at least one of the preconfiguration module, the determination module and the baud rate calculation module is integrated in the CPU;

[0038] A DMA channel and a random access memory, wherein the DMA channel is used to directly move the data stored in the storage register to the cache in the random access memory for reading by the CPU.

[0039] Optionally, the judgment module is also used to compare the ratio between the captured high-level pulse width and the low-level pulse width with a corresponding ratio threshold, or to compare the ratio of the time between two adjacent falling edges and two adjacent rising edges in the captured signal waveform with a corresponding ratio threshold, and when the comparison result is within an allowable range, it is determined that the captured signal waveform is the signal waveform of the target frame header data.

[0040] Optionally, the baud rate calculation module is further used to calculate the sum of the pulse widths of a low pulse and a high pulse and the total number of bits, and divide the sum of the pulse widths by the total number of bits to obtain a time width of one bit, and then calculate the baud rate.

[0041] Optionally, the baud rate detection device further includes:

[0042] A baud rate comparison module, used for comparing the baud rate obtained by the baud rate calculation module with the ideal baud rate;

[0043] The correction module is used to perform baud rate adaptive adjustment on the serial communication signal according to the comparison result of the baud rate comparison module.

[0044] Based on the same inventive concept, the present invention also provides a serial communication system, which includes the baud rate detection device as described in the present invention.

[0045] Optionally, the serial communication system further comprises:

[0046] The chip to be tested communicates with the baud rate detection device via a serial port.

[0047] The baud rate detection device performs baud rate testing or correction on the chip to be tested.

[0048] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0049] 1. It can automatically detect the edge, capture the pulse width and judge the signal waveform of the serial communication signal, and calculate the baud rate by taking the continuous "at least 1 low-level pulse width + at least 1 high-level pulse width" to eliminate the slope error.

[0050] 2. Able to parse the target frame header data to obtain the pulse number threshold and the ratio of low-level pulse width to high-level pulse width to simplify operations and improve efficiency.

[0051] 3. The user can freely configure the pulse number threshold and the ratio of low-level pulse width to high-level pulse width corresponding to the target frame header data to realize the configuration of personalized target frame header data and the detection of the baud rate corresponding to the personalized target frame header data. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0053] Figure 1 It is a flowchart of a baud rate detection method according to an embodiment of the present invention.

[0054] Figure 2 yes Figure 1 An exemplary flow chart of step S1 in the baud rate detection method is shown.

[0055] Figure 3A yes Figure 1The signal waveform, pulse number threshold and pulse width ratio of the target frame header data analyzed in step S1 in the baud rate detection method shown.

[0056] FIG. 3B to FIG. 3D yes Figure 1 The illustrated baud rate detection method in step S2 captures three exemplary schematic diagrams of signal waveforms that are not target frame header data.

[0057] Figure 4A and Figure 4B yes Figure 1 The schematic diagram of the principle of step S3 in the baud rate detection method shown is to determine whether the captured signal waveform is the signal waveform of the target frame header data.

[0058] Figure 5 It is a schematic diagram of an exemplary structure of a baud rate detection device according to an embodiment of the present invention.

[0059] Figure 6 It is a schematic diagram of an exemplary structure of a baud rate detection device according to another embodiment of the present invention.

[0060] Figure 7 yes Figure 6 The schematic diagram of the working process of the baud rate detection device shown.

[0061] Figure 8 It is a schematic diagram of an exemplary structure of a baud rate detection device according to another embodiment of the present invention.

[0062] Fig. 9 and Fig.10 2 are two exemplary structural diagrams of a serial communication system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0063] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0064] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0065] Please refer to Figure 1 An embodiment of the present invention provides a baud rate detection method, which includes the following steps:

[0066] S1, determining the pulse number threshold of the signal waveform of the target frame header data of the serial communication protocol;

[0067] S2, performing edge detection on the corresponding serial communication signal to capture the low level pulse width and high level pulse width of the serial communication signal;

[0068] S3, when the number of captured pulses reaches the pulse number threshold, judging whether the captured signal waveform is the signal waveform of the target frame header data according to the captured low-level pulse width and high-level pulse width;

[0069] If yes, then execute S4, select at least one continuous low level pulse width and at least one high level pulse width from all captured low level pulse widths and high level pulse widths to calculate the baud rate;

[0070] If not, the process returns to S2 and continues to detect subsequent signals until the target frame header data (ie, data corresponding to a signal waveform with specific requirements) is found, so as to ensure the accuracy of the final baud rate result.

[0071] In step S1, the target frame header data is different, and the corresponding signal waveform (pattern) is also different.

[0072] In an embodiment of the present invention, the target frame header data may be preset and fixed.

[0073] In one embodiment of the present invention, the target frame header data can also allow the user to freely configure it as needed. In this case, the target frame header data can be configured by, for example, the user directly configuring at least one of the pulse number threshold and the pulse width ratio of the high and low level pulses by configuring registers or modifying code parameters, or it can be, for example, obtained by the user through the user interface (User Interface, UI) and then parsed by the program, which at least has the target "high and low level pulse width ratio" and "pulse number threshold". Exemplarily, the user enters the format data 0xFB in the UI interface by keyboard or voice input, and step S1 performs format parsing on "0xFB" to obtain the pulse number threshold and the pulse width ratio of the high and low level pulses.

[0074] That is to say, in step S1, the pulse number threshold, high-low level pulse width ratio and other characteristics of the signal waveform of the target frame header data of the serial communication protocol can be determined by receiving preset fixed target frame data or receiving corresponding format data freely configured by the user. Among them, the user free configuration method is suitable for special communication scenarios in which the user customizes the target frame header data, and the preset fixed target frame data method is suitable for conventional communication scenarios in which fixed target frame header data is automatically generated or received.

[0075] As an example, see Figure 2 In step S1, the process of determining the pulse number threshold of the signal waveform of the target frame header data of the serial communication protocol includes:

[0076] S11, receiving corresponding target frame header data, the target frame header data format may be any suitable data that can be converted into a binary sequence, which may be an octal, decimal or hexadecimal value;

[0077] S12, parsing the obtained target frame header data into a corresponding binary sequence;

[0078] S13, taking the value of the total number of flipping times of the data frame signal of the binary sequence minus 1 as the pulse number threshold N;

[0079] S14, recording the number of bits (i.e., the number of bits) of each high level and low level in the binary sequence, wherein the ratio of the number of bits of the high level to the number of bits of the low level is the pulse width ratio between the corresponding high level pulse and the low level pulse;

[0080] S15, forming a signal waveform of the target frame header data and saving relevant data such as the pulse number threshold and the pulse width ratio between each pulse, wherein the signal waveform has at least one low-level pulse and at least one high-level pulse, and the pulse width of each pulse is at least 1 bit.

[0081] In step S2, the actually transmitted serial communication signal is received to perform edge detection and pulse width capture on it.

[0082] In one embodiment of the present invention, edge detection may be performed only after the idle (high level) time of the serial communication signal reaches a corresponding time threshold to capture the low level pulse width and high level pulse width of the serial communication signal. For example, the first pulse of the serial communication signal is a low level pulse, so the low level pulse width and high level pulse width of the serial communication signal are captured after the first falling edge is detected.

[0083] Optionally, in step S2, while capturing the low-level pulse width and the high-level pulse width of the serial communication signal, timing is also performed and the captured pulses are counted, and: (1) when the count (i.e., the number of pulses counted) within the specified time threshold Tmax reaches the pulse number threshold N, the timing ends (i.e., interrupts) the capture, and the subsequent step S3 is performed to avoid capturing other unnecessary pulses and improve efficiency, that is, when in step S2, M (pulse number threshold) pulses are detected within the specified time, step S3 is executed to determine whether the captured signal waveform is the signal waveform of the target frame header data based on the low-level pulse width and the high-level pulse width captured in step S2; or, (2) when the timing exceeds the time threshold Tmax, the capture is ended (i.e., interrupted) in time. In this case, the number of captured pulses is less than the pulse number threshold N. The interrupt mechanism can prevent falling into a state of waiting for the next pulse or edge for a long time, thereby avoiding wasting time.

[0084] Optionally, the capture interrupt (i.e., end) mechanism (i.e., interrupt mechanism) in step S2 includes: (1) whether the captured pulse number (i.e., count) reaches the pulse number threshold N; (2) whether the capture time (i.e., timing) exceeds the specified time threshold Tmax; (3) whether other capture interrupt conditions are triggered. The priorities of these interrupt mechanisms are arranged from low to high as (1)>(2)>(3).

[0085] As an example, see Figure 3A, assuming that the target frame header data received in step S1 is 0x1e, the signal waveform obtained after format analysis of the target frame header data is "2 bits of low level + 4 bits of high level + 3 bits of low level", that is, the number of edges is 4, and the pulse number threshold N = 4-1 = 3; the first pulse is a low-level pulse, and its bit number T[0] = 2, the second pulse is a high-level pulse, and its bit number T[1] = 4, and the third pulse is a low-level pulse, and its bit number T[2] = 3. The pulse width ratio (i.e., ratio threshold) of the target frame header data is T[0]:T[1]:T[2] = 2:4:3. When edge detection and pulse width capture are performed in step S2, the following situations may occur:

[0086] (1) Please refer to Figure 3B In step S2, the number of edges of the actual input serial communication signal frame header is the same as the number of edges of the target frame header data. When edge detection is performed, N (pulse number threshold) pulses can be detected within the specified time threshold. However, when executing step S3, it is determined that the bit number of the captured second pulse is T[1]=3, which is different from the bit number of the second pulse obtained by parsing the target frame header data, T[1]=4, or it is determined that the pulse width ratio of the captured signal waveform is T[0]:T[1]:T[2]=2:3:3, which is different from the pulse width ratio of the signal waveform obtained by parsing the target frame header data, T[0 ]:T[1]:T[2]=2:4:3, or, the pulse width ratio of the captured signal waveform is determined to be T[0]:T[1]:T[2]=2:3:3, and the error of the pulse width ratio (i.e., ratio threshold) T[0]:T[1]:T[2]=2:4:3 of the signal waveform obtained by parsing the target frame header data exceeds the allowable range (e.g., ±10%). Therefore, it is determined that the signal waveform captured in step S2 within the specified time is not the signal waveform of the target frame header data, thereby triggering the interrupt mechanism, ending the capture, resetting the timing and pulse counting, and waiting for the next pulse (i.e., waiting for the next edge).

[0087] (2) Please refer to Figure 3CIn step S2, the number of edges of the actual input serial communication signal frame header (6) is greater than the number of edges obtained by parsing the target frame header data. When edge detection is performed on the actual input serial communication signal, N=3 (pulse number threshold) pulses can be detected within the specified time threshold. However, in step S3, it is determined that the bit number T[1]=3 of the captured second pulse is different from the bit number T[1]=4 of the second pulse obtained by parsing the target frame header data, or it is determined that the pulse width ratio of the captured signal waveform is T[0]:T[1]:T[2]=2:3:3, which is different from the signal waveform obtained by parsing the target frame header data. The pulse width ratio of T[0]:T[1]:T[2]=2:4:3, or the pulse width ratio of the captured signal waveform is determined to be T[0]:T[1]:T[2]=2:3:3, and the error of the pulse width ratio (i.e., ratio threshold) T[0]:T[1]:T[2]=2:4:3 of the signal waveform obtained by parsing the target frame header data exceeds the allowable range (e.g., ±10%). Therefore, it is determined that the signal waveform captured in step S2 within the specified time is not the signal waveform of the target frame header data, thereby triggering the interrupt mechanism, ending the capture, resetting the timing and pulse counting, and waiting for the next pulse (i.e., waiting for the next edge).

[0088] (3) Please refer to Figure 3D In step S2, the number of edges of the actual input serial communication signal frame header (2) is less than the number of edges obtained by parsing the target frame header data. When edge detection is performed on the actual input serial communication signal, N=3 (pulse number threshold) pulses cannot be detected until the timing exceeds the specified time threshold. Therefore, there is no need to execute step S3, and the timeout interrupt mechanism is directly triggered to end the capture, reset the timing and pulse counting, and wait for the next pulse (i.e., wait for the next edge).

[0089] As another example, see Figure 4A, assuming that the target frame header data set in step S1 is 0XFB, and the signal waveform obtained by parsing the target frame header data is "1 bit low level + 2 bit high level + 1 bit low level + 6 bit high level", the pulse number threshold N is determined to be 4, and the ratio of these low level pulse widths to high level pulse widths (i.e., the ratio threshold) is 1:2:1:6. When edge detection and pulse width capture are performed in step S2, 4 pulses are captured within the specified time, and because the communication may be discontinuous, the number of bits of the last high level pulse captured is allowed to be ≥6, and then step S3 is executed to determine whether the signal waveform captured in step S2 within the specified time is the signal waveform of the target frame header data through any appropriate judgment condition, that is, to determine whether the data captured in step S2 within the specified time is the correct frame header data 0xFB. Among them, because there may be a slope error that causes the high and low level pulse width times under the same bit width to be different, the judgment condition can be appropriately relaxed in step S3.

[0090] In step S3, a judgment method is, for example, Figure 4A , it is determined whether the error between the pulse width ratio of the four captured pulses and the above-mentioned ratio threshold 1:2:1:6 is within the allowable range (for example, a 10% ratio error), rather than strictly requiring that the ratio of the captured pulse width is completely equal to the ratio of the pulse width of the target frame header data. If so, it is considered that the captured signal waveform is the signal waveform of the target frame header data, that is, the captured data can be considered to be the correct frame header data 0xFB; if not, it is considered that the captured signal waveform is not the signal waveform of the target frame header data, that is, the captured data can be considered not to be the correct frame header data 0xFB.

[0091] Another way of judging in step S3 is, for example, Figure 4B , compare the time ratio between two adjacent falling edges and two adjacent rising edges in the captured signal waveform with the corresponding proportional threshold (which can be 1), for example, compare the time ratio between the first falling edge and the second falling edge and the time ratio between the first rising edge and the second rising edge with the corresponding proportional threshold, that is, compare the ratio (L0+L1) / (L1+L2) between the sum of the pulse widths of the first pulse and the second pulse and the sum of the pulse widths of the second pulse and the third pulse with the proportional threshold 1. If it is equal to 1 or the difference between (L0+L1) / (L1+L2) and 1 is within the allowable range (for example, within ±5%), then it is considered that the captured signal waveform is the signal waveform of the target frame header data, that is, the captured data can be considered to be the correct frame header data 0xFB; if not, it is considered that the captured signal waveform is not the signal waveform of the target frame header data, that is, the captured data can be considered not to be the correct frame header data 0xFB.

[0092] After confirming in step S3 that the captured signal waveform is the signal waveform of the target frame header data (for example, the captured data can be considered as the correct frame header data 0xFB), in step S4, a continuous low-level pulse width and a high-level pulse width can be selected from the pulse widths captured in step S2 and added, and further divided by the total number of bits of the two, to obtain a time width of a bit (referred to as bit time BT), that is, the time required to transmit a bit of data. For example, the first low-level pulse width is selected and added to the first high-level pulse width thereafter, and the time width of a bit (also referred to as bit time) BT = (L0 + L1) / (1 + 2) = 104μs is calculated, and further calculation (for example, taking the inverse of BT) can obtain the baud rate BR, that is, BR = 1 / BT.

[0093] It should be understood that in other embodiments of the present invention, in step S4, at least one continuous low-level pulse width and at least one high-level pulse width may be selected from the pulse widths captured in step S2 and added, and further divided by the total number of bits of these pulse widths to obtain the bit time. For example, please refer to Figure 4B , select the first low-level pulse width and the second low-level pulse width and further select the first high-level pulse width sandwiched between the two, add the three together, and further divide by the total number of bits of the three pulse widths, and the calculated bit time BT = (L0 + L1 + L2) / (1 + 2 + 1). For another example, please refer to Figure 4B , select the pulse widths of 4 consecutive pulses, add them up and divide them by the total number of bits of these 4 pulse widths, and calculate the bit time BT = (L0+L1+L2+L3) / (1+2+1+6).

[0094] Optionally, after step S4, step S5 may be further performed to compare the baud rate calculated in step S4 with the ideal baud rate; and step S6 to determine whether the baud rate is abnormal based on the comparison result, or to perform adaptive baud rate adjustment based on the comparison result.

[0095] Based on the same invention concept, please refer to Figure 5 An embodiment of the present invention further provides a baud rate detection device 1, which can implement the baud rate detection method of the present invention and may include a pre-configuration module 11, a capture and analysis module 12, a judgment module 13 and a baud rate calculation module 14.

[0096] Among them, the pre-configuration module 11 is used to implement step S1 of the baud rate detection method of the present invention, that is, to determine the pulse number threshold of the signal waveform of the target frame header data of the serial communication protocol. Optionally, the pre-configuration module 11 can receive the corresponding target frame header data (the target frame header data can be freely configured by the user as needed, or it can be a preset fixed target frame header data sent by an external device such as a chip to be tested), and parse the target frame header data to obtain the signal waveform corresponding to the target frame header data and the pulse number threshold of the signal waveform and the pulse width ratio between each pulse, wherein the signal waveform has at least one low-level pulse and at least one high-level pulse, and the pulse width of each pulse is at least 1 bit; or, the pre-configuration module directly configures at least one of the pulse number threshold and the pulse width ratio between each pulse in the signal waveform corresponding to the target frame header data by configuring a register or modifying a code parameter, so as to realize the information such as the pulse number threshold that needs to be configured in the pre-configuration module 11. The working principle of the pre-configuration module 11 can refer to the content of step S1 above, and will not be repeated here.

[0097] The capture and analysis module 12 is used to implement step S2 of the baud rate detection method of the present invention, that is, to perform edge detection on the corresponding serial communication signal to capture the low level pulse width and high level pulse width of the serial communication signal.

[0098] Optionally, the capture and analysis module 12 includes at least one of the following circuits:

[0099] The edge detection circuit 121 is used to detect the rising edge and the falling edge of the serial communication signal to generate a rising edge trigger signal and a falling edge trigger signal;

[0100] A capture circuit 122, connected to the edge detection circuit 121, for capturing a low level pulse width and a high level pulse width of the serial communication signal according to the rising edge trigger signal and the falling edge trigger signal;

[0101] a counting circuit 123, connected to the edge detection circuit 121, and configured to be triggered when the edge detection circuit 121 detects an edge corresponding to the serial port communication signal (e.g., the first edge), so as to count the pulses captured by the capture circuit while the capture circuit 122 captures the low level pulse width and the high level pulse width of the serial port communication signal;

[0102] A timing circuit 124, connected to the edge detection circuit 121, for triggering when the edge detection circuit 121 detects an edge corresponding to the serial communication signal (e.g., the first edge), so as to perform timing while the capture circuit 122 captures the low-level pulse width and the high-level pulse width of the serial communication signal;

[0103] The storage register 125 is used to store the low level pulse width and the high level pulse width captured by the capture circuit 122. In one embodiment of the present invention, the storage register 125 may also include a configuration register to store the pulse number threshold of the signal waveform of the target frame header data configured or determined in the pre-configuration module 11 and the pulse width ratio between each pulse.

[0104] The judgment module 13 is used to implement step S3 of the baud rate detection method of the present invention, that is, when the number of pulses captured by the capture and analysis module 12 reaches the pulse number threshold, it is judged whether the signal waveform captured by the capture and analysis module 12 is the signal waveform of the target frame header data according to the low level pulse width and the high level pulse width captured by the capture and analysis module 12. For example, the judgment module 13 is also used to compare the ratio between the high level pulse width and the low level pulse width captured by the capture and analysis module 12 with the corresponding ratio threshold, or compare the ratio between the time of two adjacent falling edges and two adjacent rising edges in the captured signal waveform with the corresponding ratio threshold, and when the comparison result is within the allowable range, it is determined that the signal waveform captured by the capture and analysis module 12 is the signal waveform of the target frame header data. Among them, the working principle of the judgment module 13 can refer to the content of step S3 above, and will not be repeated here.

[0105] Optionally, after determining that the captured signal waveform is not the signal waveform of the target frame header data, the judgment module 13 resets the counting circuit 123 and the timing circuit 124 in the capture and analysis module 12 .

[0106] The baud rate calculation module 14 is used to implement step S4 of the baud rate detection method of the present invention, that is, after the judgment module 13 determines that the captured signal waveform is the signal waveform of the target frame header data, select at least one continuous low-level pulse width and at least one high-level pulse width from all low-level pulse widths and high-level pulse widths captured by the capture analysis module 12 to calculate the baud rate. For example, the baud rate calculation module 14 calculates the sum of the pulse widths of a low pulse width and a high pulse width and the total number of bits, and divides the sum of the pulse widths by the total number of bits to obtain a time width BT of one bit, and further calculates the baud rate (for example, taking the inverse of BT) based on the time width to one bit. Among them, the working principle of the baud rate calculation module 14 can refer to the content of step S4 above, which will not be repeated here.

[0107] Please refer to Figure 6 In another embodiment of the present invention, the baud rate detection device includes, in addition to the above-mentioned pre-configuration module 11, capture analysis module 12, judgment module 13, and baud rate calculation module 14, further includes:

[0108] The interrupt module 15 is used to terminate the capture of the capture circuit when the count of the capture circuit reaches the pulse number threshold within a specified time threshold, or when the timing exceeds the time threshold, or when a specified capture interrupt condition is triggered.

[0109] CPU 18, wherein at least one of the pre-configuration module 11, the determination module 13 and the baud rate calculation module 14 is integrated in the CPU;

[0110] A DMA channel 17 and a random access memory (eg, RAM) 16 , wherein the DMA channel 17 is used to directly transfer the data stored in the storage register 125 to the random access memory 16 for cache without passing through the CPU.

[0111] The working principle of the baud rate detection device of this embodiment is as follows Figure 7 As shown, the following operations are included:

[0112] First, the pulse number threshold N of the signal waveform of the target frame header data is determined by the pre-configuration module 11;

[0113] Next, the maximum count value of the counting circuit 123 (or the maximum count value in the DMA 17 ) DMA_CNT is configured to be N according to the pulse number threshold value N obtained in the pre-configuration module 11 ;

[0114] Then, the maximum timing value in the timing circuit 124 is configured as Tmax according to the pulse number threshold N and other information configured in the pre-configuration module 11;

[0115] Afterwards, the edge detection circuit 121 is set to start the capture circuit 122 and reset the counting circuit 123 and the timing circuit 124 when detecting the first rising edge or falling edge;

[0116] Wait for the count value DMA_CNT of the counting circuit 123 (or the count value in DMA 17) to reach N. If the timing circuit 124 times out, the timeout interrupt mechanism is triggered, the count value DMA_CNT of the counting circuit 123 (or the count value in DMA17) is reset, and the next baud rate detection is waited; if it reaches N and does not time out, the judgment module 13 reads the data in the random access memory RAM 16 (i.e., the pulse width of the corresponding pulse) to determine whether the data captured by the capture circuit 122 (i.e., the signal waveform) is the target frame header data. If it is determined that the data captured by the capture circuit 122 (i.e., the signal waveform) is not the target frame header data, the count value DMA_CNT of the counting circuit 123 (or the count value in DMA17) is reset, and the next baud rate detection is waited;

[0117] If the judgment module 13 determines that the data (i.e., signal waveform) captured by the capture circuit 122 is the target frame header data, the baud rate calculation module 14 reads the corresponding data (e.g., a continuous low pulse width and a high pulse width) in the random access memory RAM 16 and calculates the baud rate based on it.

[0118] In one embodiment of the present invention, please refer to Figure 8 , the baud rate detection device further comprises:

[0119] A baud rate comparison module 19, used for comparing the baud rate obtained by the baud rate calculation module 14 with the ideal baud rate;

[0120] The correction module 10 is used to perform baud rate adaptive adjustment on the serial communication signal according to the comparison result of the baud rate comparison module 19.

[0121] It should be understood that, in the baud rate detection device of the present invention, the pre-configuration module 11, the capture and analysis module 12, the judgment module 13, the baud rate calculation module 14, the interrupt module 15, the CPU 18, the DMA channel 17 and the random access memory 16, the baud rate comparison module 19, the correction module 10 and other modules can be combined in one module for implementation, or any one of the circuit modules can be split into multiple modules, or at least part of the functions or circuits of one or more of these circuit modules can be combined with at least part of the functions or circuits of other circuit modules and implemented in one module. According to an embodiment of the present invention, at least one of the modules such as the pre-configuration module 11, the capture and analysis module 12, the judgment module 13, the baud rate calculation module 14, the interrupt module 15, the CPU 18, the DMA channel 17 and the random access memory 16, the baud rate comparison module 19, and the correction module 10 can be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application-specific integrated circuit (ASIC), or can be implemented by hardware or firmware in any other reasonable way of integrating or packaging the circuit, or by an appropriate combination of software, hardware, and firmware. Alternatively, at least one of the modules such as the pre-configuration module 11, the capture and analysis module 12, the judgment module 13, the baud rate calculation module 14, the interrupt module 15, the CPU 18, the DMA channel 17 and the random access memory 16 can be at least partially implemented as a computer program module, and when the program is run by a computer, the function of the corresponding module can be executed.

[0122] For example, please combine Figure 6 and Figure 8The pre-configuration module 11, the capture and analysis module 12, the judgment module 13, the baud rate calculation module 14, the interrupt module 15, the baud rate comparison module 19, and the correction module 10 are all integrated in the CPU 18; or, one or more of the pre-configuration module 11, the capture and analysis module 12, the judgment module 13, the baud rate calculation module 14, the interrupt module 15, the baud rate comparison module 19, and the correction module 10 are arranged outside the CPU 18.

[0123] It should be understood that the baud rate detection device of the present invention is applicable to any scenario under a serial communication protocol that requires baud rate detection or correction or adaptive adjustment of baud rate.

[0124] Based on this, please refer to Fig. 9 An embodiment of the present invention further provides a serial communication system, which includes the baud rate detection device 1 as described in the present invention.

[0125] In one embodiment of the present invention, the serial communication system further comprises a chip under test 2, which communicates with the baud rate detection device 1 via a serial port (having a signal transmission module TX and a signal receiving module RX). The baud rate detection device 1 performs baud rate testing or calibration on the chip under test 2.

[0126] As an example, see Fig.10 The baud rate detection device 1 can be directly used as a test / correction device for baud rate detection of a corresponding chip to be tested 2 (for example, an MCU chip, etc.), or the baud rate detection device 1 is simply integrated as a module in a test / correction device for performing relevant tests on the corresponding chip to be tested 2. The chip to be tested 2 communicates with the baud rate detection device 1 through a serial port, and the baud rate detection device 1 is placed in the test / correction device and draws power from the test / correction device.

[0127] The chip to be tested 2 is internally provided with an RC oscillator 21, a serial port module 22, and a clock deviation correction module 23. The RC oscillator 21 is used as a clock source to configure the working clock of the system, and this clock is also provided to the peripheral modules of the chip to be tested 2, such as the serial port module 22. The serial port module 22 further divides the peripheral bus clock more accurately through a frequency divider with decimal places (such as PLL) to obtain a target baud rate, and the device coupled to the serial port module 22 (such as the baud rate detection device 1) and the chip to be tested 2 communicate at the target baud rate. However, the accuracy of the RC oscillator 21 decreases within a certain period of time, and the deviation of the clock will cause the baud rate to deviate from the expected value, which will cause the baud rate of the serial communication to decrease. If the deviation between the actual baud rate and the target baud rate is too large, it will affect the communication performance of the system. Therefore, one end of the baud rate detection device 1 of the present invention is connected to the signal sending module TX of the serial port module 22 of the chip to be tested 2, and the other end is connected to the signal receiving module RX of the serial port module 22 of the chip to be tested 2. When the baud rate detection device 1 receives the data sent by the chip to be tested 2, it can calculate the corresponding baud rate according to the received data, and then determine whether the baud rate of the chip to be tested 2 is abnormal. In a further embodiment, the baud rate detection result of the baud rate detection device 1 can be fed back to the clock deviation correction module 23 in the chip to be tested 2 through the serial port. The clock deviation correction module 23 compares the actual baud rate detected by the baud rate detection device 1 with the target baud rate, calculates the deviation between the actual baud rate and the target baud rate, and thus infers the specific deviation ratio of the clock, and then corrects the clock deviation of the RC oscillator 21, to ensure that the baud rate used by the serial port module 22 is accurate.

[0128] Optionally, the clock deviation correction module 23 may include a frequency divider with decimal places (eg, a PLL), etc., to correct the working clock of the RC oscillator 21 to a precise clock with a target baud rate.

[0129] Optionally, the testing / correcting device can also display to the user the range of deviation of the calculated baud rate relative to the target baud rate, or indicate whether the baud rate is abnormal or not, based on the result of the baud rate detecting device 1 .

[0130] In summary, the baud rate detection device and serial communication system of the present invention can accurately detect the baud rate and eliminate the slope error, and are applicable to any appropriate serial communication scenario.

[0131] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A baud rate detection method, characterized in that: The following steps are involved: S1, determining the pulse number threshold of the signal waveform of the target frame header data of the serial communication protocol; S2, performing edge detection on the corresponding serial communication signal to capture the low level pulse width and high level pulse width of the serial communication signal; S3, when the number of captured pulses reaches the pulse number threshold, judging whether the captured signal waveform is the signal waveform of the target frame header data according to the captured low-level pulse width and high-level pulse width; If yes, then S4 is executed to select at least one continuous low-level pulse width and at least one high-level pulse width from all captured low-level pulse widths and high-level pulse widths to calculate the baud rate.

2. The baud rate detection method as claimed in claim 1, wherein: In step S1, the corresponding target frame header data is received and parsed to obtain the pulse width ratio between each pulse in the signal waveform corresponding to the target frame header data and the pulse number threshold, wherein the signal waveform has at least one low-level pulse and at least one high-level pulse, and the pulse width of each pulse is at least 1 bit.

3. The baud rate detection method as claimed in claim 2, characterized in that: In step S1, the step of parsing the target frame header data includes: parsing the target frame header data into a corresponding binary sequence; taking the value of the total number of data frame signal flips of the binary sequence minus 1 as the pulse number threshold; recording the number of bits of each high level and low level in the binary sequence, wherein the ratio of the number of high level bits to the number of low level bits is the pulse width ratio between the corresponding high level pulses and the low level pulses.

4. The baud rate detection method according to claim 1, wherein: In step S1, at least one of the pulse number threshold and the pulse width ratio between pulses in the signal waveform of the target frame header data is directly configured by configuring a register or modifying a code parameter.

5. The baud rate detection method according to claim 1, wherein: In step S2, while capturing the low level pulse width and the high level pulse width of the serial communication signal, timing is also performed and the captured pulses are counted, and the capture is terminated when the count within a specified time threshold reaches the pulse number threshold, or the capture is terminated when the timing exceeds the time threshold.

6. The baud rate detection method according to claim 1, wherein: In step S3, the ratio between the captured high-level pulse width and the low-level pulse width is compared with the corresponding ratio threshold value. If the comparison result is within the allowable range, it is determined that the captured signal waveform is the signal waveform of the target frame header data. If the comparison result exceeds the allowable range, it is determined that the captured signal waveform is not the signal waveform of the target frame header data. Alternatively, in step S3, the time ratio between two adjacent falling edges and two adjacent rising edges in the captured signal waveform is compared with a corresponding proportional threshold; if the comparison result is within an allowable range, the captured signal waveform is determined to be the signal waveform of the target frame header data; if the comparison result exceeds the allowable range, the captured signal waveform is determined not to be the signal waveform of the target frame header data.

7. The baud rate detection method according to claim 1, wherein: In step S4, the sum of the pulse widths of a low pulse and a high pulse and the total number of bits are calculated, and the sum of the pulse widths is divided by the total number of bits to obtain a time width of one bit, and then the baud rate is calculated.

8. The baud rate detection method according to any one of claims 1 to 7, characterized in that: After step S4, the method further includes: Step S5, comparing the baud rate with an ideal baud rate; Step S6, judging whether the baud rate is abnormal according to the comparison result, or adaptively adjusting the baud rate according to the comparison result.

9. A baud rate detection device, characterized in that: include: A pre-configuration module, used to determine a pulse number threshold of a signal waveform of target frame header data of a serial communication protocol; A capture and analysis module, used for performing edge detection on the corresponding serial communication signal to capture the low level pulse width and high level pulse width of the serial communication signal; A judging module, used for judging whether the signal waveform captured by the capture and analysis module is the signal waveform of the target frame header data according to the captured low-level pulse width and high-level pulse width when the number of pulses captured by the capture and analysis module reaches the pulse number threshold; The baud rate calculation module is used to select at least one continuous low-level pulse width and at least one high-level pulse width from all low-level pulse widths and high-level pulse widths captured by the capture analysis module to calculate the baud rate after the judgment module determines that the captured signal waveform is the signal waveform of the target frame header data.

10. The baud rate detection device according to claim 9, characterized in that: The pre-configuration module is used to receive and parse the corresponding target frame header data, obtain the pulse width ratio between each pulse in the signal waveform corresponding to the target frame header data and the pulse number threshold, the signal waveform has at least one low-level pulse and at least one high-level pulse, and the pulse width of each pulse is at least 1 bit; Alternatively, the pre-configuration module is used to directly configure at least one of the pulse number threshold and the pulse width ratio between each pulse in the signal waveform by configuring a register or modifying a code parameter.

11. The baud rate detection device according to claim 9, characterized in that: The capture and analysis module further includes at least one of the following circuits: An edge detection circuit, used for detecting the rising edge and the falling edge of the serial communication signal to generate a rising edge trigger signal and a falling edge trigger signal; A capture circuit, connected to the edge detection circuit, for capturing the low level pulse width and the high level pulse width of the serial communication signal according to the rising edge trigger signal and the falling edge trigger signal; A counting circuit, used for counting the pulses captured by the capture circuit while the capture circuit captures the low level pulse width and the high level pulse width of the serial communication signal; A timing circuit, used for timing while the capture circuit captures the low level pulse width and the high level pulse width of the serial communication signal; The storage register is used to store the low level pulse width and the high level pulse width captured by the capture circuit.

12. The baud rate detection device according to claim 11, characterized in that: Also includes: An interrupt module, used for ending the capture of the capture circuit when the count of the counting circuit reaches the pulse number threshold within a specified time threshold, or when the timing of the timing circuit exceeds the time threshold, or when a specified capture interrupt condition is triggered; A CPU, wherein at least one of the preconfiguration module, the determination module, the baud rate calculation module and the interrupt module is integrated in the CPU; A DMA channel and a random access memory, wherein the DMA channel is used to directly move the data stored in the storage register to the random access memory for caching so as to be read by the CPU.

13. The baud rate detection device according to claim 9, characterized in that: The judgment module is also used to compare the ratio between the captured high-level pulse width and the low-level pulse width with the corresponding ratio threshold, or to compare the ratio between the time of two adjacent falling edges and two adjacent rising edges in the captured signal waveform with the corresponding ratio threshold, and when the comparison result is within the allowable range, it is determined that the captured signal waveform is the signal waveform of the target frame header data.

14. The baud rate detection device according to claim 9, characterized in that: The baud rate calculation module is also used to calculate the sum of the pulse widths of a low pulse and a high pulse and the total number of bits, and divide the sum of the pulse widths by the total number of bits to obtain a time width of one bit, thereby calculating the baud rate.

15. The baud rate detection device according to any one of claims 9 to 14, characterized in that: Also includes: A baud rate comparison module, used for comparing the baud rate obtained by the baud rate calculation module with the ideal baud rate; The correction module is used to perform baud rate adaptive adjustment on the serial communication signal according to the comparison result of the baud rate comparison module.

16. A serial communication system, characterized in that: The invention comprises the baud rate detection device according to any one of claims 9 to 15.

17. The serial communication system according to claim 16, wherein: Also includes: The chip to be tested communicates with the baud rate detection device via a serial port. The baud rate detection device performs baud rate testing or correction on the chip to be tested.

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