Commercial power failure detection circuit

Abstract

The invention discloses a mains supply power failure detection circuit which comprises a mains supply sampling unit, a voltage comparison unit, a counting zero clearing unit, a power failure judgment unit and a stable output unit. The commercial power sampling unit comprises a sampling module and a rectification module, and commercial power is transmitted to the voltage comparison unit after being subjected to voltage reduction and rectification through the sampling module and the rectification module in sequence; the voltage comparison unit comprises a pulse voltage generation circuit module and is used for comparing the commercial power after voltage reduction and rectification with reference voltage, generating pulse voltage and transmitting the pulse voltage to the counting zero clearing unit; the counting zero clearing unit comprises a logic gate circuit module, and the pulse voltage can generate a counting zero clearing signal after passing through the logic gate circuit module; the power failure judgment unit comprises a D trigger, and a power failure judgment signal is generated after the pulse voltage and the counting zero clearing signal pass through the D trigger; and the stable output unit comprises a monostable trigger IC7. The circuit completely adopts separated devices, and has the advantages of few circuit components, high response speed, strong anti-interference capability and low cost.

Description

Technical Field

[0001] The invention relates to the technical field of mains power detection, in particular to a mains power failure detection circuit. Background Art

[0002] With the rapid growth of the scale of new energy microgrid construction, there is an increasing demand for uninterrupted power supply for important loads through seamless switching of energy storage systems on and off the grid. The premise of seamless switching of energy storage on and off the grid is to be able to quickly and accurately detect power outages or abnormal conditions of the mains. The time for seamless switching of microgrids on and off the grid is generally required to be completed within 20ms, while the shutdown time of thyristor fast switches is up to 10ms, so the detection time of mains power outages cannot exceed 10ms.

[0003] Since the grid voltage is a sinusoidal 50Hz signal, the voltage waveform will "cross zero" every 10ms. Using energy storage devices for detection is prone to circuit misjudgment. In order to reduce misjudgment, a large amount of calculation is required, which will reduce the detection speed and make it difficult to complete the mains power failure detection within 10ms. In addition, some manufacturers on the market use metering chips and single-chip microcomputers to perform zero-crossing detection and cumulative calculation of sampled voltage to determine mains power failure detection. This method is easily affected by harmonic interference and produces misjudgment. In order to reduce misjudgment, a large number of algorithms still need to be added for judgment, and the judgment time is difficult to complete within 10ms. Summary of the invention

[0004] In view of the above situation, it is necessary to provide a mains power failure detection circuit to solve the problems of slow speed and high cost of existing mains power failure detection products.

[0005] To achieve the above-mentioned purpose, the technical scheme of the present invention is as follows: a mains power failure detection circuit, comprising: a mains power sampling unit, a voltage comparison unit, a count reset unit, a power failure determination unit and a stable output unit; the mains power sampling unit comprises a sampling module and a rectification module, the mains power is successively stepped down and rectified by the sampling module and the rectification module, and then transmitted to the voltage comparison unit; the voltage comparison unit comprises a pulse voltage generation circuit module, which is used to compare the stepped down and rectified mains power with a reference voltage and generate a pulse voltage to transmit to the count reset unit; the count reset unit comprises a logic gate circuit module, and the pulse voltage can generate a count reset signal after passing through the logic gate circuit module; the power failure determination unit comprises a D trigger, and the pulse voltage and the count reset signal generate a power failure determination signal after passing through the D trigger; the stable output unit comprises a monostable trigger IC7, which is used to stably output the power failure determination signal.

[0006] In the mains power failure detection circuit of the present invention, the sampling module is a precision transformer PT1, the rectifier module is a low conduction voltage drop full-wave rectifier bridge, and the precision transformer PT1 is connected to the low conduction voltage drop full-wave rectifier bridge.

[0007] In the mains power failure detection circuit of the present invention, the pulse voltage generating circuit module includes a comparator IC1, the same-direction input terminal of the comparator IC1 is connected to the adjustable resistor R2, one end of the adjustable resistor R2 is externally connected to a 5V voltage, and the other end is connected to the negative pole of the rectifier module, and the reverse input terminal of the comparator IC1 is connected to the positive pole of the rectifier module.

[0008] In the mains power failure detection circuit of the present invention, the logic gate circuit module includes a connected XOR gate circuit IC3 and a plurality of NOT gate circuits IC2.

[0009] In the mains power failure detection circuit of the present invention, the D trigger includes a trigger IC4 and a trigger IC5, and the Q7 terminal of the trigger IC4 is connected to the DSB terminal of the trigger IC5.

[0010] The mains power failure detection circuit of the present invention further includes a clock pulse generator IC6, which is connected to the CP terminal of the trigger IC4 and the CP terminal of the trigger IC5 respectively.

[0011] In the mains power failure detection circuit of the present invention, the stable output unit further includes a NOT gate IC8 and an AND gate circuit IC9. The monostable trigger IC7, the NOT gate IC8 and the AND gate circuit IC9 are used to generate a steady-state level.

[0012] The mains power failure detection circuit of the present invention further includes a first optocoupler module and a second optocoupler module. The first optocoupler module and the second optocoupler module are respectively connected to the output end of the stable output unit for outputting a control signal and a feedback signal.

[0013] In the mains power failure detection circuit of the present invention, the comparator ICl adopts LM393.

[0014] In the mains power failure detection circuit of the present invention, the clock pulse generator IC6 adopts LM565.

[0015] Through the above technical scheme, the beneficial effects of the present invention are as follows: the present invention performs step-down rectification through the mains sampling unit, and transmits the rectified voltage to the voltage comparison unit for comparison with the reference voltage and generates a pulse voltage, and the pulse voltage generates a count reset signal after passing through the count reset unit, which can generate a power failure determination signal after being transmitted to the power failure determination unit with the pulse voltage, and outputs a steady-state level through the stable output unit, thereby preventing interference such as harmonics and flicker. This circuit adopts a fully separated period, has few circuit components, fast response speed, strong anti-interference ability and low cost, and can easily compress the mains power failure determination time to within 10ms by setting the parameters of the circuit elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic diagram of the circuit principle of an embodiment of the present invention;

[0017] Figure 2 1 is a waveform diagram of key points when the mains power is normal in an embodiment of the present invention;

[0018] Figure 3 It is a waveform diagram of key points when the mains power is cut off in an embodiment of the present invention. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present invention more clear, the following is a further detailed description of a mains power failure detection circuit of the present invention in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0020] Please refer to Figure 1-3 A mains power failure detection circuit comprises: a mains power sampling unit, a voltage comparison unit, a count reset unit, a power failure determination unit and a stable output unit; the mains power sampling unit comprises a sampling module and a rectifier module, the mains power is stepped down and rectified by the sampling module and the rectifier module in turn, and then transmitted to the voltage comparison unit; the voltage comparison unit comprises a pulse voltage generation circuit module, which is used to compare the stepped down and rectified mains power with a reference voltage and generate a pulse voltage to transmit to the count reset unit; the count reset unit comprises a logic gate circuit module, and the pulse voltage can generate a count reset signal after passing through the logic gate circuit module; the power failure determination unit comprises a D trigger, and the pulse voltage and the count reset signal generate a power failure determination signal after passing through the D trigger; the stable output unit comprises a monostable trigger IC7, which is used to stably output the power failure determination signal. This solution uses the mains sampling unit to perform step-down rectification, and transmits the rectified voltage to the voltage comparison unit to compare with the reference voltage and generate a pulse voltage. The pulse voltage generates a count reset signal after passing through the count reset unit, which can generate a power failure determination signal after being transmitted to the power failure determination unit with the pulse voltage, and outputs a steady-state level through the stable output unit to prevent interference such as harmonics and flicker. This circuit uses a fully separated period, with few circuit components, fast response speed, strong anti-interference ability and low cost. By setting the parameters of the circuit components, the mains power failure determination time can be easily compressed to within 10ms.

[0021] In this embodiment, the sampling module is a precision transformer PT1, the rectifier module is a low conduction voltage drop full-wave rectifier bridge, and the precision transformer PT1 is connected to the low conduction voltage drop full-wave rectifier bridge. Figure 1 As shown, the grid voltage (L, N) is stepped down by the precision transformer PT1, rectified into a 100Hz half-wave by a low conduction voltage drop full-wave rectifier bridge, and connected to the pulse voltage generation circuit module as Ui.

[0022] In this embodiment, the pulse voltage generating circuit module includes a comparator IC1, the same-direction input terminal of the comparator IC1 is connected to the adjustable resistor R2, one end of the adjustable resistor R2 is externally connected to a 5V voltage, and the other end is connected to the negative pole of the rectifier module, and the reverse input terminal of the comparator IC1 is connected to the positive pole of the rectifier module. According to the ratio of Ui to the grid voltage and the actual application situation, the reference voltage Uref is calculated. Uref is obtained by dividing the 5V voltage through the adjustable resistor R2. Uref is connected to the non-inverting input terminal of the comparator IC1, and Ui is connected to the inverting input terminal of the comparator IC1. The output pulse voltage signal Vi' of the comparator IC1 is low level when Ui is greater than Uref, and high level when Ui is less than Uref.

[0023] In this embodiment, the logic gate circuit module includes a connected XOR gate circuit IC3 and a plurality of NOT gate circuits IC2. The pulse voltage signal Vi' generates a timing clear signal Clear after passing through the logic gate circuits IC2 and IC3.

[0024] Furthermore, the D flip-flop includes a flip-flop IC4 and a flip-flop IC5, and the Q7 terminal of the flip-flop IC4 is connected to the DSB terminal of the flip-flop IC5. Specifically, the pulse voltage signal Vi' is connected to the DSB terminal of the D flip-flop IC4 as a serial input.

[0025] In this embodiment, a clock pulse generator IC6 is also included, and the clock pulse generator IC6 is connected to the CP terminal of the trigger IC4 and the CP terminal of the trigger IC5. The clock pulse generator IC6 generates a 2KHz clock pulse signal and connects to the CP terminal of the trigger IC4 and the trigger IC5. When the rising edge occurs, the trigger IC4 and the trigger IC5 read the serial input data and shift and output it in parallel.

[0026] In this embodiment, the stable output unit also includes a NOT gate IC8 and an AND gate circuit IC9. The monostable trigger IC7, the NOT gate IC8 and the AND gate circuit IC9 are used to generate a steady-state level. When the sampling voltage Ui is lower than the reference voltage Uref for more than 7ms within a certain period of time, it is determined that the mains power is off. Q5 of the trigger IC5 is used as the 7ms power-off detection output signal, which is inverted by the NOT gate circuit IC2 and used as the Vi input signal of the monostable trigger IC7. Vi outputs the Vo' signal after passing through the monostable trigger IC7. The inverted signals of Vi and Vo' pass through the NOT gate IC8 and the AND gate circuit IC9 and are output as a stable mains power-off detection signal Vo.

[0027] In this embodiment, a first optical coupling module and a second optical coupling module are also included, and the first optical coupling module and the second optical coupling module are respectively connected to the output end of the stable output unit for outputting a control signal and a feedback signal. The first optical coupling module performs an optical coupling to output a 12V control signal for the mains power failure detection signal Vo. The second optical coupling module performs an optical coupling to output a 5V feedback signal for the mains power failure detection signal Vo.

[0028] In this embodiment, the comparator IC1 adopts LM393, which has the advantages of low power consumption, high precision, strong anti-interference ability, etc., and can accurately perform voltage comparison even when there is noise or interference in the input signal. At the same time, it also has the advantages of high gain and high speed, and can respond quickly.

[0029] In this embodiment, the clock pulse generator IC6 adopts LM565, which is suitable for applications where precise frequency control and synchronization are required in this solution.

[0030] In summary, the grid voltage (L, N) is stepped down by the precision transformer PT1, rectified by the low conduction voltage drop rectifier bridge to become a 100Hz half-wave, and connected to the inverting terminal of the comparator as Ui. According to the ratio of Ui to the grid voltage and the actual application, the reference voltage is calculated as Uref. Uref is obtained by dividing the 5V voltage by the adjustable resistor R2. Uref is connected to the positive input terminal of the comparator IC1, and Ui is connected to the inverting input terminal of the comparator IC1. The output pulse voltage signal Vi' of the comparator IC1 is low level when Ui is greater than Uref, and high level when Ui is less than Uref. The pulse voltage signal Vi' generates a timing clear signal Clear after passing through the logic gate circuits IC2 and IC3. The Q7 terminal of the trigger IC4 is connected to the DSB terminal of the trigger IC5. Specifically, the pulse voltage signal Vi' is connected to the DSB terminal of the D flip-flop of the trigger IC4 as a serial input. The clock pulse generator IC6 generates a 2KHz clock pulse signal and connects to the CP terminal of the trigger IC4 and the trigger IC5. At the rising edge, the trigger IC4 and the trigger IC5 read the serial input data and shift and output it in parallel. The Q5 of the trigger IC5 is used as the 7ms power-off detection output signal. After being inverted by the NOT gate circuit IC2, it is used as the Vi input signal of the monostable trigger IC7. Vi passes through the monostable trigger IC7 and outputs the Vo' signal. The inverse signals of Vi and Vo' pass through the NOT gate IC8 and the AND gate circuit IC9 and are output as a stable AC power-off detection signal Vo.

[0031] When the mains voltage is normal, Ui is 100Hz half-wave and is compared with the reference voltage Uref in real time. When the Ui voltage value is higher than Uref, Vi' is low level, otherwise it is high level; since the high level time width of Vi' is about 3.3ms, the output of trigger IC4 and trigger IC5 will be cleared once every 3.3ms, CF' is always in low level state, so Vo is always in high level state. The state of each signal level is as follows Figure 2 As shown. When the mains power is cut off, when the mains voltage changes from normal to zero, Ui becomes 0V, the Ui voltage value is lower than Uref, Vi flips from low level to high level and keeps on, at this time, since there is no count reset signal for trigger IC4 and trigger IC5, the CF' end will flip to high level after 7ms and keep on, and Vo will also flip to low level and keep on. The state of each signal level is as shown Figure 3 This circuit adopts separation period, has few components, fast response speed, strong anti-interference ability and low cost. By setting the parameters of circuit components, the mains power failure judgment time can be easily compressed to within 10ms.

[0032] The matters not described in detail in the present invention are all known technologies to those skilled in the art.

[0033] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A mains power failure detection circuit, characterized in that: include: Mains sampling unit, voltage comparison unit, count clearing unit, power failure determination unit and stable output unit; The mains power sampling unit includes a sampling module and a rectifier module. The mains power is stepped down and rectified by the sampling module and the rectifier module in sequence and then transmitted to the voltage comparison unit. The voltage comparison unit includes a pulse voltage generation circuit module, which is used to compare the stepped-down rectified mains power with the reference voltage and generate a pulse voltage to be transmitted to the count reset unit; The count reset unit includes a logic gate circuit module, and the pulse voltage can generate a count reset signal after passing through the logic gate circuit module; The power failure determination unit includes a D trigger, and the pulse voltage and the count reset signal are passed through the D trigger to generate a power failure determination signal; The stable output unit includes a monostable trigger IC7, which is used to stably output the power-off determination signal.

2. A mains power failure detection circuit according to claim 1, characterized in that: The sampling module is a precision transformer PT1, the rectification module is a low conduction voltage drop full-wave rectifier bridge, and the precision transformer PT1 is connected to the low conduction voltage drop full-wave rectifier bridge.

3. A mains power failure detection circuit according to claim 1, characterized in that: The pulse voltage generating circuit module includes a comparator ICl, the same-direction input terminal of the comparator IC1 is connected to the adjustable resistor R2, one end of the adjustable resistor R2 is externally connected to a 5V voltage, and the other end is connected to the negative pole of the rectifier module, and the reverse input terminal of the comparator IC1 is connected to the positive pole of the rectifier module.

4. A mains power failure detection circuit according to claim 1, characterized in that: The logic gate circuit module includes a connected XOR gate circuit IC3 and a plurality of NOT gate circuits IC2.

5. A mains power failure detection circuit according to claim 1, characterized in that: The D flip-flop includes a flip-flop IC4 and a flip-flop IC5 , and a Q7 terminal of the flip-flop IC4 is connected to a DSB terminal of the flip-flop IC5 .

6. A mains power failure detection circuit according to claim 5, characterized in that: It also includes a clock pulse generator IC6, and the clock pulse generator IC6 is connected to the CP end of the trigger IC4 and the CP end of the trigger IC5 respectively.

7. A mains power failure detection circuit according to claim 1, characterized in that: The stable output unit further includes a NOT gate IC8 and an AND gate circuit IC9. The monostable trigger IC7, the NOT gate IC8 and the AND gate circuit IC9 are used to generate a steady-state level.

8. A mains power failure detection circuit according to claim 3, characterized in that: It also includes a first optical coupling module and a second optical coupling module, wherein the first optical coupling module and the second optical coupling module are respectively connected to the output end of the stable output unit and are used to output a control signal and a feedback signal.

9. A mains power failure detection circuit according to claim 3, characterized in that: The comparator IC1 adopts LM393.

10. A mains power failure detection circuit according to claim 6, characterized in that: The clock pulse generator IC6 adopts LM565.

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