Heterogeneous semiconductor device trap density test method based on threshold voltage change

Abstract

The invention discloses a heterogeneous semiconductor device trap density test method based on threshold voltage change, and relates to the field of power semiconductor device trap test and reliability evaluation. Comprising the following steps: connecting a tested device with a transient threshold voltage test circuit; applying negative gate voltage to the device in the trap filling process, and applying test electrorheological to the source-drain section of the device in the trap test process to obtain source-drain voltage change, namely threshold voltage variation; and meanwhile, threshold voltage variation caused by each trap is obtained through processing by using a structure function, and the trap density of each trap is obtained through calculation. The transient threshold voltage test and trap density calculation of the heterogeneous semiconductor device are realized through circuit design, and the method can be applied to the trap density test of the heterogeneous semiconductor devices from different sources, and has good universality.

Description

Technical Field

[0001] The invention relates to threshold voltage testing and trap density characterization of heterogeneous semiconductor devices, and belongs to the field of power semiconductor device testing and reliability. Background Art

[0002] GaN material has a large bandgap (3.4eV), a high breakdown electric field (3.3MV / cm), and a high electron mobility (2000cm 2 / V·s) and other characteristics, so it can be used in high voltage, high temperature, high power and other fields. In order to meet the safety needs of practical applications, an enhanced GaN-based HEMT is usually made using a p-GaN gate on the basis of a depletion-mode device, so that the two-dimensional electron gas under the gate is depleted under zero bias to ensure the effective shutdown of the device. p-GaN-based HEMT has a wide range of application scenarios in the field of power switches, but its threshold voltage instability problem is still one of the key factors hindering the reliability of p-GaN-based devices.

[0003] The gate structure of p-GaN-based HEMT is relatively complex, and the gate bias voltage may cause electron or hole traps to capture carriers, resulting in threshold voltage drift. At present, the threshold voltage change of p-GaN-based devices under positive gate voltage has been widely reported. In fact, the threshold voltage of p-GaN-based HEMT is low, and it may shift under stress; usually a certain negative gate voltage is applied to the device to ensure that it is completely turned off to avoid mis-conduction in switching applications. In addition, the threshold voltage drift of p-GaN HEMT under gate bias has been widely studied. Researchers usually use pulse transfer characteristics to test the static changes of threshold voltage under different gate voltages. However, there is still a lack of effective characterization methods for the transient change process of threshold voltage after the voltage bias is removed. Therefore, it is necessary to further develop test technology to reflect the transient change process of threshold voltage of p-GaN HEMT after gate stress, and it is also necessary to further obtain trap density information that causes threshold voltage changes.

[0004] The technology of the present invention proposes a method for testing the trap density of heterogeneous semiconductor devices based on threshold voltage changes. The method is applied to the transient threshold voltage change evaluation and trap density calculation of heterogeneous semiconductor devices after the gate stress is removed, which can achieve accurate, fast and non-destructive trap parameter characterization and provide a reference for improving the reliability of the device gate. The technology can be applied to the transient threshold voltage change and trap density test of heterogeneous semiconductor devices from different sources, and has good universality. Summary of the invention

[0005] The present invention discloses a method for testing the trap density of a heterojunction semiconductor device based on the change in threshold voltage. By circuit design, the source-drain voltage Vsd of the heterojunction semiconductor device is tested to obtain the transient threshold voltage change ΔVth, and the change in threshold voltage caused by each hole trap is analyzed and the trap density is calculated. The main inventive point of the present invention is: a test circuit for the transient threshold voltage change of the heterojunction semiconductor device is designed, and the change in the threshold voltage of the device caused by traps under negative gate voltage can be quickly obtained through the source-drain voltage Vsd; at the same time, a method for calculating the trap density of the heterojunction semiconductor device based on the change in threshold voltage is proposed, providing an effective characterization technique for the trap effect and reliability evaluation of the heterojunction semiconductor device.

[0006] A method for testing the trap density of a heterojunction semiconductor device based on the change in threshold voltage, characterized in that:

[0007] 1. Connect the device under test to a gate resistor Rg, a gate driver, a gate voltage source, and a drain current source. Among them, the gate driver is connected to the device under test through the gate resistor Rg and provides a gate drive; the gate resistor Rg is used to limit the gate current to protect the circuit, and the range of the gate resistor Rg is 1 < Rg < 50 Ω; the gate voltage source is connected to the gate driver and the device under test and provides a gate-source voltage for the device under test; the drain current source is connected to the device under test, the gate driver, and the gate voltage source and provides a source-drain current for the device under test.

[0008] 2. During the trap filling process, a gate filling voltage Vgf is provided by the gate voltage source, and the filling time is tf; among them, the range of the gate filling voltage Vgf is -1V ≤ Vgf ≤ -10V, and the range of the filling time tf is 10 ms ≤ tf ≤ 200 s. After the filling time tf ends, the drain current source provides a test current Isense, and the test time is tm; among them, the range of the test current Isense is 1 mA ≤ Isense ≤ 10 mA, and the range of the test time tm is 1 s ≤ tm ≤ 1000 s. The test current Isense flows through both ends of the source and drain of the device, and the transient source-drain voltage change Vsd of the device is collected in real time, which is the threshold voltage change ΔVth of the device under test. The acquisition accuracy of the transient source-drain voltage can reach 4 ms. The negative shift of the threshold voltage under the condition of negative filling gate voltage indicates that holes inside the device are captured by traps under negative gate voltage.

[0009] 3. Based on the transient threshold voltage change ΔVth, a time constant spectrum is constructed using the structure function method. The number of trap peaks N is identified from the threshold voltage change, indicating that there are N hole traps inside the device under the condition of Vgf, where the range of N is 1 ≤ N ≤ 10. The N hole trap peaks are sequentially named H1, H2,... HN in ascending order of the time constant ti, where 1 ≤ i ≤ N; the time constants of the corresponding hole traps can be read from the horizontal axis of the time constant spectrum, which are t1, t2,... tN.

[0010] 4. Add the values ​​of the vertical axis of the data in the time constant spectrum and exchange them with the horizontal axis and perform differential calculation to construct the differential amplitude spectrum, where the difference between the horizontal axes corresponding to the N peaks is the threshold voltage change ΔVthi caused by the N traps H1, H2, ...HN. The specific threshold voltage change result caused by the i-th trap Hi under the Vgf condition is expressed in the form of |ΔVthi| absolute value, where 0.001V≤|ΔVthi|≤1V.

[0011] 5. Based on |ΔVthi|, the trap density nti=(2ε|ΔVthi|) / (qd) is calculated. ε is the GaN dielectric constant, q is the charge, and d is the depletion layer thickness, where d is in the range of 10nm≤d≤25nm. The trap density nti of each trap can be calculated based on the threshold voltage change |ΔVthi| caused by N traps under Vgf voltage, where 1E12≤nti≤1E17.

[0012] The present invention proposes for the first time a method for testing the trap density of heterogeneous semiconductor devices based on threshold voltage changes. The method can effectively obtain the threshold voltage transient change curve, extract the threshold voltage change caused by each trap, and thus effectively characterize the trap density inside the device. The beneficial effects of the present invention are: the test circuit and measurement method described in the present invention are simple, fast, and easy to operate, and can realize the effective evaluation of the threshold voltage change of heterogeneous semiconductor devices under different gate voltages, providing a simple and convenient characterization method for analyzing the trap characteristics of heterogeneous semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 : is a connection diagram of the test circuit involved in the present invention, in which: 1-p-GaN HEMT device, 2-gate resistor, 3-gate drive, 4-gate voltage source, 5-drain current source.

[0014] Figure 2 : The threshold voltage change curve of the device under negative gate voltage involved in the present invention.

[0015] Figure 3 : Time constant spectrum constructed based on threshold voltage variation under negative gate voltage.

[0016] Figure 4 : Differential amplitude spectrum constructed based on threshold voltage change under negative gate voltage.

[0017] Figure 5 : Trap amplitude in p-GaN HEMT under negative gate voltage based on differential amplitude spectrum.

[0018] Figure 6 : Trap density of p-GaN HEMT under negative gate voltage based on differential amplitude spectrum. DETAILED DESCRIPTION

[0019] The following is an example of trap density test of heterogeneous semiconductor devices based on threshold voltage change, and the EPC2010C model p-GaN HEMT produced by EPC is selected as the device under test 1, whose maximum operating voltage is 200V and the maximum operating current is 22A. The method involved in the present invention includes the following steps:

[0020] Step 1: Connect the 1-p-GaN HEMT device to the test circuit, as shown in the schematic diagram Figure 1 As shown. The 1-p-GaN HEMT device is connected to 2-gate resistor Rg, 3-gate drive, 4-gate voltage source and 5-drain current source. Among them, 3-gate drive is connected to 1-p-GaN HEMT through 2-gate resistor Rg and provides gate drive for the device under test, and 2-gate resistor Rg is 1Ω for limiting gate current; 4-gate voltage source is connected to 3-gate drive and 1-p-GaN HEMT device and provides gate-source voltage for the device under test; 5-drain current source is connected to 1-p-GaN HEMT device, 3-gate drive and 4-gate voltage source and provides source-drain current for the device under test.

[0021] Step 2: During the trap filling process, the 4-gate voltage source provides a gate filling voltage Vgf of -4V, and the filling time tf is 15s. After the filling time tf is over, the 5-drain current source provides a test current Isense of 10mA during the trap test process, and the test time tm is 500s. At this time, the test current Isense flows through the source and drain of the device, and the real-time acquisition of the device's transient source-drain voltage change Vsd is the threshold voltage change ΔVth of the device under test. The acquisition accuracy of the transient source-drain voltage can reach 4ms, and the results are as follows: Figure 2 When Vgf is -4V, the threshold voltage shifts negatively, indicating that holes inside the device are trapped under negative gate voltage, and the collected transient threshold voltage change ΔVth = -0.07639 is a negative value.

[0022] Step 3: Based on the transient threshold voltage change ΔVth, the time constant spectrum is constructed using the structure function method as follows: Figure 3 As shown. The number of trap peaks N = 3 is identified from the threshold voltage change, indicating that there are 3 hole traps inside the device under the condition of Vgf of -4V; according to the time constant ti, the 3 hole trap peaks are named H1, H2, and H3 in order from small to large, and their time constants ti are t1 = 0.024s, t2 = 2.184s, and t3 = 137.89s respectively.

[0023] Step 4: Figure 3 The vertical axis values ​​of the data in the time constant spectrum shown are added and then exchanged with the horizontal axis and differentiated to construct the differential amplitude spectrum as shown in Figure 4 As shown. The difference between the three peaks corresponding to the horizontal coordinates is the threshold voltage change ΔVthi caused by the three hole traps H1, H2, and H3. The specific test results are expressed in the form of |ΔVthi| absolute value as follows Figure 5 As shown, under the condition of Vgf of -4V, the absolute value of the threshold voltage change caused by H1 trap filling |ΔVth1| is 0.0348V, the threshold voltage change caused by H2 trap filling |ΔVth2| is 0.01552V, and the threshold voltage change caused by H3 trap filling |ΔVth3| is 0.02607V.

[0024] Step 5: Calculate the trap density nti based on |ΔVthi| = (2ε|ΔVthi|) / (qd), where ε is the GaN dielectric constant, q is the charge, and d is the depletion layer thickness. The trap density can be calculated based on the threshold voltage changes caused by the three traps obtained in step 4. The results are as follows: Figure 6 shown.

Claims

1. A method for testing trap density of heterogeneous semiconductor devices based on threshold voltage variation, characterized in that: 1) Connecting the heterogeneous semiconductor device under test with a gate resistor Rg, a gate driver, a gate voltage source and a drain current source; wherein the gate driver is connected to the heterogeneous semiconductor device under test through the gate resistor Rg and provides a gate driver for the device under test; the gate resistor Rg is used to limit the gate current to protect the circuit; the gate voltage source is connected to the gate driver and the heterogeneous semiconductor device under test and provides a gate-source voltage for the heterogeneous semiconductor device under test; the drain current source is connected to the device under test, the gate driver and the gate voltage source and provides a source-drain current for the heterogeneous semiconductor device under test; 2) During the trap filling process, a gate filling voltage Vgf is provided by a gate voltage source, and the filling time is tf; after the filling time tf is over, a drain current source provides a test current Isense, and the test time is tm; the test current Isense flows through the source and drain ends of the device, and the device transient source-drain voltage change Vsd is collected in real time, which is the threshold voltage change ΔVth of the heterogeneous semiconductor device under test; 3) Based on the transient threshold voltage change ΔVth, a time constant spectrum is constructed using the structure function method; the number of trap peaks N is identified from the transient threshold voltage change, indicating that there are N hole traps inside the heterogeneous semiconductor device under Vgf conditions; the N hole trap peaks are named H1, H2, ... HN in sequence from small to large according to the time constant ti, where 1≤i≤N; the time constants of the corresponding hole traps are read from the horizontal axis of the time constant spectrum, which are t1, t2, ... tN respectively; 4) Add the values ​​of the vertical axis of the data in the time constant spectrum and exchange them with the horizontal axis and perform differential calculation to construct a differential amplitude spectrum, where the difference between the horizontal axes corresponding to the N peaks is the threshold voltage change ΔVthi caused by the N traps H1, H2, ...HN; the specific threshold voltage change result caused by the i-th trap Hi under the Vgf condition is expressed in the form of the absolute value of |ΔVthi|; 5) Calculate each trap density nti according to the threshold voltage change |ΔVthi| caused by N traps under Vgf voltage.

2. The method for testing trap density of heterogeneous semiconductor devices based on threshold voltage variation according to claim 1, characterized in that: In the threshold voltage transient test, the test current Isense flows through the source and drain of the device, and the range of the test current Isense is 1mA≤Isense≤10mA; The threshold voltage change ΔVth of the heterogeneous semiconductor device under test is obtained by real-time acquisition of the transient source-drain voltage change Vsd of the p-GaN HEMT device, and the gate resistance Rg in the threshold voltage test circuit is in the range of 1 <Rg<50Ω。 3. The method for testing trap density of heterogeneous semiconductor devices based on threshold voltage variation according to claim 1, characterized in that: The trap filling type can be determined based on the threshold voltage change ΔVth of the device under test; wherein ΔVth<0 indicates that the threshold voltage is negatively shifted, and holes inside the heterogeneous semiconductor device under test are trapped; ΔVth>0 indicates that the threshold voltage is positively shifted, and electrons inside the heterogeneous semiconductor device under test are trapped.

4. The method for testing trap density of heterogeneous semiconductor devices based on threshold voltage variation according to claim 1, characterized in that: The range of gate filling voltage Vgf is -1V≤Vgf≤-10V, the range of filling time tf is 10ms≤tf≤200s, the range of test time tm is 1s≤tm≤1000s, and the acquisition accuracy of transient source-drain voltage is 4ms.

5. The method for testing trap density of heterogeneous semiconductor devices based on threshold voltage variation according to claim 1, characterized in that: The structure function method is used to identify the trap peak in the transient threshold voltage change of the heterogeneous semiconductor device, where the range of the trap peak number N is 1≤N≤10; the trap time constant ti can be read from the peak horizontal coordinate, where the range of i is 1≤i≤N.

6. The method for testing trap density of heterogeneous semiconductor devices based on threshold voltage variation according to claim 1, characterized in that: Based on the difference between the peak values ​​in the differential amplitude spectrum corresponding to the horizontal coordinates, the transient threshold voltage change ΔVthi caused by each trap is directly read, where 0.001V≤|ΔVthi|≤1V.

7. The method for testing trap density of heterogeneous semiconductor devices based on threshold voltage variation according to claim 1, characterized in that: Each trap density nti=(2ε|ΔVthi|) / (qd) is directly calculated based on |ΔVthi|, where d is in the range of 10nm≤d≤25nm and the trap density nti is in the range of 1E12≤nti≤1E17.

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