CNTFET trap characterization method based on transient drain-source current response

Abstract

The invention discloses a CNTFET trap characterization method based on transient drain-source current response, and belongs to the field of semiconductor device reliability. Comprising the steps of giving a grid filling voltage interval of a trap filling stage; giving a test voltage condition of a trap test stage; giving a test time range and precision of transient current response in a trap test stage; and giving a test range of a trap energy level and a time constant. A certain grid filling voltage is applied to the CNTFET to fill the hole trap, transient current response curves of the drain end and the source end of the CNTFET under the grid and drain test voltage are collected, a time constant spectrum of the hole trap is established through Bayesian deconvolution, and time constant parameters of the trap in the CNTFET are extracted. And repeatedly testing under multiple groups of temperature conditions and acquiring changes of trap time constants, and calculating trap level parameters of the CNTFET by using an Arrhenius formula. The method provided by the invention is simple and convenient to operate, can be suitable for CNTFET devices from various sources, and can realize accurate, lossless and in-situ characterization of trap parameters of the CNTFET.

Description

Technical Field

[0001] The invention relates to electrical characteristic testing and trap parameter characterization of a carbon nanotube field effect transistor (CNTFET), and belongs to the field of reliability testing of novel semiconductor devices. Background Art

[0002] Carbon nanotube electronic devices have become a technical route with great potential to break Moore's Law due to their advantages such as low power consumption, small size and high mobility. With the continuous development and maturity of carbon-based electronic technology, its practical application and industrialization have begun to see the dawn; especially in the technical applications of submicron waves and high-performance thin films, it is possible to achieve significant development, further making up for the application limitations of traditional semiconductor devices. The reliability of carbon-based electronic devices is an important issue to promote their application development. Among them, the trap effect is a key factor affecting the reliability of carbon nanotube field effect transistors (CNTFETs) under stress conditions such as irradiation and voltage. Compared with common interface states such as Si / SiO2 and SiC / SiO2, the interface state density of CNTFET can be about one to two orders of magnitude higher. At present, the gate structure of carbon-based devices is not mature. The mismatch between the quasi-one-dimensional carbon tube channel and the three-dimensional gate dielectric lattice structure may lead to complex interface state problems, thereby causing hysteresis effects, device mobility reduction and threshold voltage instability, which brings serious hidden dangers to the application of carbon-based devices and integrated circuits.

[0003] At present, the characterization methods of CNTFET trap effects mainly include hysteresis curve test, pulse transfer characteristic test, noise characteristic test and time domain curve test. Among them, hysteresis curve and pulse transfer characteristic can intuitively reflect the influence of traps on the electrical characteristics of the device under test, but the detailed analysis of trap characteristics and their location distribution has not yet been realized. The energy level of CNTFET internal traps can be obtained by using test methods such as low-frequency noise test (LFN), random telegraph noise and 1 / f noise. However, the corresponding noise characteristic test is difficult to eliminate the errors caused by intrinsic noise, and it is impossible to fully analyze the trap location and physical source. At present, there is still a lack of accurate and non-destructive characterization methods for CNTFET trap parameters.

[0004] The technology of the present invention proposes a trap parameter testing method based on transient drain-source current response for CNTFET trap characterization. By evaluating the release of CNTFET traps after the gate fill voltage is removed, the trap time constant and energy level information are obtained, thereby achieving accurate, non-destructive, and in-situ characterization of the internal trap parameters of CNTFET, providing a basis for analyzing the CNTFET trap effect under different stress conditions. Summary of the invention

[0005] CNTFET interface traps, gate dielectric traps, etc. may lead to reliability issues such as threshold voltage drift and increased hysteresis window. Under various stresses such as electrical, thermal, and irradiation, the reliability issues caused by the CNTFET trap effect are becoming increasingly prominent. The generation and increase of defects and traps may lead to device performance degradation and failure. The currently proposed methods such as pulse transfer characteristic test and noise characteristic test are difficult to achieve accurate, non-destructive, and in-situ CNTFET trap parameter characterization. In order to solve this problem, we use the transient drain-source current response curve of CNTFET under electrical bias to analyze the time constant, energy level and other parameters of CNTFET internal traps, correctly analyze the CNTFET trap filling mechanism under gate bias, and obtain accurate trap information.

[0006] The technical solution adopted by the present invention is a CNTFET trap characterization method based on transient drain-source current response, and the specific implementation process is as follows:

[0007] S1. Set the temperature of the constant temperature platform in the high and low temperature probe station to T. The setting range of T in this step is 20℃≤T≤30℃ to evaluate the change of the drain-source current of the device under test at room temperature over time. Then, place the CNTFET device under test on the constant temperature platform in the high and low temperature probe station, and connect the CNTFET device to the corresponding interface of the semiconductor parameter meter B1500 through three probes. The trap test of the device under test can be completed using existing test equipment. The operation is simple and convenient, and there is no need to build an additional complex test platform.

[0008] S2. Place the device on a constant temperature platform at a temperature of T without power and keep it still for t d Minutes, where the range of static time is 10min≤t d ≤20min, the device is in the initial state without being affected by electrical stress, and the device temperature is kept consistent with the set constant temperature platform temperature T.

[0009] S3. Set the test conditions of the semiconductor parameter analyzer B1500. In the trap filling stage, apply the gate filling voltage V to the CNTFET device under test. GF To achieve carrier filling, the drain voltage is 0V and the gate filling voltage V is applied GF The time is t f Among them, V GF The range is -25V≤t d ≤15V, filling time t f The range is 10s≤t d ≤100s. During the trap release phase, a gate test voltage V is applied to the CNTFET device under test. GM and drain test voltage V DM ; Where gate test voltage V GMThe range is -7V≤t d ≤0V, drain test voltage V DM The range is -1V≤t d ≤-0.1V. Obtain the device drain-source current I in logarithmic form DS The change over time until the drain-source current remains stable, the test time is t m , which is the response curve corresponding to the trap release process. The logarithmic form can be set to log 10, log20, log50 or log100, and the test time t m The range is 10s≤t m ≤1000s, the sampling accuracy of transient curve changing with time can reach 10ms.

[0010] S4. Based on the acquired transient current response curve, use Bayesian deconvolution technology to establish the time constant spectrum and identify the trap peak. Set the Bayesian deconvolution fitting order A and the number of iterations B to complete the Bayesian deconvolution and construct the time constant spectrum, where the fitting order represents the number of traps inside the device, and its range is 2≤A≤8; the number of iterations represents the data density of the time constant spectrum after the Bayesian deconvolution operation, and its range is 100≤B≤1000. In the set V GF and V DF Trap peaks are identified under test conditions, where the horizontal axis corresponding to each peak is the time constant parameter of the CNTFET trap, and the vertical axis corresponding to the peak is the relative amplitude parameter of the CNTFET trap.

[0011] S5. Determine whether the constant temperature platform temperature T is greater than or equal to 70°C at this time. If the constant temperature platform temperature T is less than 70°C, increase the platform temperature by 10°C and repeat steps 2 to 4 until the platform temperature is greater than or equal to 70°C. If the constant temperature platform temperature T is already greater than or equal to 70°C, stop the transient curve test and summarize the time constants of the traps at different temperatures. After the transient curve test stops, the corresponding transient current curves under N temperature conditions can be obtained. If the constant temperature platform temperature T is greater than 70°C, the drain-source current response curves under N=6 temperature conditions are obtained; if the constant temperature platform temperature T is equal to 70°C, the drain-source current response curves under N=5 temperature conditions are obtained.

[0012] S6. Based on steps 1 to 5, the trap parameters of CNTFET at 10°C intervals are obtained. Based on the time constants of CNTFET traps at N temperature conditions, the Arrhenius formula can be further used to draw the Arrhenius diagram. The horizontal axis of the Arrhenius diagram is ln(T 2t), where T is the temperature condition; t is the trap time constant, and the range of the trap time constant is 10ms≤t≤1000s. The ordinate of the Arrhenius plot is 1 / kT, where k is the Boltzmann constant and T is the temperature condition. The slope of the linear fit of the data in the Arrhenius plot is the trap energy level Ea, where the range of the trap energy level is 0.01eV≤Ea≤1eV.

[0013] The present invention proposes for the first time a CNTFET trap characterization method based on transient drain-source current response. For the trap parameter test of carbon-based devices, this method can obtain the transient drain-source current response of the device under test at a certain filling voltage, thereby realizing accurate, non-destructive, and in-situ CNTFET trap parameter extraction. The beneficial effects of the present invention are: the characterization method described in the present invention is simple and fast, the test steps are easy to operate, and the test voltage conditions involved in the present invention can be adjusted, which is applicable to trap tests of CNTFET devices from different sources, providing an accurate and convenient characterization method for trap testing and reliability evaluation of carbon-based devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 : is a schematic diagram of the device electrical testing device involved in the present invention, in which: 1-CNTFET device, 2-constant temperature platform, 3-high and low temperature probe station, 4-Keysight B1500 semiconductor parameter tester.

[0015] Figure 2 :Flowchart of device testing involved in the present invention.

[0016] Figure 3 : The device trap test timing diagram involved in the present invention.

[0017] Figure 4 : Drain-source current response curves at different temperatures.

[0018] Figure 5 : Trap time constant parameter test results.

[0019] Figure 6 : Trap energy level parameter test results. DETAILED DESCRIPTION

[0020] The present invention will be described in more detail below with reference to the accompanying drawings and specific embodiments.

[0021] Taking CNTFET device as an example, the device electrical testing device involved in the present invention is as follows: Figure 1 As shown, it includes a CNTFET device, a constant temperature platform, a high and low temperature probe station and a semiconductor parameter tester, wherein the CNTFET to be tested is a p-type bottom gate CNTFET. The test process of the method involved in the present invention is as follows Figure 2 As shown, the following steps are included:

[0022] Step 1: Set the temperature T of the constant temperature platform in the high and low temperature probe station to 30°C, place the CNTFET device on the constant temperature platform in the high and low temperature probe station, and connect the CNTFET device under test to the corresponding interface of the semiconductor parameter analyzer B1500 through the three probes of the high and low temperature probe station to complete the preparation work before electrical testing.

[0023] Step 2: Leave the device alone without power for a period of time t d The device is in an initial state without being affected by electrical stress and its temperature is consistent with the set temperature of the constant temperature platform.

[0024] Step 3: Set the test conditions of the semiconductor parameter analyzer B1500 and set the gate fill voltage V GF Set to -16V, drain voltage is 0V, fill time t f After the 15-second filling phase is completed, the gate test voltage V GM and drain test voltage V DM Set to -5V and -1V respectively, and obtain the drain-source current I in log50 form DS The curve changes with time until the drain-source current remains stable. This curve is the response curve corresponding to the trap release process. The test time t m The test sequence is as follows: Figure 3 As shown in the figure, the measured transient drain-source current curve is as follows Figure 4 shown.

[0025] Step 4: Based on the acquired transient current response curve, use Bayesian deconvolution technology to establish the time constant spectrum and identify the trap peak. Set the fitting order A to 3 times and the number of iterations B to 300 times. The time constant spectrum processing results are as follows: Figure 5 As shown. At V GF for -5V and V DF Three trap peaks H1, H2 and H3 are identified under -1V test conditions, where the horizontal axis corresponding to each peak is the time constant parameter of the CNTFET trap. Under 30℃ temperature conditions, the three trap time constants are 0.7s, 8s and 75s in ascending order.

[0026] Step 5: Determine whether the constant temperature platform temperature T is greater than or equal to 70°C. If the constant temperature platform temperature is less than 70°C, increase the platform temperature by 10°C and repeat the operations from step 2 to step 4; if the constant temperature platform temperature is greater than or equal to 70°C, stop the transient curve test and summarize the time constants of the traps at different temperatures. After the transient curve test is stopped, the constant temperature platform temperature T is equal to 70°C, and the transient drain-source current curves under N = 5 temperature conditions are obtained, such as Figure 5 shown.

[0027] Step 6: Based on steps 1 to 5, the trap parameters of CNTFET were obtained under the temperature conditions of 30°C to 70°C with an interval of 10°C. Figure 5 The trap time constants of CNTFET under the five temperature conditions shown can be plotted using the Arrhenius formula. Figure 6 As shown, at V GF For -16V filling condition, V GF for -5V and V DF Under -1V test conditions, three CNTFET trap energy levels Ea can be identified from the Arrhenius plot by linear fitting, where the trap energy levels of H1, H2 and H3 are 0.190, 0.155 and 0.080 eV, respectively.

Claims

1. A CNTFET trap characterization method based on transient drain-source current response, characterized in that: Step 1: Set the temperature of the constant temperature platform in the high and low temperature probe station to T; then, place the CNTFET device to be tested on the constant temperature platform in the high and low temperature probe station, connect the CNTFET device to the corresponding interface of the semiconductor parameter analyzer B1500 through three probes, and complete the trap test of the device to be tested; Step 2: Place the CNTFET device under test on a constant temperature platform at a temperature of T without power and keep it still for t d Minutes, the CNTFET device under test is in an initial state not affected by electrical stress, and the temperature of the CNTFET device under test is consistent with the set constant temperature platform temperature T; Step 3: Set the test conditions of the semiconductor parameter analyzer B1500; in the trap filling stage, apply the gate filling voltage V to the CNTFET device under test GF To achieve carrier filling, the drain voltage is 0V and the gate filling voltage V is applied GF The time is t f ; In the trap release phase, a gate test voltage V is applied to the CNTFET device under test GM and drain test voltage V DM ; Obtain the device drain-source current I in logarithmic form DS The change over time until the drain-source current remains stable, the test time is t m , this curve is the response curve corresponding to the trap release process; Step 4: Based on the acquired transient current response curve, use Bayesian deconvolution technology to establish the time constant spectrum and identify the trap peak; set the Bayesian deconvolution fitting order A and the number of iterations B to complete the Bayesian deconvolution and construct the time constant spectrum; GF and V DF The trap peaks are identified under the test conditions, where the abscissa corresponding to each peak is the time constant parameter of the CNTFET trap, and the ordinate corresponding to the peak is the relative amplitude parameter of the CNTFET trap; Step 5: Determine whether the constant temperature platform temperature T is greater than or equal to 70°C at this time; if the constant temperature platform temperature T is less than 70°C, increase the platform temperature by 10°C and repeat the operations of steps 2 to 4 until the platform temperature is greater than or equal to 70°C; if the constant temperature platform temperature T is already greater than or equal to 70°C, stop the transient curve test and summarize the time constants of the traps at different temperatures; after the transient curve test is stopped, obtain the transient curves corresponding to N temperature conditions; Step 6: Based on steps 1 to 5, the trap parameters of CNTFET at 10°C interval temperature conditions are obtained; based on the CNTFET trap time constants at N temperature conditions, the Arrhenius diagram is drawn using the Arrhenius formula; the horizontal axis of the Arrhenius diagram is ln(T 2 t), where T is the temperature condition and t is the trap time constant; the ordinate of the Arrhenius diagram is 1 / kT, where k is the Boltzmann constant; a linear fit is performed on the data in the Arrhenius diagram, and its slope is the trap energy level Ea.

2. The CNTFET trap characterization method based on transient drain-source current response according to claim 1, characterized in that: In step 1, the setting range of T is 20°C ≤ T ≤ 30°C to evaluate the change of the drain-source current of the CNTFET device under test at room temperature over time.

3. The CNTFET trap characterization method based on transient drain-source current response according to claim 1, characterized in that: In step 2, the standing time t d The range is 10min≤t d ≤20min, and the standing time t d The device is in an unpowered state during the corresponding time.

4. The CNTFET trap characterization method based on transient drain-source current response according to claim 1, characterized in that: In step 3, the gate filling voltage V GF The range is -25V≤t d ≤15V, filling time t f The range is 10s≤t d ≤100s; Gate test voltage V GM The range is -7V≤t d ≤0V, drain test voltage V DM The range is -1V≤t d ≤-0.1V.

5. The CNTFET trap characterization method based on transient drain-source current response according to claim 1, characterized in that: In step 3, the transient drain-source current is obtained in logarithmic form, where the logarithmic form is set to log 10, log20, log50 or log100, and the test time t m The range is 10s≤t m ≤1000s, the sampling accuracy of transient curve changing with time is 10ms.

6. The CNTFET trap characterization method based on transient drain-source current response according to claim 1, characterized in that: In step 4, the time constant spectrum is constructed using Bayesian iteration, where the fitting order represents the number of traps inside the device, and its range is 2≤A≤8; the number of iterations represents the data density of the time constant spectrum after the Bayesian deconvolution operation, and its range is 100≤B≤1000.

7. The CNTFET trap characterization method based on transient drain-source current response according to claim 1, characterized in that: In step 4, the time constant spectrum is constructed using Bayesian iteration, where the fitting order represents the number of traps inside the device, and its range is 2≤A≤8; the number of iterations represents the data density of the time constant spectrum after the Bayesian deconvolution operation, and its range is 100≤B≤1000.

8. The CNTFET trap characterization method based on transient drain-source current response according to claim 1, characterized in that: In step 5, N is the number of temperature conditions; after the transient curve test stops, if the constant temperature platform temperature T is greater than 70° C., then N=6; if the constant temperature platform temperature T is equal to 70° C., then N=5.

9. The CNTFET trap characterization method based on transient drain-source current response according to claim 1, characterized in that: In step six, the range of the trap time constant is 10 ms ≤ t ≤ 1000 s, and the range of the trap energy level obtained using the Arrhenius diagram is 0.01 eV ≤ Ea ≤ 1 eV.

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