Chip junction temperature testing method and device

Abstract

The invention provides a chip junction temperature testing method and device, and the method comprises the steps: obtaining a relation curve between the temperature of an environment where a tested chip is located and the electrical parameters of a protection element in an ESD protection circuit in advance when the tested chip is in a non-power-on state, and carrying out the testing of the junction temperature of the chip in a power-on working state of the tested chip, and detecting electrical parameters of a protection element in the ESD protection circuit, and then according to the electrical parameters, through a relation curve of the environment temperature and the electrical parameters of the protection element in the ESD protection circuit, calculating to obtain the current environment temperature when the detected chip works. Therefore, the junction temperature detection of the chip can be realized by multiplexing the ESD protection circuit on the basis of not additionally increasing a chip circuit structure, and the temperature detection precision is ensured while the cost and the chip area are reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor device packaging and testing, and in particular to a chip junction temperature testing method and device. Background Art

[0002] With the continuous development of the chip industry, people have higher and higher expectations for chip reliability and performance. In order to improve the performance of the chip, it is necessary to test the chip accurately. In order to ensure the accuracy of chip testing, it is necessary to provide an accurate test environment for the chip when testing the chip, especially the test temperature of the chip. The test temperature of the chip is the actual temperature of the chip when the chip is tested for performance.

[0003] In the prior art, the ambient temperature of the chip under test or the actual on-chip temperature of the chip under test is often tested, and the ambient temperature of the chip under test or the actual on-chip temperature of the chip under test is used as the test temperature of the chip under test. However, when the actual on-chip temperature of the chip under test is different from the ambient temperature, the actual on-chip temperature of the chip under test is in an unstable state, and the test temperature of the chip under test cannot be accurately determined by the ambient temperature of the chip under test or the actual on-chip temperature of the chip under test, resulting in an inability to provide an accurate test environment for the chip under test, affecting the test accuracy of the chip under test.

[0004] Traditional packaged chip junction temperature testing methods usually include two methods: an inference method based on the package thermal resistance coefficient (refer to formula (1)) and a design of a dedicated junction temperature detection circuit. Figure 1 The junction temperature calculation formula for the device shown based on the package thermal resistance coefficient using the extrapolation method is:

[0005] (1)

[0006] is the chip junction temperature, is the thermal resistance coefficient from chip junction to package shell, P is the power consumption, The surface temperature of the chip package shell. This method is highly dependent on the accuracy of the thermal resistance coefficient, but the thermal resistance coefficient mainly comes from simulation, which is greatly affected by the packaging material (lead frame, molding material, die bonding material) and the specific packaging design (die thickness, exposed pad, internal heat dissipation vias, thermal conductivity of the metal material used). Therefore, the accuracy of the thermal resistance coefficient is highly dependent on the specific environment, and the actual use error is large.

[0007] Dedicated junction temperature detection circuits are more suitable for scenarios where the chip area is small. However, when the chip area is large, the dedicated temperature detection circuit can only accurately detect the temperature near the circuit. Since the distribution of the chip heat field is random, the temperature far away from the chip cannot be accurately measured, which is very limited. In addition, adding a designed temperature detection circuit will also occupy the chip area, limiting the overall size of the chip, which is not conducive to high integration and miniaturization. Summary of the invention

[0008] In order to solve the above technical problems, the present disclosure provides a chip junction temperature testing method and device, which can realize chip temperature detection by reusing ESD protection circuit without adding additional chip circuit structure, thereby reducing cost and chip area while ensuring temperature detection accuracy.

[0009] In one aspect, the present disclosure provides a chip junction temperature testing method, which includes:

[0010] When the chip under test is in an unpowered state, a relationship curve between the ambient temperature of the chip under test and the electrical parameters of the protection element in the ESD protection circuit is obtained in advance;

[0011] In the electrical working state of the chip under test, detecting electrical parameters of the protection element in the ESD protection circuit;

[0012] The ambient temperature when the chip under test is currently working is calculated based on the electrical parameters through the relationship curve between the ambient temperature and the electrical parameters of the protection element in the ESD protection circuit.

[0013] In some embodiments, the electrical parameters obtained are analog quantities, including detection voltage and / or detection current.

[0014] In some embodiments, the step of obtaining in advance a relationship curve between the ambient temperature of the chip under test and the electrical parameters of the protection element in the ESD protection circuit when the chip under test is in an unpowered state comprises:

[0015] When the chip under test is at a certain temperature in an unpowered state, obtaining electrical parameters of protection elements in an ESD protection circuit of the chip under test;

[0016] Traversing each temperature value within the preset temperature range in sequence at fixed intervals, and correspondingly obtaining a plurality of the electrical parameters;

[0017] A relationship curve between the ambient temperature and the electrical parameters is obtained by fitting and calculating the plurality of electrical parameters and their corresponding temperature values.

[0018] In some embodiments, the protection element includes a first diode and a second diode connected in series between an excitation power supply and ground, a connection node between the first diode and the second diode is connected to a detection pin of the chip under test, and a conduction current path of the first diode and the second diode is from ground to the excitation power supply.

[0019] In some embodiments, the step of obtaining electrical parameters of protection elements in the ESD protection circuit of the chip under test includes:

[0020] Applying an excitation voltage to a diode of an ESD protection circuit of the chip under test, and obtaining a detection current flowing through the diode through a connection node;

[0021] Alternatively, an excitation current is applied to a diode of the ESD protection circuit of the chip under test to obtain a detection voltage across the diode.

[0022] In some embodiments, the step of applying an excitation voltage to a diode of the ESD protection circuit of the chip under test and obtaining a detection current flowing through the diode by connecting a node comprises:

[0023] Applying an excitation voltage to a diode of an ESD protection circuit of the chip under test at a current temperature, obtaining a first detection current flowing through the diode by connecting nodes, and calculating a first detection voltage according to the first detection current;

[0024] Obtaining a second detection current flowing through a diode in an ESD protection circuit of the chip under test at a current temperature, and calculating a second detection voltage according to the second detection current;

[0025] A test voltage corresponding to the current temperature is obtained according to a voltage difference between the second detection voltage and the first detection voltage, and the electrical parameters include the test voltage.

[0026] In some embodiments, the step of obtaining the relationship curve between the ambient temperature and the electrical parameters by fitting and calculating the plurality of electrical parameters and their corresponding temperature values ​​comprises:

[0027] A relationship curve between the ambient temperature and the electrical parameters is obtained by fitting and calculating the multiple test voltages and their corresponding temperature values.

[0028] In some embodiments, the chip under test is a single chip or at least two chips connected in parallel or multiple chips distributed in an array.

[0029] Alternatively, the chip under test includes a plurality of the detection pins, and the plurality of detection pins are distributed at different positions of the chip under test.

[0030] In some embodiments, the chip junction temperature testing method further includes:

[0031] Based on the detection voltage across the diode and / or the detection current flowing through the diode, and the ambient temperature of the chip under test, it is determined whether the detection voltage across the diode is within a specific voltage range and / or whether the detection current flowing through the diode is within a specific current range and / or whether the ambient temperature of the chip under test is within a specific temperature range.

[0032] On the other hand, the present disclosure provides a chip junction temperature testing device, which includes:

[0033] A detection unit, used to detect electrical parameters of protection elements in the ESD protection circuit of the chip under test;

[0034] The processing unit is used to calculate the ambient temperature of the current working environment of the chip under test according to the electrical parameters through the relationship curve between the ambient temperature and the electrical parameters obtained in advance.

[0035] In some embodiments, the protection element includes a first diode and a second diode connected in series between an excitation power supply and ground, a connection node between the first diode and the second diode is connected to a detection pin of the chip under test, and a conduction current path of the first diode and the second diode is from ground to the excitation power supply.

[0036] In some embodiments, the electrical parameters obtained are analog quantities, including a detection voltage and / or a detection current of a diode in the ESD protection circuit.

[0037] In some embodiments, the processing unit is further configured to:

[0038] When the chip under test is at a certain temperature in an unpowered state, electrical parameters of protection elements in an ESD protection circuit of the chip under test obtained by the detection unit;

[0039] and sequentially traverse each temperature value within the preset temperature range at fixed intervals, and obtain a plurality of corresponding electrical parameters through the detection unit;

[0040] And a relationship curve between the ambient temperature and the electrical parameters is obtained by fitting and calculating the plurality of electrical parameters and their corresponding temperature values.

[0041] In some embodiments, the chip junction temperature testing device further includes:

[0042] The output unit is used to display the ambient temperature and / or the electrical parameters of the chip under test.

[0043] In some embodiments, the detection unit comprises:

[0044] An excitation voltage providing unit, used to input a voltage signal to the ESD protection circuit of the chip under test through a signal pin connected between the chip under test and the ESD protection circuit, so as to provide an excitation voltage for the ESD protection circuit of the chip under test;

[0045] A voltage detection unit, one end of which is connected to a signal pin connected between the chip under test and the ESD protection circuit, and the other end is grounded, and is used to detect the voltage across the diode in the ESD protection circuit of the chip under test;

[0046] and / or a current detection unit, connected to a signal pin derived from the chip under test being connected to the ESD protection circuit, for detecting a current flowing through a diode in the ESD protection circuit of the chip under test.

[0047] In some embodiments, the chip under test is a single chip or at least two chips connected in parallel or multiple chips distributed in an array.

[0048] Alternatively, the chip under test includes a plurality of the detection pins, and the plurality of detection pins are distributed at different positions of the chip under test.

[0049] The beneficial effect of the present disclosure is that the present disclosure provides a chip junction temperature test method and device, by obtaining the relationship curve between the ambient temperature of the tested chip and the electrical parameters of the protection element in the ESD protection circuit in advance when the tested chip is in an unpowered state, and then detecting the electrical parameters of the protection element in the ESD protection circuit when the tested chip is powered on, and then calculating the ambient temperature of the current working chip according to the electrical parameters through the relationship curve between the ambient temperature and the electrical parameters of the protection element in the ESD protection circuit. In this way, the temperature detection of the chip can be realized by reusing the ESD protection circuit without adding an additional chip circuit structure, thereby reducing the cost and chip area while ensuring the temperature detection accuracy.

[0050] In addition, considering that when the volume of the chip under test reaches a certain level, the heat generation conditions at different positions are inconsistent, the embodiments of the present application may consider designing multiple high-resistance pins at different chip pins, so as to support multi-channel testing at multiple positions, thereby improving the temperature detection accuracy, and at the same time achieving the temperature difference at different positions of the detection chip and the consistency of the chip junction temperature calibration between the pins. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings.

[0052] Figure 1A schematic diagram showing a structure for calculating junction temperature based on package thermal resistance coefficient in the prior art;

[0053] Figure 2 A schematic diagram of the structure of a temperature detection device provided by an embodiment of the present disclosure is shown;

[0054] Figure 3 Show Figure 2 A schematic diagram of an application of the temperature detection device shown in a specific implementation scenario;

[0055] Figure 4 A schematic diagram showing a flow chart of a temperature detection method provided by an embodiment of the present disclosure;

[0056] Figure 5 Show Figure 4 Schematic diagram of the flow of sub-steps of step S110;

[0057] Figure 6 A schematic diagram showing the distribution of high-resistance detection pins arranged at different positions of a chip under test in another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0058] In order to facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present disclosure are given in the drawings. However, the present disclosure can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the content of the present disclosure more thorough and comprehensive.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0060] First, the technical terms involved in the embodiments of the present application are introduced:

[0061] 1. Thermal equilibrium

[0062] Thermal equilibrium refers to the condition in which the internal temperature of an object (such as a chip under test) in contact with the outside world is uniform everywhere (mainly when the chip under test is small) and equal to the outside temperature (in the ideal state, heat loss is ignored). In thermal equilibrium, there is no heat exchange between the various parts of the object and between the object and the outside world.

[0063] 2. Analog quantity

[0064] Analog quantity refers to the variable (such as voltage, current) that changes continuously within a certain range; that is, it can take any value (within the value range) within a certain range (domain). For example, analog current value, analog voltage value.

[0065] Digital quantities are discrete quantities, not continuously changing quantities, and can only take on a few discrete values, such as a binary digital variable that can only take on two values, such as digital current values ​​and digital voltage values.

[0066] In order to obtain the performance of the chip, it is often necessary to perform performance tests on the chip, such as high and low temperature tests on the chip to obtain the performance of the chip in high and low temperature environments. During the high and low temperature test, it is necessary to ensure that the chip is at a specific test temperature. However, the existing method of obtaining the temperature of the target chip cannot ensure that the chip under test reaches thermal equilibrium with its environment, resulting in the inability to accurately determine the true temperature of the chip under test, and the error is large or the chip area is sacrificed. The limitations are strong.

[0067] Based on the above problems, the present application provides a chip junction temperature testing method. Wherein, the chip under test has an electrostatic discharge (ESD) protection circuit, and the ESD protection circuit has multiple protection elements (mainly diodes and other passive elements). When the chip under test meets the soaking time in the test environment, the voltage across the diode in the ESD protection circuit of the chip under test and / or the current flowing through the diode are obtained by a temperature detection device, and then the ambient temperature of the chip under test when working is determined based on the voltage and / or current and the corresponding relationship between the voltage and / or current of the diode of the chip under test and the temperature.

[0068] It can be understood that the soaking time, also known as the soaking time, is the time required for the actual temperature of the test sample (Device under test, DUT) to reach thermal equilibrium with its test environment. The soaking time can be a time period, such as 45 seconds to 60 seconds, or a time point, such as 50 seconds.

[0069] It can be understood that the stabilization time of the test sample (such as the chip under test) is different due to the different test environment temperatures. For example, if the ambient temperature is 60°, the stabilization time of the test sample is 1 minute, that is, the test sample is placed in a test environment at 60°, and the time for the test sample and the test environment to reach thermal equilibrium is 1 minute; if the ambient temperature is 80°, the stabilization time of the test sample is 1 minute and 20 seconds.

[0070] It can be understood that since the chip under test meets the stabilization time in the test environment, the chip under test and the test environment reach thermal equilibrium, and the temperature of the test chip is in a stable state at this time. The measured temperature of the chip under test is the real temperature when the chip under test is stable, and it can be determined whether the chip under test reaches the test temperature based on the temperature. By accurately measuring the test temperature of the chip under test, the test performance of the chip under test can be improved. Among them, the test temperature can be the ambient temperature of the test environment.

[0071] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings.

[0072] Figure 2 A schematic diagram of the structure of a temperature detection device provided by an embodiment of the present disclosure is shown. Figure 3 Show Figure 2 The schematic diagram of the application of the temperature detection device in a specific implementation scenario is shown. Figure 4 A schematic diagram of a temperature detection method provided by an embodiment of the present disclosure is shown. Figure 5 Show Figure 4 Schematic diagram of the flow chart of the sub-steps of step S110.

[0073] refer to Figure 2 On the one hand, an embodiment of the present disclosure provides a chip junction temperature testing device 10 , which at least includes: a detection unit 110 , a processing unit 120 and an output unit 130 .

[0074] Among them, the detection unit 110 is used to detect the electrical parameters of the protection elements in the ESD protection circuit of the chip under test, the processing unit 120 is communicated with the detection unit 110, and is used to calculate the ambient temperature of the current working environment of the chip under test 200 based on the electrical parameters through a pre-acquired relationship curve between the ambient temperature and the electrical parameters, and the output unit 130 is used to display the ambient temperature and / or the electrical parameters of the chip under test 200.

[0075] In some embodiments, the ambient temperature of the chip under test 200 when it is working is used to characterize the junction temperature of the chip. In practical applications, some high-precision and high-sensitivity chips need to control their performance safety in real time. For example, the chip inside the IGBT module has a maximum operating temperature limit. Therefore, the temperature of the chip must be monitored. When the set protection temperature value is exceeded, the chip must be over-temperature protected and the chip must be stopped to prevent chip failure. This requires effective monitoring of the junction temperature of the chip and quick feedback. The chip junction temperature test device 10 in this embodiment is intended to improve the real-time detection accuracy of the chip junction temperature to achieve chip protection.

[0076] In some embodiments, the protection element includes a first diode and a second diode connected in series between an excitation power supply and ground, the connection node of the first diode and the second diode is connected to the detection pin of the chip under test 200, and the conduction current path of the first diode and the second diode is from the ground to the excitation power supply. In this embodiment, the detection pin of the chip under test 200 is designed to be a high-impedance type pin (HZ) by default. In other alternative embodiments, other passive elements such as resistors, capacitors, or a combination of resistors and capacitors can be added to improve the detection accuracy, and the circuit can be further optimized by voltage stabilization and filtering. There is no limitation here, and it is only exhibited as a simple example structure to facilitate the description of the specific implementation of the following temperature detection method.

[0077] In some embodiments, the electrical parameters obtained are analog quantities, including a detection voltage and / or a detection current of a diode in the ESD protection circuit.

[0078] In some embodiments, the processing unit 120 is further configured to:

[0079] When the chip under test 200 is at a certain temperature in an unpowered state, electrical parameters of protection elements in the ESD protection circuit of the chip under test 200 obtained by the detection unit 110;

[0080] and sequentially traverse each temperature value within the preset temperature range at fixed intervals, and obtain a plurality of electrical parameters correspondingly through the detection unit 110;

[0081] And a relationship curve between the ambient temperature and the electrical parameters is obtained by fitting and calculating the plurality of electrical parameters and their corresponding temperature values.

[0082] In this embodiment, the processing unit 120 may specifically be a digital signal processor. In a specific implementation, if the detection voltage across the diode and / or the detection current flowing through the diode received from the detection unit 110 is an analog quantity, the processing unit 120 performs analog-to-digital conversion on the analog quantity of the detection voltage across the diode and / or the detection current flowing through the diode to obtain the digital quantity of the detection voltage across the diode and / or the detection current flowing through the diode; the ambient temperature of the chip under test 200 is obtained according to the digital quantity of the detection voltage across the diode and / or the digital quantity of the detection current flowing through the diode. For example, if the voltage detection unit is an AD sampling circuit or an AD sampling chip, the detection voltage across the diode detected is a digital quantity, and no analog-to-digital conversion is required.

[0083] In some embodiments, the detection unit 110 includes:

[0084] An excitation voltage providing unit, used to input a voltage signal to the ESD protection circuit of the chip under test 200 through a signal pin connected between the chip under test 200 and the ESD protection circuit, so as to provide an excitation voltage for the ESD protection circuit of the chip under test 200;

[0085] A voltage detection unit 110, one end of which is connected to a signal pin connected between the chip under test 200 and the ESD protection circuit, and the other end is grounded, and is used to detect the voltage across the diode in the ESD protection circuit of the chip under test 200;

[0086] and / or a current detection unit 110 , connected to a signal pin derived from the chip under test 200 connected to the ESD protection circuit, for detecting a current flowing through a diode in the ESD protection circuit of the chip under test 200 .

[0087] Further, the processing unit 120 may determine whether the voltage drop across the diode is within a specific voltage range and / or whether the current flowing through the diode is within a specific current range and / or whether the temperature of the chip under test 200 is within a specific temperature range according to the voltage drop across the diode, and / or the test voltage, and / or the current flowing through the diode, and the temperature of the chip under test 200, which may specifically include the following implementations:

[0088] In one embodiment, the processor 120 may determine whether the voltage drop across the diode is within a specific voltage range or whether the temperature of the chip under test 200 is within a specific temperature range based on the voltage drop across the diode and the temperature of the chip under test 200 .

[0089] In a specific embodiment, the processing unit 120 can determine whether the voltage drop across the diode is within a specific voltage range or whether the temperature of the chip under test 200 is within a specific temperature range based on the voltage drop across the diode and the temperature of the chip under test 200, as well as the correspondence (including a correspondence table or a correspondence curve) between the voltage drop across the diode in the chip ESD protection circuit under ideal conditions (the same as the chip under test 200) and the chip junction temperature obtained in advance.

[0090] More specifically, based on the correspondence between the voltage drop across the diode in the chip ESD protection circuit under ideal conditions (the same as the chip 200 under test) and the chip junction temperature obtained in advance, a first voltage drop corresponding to the temperature of the chip 200 under test is determined, and based on the first voltage drop, a specific voltage range (the voltage drop across the diode in the ESD protection circuit of the chip 200 under test) corresponding to the temperature of the chip 200 under test is determined, and it is judged whether the voltage drop across the diode (in the ESD protection circuit of the chip 200 under test) is within the specific voltage range; or, based on the correspondence between the voltage drop across the diode in the chip ESD protection circuit under ideal conditions (the same as the chip 200 under test) and the chip junction temperature obtained in advance, a first temperature corresponding to the voltage drop across the diode (in the ESD protection circuit of the chip 200 under test) is determined, and based on the first temperature, a first specific temperature range (the temperature of the chip 200 under test) corresponding to the voltage drop across the diode (in the ESD protection circuit of the chip 200 under test) is determined, and it is judged whether the temperature of the chip 200 under test is within the first specific temperature range.

[0091] In another embodiment, the processing unit 120 may determine whether the current flowing through the diode is within a specific current range or whether the temperature of the chip under test is within a specific temperature range according to the current flowing through the diode and the temperature of the chip under test.

[0092] In a specific embodiment, the processing unit 120 determines whether the current flowing through the diode is within a specific current range or whether the temperature of the chip under test 200 is within a specific temperature range based on the current flowing through the diode and the temperature of the chip under test 200, as well as a pre-obtained correspondence (including a correspondence table or a correspondence curve) between the current flowing through the diode in the chip ESD protection circuit and the chip junction temperature under ideal conditions (the same as the chip under test 200).

[0093] More specifically, a first current corresponding to the temperature of the chip under test 200 is determined based on the correspondence between the current flowing through the diode in the chip ESD protection circuit (the same as the chip under test 200) under ideal conditions and the chip junction temperature obtained in advance, and a specific current range (of the current flowing through the diode in the ESD protection circuit of the chip under test 200) corresponding to the temperature of the chip under test is determined based on the first current, and it is judged whether the current flowing through both ends of the diode (in the ESD protection circuit of the chip under test 200) is within the specific current range; or, a second temperature corresponding to the current flowing through the diode (in the ESD protection circuit of the chip under test 200) is determined based on the correspondence between the current flowing through the diode in the chip ESD protection circuit (the same as the chip under test 200) under ideal conditions and the chip junction temperature obtained in advance, and a second specific temperature range (of the temperature of the chip under test 200) corresponding to the current flowing through both ends of the diode (in the ESD protection circuit of the chip under test 200) is determined based on the second temperature, and it is judged whether the temperature of the chip under test 200 is within the second specific temperature range.

[0094] Further, the output unit 130 may be specifically a computer, connected to the interface of the processing unit 120 via a USB interface and a serial interface, so as to receive the detection voltage at both ends of the diode and / or the detection current flowing through the diode sent by the processing unit 120. Specifically, the processing unit 120 uses software with a data linear fitting function (e.g., MATLAB software) to perform linear fitting on the detection voltage at both ends of the diode and the temperature of the chip under test 200, and / or the detection current flowing through the diode and the temperature of the chip under test 200, and / or as described above, the test voltage obtained by detecting the diode and the temperature of the chip under test 200 are linearly fitted, and a relationship curve between the detection voltage at both ends of the diode and the temperature of the chip under test 200, and / or the relationship curve between the detection current flowing through the diode and the temperature of the chip under test 200, and / or as described above, the relationship curve between the test voltage obtained by detecting the diode and the temperature of the chip under test 200 is generated, and displayed.

[0095] Further, the output unit 130 determines whether the chip under test 200 has abnormal performance according to the relationship curve between the detection voltage across the diode and the temperature of the chip under test 200, and / or the relationship curve between the detection current flowing through the diode and the temperature of the chip under test 200, and / or the relationship curve between the test voltage obtained by detecting the diode and the temperature of the chip under test 200 as described above. The situation where the chip under test 200 has abnormal performance includes, for example, the chip fails due to excessive operating temperature, so that the voltage drop across the diode and / or the current flowing through the diode and / or the temperature of the chip under test 200 obtained by actual measurement do not match the normal working state of the chip under test 200.

[0096] Specifically, refer to Figure 3 , the detection unit 110 includes, for example, a constant current source and a voltage source connected in parallel. When the chip 200 under test is not powered on, a constant current source and a voltage source are connected in parallel to the detection pin, and the ambient temperature is set to T0. At this time, the external constant current source first extracts the uA level (uA and A are both current units, that is, the conversion relationship is: 1A equals 1000mA, 1mA equals 1000uA, so the conversion relationship between uA and A is 1000000:1) detection current i1, and the detection voltage v1 at this time is:

[0097] (2)

[0098] In the formula, i0 is the reverse saturation current of the diode, q is the electron charge, k is the Boltzmann constant, T0 is the thermodynamic temperature, which represents the temperature of the environment in which the diode is located, and can be approximately regarded as the ambient temperature of the chip under test, v1 is the ESD reverse bias diode voltage, and i2 is the current when the diode is reverse biased to ground, and is consistent with i1.

[0099] The external constant current source draws the uA level detection current i1´ for the second time, and the detection voltage v1´ is:

[0100] (3)

[0101] Therefore, when the ambient temperature is T0, the test voltage ∆v can be obtained by combining the above equations (2) and (3):

[0102] (4)

[0103] Where β is a constant.

[0104] Then, T0 is sequentially traversed between Tmin and Tmax in the preset temperature range at fixed intervals, and steps 2 to 5 are repeated after the temperature stabilizes, and a plurality of electrical parameters are obtained correspondingly by the detection unit 110, and a relationship curve between the ambient temperature and the test voltage is obtained by fitting and calculating according to the plurality of electrical parameters and their corresponding temperature values. In this embodiment, for example, the relationship expression between the ambient temperature and the test voltage ∆v is obtained by using the least squares fitting method:

[0105] (5)

[0106] Wherein m is the fitting slope, and b is the offset. Of course, in other alternative embodiments, an expression of the relationship between voltage and temperature can also be found based on other fitting methods, which is not limited here.

[0107] After the relationship curve between the ambient temperature and the test voltage ∆v is obtained through the above steps, the chip under test 200 is powered on and starts to work normally. The detection pin of the chip under test 200 continues to be configured as a high-impedance state. Referring to the above steps, the detection currents i1 and i1´ are respectively extracted. At this time, the corresponding detection voltage can be tested and obtained. , and then put it into formula (4) to get the test voltage: , and then the processor 120 compiles the formula, and then obtains the ambient temperature of the current chip under test 200 when it is working according to the relationship between the ambient temperature and the test voltage ∆v (5): .

[0108] In some embodiments, the chip under test 200 is a single chip or at least two chips connected in parallel or multiple chips distributed in an array.

[0109] Alternatively, the chip under test 200 includes a plurality of the detection pins, and the plurality of detection pins are distributed at different positions of the chip under test 200, such as Figure 6 shown.

[0110] Considering that when the volume of the chip under test 200 reaches a certain level, the heating conditions at different positions thereof are inconsistent, the embodiment of the present disclosure may consider designing multiple high-impedance (HZ) pins at different chip pins, so as to support multi-channel testing, thereby achieving:

[0111] 1) Detect temperature differences in different parts of the chip;

[0112] 2) Chip junction temperature calibration consistency between each pin.

[0113] More specifically, through experimental verification, for a 9mm*9mm, 196-pin BGA chip, the test result accuracy can reach ±2°C. Therefore, the temperature testing device 10 in this embodiment can realize chip temperature detection by reusing the ESD protection circuit without adding an additional chip circuit structure, thereby reducing the cost and chip area while ensuring the temperature detection accuracy.

[0114] refer to Figure 4 and Figure 5 Based on the same inventive concept, on the other hand, the embodiment of the present disclosure also provides a chip junction temperature testing method for the above-mentioned chip testing device 10, which includes:

[0115] S110: When the chip under test is in an unpowered state, a relationship curve between the ambient temperature of the chip under test and the electrical parameters of the protection element in the ESD protection circuit is obtained in advance.

[0116] In some embodiments, the electrical parameters obtained are analog quantities, including detection voltage and / or detection current.

[0117] In some embodiments, the protection element includes a first diode and a second diode connected in series between an excitation power supply and ground, a connection node between the first diode and the second diode is connected to a detection pin of the chip under test, and a conduction current path of the first diode and the second diode is from ground to the excitation power supply.

[0118] In some embodiments, in step S110, when the chip under test is in an unpowered state, pre-obtaining a relationship curve between the ambient temperature of the chip under test and the electrical parameters of the protection element in the ESD protection circuit may specifically include:

[0119] S111: When the chip under test is at a certain temperature in an unpowered state, obtaining electrical parameters of protection elements in an ESD protection circuit of the chip under test.

[0120] S112: traverse each temperature value within the preset temperature range in sequence at fixed intervals, and obtain a plurality of corresponding electrical parameters.

[0121] S113: Obtaining a relationship curve between the ambient temperature and the electrical parameters by fitting and calculating according to the plurality of electrical parameters and their corresponding temperature values.

[0122] In some embodiments, the step of obtaining electrical parameters of protection elements in the ESD protection circuit of the chip under test includes:

[0123] Applying an excitation voltage to a diode of an ESD protection circuit of the chip under test, and obtaining a detection current flowing through the diode through a connection node;

[0124] Alternatively, an excitation current is applied to a diode of the ESD protection circuit of the chip under test to obtain a detection voltage across the diode.

[0125] In some embodiments, the step of applying an excitation voltage to a diode of the ESD protection circuit of the chip under test and obtaining a detection current flowing through the diode by connecting a node comprises:

[0126] Applying an excitation voltage to a diode of an ESD protection circuit of the chip under test at a current temperature, obtaining a first detection current flowing through the diode by connecting nodes, and calculating a first detection voltage according to the first detection current;

[0127] Obtaining a second detection current flowing through a diode in an ESD protection circuit of the chip under test at a current temperature, and calculating a second detection voltage according to the second detection current;

[0128] A test voltage corresponding to the current temperature is obtained according to a voltage difference between the second detection voltage and the first detection voltage, and the electrical parameters include the test voltage.

[0129] In some embodiments, the step of obtaining the relationship curve between the ambient temperature and the electrical parameters by fitting and calculating the plurality of electrical parameters and their corresponding temperature values ​​comprises:

[0130] A relationship curve between the ambient temperature and the electrical parameters is obtained by fitting and calculating the multiple test voltages and their corresponding temperature values.

[0131] S120: In the electrical working state of the chip under test, detect electrical parameters of protection elements in the ESD protection circuit.

[0132] S130: Calculate the ambient temperature when the chip under test is currently working according to the electrical parameters through the relationship curve between the ambient temperature and the electrical parameters of the protection element in the ESD protection circuit.

[0133] In some embodiments, the chip under test is a single chip or at least two chips connected in parallel or multiple chips distributed in an array.

[0134] Alternatively, the chip under test includes a plurality of the detection pins, and the plurality of detection pins are distributed at different positions of the chip under test.

[0135] In some embodiments, the chip junction temperature testing method further includes:

[0136] Based on the detection voltage across the diode and / or the detection current flowing through the diode, and the ambient temperature of the chip under test, it is determined whether the detection voltage across the diode is within a specific voltage range and / or whether the detection current flowing through the diode is within a specific current range and / or whether the ambient temperature of the chip under test is within a specific temperature range.

[0137] In summary, the chip junction temperature test method and device provided by the embodiment of the present disclosure obtains the relationship curve between the ambient temperature of the chip under test 200 and the electrical parameters of the protection element in the ESD protection circuit in advance when the chip under test 200 is in an unpowered state, and then detects the electrical parameters of the protection element in the ESD protection circuit when the chip under test 200 is powered on and working, and then calculates the ambient temperature of the chip under test 200 when it is currently working based on the electrical parameters through the relationship curve between the ambient temperature and the electrical parameters of the protection element in the ESD protection circuit. In this way, the temperature detection of the chip can be realized by reusing the ESD protection circuit without adding an additional chip circuit structure, thereby reducing the cost and chip area while ensuring the temperature detection accuracy.

[0138] In addition, considering that when the volume of the chip under test reaches a certain level, the heat generation conditions at different positions are inconsistent, the embodiments of the present application may consider designing multiple high-resistance pins at different chip pins, so as to support multi-channel testing at multiple positions, thereby improving the temperature detection accuracy, and at the same time achieving the temperature difference at different positions of the detection chip and the consistency of the chip junction temperature calibration between the pins.

[0139] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope and spirit of the present invention and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. In addition, each functional unit may be integrated into a processing unit, each unit may exist physically separately, or two or more units may be integrated into one unit.

[0140] In the several embodiments provided in the present disclosure, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the units can be a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0141] The units described as separate components may or may not be physically separated, and the components of the control device may or may not be physical units, that is, they may be located in one place or distributed in multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0142] It should be noted that in the description of the present disclosure, it needs to be understood that the terms "upper", "lower", "inner" and the like indicating orientation or positional relationship are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the components or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0143] In addition, in this article, the terms "comprises", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device that includes the element.

[0144] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly illustrating the present disclosure, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present disclosure.

Claims

1. A chip junction temperature testing method, wherein: include: When the chip under test is in an unpowered state, a relationship curve between the ambient temperature of the chip under test and the electrical parameters of the protection element in the ESD protection circuit is obtained in advance; In the electrical working state of the chip under test, detecting electrical parameters of the protection element in the ESD protection circuit; The ambient temperature when the chip under test is currently working is calculated based on the electrical parameters through the relationship curve between the ambient temperature and the electrical parameters of the protection element in the ESD protection circuit.

2. The chip junction temperature testing method according to claim 1, wherein: The electrical parameters obtained are analog quantities, including detection voltage and / or detection current.

3. The chip junction temperature testing method according to claim 2, wherein: The step of obtaining in advance a relationship curve between the ambient temperature of the chip under test and the electrical parameters of the protection element in the ESD protection circuit when the chip under test is in an unpowered state comprises: When the chip under test is at a certain temperature in an unpowered state, obtaining electrical parameters of protection elements in an ESD protection circuit of the chip under test; Traversing each temperature value within the preset temperature range in sequence at fixed intervals, and correspondingly obtaining a plurality of the electrical parameters; A relationship curve between the ambient temperature and the electrical parameters is obtained by fitting and calculating the plurality of electrical parameters and their corresponding temperature values.

4. The chip junction temperature testing method according to claim 3, wherein: The protection element includes a first diode and a second diode connected in series between an excitation power supply and ground, a connection node between the first diode and the second diode is connected to a detection pin of the chip under test, and a conduction current path of the first diode and the second diode is from ground to the excitation power supply.

5. The chip junction temperature testing method according to claim 4, wherein: The step of obtaining electrical parameters of protection elements in the ESD protection circuit of the chip under test includes: Applying an excitation voltage to a diode of an ESD protection circuit of the chip under test, and obtaining a detection current flowing through the diode through a connection node; Alternatively, an excitation current is applied to a diode of the ESD protection circuit of the chip under test to obtain a detection voltage across the diode.

6. The chip junction temperature testing method according to claim 5, wherein: The step of applying an excitation voltage to a diode of the ESD protection circuit of the chip under test and obtaining a detection current flowing through the diode by connecting a node comprises: Applying an excitation voltage to a diode of an ESD protection circuit of the chip under test at a current temperature, obtaining a first detection current flowing through the diode by connecting nodes, and calculating a first detection voltage according to the first detection current; Obtaining a second detection current flowing through a diode in an ESD protection circuit of the chip under test at a current temperature, and calculating a second detection voltage according to the second detection current; A test voltage corresponding to the current temperature is obtained according to a voltage difference between the second detection voltage and the first detection voltage, and the electrical parameters include the test voltage.

7. The chip junction temperature testing method according to claim 6, wherein: The step of obtaining the relationship curve between the ambient temperature and the electrical parameters by fitting and calculating according to the plurality of electrical parameters and their corresponding temperature values ​​comprises: A relationship curve between the ambient temperature and the electrical parameters is obtained by fitting and calculating the multiple test voltages and their corresponding temperature values.

8. The chip junction temperature testing method according to claim 7, wherein: The chip under test is one chip or at least two chips connected in parallel or multiple chips distributed in an array. Alternatively, the chip under test includes a plurality of the detection pins, and the plurality of detection pins are distributed at different positions of the chip under test.

9. The chip junction temperature testing method according to claim 7, wherein: Also includes: Based on the detection voltage across the diode and / or the detection current flowing through the diode, and the ambient temperature of the chip under test, it is determined whether the detection voltage across the diode is within a specific voltage range and / or whether the detection current flowing through the diode is within a specific current range and / or whether the ambient temperature of the chip under test is within a specific temperature range.

10. A chip junction temperature testing device, wherein: include: A detection unit, used to detect electrical parameters of protection elements in the ESD protection circuit of the chip under test; The processing unit is used to calculate the ambient temperature of the current working environment of the chip under test according to the electrical parameters through the relationship curve between the ambient temperature and the electrical parameters obtained in advance.

11. The chip junction temperature testing device according to claim 10, wherein: The protection element includes a first diode and a second diode connected in series between an excitation power supply and ground, a connection node between the first diode and the second diode is connected to a detection pin of the chip under test, and a conduction current path of the first diode and the second diode is from ground to the excitation power supply.

12. The chip junction temperature testing device according to claim 11, wherein: The electrical parameters obtained are analog quantities, including the detection voltage and / or detection current of the diode in the ESD protection circuit.

13. The chip junction temperature testing device according to claim 12, wherein: The processing unit is also used for: When the chip under test is at a certain temperature in an unpowered state, electrical parameters of protection elements in an ESD protection circuit of the chip under test obtained by the detection unit; and sequentially traverse each temperature value within the preset temperature range at fixed intervals, and obtain a plurality of corresponding electrical parameters through the detection unit; And a relationship curve between the ambient temperature and the electrical parameters is obtained by fitting and calculating the plurality of electrical parameters and their corresponding temperature values.

14. The chip junction temperature testing device according to claim 13, wherein: Also includes: The output unit is used to display the ambient temperature and / or the electrical parameters of the chip under test.

15. The chip junction temperature testing device according to claim 14, wherein: The detection unit comprises: An excitation voltage providing unit, used to input a voltage signal to the ESD protection circuit of the chip under test through a signal pin connected between the chip under test and the ESD protection circuit, so as to provide an excitation voltage for the ESD protection circuit of the chip under test; A voltage detection unit, one end of which is connected to a signal pin connected between the chip under test and the ESD protection circuit, and the other end is grounded, and is used to detect the voltage across the diode in the ESD protection circuit of the chip under test; and / or a current detection unit, connected to a signal pin derived from the chip under test being connected to the ESD protection circuit, for detecting a current flowing through a diode in the ESD protection circuit of the chip under test.

16. The chip junction temperature testing device according to claim 15, wherein: The chip under test is one chip or at least two chips connected in parallel or multiple chips distributed in an array. Alternatively, the chip under test includes a plurality of the detection pins, and the plurality of detection pins are distributed at different positions of the chip under test.

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