Chip short circuit point positioning method and system

Abstract

The embodiment of the invention provides a chip short circuit point positioning method and system. A to-be-tested chip comprises a chip layer, a packaging layer and a substrate layer which are stacked in sequence. The method comprises the following steps: applying a test voltage to the chip to be tested; obtaining a thermal imaging image of the surface of the chip to be detected and obtaining time of obtaining the thermal imaging image; and according to the test voltage, the thermal imaging image and the acquisition time, positioning the short circuit point position of the to-be-tested chip. According to the chip short-circuit point positioning method and system provided by the embodiment of the invention, the thermal imaging image of the short-circuit point is obtained, and the positions of the short-circuit point in the horizontal direction and the vertical direction are obtained at the same time in combination with the conditions such as the image display time and the voltage applied during image display; direct and accurate positioning of the short-circuit failure point of the electronic component such as the chip is achieved, screening is not needed layer by layer, and the chip short-circuit point positioning efficiency is greatly improved.

Description

Technical Field

[0001] The embodiments of the present disclosure belong to the technical field of electronic component failure analysis, and specifically relate to a chip short-circuit point locating method and system. Background Art

[0002] In the existing methods for locating short-circuit failure points of electronic components, especially chips, the principle of infrared thermal imaging is usually used to apply voltage to the chip while using an infrared thermal imager to vertically shoot the chip, thereby detecting the short-circuit failure position in the integrated circuit. Although it is currently possible to accurately locate the short-circuit failure point on the electronic component in the horizontal direction, it is impossible to accurately locate its vertical position. After locating the horizontal coordinates of the short-circuit failure point, it is still necessary to screen layer by layer in the vertical direction, which is time-consuming and labor-intensive, resulting in low efficiency in electronic component failure analysis. Summary of the invention

[0003] The embodiments of the present disclosure aim to solve at least one of the technical problems existing in the prior art and provide a chip short-circuit point locating method and system.

[0004] One aspect of the present disclosure provides a method for locating a chip short-circuit point, wherein the chip to be tested includes a chip layer, a packaging layer, and a substrate layer stacked in sequence, and the method includes:

[0005] Applying a test voltage to the chip to be tested;

[0006] Acquire a thermal imaging image of the surface of the chip to be tested and the acquisition time of the thermal imaging image;

[0007] The short-circuit point of the chip to be tested is located according to the test voltage, the thermal imaging image and the acquisition time.

[0008] Further, the applied test voltage is a first test voltage;

[0009] The step of locating the position of the short-circuit point of the chip under test according to the test voltage, the thermal imaging image and the acquisition time includes:

[0010] If the thermal imaging image is not acquired within the first set time, it is determined that there is no short circuit point in the chip to be tested;

[0011] If the thermal imaging image is acquired within the first set time, it is determined that a short circuit point exists in the chip to be tested.

[0012] Further, when there is a short-circuit point in the chip under test, locating the position of the short-circuit point in the chip under test according to the test voltage, the thermal imaging image and the acquisition time includes:

[0013] If the acquisition time of the thermal imaging image is less than the second set time, it is determined that a short-circuit point exists in the chip layer of the chip to be tested, and the short-circuit point position of the chip layer is located according to the size of the thermal imaging image and the acquisition time;

[0014] If the acquisition time is equal to the second set time, it is determined that a short circuit point exists at the junction of the chip layer and the packaging layer of the chip to be tested;

[0015] If the acquisition time is greater than the second set time, it is determined that a short circuit point exists at any position of the packaging layer, the substrate layer, or the junction between the packaging layer and the substrate layer of the chip to be tested;

[0016] The second set time is smaller than the first set time.

[0017] Further, when a short circuit point exists at any position of the packaging layer, substrate layer, or the junction of the packaging layer and substrate layer of the chip to be tested, the test voltage is adjusted to a second test voltage; wherein the second test voltage is greater than the first test voltage;

[0018] The step of locating the position of the short-circuit point of the chip under test according to the test voltage, the thermal imaging image and the acquisition time includes:

[0019] If the acquisition time of the thermal imaging image is less than or equal to a third set time, it is determined that a short-circuit point exists in the packaging layer of the chip to be tested, and the short-circuit point of the packaging layer is located according to the size of the thermal imaging image and the acquisition time;

[0020] If the acquisition time is greater than the third set time, it is determined that a short circuit point exists at any position of the junction between the substrate layer, the packaging layer and the substrate layer of the chip to be tested.

[0021] Further, when a short circuit point exists at any position of the junction between the substrate layer, the packaging layer and the substrate layer of the chip to be tested, the test voltage is adjusted to a third test voltage; wherein the third test voltage is greater than the second test voltage;

[0022] The step of locating the position of the short-circuit point of the chip under test according to the test voltage, the thermal imaging image and the acquisition time includes:

[0023] If the acquisition time of the thermal imaging image is less than a fourth set time, it is determined that a short-circuit point exists in the substrate layer of the chip to be tested, and the position of the short-circuit point of the substrate layer is located according to the size of the thermal imaging image and the acquisition time;

[0024] If the acquisition time is greater than or equal to the fourth set time, it is determined that a short circuit point exists at the junction of the packaging layer and the substrate layer of the chip to be tested.

[0025] Optionally, before applying the test voltage to the chip to be tested, the method further includes:

[0026] Detect whether the chip to be tested is in a target detection position. If the chip to be tested is in the target detection position, apply a test voltage to the chip to be tested, and obtain a thermal imaging image of the surface of the chip to be tested.

[0027] Another aspect of the present disclosure provides a chip short-circuit point positioning system, the system comprising:

[0028] The test module is used to place the chip to be tested and provide the required test environment;

[0029] A power-on module, used for applying a test voltage to the chip to be tested;

[0030] An acquisition module, used for acquiring a thermal imaging image of the surface of the chip to be tested;

[0031] A timing module, used to obtain the acquisition time when the acquisition module acquires the thermal imaging image;

[0032] A control module is used to locate the short-circuit point of the chip to be tested according to the test voltage, the thermal imaging image and the acquisition time.

[0033] Further, the applied test voltage is a first test voltage;

[0034] The control module is specifically used for:

[0035] If the thermal imaging image is not acquired within the first set time, it is determined that there is no short circuit point in the chip to be tested;

[0036] If the thermal imaging image is acquired within the first set time, it is determined that a short circuit point exists in the chip to be tested.

[0037] Furthermore, when there is a short circuit point in the chip to be tested, the control module is specifically used to:

[0038] If the acquisition time of the thermal imaging image is less than the second set time, it is determined that a short-circuit point exists in the chip layer of the chip to be tested, and the short-circuit point position of the chip layer is located according to the size of the thermal imaging image and the acquisition time;

[0039] If the acquisition time is equal to the second set time, it is determined that a short circuit point exists at the junction of the chip layer and the packaging layer of the chip to be tested;

[0040] If the acquisition time is greater than the second set time, it is determined that a short circuit point exists at any position of the packaging layer, the substrate layer, or the junction between the packaging layer and the substrate layer of the chip to be tested;

[0041] The second set time is smaller than the first set time.

[0042] Furthermore, when a short circuit point exists at any position of the packaging layer, substrate layer, or the junction of the packaging layer and substrate layer of the chip to be tested, the power-on module is further used to adjust the test voltage to a second test voltage to form a second test current inside the chip to be tested; wherein the second test voltage is greater than the first test voltage;

[0043] The control module is specifically used for:

[0044] If the acquisition time of the thermal imaging image is less than or equal to a third set time, it is determined that a short-circuit point exists in the packaging layer of the chip to be tested, and the short-circuit point of the packaging layer is located according to the size of the thermal imaging image and the acquisition time;

[0045] If the acquisition time is greater than the third set time, it is determined that a short circuit point exists at any position of the junction between the substrate layer, the packaging layer and the substrate layer of the chip to be tested.

[0046] Further, when a short circuit point exists at any position of the junction of the substrate layer, the packaging layer and the substrate layer of the chip to be tested, the power-on module is further used to adjust the test voltage to a third test voltage to form a third test current inside the chip to be tested; wherein the third test voltage is greater than the second test voltage;

[0047] The positioning module is specifically used for:

[0048] If the acquisition time of the thermal imaging image is less than a fourth set time, it is determined that a short-circuit point exists in the substrate layer of the chip to be tested, and the position of the short-circuit point of the substrate layer is located according to the size of the thermal imaging image and the acquisition time;

[0049] If the acquisition time is greater than or equal to the fourth set time, it is determined that a short circuit point exists at the junction of the packaging layer and the substrate layer of the chip to be tested.

[0050] Optionally, the system further comprises a sensing module;

[0051] The sensing module is used to detect whether the chip to be tested is placed in the testing module;

[0052] The control module is also used to control the test module, the power-on module, the acquisition module and the timing module to start when the chip to be tested is placed in the test module; and to control the acquisition module to standby or shut down when the chip to be tested is not placed in the test module.

[0053] A chip short-circuit point locating method and system according to an embodiment of the present disclosure obtains a thermal imaging image of the short-circuit point and combines conditions such as the image display time and the voltage applied when the image is displayed, thereby obtaining the position of the short-circuit point in the horizontal and vertical directions. This achieves direct and precise positioning of the short-circuit failure point of electronic components such as chips, without the need for layer-by-layer screening, and greatly improves the efficiency of chip short-circuit point positioning. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 A schematic diagram of a process of locating a chip short-circuit point according to an embodiment of the present disclosure;

[0055] Figure 2 A schematic diagram of a chip short-circuit point location process according to another embodiment of the present disclosure;

[0056] Figure 3 The figure is a schematic diagram of the structure of a chip short-circuit point positioning system according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0057] A short circuit refers to a circuit or part of a circuit being short-circuited. If the load and the power supply are connected together by a wire, it is called a short circuit. During a short circuit, the current provided by the power supply will be much larger than the current provided when the circuit is open. Generally, short circuits are not allowed. If a short circuit occurs, the power supply or equipment will be burned out in serious cases. At present, with the advancement of technology, threads are constantly shrinking, and the size of short circuit defects is often only tens to hundreds of nanometers. Therefore, how to locate the failure position of the short circuit in a large range has become a key step in failure analysis. Short circuit defects are one of the main failure modes of poor electrical properties of semiconductor components. Therefore, monitoring and failure analysis of short circuit defects can promote process improvement and increase yield.

[0058] Infrared thermal imaging camera is the mainstream failure analysis equipment for capturing chip short circuit anomalies. Its principle is to use a highly sensitive InSb probe to detect the distribution of heat radiation generated by the defective position of the IC when it is powered on, so as to locate the failure position. The principle of this equipment is similar to the early liquid crystal detection technology. In addition to IC and Package, it can also be applied to large-area products such as PCB, panel, passive components, etc.

[0059] At present, the most common method for locating short circuit failures is to use the principle of infrared thermal imaging to detect the failure position in the integrated circuit. Although it is currently possible to accurately locate the short circuit failure point on the electronic component in the horizontal direction, there are problems with its accurate vertical positioning.

[0060] The structure of the chip product can be viewed from top to bottom as the chip layer, packaging layer and substrate layer. The chip layer is provided with a chip, the main material of which is metal. The materials of the packaging layer and the substrate layer are both non-metallic, and the short-circuit failure position is generally the pin welding point. According to the materials of the three-layer structure, there are obvious differences in the thermal conductivity between the three. When voltage is applied to the chip, if there is a short-circuit failure point inside it, there are significant differences in the acquisition time of the thermal imaging image and the specific size of the failure position. Therefore, by utilizing this phenomenon, a method and system for locating the vertical position of the short-circuit failure point can be designed.

[0061] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0062] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the present disclosure.

[0063] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0064] It should be understood that although the terms first, second, third, etc. may be used in this disclosure to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another component. Therefore, the first component discussed below can be referred to as the second component without departing from the teachings of the concepts of the present disclosure. As used in this disclosure, the term "and / or" includes any one of the associated listed items and all combinations of one or more.

[0065] Those skilled in the art will appreciate that the drawings are merely schematic diagrams of example embodiments, and the modules or processes in the drawings are not necessarily necessary for implementing the present disclosure, and therefore cannot be used to limit the protection scope of the present disclosure.

[0066] An embodiment of the present disclosure provides a method for locating a chip short-circuit point. The chip to be tested includes a chip layer, a packaging layer, and a substrate layer stacked in sequence. Figure 1 As shown, the method includes:

[0067] Step S1, applying a test voltage to the chip to be tested;

[0068] Step S2, obtaining a thermal imaging image of the surface of the chip to be tested and the acquisition time of the thermal imaging image;

[0069] Step S3, locating the short-circuit point of the chip to be tested according to the test voltage, the thermal imaging image and the acquisition time.

[0070] Specifically, before step S1, a chip to be tested should be provided, the chip should be placed in a target detection position, and a suitable test environment should be provided, such as normal temperature and pressure. Figure 2 The schematic diagram of the chip short-circuit point positioning process shown in the figure uses devices such as photosensors or pressure sensors to detect whether the chip to be tested is in the target detection position, and cooperates with the controller to control the thermal imaging device to standby or shut down with low power consumption when the chip to be tested is not detected.

[0071] When the detection chip is placed in place, step S1 is executed, a certain value of test voltage is applied to the chip, so as to generate a test current in the chip, and a thermal imaging device is used to shoot in the vertical direction of the chip to perform real-time thermal imaging. The thermal imaging image described in step S2 is the final thermal imaging image taken by the thermal imaging device after the high temperature point appears on the chip. Since a large amount of heat is generated when the short circuit point of the circuit is energized, the high temperature point that appears in the chip can be identified as a short circuit point. When the thermal imaging image is obtained, the acquisition time of the image is recorded. The acquisition time is obtained by subtracting the time when the chip starts to be energized from the final time. Finally, step S3 is executed. According to the position of the high temperature point in the thermal imaging image, the position of the short circuit point in the horizontal direction can be located. Based on the principle that the materials between different layers of the chip are different, resulting in different sizes of hot spots in the thermal imaging image, different voltages for heating the short circuit points of different layers, and different energization times, the position of the short circuit point in the vertical direction is located.

[0072] The method for locating the chip short-circuit point in the vertical direction will be described in detail below.

[0073] During the entire process of locating the chip short-circuit point, a maximum time threshold called the first set time T1 can be set overall. If the thermal imaging image is not obtained within the first set time T1, it is determined that there is no short-circuit point in the chip to be tested; if the thermal imaging image is obtained within the first set time T1, it is determined that there is a short-circuit point in the chip to be tested, and the acquisition time t1 of the thermal imaging image is recorded.

[0074] When the test voltage starts to be applied to the chip, a smaller first test voltage V1 is first applied, thereby forming a smaller first test current A1 in the chip, and the current magnitude is in the milliampere level. The second setting time T2 is set according to the actual situation as a basis for judging whether there is a short-circuit point in the chip layer, and the second setting time T2 is less than the first setting time T1 (T2<T1). If the acquisition time t1 of the thermal imaging image is less than the second setting time T2 (t1<T2), it is determined that there is a short-circuit point in the chip layer of the chip to be tested, and the specific position of the short-circuit point in the chip layer is located according to the size s1 of the thermal imaging image and the acquisition time t1. Under the premise of the same test voltage and the same acquisition time t1, the larger the size s1 of the thermal imaging image, the closer the short-circuit point will be to the packaging layer. If the acquisition time t1 is equal to the second setting time T2 (t1=T2), it is determined that the short-circuit point is located at the junction of the chip layer and the packaging layer of the chip to be tested. If the thermal imaging image is not obtained after the second set time T2, that is, the acquisition time t1 is greater than the second set time T2 (t1>T2), it is determined that the short-circuit point does not exist in the chip layer or at the junction of the chip layer and the packaging layer, but a short-circuit point exists in the packaging layer, substrate layer, or the junction of the packaging layer and the substrate layer of the chip to be tested. The short-circuit point is located at the junction of the packaging layer / substrate layer / packaging layer and substrate layer

[0075] When it is determined that there is a short circuit point in the package layer, substrate layer, or the junction of the package layer and substrate layer of the chip to be tested, the test voltage is adjusted to a second test voltage V2; wherein the second test voltage V2 is greater than the first test voltage V1, so that a second test current A2 is formed inside the chip, the current magnitude is milliampere level, and the second test current A2 is 2 to 4 times the first test current A1. Record the acquisition time t2 of the thermal imaging image.

[0076] If the acquisition time t2 of the thermal imaging image is less than or equal to the third set time T3 (t2≤T3), that is, the thermal imaging image is acquired within the third set time T3, it is determined that there is a short-circuit point in the packaging layer of the chip to be tested, and the specific position of the short-circuit point in the packaging layer is located according to the size s2 of the thermal imaging image and the acquisition time t2. Under the premise of the same test voltage and the same acquisition time t2, the larger the size s2 of the thermal imaging image, the closer the short-circuit point will be to the junction of the packaging layer and the substrate layer. If the acquisition time t2 is greater than the third set time T3 (t2>T3), it is determined that the short-circuit point does not exist in the packaging layer, but there is a short-circuit point in the substrate layer of the chip to be tested, or at the junction of the packaging layer and the substrate layer.

[0077] When it is determined that there is a short circuit point at the substrate layer of the chip to be tested, or at the junction of the packaging layer and the substrate layer, the test voltage is adjusted to a third test voltage V3; wherein the third test voltage V3 is greater than the second test voltage V2; so that a third test current A3 is formed inside the chip, the current magnitude is milliampere level, and the third test current A3 is 5 to 10 times the second test current A2. Record the acquisition time t3 of the thermal imaging image.

[0078] If the acquisition time t3 of the thermal imaging image is less than the fourth set time T4 (t3<T4), it is determined that there is a short-circuit point in the substrate layer of the chip to be tested, and the specific position of the short-circuit point in the substrate layer is located according to the size s3 of the thermal imaging image and the acquisition time t3. If the acquisition time t3 is greater than or equal to the fourth set time T4 (t3≥T4), it is determined that the short-circuit point is located at the junction of the packaging layer and the substrate layer of the chip to be tested.

[0079] A chip short-circuit point locating method according to an embodiment of the present disclosure obtains a thermal imaging image of the short-circuit point and combines conditions such as the image display time and the voltage applied when the image is displayed to simultaneously obtain the position of the short-circuit point in the horizontal and vertical directions, thereby achieving direct and precise positioning of the short-circuit failure point of electronic components such as chips without the need for layer-by-layer screening, thereby greatly improving the efficiency of chip short-circuit point positioning.

[0080] like Figure 3 As shown, another embodiment of the present disclosure provides a chip short-circuit point positioning system, the system comprising:

[0081] The test module 301 is used to place the chip to be tested and provide the required test environment;

[0082] A power-on module 302, used for applying a test voltage to the chip under test;

[0083] An acquisition module 303 is used to acquire a thermal imaging image of the surface of the chip to be tested;

[0084] A timing module 304 is used to obtain the acquisition time when the acquisition module acquires the thermal imaging image;

[0085] The control module 305 is used to locate the short-circuit point of the chip to be tested according to the test voltage, the thermal imaging image and the acquisition time.

[0086] Specifically, the test module 301, the power-on module 302, the acquisition module 303, and the timing module 304 are all electrically connected to the control module 305. The test module 301 is provided with a target detection position for placing the chip to be tested, and can provide the test environment required for locating the chip short-circuit point, such as suitable temperature, humidity, air pressure, etc.; the power-on module 302 provides an adjustable voltage to the chip to be tested; the acquisition module 303 includes an image sensor such as an infrared camera or a thermal imaging sensor, which is arranged in the vertical direction of the chip to be tested, and is used to obtain a thermal imaging image on the surface of the chip after the short-circuit point inside the chip is heated; the timing module 304 is used to record the time from the power-on module 302 applying the test voltage to the chip to be tested until the acquisition module 303 obtains the feedback of the thermal imaging image, which is called the acquisition time; the control module 305 receives the feedback signals of each module electrically connected thereto, and sends signals to each module to control the corresponding module to make a corresponding reaction action, and locates the short-circuit point position of the chip to be tested according to the feedback signals of each module.

[0087] refer to Figure 2 As shown in the schematic diagram of the chip short-circuit point location process, the power-on module 302 first applies a first test voltage V1 to the chip to be tested to form a first test current A1 inside the chip to be tested. If the thermal imaging image is not obtained within the first set time T1, the control module 305 determines that there is no short-circuit point in the chip to be tested; if the thermal imaging image is obtained within the first set time T1, the control module 305 determines that there is a short-circuit point in the chip to be tested.

[0088] When there is a short-circuit point in the chip under test, if the acquisition time t1 of the thermal imaging image is less than the second set time T2, the control module 305 determines that there is a short-circuit point in the chip layer of the chip under test, and locates the short-circuit point of the chip layer according to the size s1 of the thermal imaging image and the acquisition time t1. If the acquisition time t1 is equal to the second set time T2, the control module 305 determines that there is a short-circuit point at the junction of the chip layer and the packaging layer of the chip under test.

[0089] If the acquisition time t1 is greater than the second set time T2, the control module 305 determines that there is a short circuit point in the packaging layer, substrate layer, or the junction of the packaging layer and the substrate layer of the chip to be tested; at this time, the power-on module 302 adjusts the test voltage to the second test voltage V2 to form a second test current A2 inside the chip to be tested, and the second test current A2 is 2 to 4 times the first test current A1. The second set time T2 is less than the first set time T1. Then the control module 305 continues to determine that if the acquisition time t2 of the thermal imaging image is less than or equal to the third set time T3, it is determined that there is a short circuit point in the packaging layer of the chip to be tested, and the short circuit point of the packaging layer is located according to the size s2 of the thermal imaging image and the acquisition time t2.

[0090] If the acquisition time t2 is greater than the third set time T3, the control module 305 determines that there is a short circuit point at the junction of the substrate layer, or the packaging layer and the substrate layer of the chip to be tested; at this time, the power-on module 302 adjusts the test voltage to the third test voltage V3 to form a third test current A3 inside the chip to be tested, and the third test current A3 is 5 to 10 times the second test current A2. Then the control module 305 continues to determine that if the acquisition time t3 of the thermal imaging image is less than the fourth set time T4, it is determined that there is a short circuit point in the substrate layer of the chip to be tested, and the position of the short circuit point of the substrate layer is located according to the size s3 of the thermal imaging image and the acquisition time t3. If the acquisition time t3 is greater than or equal to the fourth set time T4, the control module 305 determines that there is a short circuit point at the junction of the packaging layer and the substrate layer of the chip to be tested.

[0091] For example, Figure 3 As shown, the system further includes a sensing module 306, which is electrically connected to the control module 305 and is used to detect whether the chip to be tested is placed in the target detection position in the test module 301. The control module 305 is also used to control the test module 301, the power-on module 302, the acquisition module 303 and the timing module 304 to start when the chip to be tested is placed in the target detection position in the test module 301 by sensing, and to control the acquisition module 303 to standby or shut down with low power consumption when the chip to be tested is not placed in the target detection position in the test module 301, thereby reducing the power consumption of the entire system.

[0092] A chip short-circuit point positioning system of an embodiment of the present disclosure obtains a thermal imaging image of the short-circuit point and combines conditions such as the image display time and the voltage applied when the image is displayed to simultaneously obtain the position of the short-circuit point in the horizontal and vertical directions, thereby achieving direct and precise positioning of the short-circuit failure point of electronic components such as chips without the need for layer-by-layer screening, thereby greatly improving the efficiency of chip short-circuit point positioning.

[0093] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A method for locating a chip short-circuit point, wherein the chip to be tested comprises a chip layer, a packaging layer and a substrate layer stacked in sequence, characterized in that: The method comprises: Applying a test voltage to the chip to be tested; Acquire a thermal imaging image of the surface of the chip to be tested and the acquisition time of the thermal imaging image; The short-circuit point of the chip to be tested is located according to the test voltage, the thermal imaging image and the acquisition time.

2. The chip short-circuit point positioning method according to claim 1, characterized in that: The applied test voltage is a first test voltage; The step of locating the position of the short-circuit point of the chip under test according to the test voltage, the thermal imaging image and the acquisition time includes: If the thermal imaging image is not acquired within the first set time, it is determined that there is no short circuit point in the chip to be tested; If the thermal imaging image is acquired within the first set time, it is determined that a short circuit point exists in the chip to be tested.

3. The chip short-circuit point positioning method according to claim 2, characterized in that: When a short circuit point exists in the chip under test, locating the position of the short circuit point of the chip under test according to the test voltage, the thermal imaging image and the acquisition time includes: If the acquisition time of the thermal imaging image is less than the second set time, it is determined that a short-circuit point exists in the chip layer of the chip to be tested, and the short-circuit point position of the chip layer is located according to the size of the thermal imaging image and the acquisition time; If the acquisition time is equal to the second set time, it is determined that a short circuit point exists at the junction of the chip layer and the packaging layer of the chip to be tested; If the acquisition time is greater than the second set time, it is determined that a short circuit point exists at any position of the packaging layer, the substrate layer, or the junction between the packaging layer and the substrate layer of the chip to be tested; The second set time is smaller than the first set time.

4. The chip short-circuit point positioning method according to claim 3, characterized in that: When a short circuit point exists at any position of the packaging layer, substrate layer, or the junction of the packaging layer and substrate layer of the chip to be tested, the test voltage is adjusted to a second test voltage; wherein the second test voltage is greater than the first test voltage; The step of locating the position of the short-circuit point of the chip under test according to the test voltage, the thermal imaging image and the acquisition time includes: If the acquisition time of the thermal imaging image is less than or equal to a third set time, it is determined that a short-circuit point exists in the packaging layer of the chip to be tested, and the short-circuit point of the packaging layer is located according to the size of the thermal imaging image and the acquisition time; If the acquisition time is greater than the third set time, it is determined that a short circuit point exists at any position of the junction between the substrate layer, the packaging layer and the substrate layer of the chip to be tested.

5. The chip short-circuit point positioning method according to claim 4, characterized in that: When a short circuit point exists at any position of the junction between the substrate layer, the packaging layer and the substrate layer of the chip to be tested, the test voltage is adjusted to a third test voltage; wherein the third test voltage is greater than the second test voltage; The step of locating the position of the short-circuit point of the chip under test according to the test voltage, the thermal imaging image and the acquisition time includes: If the acquisition time of the thermal imaging image is less than a fourth set time, it is determined that a short-circuit point exists in the substrate layer of the chip to be tested, and the position of the short-circuit point of the substrate layer is located according to the size of the thermal imaging image and the acquisition time; If the acquisition time is greater than or equal to the fourth set time, it is determined that a short circuit point exists at the junction of the packaging layer and the substrate layer of the chip to be tested.

6. The chip short-circuit point locating method according to any one of claims 1 to 5, characterized in that: Before applying a test voltage to the chip to be tested, the method further includes: Detect whether the chip to be tested is in a target detection position. If the chip to be tested is in the target detection position, apply a test voltage to the chip to be tested, and obtain a thermal imaging image of the surface of the chip to be tested.

7. A chip short-circuit point positioning system, characterized in that: The system comprises: The test module is used to place the chip to be tested and provide the required test environment; A power-on module, used for applying a test voltage to the chip to be tested; An acquisition module, used for acquiring a thermal imaging image of the surface of the chip to be tested; A timing module, used to obtain the acquisition time when the acquisition module acquires the thermal imaging image; A control module is used to locate the short-circuit point of the chip to be tested according to the test voltage, the thermal imaging image and the acquisition time.

8. The chip short-circuit point positioning system according to claim 7, characterized in that: The applied test voltage is a first test voltage; The control module is specifically used for: If the thermal imaging image is not acquired within the first set time, it is determined that there is no short circuit point in the chip to be tested; If the thermal imaging image is acquired within the first set time, it is determined that a short circuit point exists in the chip to be tested.

9. The chip short-circuit point positioning system according to claim 8, characterized in that: When there is a short circuit point in the chip to be tested, the control module is specifically used to: If the acquisition time of the thermal imaging image is less than the second set time, it is determined that a short-circuit point exists in the chip layer of the chip to be tested, and the short-circuit point position of the chip layer is located according to the size of the thermal imaging image and the acquisition time; If the acquisition time is equal to the second set time, it is determined that a short circuit point exists at the junction of the chip layer and the packaging layer of the chip to be tested; If the acquisition time is greater than the second set time, it is determined that a short circuit point exists at any position of the packaging layer, the substrate layer, or the junction between the packaging layer and the substrate layer of the chip to be tested; The second set time is smaller than the first set time.

10. The chip short-circuit point positioning system according to claim 9, characterized in that: When a short circuit point exists at any position of the packaging layer, substrate layer, or the junction of the packaging layer and substrate layer of the chip to be tested, the power-on module is further used to adjust the test voltage to a second test voltage to form a second test current inside the chip to be tested; wherein the second test voltage is greater than the first test voltage; The control module is specifically used for: If the acquisition time of the thermal imaging image is less than or equal to a third set time, it is determined that a short-circuit point exists in the packaging layer of the chip to be tested, and the short-circuit point of the packaging layer is located according to the size of the thermal imaging image and the acquisition time; If the acquisition time is greater than the third set time, it is determined that a short circuit point exists at any position of the junction between the substrate layer, the packaging layer and the substrate layer of the chip to be tested.

11. The chip short-circuit point positioning system according to claim 10, characterized in that: When a short circuit point exists at any position of the junction of the substrate layer, the packaging layer and the substrate layer of the chip to be tested, the power-on module is further used to adjust the test voltage to a third test voltage to form a third test current inside the chip to be tested; wherein the third test voltage is greater than the second test voltage; The positioning module is specifically used for: If the acquisition time of the thermal imaging image is less than a fourth set time, it is determined that a short-circuit point exists in the substrate layer of the chip to be tested, and the position of the short-circuit point of the substrate layer is located according to the size of the thermal imaging image and the acquisition time; If the acquisition time is greater than or equal to the fourth set time, it is determined that a short circuit point exists at the junction of the packaging layer and the substrate layer of the chip to be tested.

12. The chip short-circuit point positioning system according to any one of claims 7 to 11, characterized in that: The system also includes a sensing module; The sensing module is used to detect whether the chip to be tested is placed in the testing module; The control module is also used to control the test module, the power-on module, the acquisition module and the timing module to start when the chip to be tested is placed in the test module; and to control the acquisition module to standby or shut down when the chip to be tested is not placed in the test module.

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