Method for automatically calculating coordinate value of alignment chip in photoetching pattern

Abstract

The invention discloses a method for automatically calculating a coordinate value of an alignment chip in a photoetching pattern. The method comprises the following steps: S1, obtaining the size of a single chip and the row number and the column number of the chip in a unit domain; forming a wafer drawing, and defining the coordinates of the central point of the unit domain graph as (0, 0); s2, designing, arranging and aligning a chip graph template in the unit domain graph; s3, automatically identifying a base point coordinate of each alignment chip graphic template, and calculating a difference value from the base point coordinates of different alignment chip graphic templates to the X direction and the Y direction of the center point coordinate of the unit domain graph; the difference value is the coordinate value of the alignment chip graph. According to the method, the coordinate value of the alignment chip graph can be automatically calculated, various personal errors are effectively avoided, the accuracy of the drawing is greatly improved, reworking is avoided, the delivery time is guaranteed to the maximum extent, and cost is saved to the maximum extent.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and more specifically to a method for automatically calculating coordinate values ​​of aligned chips in photolithography graphics. Background Art

[0002] With the continuous development of packaging technology, in the field of lithography, packaging processes such as eWLB (embedded Wafer Level BGA), FOCT-S (FANOUT-Connected Tech-silicon), and FOCT-R (FANOUT-Connected Tech-RDL) require exposure alignment by inputting the alignment chip (mark) graphic coordinate values ​​as long as the real wafer is not used during exposure.

[0003] There will be 2 to 4 alignment chips in a unit field, and there will be more than 2 alignment patterns in the alignment chip, and each alignment pattern requires a coordinate value.

[0004] In conventional design, designers need to draw a unit field graphic and a mark graphic first, and manually mark the distance between the mark graphic and the unit field, and write it manually in a table. Therefore, it is necessary to measure and read the coordinate values ​​of different mark graphics in each layer of the mask in a unit field in the CAD drawing. In conventional measurement, click "Annotation"-"Linear" in the CAD drawing interface, move the mouse to the center point of the mark graphic and confirm, move the mouse to the center point of the field again and confirm, you can pull out the distance value in the X / Y direction, and manually fill in the coordinate value.

[0005] The above manual operation is prone to errors in identifying the center point. The slight error in the center point selection cannot be recognized by the naked eye unless it is magnified and observed; and there is a certain probability of error when manually inputting numerical values.

[0006] Due to the uncontrollability of manual operation, errors are likely to occur, resulting in exposure offset during the exposure process, product failure and rework.

[0007] Therefore, there is an urgent need to provide a method that can automatically calculate the coordinate values ​​of the chip alignment in the lithography pattern. Summary of the invention

[0008] In order to solve the above problems, the present invention provides a method for automatically calculating the coordinate values ​​of the chip alignment in the lithography pattern. The method can be used to automatically calculate the coordinate values ​​of the chip alignment pattern, effectively avoid various human errors, greatly improve the accuracy of the drawings, avoid rework, and maximize the delivery time and cost savings.

[0009] In order to achieve the above object, the present invention discloses a method for automatically calculating the coordinate value of the chip alignment in the lithography pattern, the method comprising the following steps:

[0010] S1, obtain the size step_X in the X direction and the size step_Y in the Y direction of a single chip, the number of chip rows ReticleX_F1 and the number of columns ReticleY_F1 in the unit domain; and form a wafer drawing, which includes a unit domain graphic, and defines the coordinates of the center point of the unit domain graphic as (0,0);

[0011] S2. Design and arrange the chip pattern template in the unit domain pattern. The specific method is as follows:

[0012] a. There are at least two chip pattern templates for alignment in each layer of mask pattern in the unit domain pattern, and the distance between the chip pattern templates for alignment in adjacent layers of mask pattern is at least greater than 150μm;

[0013] b. Build and name different alignment chip graphic templates respectively, with the naming format of: layer-alignment chip serial number-alignment chip graphic template serial number, and use the center point of each alignment chip graphic template as the base point coordinate;

[0014] S3, automatically identifying the base point coordinates of each alignment chip graphic template, and calculating the difference in the X and Y directions from the base point coordinates of different alignment chip graphic templates to the center point coordinates of the unit domain graphic; the difference is the coordinate value of the alignment chip graphic.

[0015] In some implementations, the mask pattern file has multiple layers, and the distance between the chip pattern templates of adjacent mask patterns is at least greater than 150 μm to ensure that each chip pattern template can be accurately identified.

[0016] In some implementations, different alignment chip pattern templates are collected to form a template library, and the alignment chip pattern template is called according to its name.

[0017] In some implementations, in step S3, the center point of each alignment chip graphic template is automatically identified using CAD software.

[0018] In some implementations, the method further includes step S4: arranging all the measured values ​​in the above step in a table and outputting them as needed.

[0019] In some implementations, the checking step is: when the spacing between the alignment chip pattern templates does not exceed a specified value, the form is sorted and output; otherwise, the form is not output.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] The present invention establishes chip pattern templates for alignment of various common packaging products; for products that do not use real wafers during exposure, it is only necessary to draw the unit domain pattern once according to the unit domain pattern arrangement determined by the FAB factory, but the chip pattern does not need to be drawn repeatedly, and the corresponding chip pattern template can be directly applied.

[0022] The method described in the present invention can automatically calculate the coordinate values ​​of the alignment chip graphics, effectively avoid various human errors, greatly improve the accuracy of the drawings, avoid rework, and guarantee the delivery time and save costs to the greatest extent possible. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of the center point of the unit domain graphic in the present invention;

[0024] Figure 2 A schematic diagram of arranging an alignment chip pattern template in a unit domain pattern in the present invention;

[0025] Figure 3 Schematic diagram of some common alignment chip patterns in the present invention. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0027] The method disclosed in the present invention for automatically calculating the coordinate values ​​of the aligned chips in the lithography pattern relies on the Visual Basic macro language. The corresponding program functions are written in VBA according to the above method, and then applied in CAD to realize the required functions.

[0028] Example 1

[0029] This embodiment discloses a method for automatically calculating the coordinate values ​​of the aligned chip in the lithography pattern, the method comprising the following steps:

[0030] S1. Obtain the size step_X in the X direction and the size step_Y in the Y direction of a single chip, the number of chip rows ReticleX_F1 and the number of columns ReticleY_F1 in the unit domain; and form a wafer drawing, which includes a unit domain graphic, and defines the center point coordinates of the unit domain graphic as (0,0), that is, Figure 1 The geometric center point of

[0031] S2. Design and arrange the chip pattern template in the unit domain pattern. The specific arrangement diagram is as follows: Figure 2 As shown, Figure 2 1-4 in the figure represent 4 alignment chip pattern templates;

[0032] The specific arrangement method is:

[0033] a. There are at least two chip pattern templates for alignment in each layer of mask pattern in the unit domain pattern, and the distance between the chip pattern templates for alignment in adjacent layers of mask pattern is at least greater than 150μm;

[0034] b. Build and name different alignment chip graphic templates respectively, with the naming format of: layer-alignment chip serial number-alignment chip graphic template serial number, and use the center point of each alignment chip graphic template as the base point coordinate;

[0035] S3, automatically identifying the base point coordinates of each alignment chip graphic template, and calculating the difference in the X and Y directions from the base point coordinates of different alignment chip graphic templates to the center point coordinates of the unit domain graphic; the difference is the coordinate value of the alignment chip graphic.

[0036] The mask pattern file has multiple layers, and the chip pattern templates between adjacent layers of mask patterns are at least 150 μm apart to ensure that each chip pattern template can be accurately identified.

[0037] In step S3, the center point of each alignment chip graphic template is automatically identified using CAD software.

[0038] The above method further comprises step S4: after checking all the measured values ​​in step S4, they are sorted in a form and output as required.

[0039] The checking steps are as follows: when the spacing between the alignment chip pattern templates does not exceed the specified value, the form is sorted and output; otherwise, the form is not output.

[0040] The specified value refers to different alignment pattern coordinate spacing values ​​corresponding to different chip sizes. When the chip size is determined, the alignment pattern coordinate spacing is also determined accordingly.

[0041] When the spacing between the alignment chip graphic templates meets the alignment graphic coordinate spacing corresponding to the current chip size, it is judged to be correct and the form is output; when the spacing between the alignment chip graphic templates does not meet the alignment graphic coordinate spacing corresponding to the current chip size, it is judged to be wrong and the form is not output.

[0042] Through the present invention, it is possible to establish alignment chip graphic templates for a variety of common packaged products, collect different alignment chip graphic templates to form a template library, and call them according to the name of the alignment chip graphic template. Specifically, for products that do not use real wafers during exposure, it is only necessary to draw the unit domain graphic once according to the unit domain graphic arrangement set by the FAB factory, but the alignment chip graphic does not need to be drawn repeatedly, and the corresponding alignment chip graphic template in the template library can be directly applied. Then, the various steps of automatically calculating the coordinate values ​​of the alignment chip graphic described in the present invention are used.

[0043] Some common chip alignment patterns are as follows: Figure 3 As shown, according to different alignment patterns, alignment can be performed in the exposure process.

[0044] The method described in the present invention can automatically calculate the coordinate values ​​of the alignment chip graphics, effectively avoid various human errors, greatly improve the accuracy of the drawings, avoid rework, and guarantee the delivery time and save costs to the greatest extent possible.

[0045] The above are only some embodiments of the present invention. It should be pointed out that for ordinary technicians in this field, other modifications and improvements can be made without departing from the creative concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A method for automatically calculating the coordinate value of the chip in the lithography pattern, characterized in that: The method comprises the following steps: S1, obtain the size step_X in the X direction and the size step_Y in the Y direction of a single chip, the number of chip rows ReticleX_F1 and the number of columns ReticleY_F1 in the unit domain; and form a wafer drawing, which includes a unit domain graphic, and defines the coordinates of the center point of the unit domain graphic as (0,0); S2. Design and arrange the chip pattern template in the unit domain pattern. The specific method is as follows: a. There are at least two chip pattern templates for alignment in each layer of mask pattern in the unit domain pattern, and the distance between the chip pattern templates for alignment in adjacent layers of mask pattern is at least greater than 150μm; b. Build and name different alignment chip graphic templates respectively, with the naming format of: layer-alignment chip serial number-alignment chip graphic template serial number, and use the center point of each alignment chip graphic template as the base point coordinate; S3, automatically identifying the base point coordinates of each alignment chip graphic template, and calculating the difference in the X and Y directions from the base point coordinates of different alignment chip graphic templates to the center point coordinates of the unit domain graphic; the difference is the coordinate value of the alignment chip graphic.

2. The method for automatically calculating the coordinate value of the chip in the lithography pattern according to claim 1, characterized in that: The mask pattern file has multiple layers, and the distance between the chip pattern templates of adjacent mask patterns is at least greater than 150 μm to ensure that each chip pattern template can be accurately identified.

3. The method for automatically calculating the coordinate value of the chip in the lithography pattern according to claim 2, characterized in that: Different alignment chip graphic templates are collected to form a template library, and the alignment chip graphic template is called according to the name of the template.

4. The method for automatically calculating the coordinate value of the chip in the lithography pattern according to claim 3, characterized in that: In step S3, the center point of each alignment chip graphic template is automatically identified using CAD software.

5. The method for automatically calculating the coordinate value of the chip in the lithography pattern according to claim 4, characterized in that: The method further comprises step S4: after checking all the measured values ​​in the above step, arranging them in a form and outputting them as required.

6. The method for automatically calculating the coordinate value of the chip in the lithography pattern according to claim 5, characterized in that: The checking step is: when the spacing between the alignment chip pattern templates does not exceed the specified value, the form is sorted and output, otherwise the form is not output.

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