Solid state disk low-power-consumption control circuit and storage device

Abstract

The invention provides a solid state disk low-power-consumption control circuit and a storage device, and relates to the technical field of solid state disks, and the solid state disk low-power-consumption control circuit comprises an interface module connected with an external power supply, a switch module, a main control module and flash memory particles. Wherein the interface module is electrically connected with the switch module and the main control module respectively, the switch module is electrically connected with the main control module and the flash memory particles respectively, and the main control module is in communication connection with the flash memory particles and the equipment system respectively. The interface module is used for outputting multiple paths of different power supply voltages to the main control module and the flash memory particles through the switch module, and the interface module is also used for outputting multiple paths of different power supply voltages to the main control module. And the main control module is used for controlling the enabling end of the switch module to be invalid when receiving a low-power-consumption mode instruction sent by the equipment system, so that the switch module cuts off multiple paths of power supply voltages flowing to the main control module and the flash memory particles, thereby reducing the energy consumption of the solid state disk when the equipment system is in a low-power-consumption state, and improving the cruising ability of the equipment system.

Description

Technical Field

[0001] The present application relates to the technical field of solid state hard disks, and in particular to a low power consumption control circuit and a storage device for a solid state hard disk. Background Art

[0002] Ball grid array solid state drive (BGA SSD) is a solid state drive packaged in chip form, that is, a solid state drive storage product that encapsulates the main control module and flash memory particles in one chip. Compared with onboard solid state drives, it has the advantages of small size and high integration, and can be widely used in tablet computers and other mobile terminals.

[0003] The protocol specification defines that the power supply of BGA SSD comes from external supply, that is, the power conversion module is not integrated inside the BGA SSD, and the BGA SSD cannot effectively control the power circuit. As a result, when the BGA SSD is in low-power state such as sleep mode, the power supply of the BGA SSD chip is still present, and the functional modules inside the chip are still in a power-consuming state, and it has not really entered the low-power mode. Since mobile terminal devices are generally powered by power supply, this will affect the endurance of the device system.

[0004] In summary, how to reduce the energy consumption of the solid-state drive when the device system is in a low-power state is a technical problem that needs to be urgently solved by those skilled in the art. Summary of the invention

[0005] The purpose of the present application is to provide a low-power consumption control circuit and a storage device for a solid-state hard disk, so as to reduce the energy consumption of the solid-state hard disk when the device system is in a low-power consumption state.

[0006] In order to achieve the above purpose, the technical solution adopted in this application is as follows:

[0007] On the one hand, the present application provides a low-power consumption control circuit for a solid-state hard disk, comprising: an interface module connected to an external power supply, a switch module, a main control module, and flash memory particles; the interface module is electrically connected to the switch module and the main control module respectively, the switch module is electrically connected to the main control module and the flash memory particles respectively, and the main control module is communicatively connected to the flash memory particles and a device system respectively;

[0008] The interface module is used to output multiple different power supply voltages to the main control module and the flash memory particles through the switch module, and the interface module is also used to output multiple different power supply voltages to the main control module;

[0009] The switch module is used to be turned on when receiving a valid enable signal;

[0010] The main control module is used to control the enable end of the switch module to be invalid when receiving the low power mode instruction sent by the device system, so that the switch module cuts off the multi-channel power supply voltage flowing to the main control module and the flash memory particles.

[0011] Furthermore, the enable signal is valid at a high level.

[0012] Further, the interface module includes a first output terminal, a second output terminal and a third output terminal, which are respectively used to output a first power supply voltage, a second power supply voltage and a third power supply voltage;

[0013] The first output end of the interface module is connected to the main power supply end of the flash memory particle through the switch module, and the first output end of the interface module is also connected to the first interface power supply end of the main control module;

[0014] The third output terminal of the interface module is connected to the analog power supply terminal of the main control module through the switch module, and the third output terminal of the interface module is also connected to the main power supply terminal of the main control module;

[0015] The second output end of the interface module is connected to the second interface power end of the main control module and the interface power end of the flash memory particle through the switch module; wherein the first interface power end is the power supply end of the general input and output interface module inside the main control module, and the second interface power end is the power supply end of the input and output interface module inside the main control module that controls the flash memory particle;

[0016] The input and output interface end of the main control module is connected to the enable end of the switch module;

[0017] When the main control module receives the low power consumption mode instruction, the input and output interface terminal of the main control module outputs a low level to the enable terminal of the switch module.

[0018] Further, the switch module includes a first switch unit, a second switch unit and a third switch unit;

[0019] The first output end of the interface module is connected to the main power supply end of the flash memory particle through the first switch unit, and the first output end of the interface module is also connected to the first interface power supply end of the main control module;

[0020] The third output terminal of the interface module is connected to the analog power terminal of the main control module through the third switch unit, and the third output terminal of the interface module is also connected to the main power terminal of the main control module;

[0021] The second output end of the interface module is connected to the second interface power end of the main control module and the interface power end of the flash memory particle respectively through the second switch unit;

[0022] The first input / output interface terminal of the main control module is connected to the enable terminal of the first switch unit, the second input / output interface terminal of the main control module is connected to the enable terminal of the second switch unit, and the third input / output interface terminal of the main control module is connected to the enable terminal of the third switch unit;

[0023] When the main control module receives the low power mode instruction, the first input / output interface terminal, the second input / output interface terminal and the third input / output interface terminal of the main control module output low levels to the enable terminal of the first switch unit, the enable terminal of the second switch unit and the enable terminal of the third switch unit respectively.

[0024] Further, the first switch unit includes a first switch chip, a first input filter capacitor and a first output filter capacitor; one end of the first input filter capacitor is respectively connected to the first output end of the interface module and the input end of the first switch chip, and the other end of the first input filter capacitor is grounded; one end of the first output filter capacitor is respectively connected to the output end of the first switch chip and the main power supply end of the flash memory particle, and the other end of the first output filter capacitor is grounded; the enable end of the first switch chip is connected to the first input and output interface end of the main control module;

[0025] The third switch unit includes a third switch chip, a third input filter capacitor and a third output filter capacitor; one end of the third input filter capacitor is respectively connected to the third output end of the interface module and the input end of the third switch chip, and the other end of the third input filter capacitor is grounded; one end of the third output filter capacitor is respectively connected to the output end of the third switch chip and the analog power supply end of the main control module, and the other end of the third output filter capacitor is grounded; the enable end of the third switch chip is connected to the third input and output interface end of the main control module;

[0026] The second switch unit includes a second switch chip, a second input filter capacitor and a second output filter capacitor; one end of the second input filter capacitor is respectively connected to the second output end of the interface module and the input end of the second switch chip, and the other end of the second input filter capacitor is grounded; one end of the second output filter capacitor is respectively connected to the output end of the second switch chip, the second interface power supply end of the main control module and the interface power supply end of the flash memory particle, and the other end of the second output filter capacitor is grounded; the enable end of the second switch chip is connected to the second input and output interface end of the main control module.

[0027] Further, the switch module includes a first switch unit, a second switch unit and a third switch unit, and the solid state hard disk low power consumption control circuit also includes a first resistor;

[0028] The first output end of the interface module is connected to the main power supply end of the flash memory particle through the first switch unit, and the first output end of the interface module is also connected to the first interface power supply end of the main control module;

[0029] The third output terminal of the interface module is connected to the analog power terminal of the main control module through the third switch unit, and the third output terminal of the interface module is also connected to the main power terminal of the main control module;

[0030] The second output end of the interface module is connected to the second interface power end of the main control module and the interface power end of the flash memory particle respectively through the second switch unit;

[0031] The fourth input / output interface terminal of the main control module is connected to the enable terminal of the third switch unit, the control terminal of the third switch unit is connected to the analog power supply terminal of the main control module through the first resistor, and the control terminal of the third switch unit is also connected to the enable terminal of the first switch unit and the enable terminal of the second switch unit respectively;

[0032] When the main control module receives the low power consumption mode instruction, the fourth input-output interface terminal of the main control module outputs a low level to the enable terminal of the third switch unit.

[0033] Further, the first switch unit includes a first switch chip, a first input filter capacitor and a first output filter capacitor; one end of the first input filter capacitor is respectively connected to the first output end of the interface module and the input end of the first switch chip, and the other end of the first input filter capacitor is grounded; one end of the first output filter capacitor is respectively connected to the output end of the first switch chip and the main power supply end of the flash memory particle, and the other end of the first output filter capacitor is grounded;

[0034] The second switch unit includes a second switch chip, a second input filter capacitor and a second output filter capacitor; one end of the second input filter capacitor is respectively connected to the second output end of the interface module and the input end of the second switch chip, and the other end of the second input filter capacitor is grounded; one end of the second output filter capacitor is respectively connected to the output end of the second switch chip, the second interface power supply end of the main control module and the interface power supply end of the flash memory particle, and the other end of the second output filter capacitor is grounded;

[0035] The third switch unit includes a third switch chip, a third input filter capacitor and a third output filter capacitor; one end of the third input filter capacitor is respectively connected to the third output end of the interface module and the input end of the third switch chip, and the other end of the third input filter capacitor is grounded; one end of the third output filter capacitor is respectively connected to the output end of the third switch chip and the analog power supply end of the main control module, and the other end of the third output filter capacitor is grounded;

[0036] The enable end of the third switch chip is connected to the fourth input / output interface end of the main control module, the control end of the third switch chip is connected to the analog power supply end of the main control module through the first resistor, and the control end of the third switch chip is also connected to the enable end of the first switch chip and the enable end of the second switch chip, respectively.

[0037] Furthermore, the solid-state hard disk low-power control circuit further includes a voltage conversion module, and the first output terminal of the interface module is connected to the first interface power terminal of the main control module through the voltage conversion module;

[0038] The voltage conversion module is used to convert the first power supply voltage into the power supply voltage required by the universal input and output interface module inside the main control module.

[0039] Further, the voltage conversion module includes a voltage conversion chip, a fourth input filter capacitor and a fourth output filter capacitor; one end of the fourth input filter capacitor is respectively connected to the first output end of the interface module, the input end of the voltage conversion chip and the enable end of the voltage conversion chip, and the other end of the fourth input filter capacitor is grounded; one end of the fourth output filter capacitor is respectively connected to the output end of the voltage conversion chip and the first interface power supply end of the main control module, and the other end of the fourth output filter capacitor is grounded.

[0040] On the other hand, the present application also provides a storage device, which includes the low-power consumption control circuit of the solid-state hard disk as described in any of the aforementioned embodiments.

[0041] Compared with the prior art, this application has the following beneficial effects:

[0042] The present application provides a low-power control circuit and storage device for a solid-state hard disk, including: an interface module connected to an external power supply, a switch module, a main control module, and flash memory particles. The interface module outputs multiple different power supply voltages to the main control module and the flash memory particles through the switch module, and the interface module also directly outputs multiple power supply voltages to the main control module to ensure that the main control module can always communicate with the device system. When the main control module receives a low-power mode instruction sent by the device system, it indicates that the device system will be in a low-power sleep state. The main control module controls the enable end of the switch module to be invalid, so that the switch module turns off the multiple power supply voltages flowing to the main control module and the flash memory particles. At this time, the entire solid-state hard disk is in an extremely low power consumption state, which makes the low energy consumption characteristics of the solid-state hard disk in the device system more prominent and improves the endurance of the device system. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians of the art without making creative work are within the scope of protection of the present application.

[0044] Figure 1 This is one of the structural schematic diagrams of a low-power consumption control circuit of a solid-state hard disk provided in this application;

[0045] Figure 2 This is a second structural diagram of a low-power consumption control circuit for a solid-state hard disk provided in the present application;

[0046] Figure 3 This is a third structural diagram of a low-power consumption control circuit for a solid-state hard disk provided in the present application;

[0047] Figure 4 This is a fourth structural diagram of a low-power consumption control circuit for a solid-state hard disk provided in the present application;

[0048] Figure 5 This is the fifth structural schematic diagram of a low-power control circuit for a solid-state hard disk provided in this application.

[0049] Reference numerals: 100 -interface module; 200 -switch module; 210 -first switch unit; 220 -second switch unit; 230 -third switch unit; 300 -main control module; 400 -flash memory particle; 500 -voltage conversion module. DETAILED DESCRIPTION

[0050] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0051] In the description of this application, it should be noted that relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The term "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium.

[0052] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0053] As mentioned in the background technology, since the BGA SSD does not have an integrated power conversion module, the BGA SSD cannot effectively control the power circuit. As a result, when the BGA SSD device system is in a low-power state such as sleep, the power supplies of the BGA SSD chip are still present, and the functional modules inside the chip are still in a power-consuming state, and the low-power mode has not been truly entered, affecting the endurance of the device system.

[0054] Therefore, how to reduce the energy consumption of the solid-state drive when the device system is in a low-power state is a technical problem that needs to be solved urgently by those skilled in the art.

[0055] To solve the above technical problems, please refer to Figure 1The embodiment of the present application provides a low-power consumption control circuit for a solid-state hard disk, including: an interface module 100, a switch module 200, a main control module 300, and a flash memory particle 400. The interface module 100 is electrically connected to the switch module 200 and the main control module 300, respectively; the switch module 200 is electrically connected to the main control module 300 and the flash memory particle 400, respectively; and the main control module 300 is communicatively connected to the flash memory particle 400 and the device system, respectively.

[0056] The switch module 200, the main control module 300 and the flash memory particles 400 are internal modules of the solid state drive, and the device system can be a tablet computer or other mobile terminal. The main control module 300 transmits data with the device system through the TX / RX communication interface to obtain the working status of the device system. The TX / RX communication interface can be a SATA interface or a PCIe interface.

[0057] The interface module 100 is used to output multiple different power supply voltages to the main control module 300 and the flash memory particles 400 through the switch module 200. The interface module 100 is also used to output multiple different power supply voltages to the main control module 300.

[0058] The switch module 200 is configured to be turned on when receiving a valid enable signal.

[0059] The main control module 300 is used to control the enable terminal EN of the switch module 200 to be invalid when receiving the low power mode instruction sent by the device system, so that the switch module 200 cuts off the multi-channel power supply voltage flowing to the main control module 300 and the flash memory particles 400.

[0060] Based on the above design, since the interface module 100 outputs multiple different power supply voltages to the main control module 300 and the flash memory particles 400 through the switch module 200, and the interface module 100 also directly outputs part of the multiple power supply voltages to the main control module 300 to ensure that the main control module 300 can always communicate with the device system. Therefore, when the device system is working normally, the main control module 300 controls the enable terminal EN of the switch module 200 to be valid, and the switch module 200 is turned on to transmit the multiple different power supply voltages output by the interface module 100 to the corresponding power supply ports of the main control module 300 and the flash memory particles 400, respectively, so as to maintain the normal operation of the device system.

[0061] When the main control module 300 receives the low power mode instruction sent by the device system, it indicates that the device system will be in a low power sleep state. The main control module 300 controls the enable terminal EN of the switch module 200 to be invalid, so that the switch module 200 cuts off the multi-channel power supply voltage flowing to the main control module 300 and the flash memory particles 400. At this time, the entire solid state drive is in an extremely low power consumption state.

[0062] In the protocol specification, it is generally necessary to provide three different power supply voltages to the solid state drive. In order to better understand the working principle of the low power control circuit of the solid state drive, the following description is given by taking the interface module 100 outputting three power supply voltages as an example.

[0063] like Figure 1 As shown, the interface module 100 includes a first output terminal OUT1, a second output terminal OUT2 and a third output terminal OUT3, which are respectively used to output a first power supply voltage PWR_1, a second power supply voltage PWR_2 and a third power supply voltage PWR_3.

[0064] The first output terminal OUT1 of the interface module 100 is connected to the main power terminal VCC of the flash memory particle 400 through the switch module 200 . The first output terminal OUT1 of the interface module 100 is also connected to the first interface power terminal VIO of the main control module 300 .

[0065] The third output terminal OUT3 of the interface module 100 is connected to the analog power terminal AVDD of the main control module 300 through the switch module 200 . The third output terminal OUT3 of the interface module 100 is also connected to the main power terminal VDD of the main control module 300 .

[0066] The second output terminal OUT2 of the interface module 100 is connected to the second interface power terminal FVDD of the main control module 300 and the interface power terminal VCCQ of the flash memory particle 400 through the switch module 200 .

[0067] The input / output interface terminal GPIO of the main control module 300 is connected to the enable terminal EN of the switch module 200 .

[0068] It should be noted that the main power supply terminal VDD of the main control module 300 is the core voltage power supply terminal of the main control module 300, the analog power supply terminal AVDD is the power supply terminal of the analog function module inside the main control module 300, the first interface power supply terminal VIO is the power supply terminal of the general input and output interface module inside the main control module 300, and the second interface power supply terminal FVDD is the power supply terminal of the input and output interface module that controls the flash memory particles 400 inside the main control module 300.

[0069] The main power supply terminal VCC of the flash memory particle 400 is a core voltage power supply terminal of the flash memory particle 400 , and the interface power supply terminal VCCQ is a power supply terminal of a general input / output interface module inside the flash memory particle 400 .

[0070] The voltage at the second interface power terminal FVDD of the main control module 300 is equal to the voltage at the interface power terminal VCCQ of the flash memory particle 400 .

[0071] In the embodiment of the present application, the enable signal is valid at a high level. When the main control module 300 receives a low power mode instruction, the input and output interface terminal GPIO of the main control module 300 outputs a low level to the enable terminal EN of the switch module 200, and the switch module 200 is turned off. At this time, the interface module 100 only outputs the third power supply voltage PWR_3 to the main power supply terminal VDD of the main control module 300, and outputs the first power supply voltage PWR_1 to the first interface power supply terminal VIO of the main control module 300, which greatly reduces the energy consumption of the solid-state hard disk when the device system is in a low power state, and improves the working endurance of the device system.

[0072] It should be noted that, since the interface module 100 outputs multiple supply voltages, the switch module 200 may be: Figure 1 The single chip shown integrates multiple switches to realize the functions of multiple discrete switches, or it can be multiple separate switch units to control the on and off of multiple power supply voltages respectively.

[0073] When the switch module 200 is a plurality of separate switch units, the present application embodiment provides two control schemes. The first control scheme is as follows: Figure 2 As shown, the switch module 200 includes a first switch unit 210 , a second switch unit 220 and a third switch unit 230 .

[0074] The first output terminal OUT1 of the interface module 100 is connected to the main power terminal VCC of the flash memory particle 400 through the first switch unit 210 , and the first output terminal OUT1 of the interface module 100 is also connected to the first interface power terminal VIO of the main control module 300 .

[0075] The third output terminal OUT3 of the interface module 100 is connected to the analog power terminal AVDD of the main control module 300 through the third switch unit 230 . The third output terminal OUT3 of the interface module 100 is also connected to the main power terminal VDD of the main control module 300 .

[0076] The second output terminal OUT2 of the interface module 100 is connected to the second interface power terminal FVDD of the main control module 300 and the interface power terminal VCCQ of the flash memory particle 400 through the second switch unit 220 .

[0077] The first input / output interface terminal GPIO1 of the main control module 300 is connected to the enable terminal EN1 of the first switch unit 210 , the second input / output interface terminal GPIO2 of the main control module 300 is connected to the enable terminal EN2 of the second switch unit 220 , and the third input / output interface terminal GPIO3 of the main control module 300 is connected to the enable terminal EN3 of the third switch unit 230 .

[0078] The control process of the entire SSD low power control circuit is as follows:

[0079] When the main control module 300 receives an instruction from the device system to enter the low power consumption mode, the main control module 300 completes data preservation through internal software control, and then outputs a low level to the enable terminal EN1 of the first switch unit 210 through the first input-output interface terminal GPIO1 to turn off the first switch unit 210, and the main power supply voltage supplied to the flash memory particle 400 is 0V; outputs a low level to the enable terminal EN3 of the third switch unit 230 through the third input-output interface terminal GPIO3 to turn off the third switch unit 230, and the analog power supply voltage supplied to the main control module 300 is 0V; outputs a low level to the enable terminal EN2 of the second switch unit 220 through the second input-output interface terminal GPIO2 to turn off the second switch unit 220, and the interface power supply voltage supplied to the flash memory particle 400 and the second interface power supply voltage supplied to the main control module 300 are both 0V.

[0080] At this time, the voltage of the flash memory particles 400 is all turned off, and the flash memory particles 400 are in a non-power consumption state. The analog power supply voltage and the second interface power supply voltage of the main control module 300 are all turned off, and the corresponding functional modules inside the main control module 300 and the flash memory particle 400 control module are also in a non-power consumption state. That is, the entire solid-state hard disk power consumption module only has the first interface power supply voltage module of the main control module 300, the main power supply voltage module, and the self-consumption of the three switch units themselves, and the whole enters an extremely low power consumption state.

[0081] When the main control module 300 receives the wake-up work instruction, it will re-enable and open the first switch unit 210, the second switch unit 220 and the third switch unit 230 through the first input and output interface terminal GPIO1, the second input and output interface terminal GPIO2 and the third input and output interface terminal GPIO3, and each voltage will resume power supply, and the solid-state hard disk will resume normal working power consumption state.

[0082] Furthermore, the specific circuit structure of each switch unit is as follows: Figure 3 As shown. In an embodiment of the present application, the first switch unit 210 includes a first switch chip U1, a first input filter capacitor CIN1 and a first output filter capacitor COUT1. Among them, one end of the first input filter capacitor CIN1 is respectively connected to the first output terminal OUT1 of the interface module 100 and the input terminal VIN1 of the first switch chip U1, and the other end of the first input filter capacitor CIN1 is grounded. One end of the first output filter capacitor COUT1 is respectively connected to the output terminal VOUT1 of the first switch chip U1 and the main power supply terminal VCC of the flash memory particle 400, and the other end of the first output filter capacitor COUT1 is grounded. The enable terminal EN1 of the first switch chip U1 is connected to the first input and output interface terminal GPIO1 of the main control module 300.

[0083] The third switch unit 230 includes a third switch chip U3, a third input filter capacitor CIN3 and a third output filter capacitor COUT3. One end of the third input filter capacitor CIN3 is respectively connected to the third output terminal OUT3 of the interface module 100 and the input terminal VIN3 of the third switch chip U3, and the other end of the third input filter capacitor CIN3 is grounded. One end of the third output filter capacitor COUT3 is respectively connected to the output terminal VOUT3 of the third switch chip U3 and the analog power supply terminal AVDD of the main control module 300, and the other end of the third output filter capacitor COUT3 is grounded. The enable terminal EN3 of the third switch chip U3 is connected to the third input and output interface terminal GPIO3 of the main control module 300.

[0084] The second switch unit 220 includes a second switch chip U2, a second input filter capacitor CIN2, and a second output filter capacitor COUT2. One end of the second input filter capacitor CIN2 is respectively connected to the second output terminal OUT2 of the interface module 100 and the input terminal VIN2 of the second switch chip U2, and the other end of the second input filter capacitor CIN2 is grounded. One end of the second output filter capacitor COUT2 is respectively connected to the output terminal VOUT2 of the second switch chip U2, the second interface power supply terminal FVDD of the main control module 300, and the interface power supply terminal VCCQ of the flash memory particle 400, and the other end of the second output filter capacitor COUT2 is grounded. The enable terminal EN2 of the second switch chip U2 is connected to the second input and output interface terminal GPIO2 of the main control module 300.

[0085] In order to adjust the slope of the output voltage of each switch chip and suppress the surge current at the power-on moment, in a feasible implementation, the first switch unit 210 also includes a first adjustment capacitor CT1, and the adjustment end of the first switch chip U1 is grounded through the first adjustment capacitor CT1.

[0086] The second switch unit 220 further includes a second adjustment capacitor CT2 , and the adjustment end of the second switch chip U2 is grounded through the second adjustment capacitor CT2 .

[0087] The third switch unit 230 further includes a third adjustment capacitor CT3, and the adjustment end of the third switch chip U3 is grounded through the third adjustment capacitor CT3.

[0088] In addition, in the embodiment of the present application, the low power consumption control circuit of the solid state drive further includes a voltage conversion module 500. The first output terminal OUT1 of the interface module 100 is connected to the first interface power terminal VIO of the main control module 300 through the voltage conversion module 500.

[0089] Specifically, the voltage conversion module 500 includes a voltage conversion chip U4, a fourth input filter capacitor CIN4 and a fourth output filter capacitor COUT4. One end of the fourth input filter capacitor CIN4 is respectively connected to the first output terminal OUT1 of the interface module 100, the input terminal IN4 of the voltage conversion chip U4 and the enable terminal EN4 of the voltage conversion chip U4, and the other end of the fourth input filter capacitor CIN4 is grounded. One end of the fourth output filter capacitor COUT4 is respectively connected to the output terminal OUT4 of the voltage conversion chip U4 and the first interface power supply terminal VIO of the main control module 300, and the other end of the fourth output filter capacitor COUT4 is grounded.

[0090] The voltage conversion module 500 can convert the first power supply voltage PWR_1 output by the interface module 100 into the power supply voltage required by the universal input and output interface module inside the main control module 300 .

[0091] It can be seen that in the above control scheme, the main control module 300 needs to control three switch units respectively through three input and output interface terminals. If the interface module 100 outputs more supply voltages, the main control module 300 needs to control multiple switch units respectively through more input and output interface terminals.

[0092] In order to reduce the number of input and output interface terminals of the main control module 300, the second control scheme provided in the embodiment of the present application is as follows: Figure 4 The switch module 200 includes a first switch unit 210, a second switch unit 220 and a third switch unit 230, and the solid state hard disk low power consumption control circuit also includes a first resistor R1.

[0093] The first output terminal OUT1 of the interface module 100 is connected to the main power terminal VCC of the flash memory particle 400 through the first switch unit 210 , and the first output terminal OUT1 of the interface module 100 is also connected to the first interface power terminal VIO of the main control module 300 .

[0094] The third output terminal OUT3 of the interface module 100 is connected to the analog power terminal AVDD of the main control module 300 through the third switch unit 230 . The third output terminal OUT3 of the interface module 100 is also connected to the main power terminal VDD of the main control module 300 .

[0095] The second output terminal OUT2 of the interface module 100 is connected to the second interface power terminal FVDD of the main control module 300 and the interface power terminal VCCQ of the flash memory particle 400 through the second switch unit 220 .

[0096] The fourth input-output interface terminal GPIO4 of the main control module 300 is connected to the enable terminal EN3 of the third switch unit 230, the control terminal PG of the third switch unit 230 is connected to the analog power supply terminal AVDD of the main control module 300 through the first resistor R1, and the control terminal PG of the third switch unit 230 is also connected to the enable terminal EN1 of the first switch unit 210 and the enable terminal EN2 of the second switch unit 220 respectively.

[0097] Furthermore, the specific circuit structure of each switch unit is as follows: Figure 5 As shown. In the embodiment of the present application, the first switch unit 210 includes a first switch chip U1, a first input filter capacitor CIN1 and a first output filter capacitor COUT1. Among them, one end of the first input filter capacitor CIN1 is respectively connected to the first output terminal OUT1 of the interface module 100 and the input terminal VIN1 of the first switch chip U1, and the other end of the first input filter capacitor CIN1 is grounded. One end of the first output filter capacitor COUT1 is respectively connected to the output terminal VOUT1 of the first switch chip U1 and the main power supply terminal VCC of the flash memory particle 400, and the other end of the first output filter capacitor COUT1 is grounded.

[0098] The second switch unit 220 includes a second switch chip U2, a second input filter capacitor CIN2, and a second output filter capacitor COUT2. One end of the second input filter capacitor CIN2 is respectively connected to the second output terminal OUT2 of the interface module 100 and the input terminal VIN2 of the second switch chip U2, and the other end of the second input filter capacitor CIN2 is grounded. One end of the second output filter capacitor COUT2 is respectively connected to the output terminal VOUT2 of the second switch chip U2, the second interface power terminal FVDD of the main control module 300, and the interface power terminal VCCQ of the flash memory particle 400, and the other end of the second output filter capacitor COUT2 is grounded.

[0099] The third switch unit 230 includes a third switch chip U3, a third input filter capacitor CIN3 and a third output filter capacitor COUT3. One end of the third input filter capacitor CIN3 is connected to the third output terminal OUT3 of the interface module 100 and the input terminal VIN3 of the third switch chip U3, respectively, and the other end of the third input filter capacitor CIN3 is grounded. One end of the third output filter capacitor COUT3 is connected to the output terminal VOUT3 of the third switch chip U3 and the analog power supply terminal AVDD of the main control module 300, respectively, and the other end of the third output filter capacitor COUT3 is grounded.

[0100] The enable terminal EN3 of the third switch chip U3 is connected to the fourth input / output interface terminal GPIO4 of the main control module 300, the control terminal PG of the third switch chip U3 is connected to the analog power supply terminal AVDD of the main control module 300 through the first resistor R1, and the control terminal PG of the third switch chip U3 is also connected to the enable terminal EN1 of the first switch chip U1 and the enable terminal EN2 of the second switch chip U2 respectively.

[0101] Similarly, in order to adjust the slope of the output voltage of each switch chip and suppress the surge current at the moment of power-on, the first switch unit 210 also includes a first adjustment capacitor CT1, and the adjustment end of the first switch chip U1 is grounded through the first adjustment capacitor CT1. The second switch unit 220 also includes a second adjustment capacitor CT2, and the adjustment end of the second switch chip U2 is grounded through the second adjustment capacitor CT2. The third switch unit 230 also includes a third adjustment capacitor CT3, and the adjustment end of the third switch chip U3 is grounded through the third adjustment capacitor CT3.

[0102] In addition, the low power consumption control circuit of the solid state drive further includes a voltage conversion module 500. The first output terminal OUT1 of the interface module 100 is connected to the first interface power terminal VIO of the main control module 300 through the voltage conversion module 500. The voltage conversion module 500 is used to convert the first power supply voltage PWR_1 into the power supply voltage required by the general input and output interface module inside the main control module 300.

[0103] Specifically, the voltage conversion module 500 includes a voltage conversion chip U4, a fourth input filter capacitor CIN4 and a fourth output filter capacitor COUT4. One end of the fourth input filter capacitor CIN4 is respectively connected to the first output terminal OUT1 of the interface module 100, the input terminal IN4 of the voltage conversion chip U4 and the enable terminal EN4 of the voltage conversion chip U4, and the other end of the fourth input filter capacitor CIN4 is grounded. One end of the fourth output filter capacitor COUT4 is respectively connected to the output terminal OUT4 of the voltage conversion chip U4 and the first interface power supply terminal VIO of the main control module 300, and the other end of the fourth output filter capacitor COUT4 is grounded.

[0104] Based on the above design, please refer to Figure 4 and Figure 5 , the control process of the entire solid state drive low power control circuit is as follows:

[0105] When the device system is working normally, the third power supply voltage PWR_3 output by the interface module 100 supplies power to the main power supply terminal VDD of the main control module 300, and the first power supply voltage PWR_1 is processed by the voltage conversion module 500 and supplies power to the first interface power supply terminal VIO of the main control module 300. The main control module 300 controls the enable terminal EN3 of the third switch unit 230 to be valid through the fourth input and output interface terminal GPIO4, and the third power supply voltage PWR_3 supplies power to the analog power supply terminal AVDD of the main control module 300 through the third switch unit 230. At the same time, the control terminal PG of the third switch unit 230 is pulled up to the analog power supply voltage through the first resistor R1, and the control terminal PG is at a high level. At this time, the enable terminal EN1 of the first switch unit 210 and the enable terminal EN2 of the second switch unit 220 are both valid, and the first switch unit 210 and the second switch unit 220 are both in a conducting state. The second power supply voltage PWR_2 supplies power to the second interface power supply terminal FVDD of the main control module 300 and the interface power supply terminal VCCQ of the flash memory particle 400 through the second switch unit 220, and the first power supply voltage PWR_1 supplies power to the main power supply terminal VCC of the flash memory particle 400 through the first switch unit 210. At this time, the main control module 300 can communicate and transmit data with the device system through the TX / RX communication interface.

[0106] When the device system is in low power consumption state, after the main control module 300 receives the instruction that the device system is to enter low power consumption through the TX / RX communication interface, it saves the data, and then outputs a low level to the enable terminal EN3 of the third switch unit 230 through the fourth input and output interface terminal GPIO4, so that the enable terminal EN3 of the third switch unit 230 is invalid. The third switch unit 230 shuts off the third power supply voltage PWR_3 flowing to the analog power supply terminal AVDD of the main control module 300. At the same time, the control terminal PG of the third switch unit 230 outputs a low level to pull down the enable terminal EN1 of the first switch unit 210 and the enable terminal EN2 of the second switch unit 220 to be invalid. The second switch unit 220 shuts off the second power supply voltage PWR_2 flowing to the first interface power supply terminal VIO of the main control module 300 and the interface power supply terminal of the flash memory particle 400, and the first switch unit 210 shuts off the first power supply voltage PWR_1 flowing to the main power supply terminal of the flash memory particle 400. At this time, the interface module 100 only supplies power to the main power terminal VDD and the first interface power terminal VIO of the main control module 300, and the entire solid state drive is in an extremely low power consumption state.

[0107] When the main control module 300 receives the wake-up command of the device system, the main control module 300 controls the enable terminal EN3 of the third switch unit 230 to be valid through the fourth input and output interface terminal GPIO4, turns on the third switch unit 230, and restores power to the analog power terminal AVDD of the main control module 300. At the same time, the control terminal PG of the third switch unit 230 is pulled high, that is, the enable terminal EN1 of the first switch unit 210 and the enable terminal EN2 of the second switch unit 220 are valid, the first switch unit 210 and the second switch unit 220 are turned on, the second interface power terminal FVDD of the main control module 300, the interface power terminal VCCQ of the flash memory particle 400, and the main power terminal VCC are all restored to power, and the device system resumes normal operation.

[0108] It can be seen that the second control scheme can simultaneously control the on and off of multiple switch units through an input and output interface terminal (GPIO4) of the main control module 300, which not only reduces the energy consumption of the solid-state hard disk when the device system is in a low power state, but also saves input and output interface resources, simplifies circuit design, and reduces costs.

[0109] Furthermore, an embodiment of the present application also provides a storage device, which includes the low-power consumption control circuit of the solid-state hard disk as described in any of the aforementioned embodiments.

[0110] In summary, the embodiments of the present application provide a low-power control circuit and storage device for a solid-state hard disk, including: an interface module connected to an external power supply, a switch module, a main control module, and flash memory particles. The interface module outputs multiple different power supply voltages to the main control module and the flash memory particles through the switch module, and the interface module also directly outputs multiple power supply voltages to the main control module to ensure that the main control module can always communicate with the device system. When the device system is working normally, the main control module controls the enable end of the switch module to be effective, and the switch module is turned on to transmit the multiple different power supply voltages output by the interface module to the power supply ports corresponding to the main control module and the flash memory particles, respectively, so as to maintain the normal operation of the device system.

[0111] When the main control module receives the low power mode command sent by the device system, it indicates that the device system will be in a low power sleep state. The main control module controls the enable end of the switch module to be invalid, so that the switch module cuts off the multi-channel power supply voltage flowing to the main control module and the flash memory particles. At this time, the entire solid-state drive is in an extremely low power consumption state, making the low energy consumption feature of the solid-state drive in the device system more prominent and improving the endurance of the device system.

[0112] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0113] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A low power consumption control circuit for a solid state hard disk, characterized in that: include: An interface module, a switch module, a main control module and flash memory particles connected to an external power supply; the interface module is electrically connected to the switch module and the main control module respectively, the switch module is electrically connected to the main control module and the flash memory particles respectively, and the main control module is communicatively connected to the flash memory particles and the device system respectively; The interface module is used to output multiple different power supply voltages to the main control module and the flash memory particles through the switch module, and the interface module is also used to output multiple different power supply voltages to the main control module; The switch module is used to be turned on when receiving a valid enable signal; The main control module is used to control the enable end of the switch module to be invalid when receiving the low power mode instruction sent by the device system, so that the switch module cuts off the multi-channel power supply voltage flowing to the main control module and the flash memory particles.

2. The low power consumption control circuit of the solid state hard disk according to claim 1, characterized in that: The enable signal is effective at a high level.

3. The low power consumption control circuit of the solid state hard disk according to claim 2, characterized in that: The interface module comprises a first output terminal, a second output terminal and a third output terminal, which are used to output a first power supply voltage, a second power supply voltage and a third power supply voltage respectively; The first output end of the interface module is connected to the main power supply end of the flash memory particle through the switch module, and the first output end of the interface module is also connected to the first interface power supply end of the main control module; The third output terminal of the interface module is connected to the analog power supply terminal of the main control module through the switch module, and the third output terminal of the interface module is also connected to the main power supply terminal of the main control module; The second output end of the interface module is connected to the second interface power end of the main control module and the interface power end of the flash memory particle through the switch module; wherein the first interface power end is the power supply end of the general input and output interface module inside the main control module, and the second interface power end is the power supply end of the input and output interface module inside the main control module that controls the flash memory particle; The input and output interface end of the main control module is connected to the enable end of the switch module; When the main control module receives the low power consumption mode instruction, the input and output interface terminal of the main control module outputs a low level to the enable terminal of the switch module.

4. The low power consumption control circuit of the solid state hard disk according to claim 3, characterized in that: The switch module includes a first switch unit, a second switch unit and a third switch unit; The first output end of the interface module is connected to the main power supply end of the flash memory particle through the first switch unit, and the first output end of the interface module is also connected to the first interface power supply end of the main control module; The third output terminal of the interface module is connected to the analog power terminal of the main control module through the third switch unit, and the third output terminal of the interface module is also connected to the main power terminal of the main control module; The second output end of the interface module is connected to the second interface power end of the main control module and the interface power end of the flash memory particle respectively through the second switch unit; The first input / output interface terminal of the main control module is connected to the enable terminal of the first switch unit, the second input / output interface terminal of the main control module is connected to the enable terminal of the second switch unit, and the third input / output interface terminal of the main control module is connected to the enable terminal of the third switch unit; When the main control module receives the low power mode instruction, the first input / output interface terminal, the second input / output interface terminal and the third input / output interface terminal of the main control module output low levels to the enable terminal of the first switch unit, the enable terminal of the second switch unit and the enable terminal of the third switch unit respectively.

5. The low power consumption control circuit of the solid state hard disk according to claim 4, characterized in that: The first switch unit includes a first switch chip, a first input filter capacitor and a first output filter capacitor; one end of the first input filter capacitor is respectively connected to the first output end of the interface module and the input end of the first switch chip, and the other end of the first input filter capacitor is grounded; one end of the first output filter capacitor is respectively connected to the output end of the first switch chip and the main power supply end of the flash memory particle, and the other end of the first output filter capacitor is grounded; the enable end of the first switch chip is connected to the first input and output interface end of the main control module; The third switch unit includes a third switch chip, a third input filter capacitor and a third output filter capacitor; one end of the third input filter capacitor is respectively connected to the third output end of the interface module and the input end of the third switch chip, and the other end of the third input filter capacitor is grounded; one end of the third output filter capacitor is respectively connected to the output end of the third switch chip and the analog power supply end of the main control module, and the other end of the third output filter capacitor is grounded; the enable end of the third switch chip is connected to the third input and output interface end of the main control module; The second switch unit includes a second switch chip, a second input filter capacitor and a second output filter capacitor; one end of the second input filter capacitor is respectively connected to the second output end of the interface module and the input end of the second switch chip, and the other end of the second input filter capacitor is grounded; one end of the second output filter capacitor is respectively connected to the output end of the second switch chip, the second interface power supply end of the main control module and the interface power supply end of the flash memory particle, and the other end of the second output filter capacitor is grounded; the enable end of the second switch chip is connected to the second input and output interface end of the main control module.

6. The low power consumption control circuit of the solid state hard disk according to claim 3, characterized in that: The switch module includes a first switch unit, a second switch unit and a third switch unit, and the solid state hard disk low power consumption control circuit also includes a first resistor; The first output end of the interface module is connected to the main power supply end of the flash memory particle through the first switch unit, and the first output end of the interface module is also connected to the first interface power supply end of the main control module; The third output terminal of the interface module is connected to the analog power terminal of the main control module through the third switch unit, and the third output terminal of the interface module is also connected to the main power terminal of the main control module; The second output end of the interface module is connected to the second interface power end of the main control module and the interface power end of the flash memory particle respectively through the second switch unit; The fourth input / output interface terminal of the main control module is connected to the enable terminal of the third switch unit, the control terminal of the third switch unit is connected to the analog power supply terminal of the main control module through the first resistor, and the control terminal of the third switch unit is also connected to the enable terminal of the first switch unit and the enable terminal of the second switch unit respectively; When the main control module receives the low power mode instruction, the fourth input-output interface terminal of the main control module outputs a low level to the enable terminal of the third switch unit.

7. The low power consumption control circuit of the solid state hard disk according to claim 6, characterized in that: The first switch unit includes a first switch chip, a first input filter capacitor and a first output filter capacitor; one end of the first input filter capacitor is respectively connected to the first output end of the interface module and the input end of the first switch chip, and the other end of the first input filter capacitor is grounded; one end of the first output filter capacitor is respectively connected to the output end of the first switch chip and the main power supply end of the flash memory particle, and the other end of the first output filter capacitor is grounded; The second switch unit includes a second switch chip, a second input filter capacitor and a second output filter capacitor; one end of the second input filter capacitor is respectively connected to the second output end of the interface module and the input end of the second switch chip, and the other end of the second input filter capacitor is grounded; one end of the second output filter capacitor is respectively connected to the output end of the second switch chip, the second interface power supply end of the main control module and the interface power supply end of the flash memory particle, and the other end of the second output filter capacitor is grounded; The third switch unit includes a third switch chip, a third input filter capacitor and a third output filter capacitor; One end of the third input filter capacitor is connected to the third output end of the interface module and the input end of the third switch chip respectively, and the other end of the third input filter capacitor is grounded; one end of the third output filter capacitor is connected to the output end of the third switch chip and the analog power supply end of the main control module respectively, and the other end of the third output filter capacitor is grounded; The enable end of the third switch chip is connected to the fourth input / output interface end of the main control module, the control end of the third switch chip is connected to the analog power supply end of the main control module through the first resistor, and the control end of the third switch chip is also connected to the enable end of the first switch chip and the enable end of the second switch chip, respectively.

8. The low power consumption control circuit for a solid state hard disk according to claim 4 or 5, characterized in that: The solid state hard disk low power consumption control circuit further comprises a voltage conversion module, and the first output terminal of the interface module is connected to the first interface power terminal of the main control module through the voltage conversion module; The voltage conversion module is used to convert the first power supply voltage into the power supply voltage required by the universal input and output interface module inside the main control module.

9. The low power consumption control circuit of the solid state hard disk according to claim 8, characterized in that: The voltage conversion module includes a voltage conversion chip, a fourth input filter capacitor and a fourth output filter capacitor; one end of the fourth input filter capacitor is respectively connected to the first output end of the interface module, the input end of the voltage conversion chip and the enable end of the voltage conversion chip, and the other end of the fourth input filter capacitor is grounded; one end of the fourth output filter capacitor is respectively connected to the output end of the voltage conversion chip and the first interface power supply end of the main control module, and the other end of the fourth output filter capacitor is grounded.

10. A storage device, characterized in that: The storage device comprises the solid state hard disk low power consumption control circuit as claimed in any one of claims 1 to 9.

Images