Power supply fault management method and system, server and readable storage medium

Abstract

The invention discloses a power supply fault management method and system, a server and a readable storage medium, relates to the field of servers, and aims to solve the problem of low fault cause positioning efficiency of a power supply fault, the power supply fault management system comprises at least one expansion chip, the expansion chip comprises a plurality of voltage monitoring pins, and the voltage monitoring pins are connected with the expansion chip. The voltage monitoring pin is connected with the fault indication pin; the processing component is used for responding to the condition that the received power supply good signal of any power supply chip is in a fault level state, and obtaining the voltage value of the voltage monitoring pin of the expansion chip corresponding to the power supply good signal; and the control assembly is used for positioning a power failure reason based on the voltage value, and the power failure reason is determined based on the error type. The method can quickly position the power supply fault reason, simplify the diagnosis process, improve the problem reason positioning capability, accelerate the later debugging efficiency, and improve the reliability and the operation and maintenance efficiency of the server.

Description

Technical Field

[0001] The present invention relates to the field of servers, and in particular to a power failure management method, system, server and readable storage medium. Background Art

[0002] During the operation of the server, the motherboard and other boards may encounter power failures, resulting in unexpected power outages. Currently, most servers use CPLD (complex programmable logic device) to monitor the PWRGD (power good) signal of the power chip to determine whether the power chip is faulty. However, the low level state of the PWRGD signal can only indicate that the power supply has no output. This monitoring method has great limitations and cannot accurately point out the specific cause of the power failure. In the subsequent troubleshooting (debugging) process, it is necessary to reproduce the problem phenomenon through multiple methods to determine the cause of the failure. This approach is inefficient.

[0003] Therefore, how to provide a solution to the above technical problems is a problem that those skilled in the art need to solve at present. Summary of the invention

[0004] The purpose of the present invention is to provide a power supply fault management method, system, server and readable storage medium, which can quickly locate the cause of the power supply fault, simplify the diagnosis process, improve the ability to locate the cause of the problem, speed up the efficiency of later debugging, and improve the reliability and operation and maintenance efficiency of the server.

[0005] In order to solve the above technical problems, the present invention provides a power supply fault management system, which is applied to a server, wherein the server further comprises at least one power supply chip, wherein the power supply chip has at least one fault indication pin for indicating an error type, and the power supply fault management system comprises:

[0006] at least one extension chip, the extension chip comprising a plurality of voltage monitoring pins, the voltage monitoring pins being connected to the fault indication pins;

[0007] a processing component, configured to, in response to a received power good signal of any of the power chips being in a fault level state, obtain a voltage value of a voltage monitoring pin of the expansion chip corresponding to the power good signal;

[0008] A control component is used to locate a cause of a power failure based on the voltage value, wherein the cause of the power failure is determined based on the error type.

[0009] Optionally, the processing component is specifically configured to obtain voltage values ​​of all voltage monitoring pins on the extension chip corresponding to the power good signal in response to the received power good signal being in a fault level state;

[0010] or,

[0011] The processing component is specifically used to determine the voltage value of the target monitoring pin on the extension chip corresponding to the power good signal in response to the received power good signal being in a fault level state; the target monitoring pin is the voltage monitoring pin on the extension chip corresponding to the power chip whose power good signal is in a fault level state.

[0012] Optionally, all fault indication pins on the power chip are connected to voltage monitoring pins on the same expansion chip in a one-to-one correspondence.

[0013] Optionally, the processing component is further used to establish a corresponding relationship between the address of the extension chip and the power chip;

[0014] The processing component is specifically used to respond to the power good signal of any of the power chips received being in a fault level state, determine the address of the expansion chip corresponding to the power chip whose power good signal is in a fault level state based on the corresponding relationship, and read the voltage value of the voltage monitoring pin according to the address.

[0015] Optionally, the processing component is also used to obtain the fault power supply name corresponding to the power good signal in the fault level state, transmit the fault power supply name and the voltage value to the control component, and control the power supply of the powered device corresponding to the power chip to be shut down, so that the server enters a shutdown state.

[0016] Optionally, the control component includes:

[0017] A processor, configured to store the voltage value and the faulty power supply name in a device abnormality record file;

[0018] The display is used to prompt the abnormal record file and the alarm information corresponding to the faulty power supply name, so as to determine and locate the cause of the power supply failure based on the abnormal record file.

[0019] Optionally, the process of locating the cause of the power failure based on the voltage value includes:

[0020] Reading configuration information of each of the power chips;

[0021] Determine an error type indication mode of a fault indication pin of each of the power supply chips based on the configuration information;

[0022] Determine at least one error type based on the voltage value of each of the fault indication pins, the preset voltage range of each of the fault indication pins, and the error type indication mode;

[0023] Associating at least one error type with a record in a fault cause database, wherein the error type and the association rule obtain at least one power supply fault cause;

[0024] Outputting at least one of the power failure reasons to a server management interface and / or triggering an alarm mechanism;

[0025] The error type indication mode includes at least one of a first indication mode, a second indication mode and a third indication mode. The first indication mode is that multiple fault indication pins correspond one-to-one to indicate multiple error types. The second indication mode is that a combination of multiple fault indication pins indicates one error type. The third indication mode includes multiple voltage values ​​of one fault indication pin corresponding one-to-one to indicate multiple error types.

[0026] To solve the above technical problems, the present invention further provides a server, comprising at least one power chip, wherein the power chip has at least one fault indication pin for indicating an error type, and a power fault management system as described in any one of the above.

[0027] To solve the above technical problems, the present invention further provides a power failure management method, which is applied to a server, wherein the server includes at least one power chip, and the power chip has at least one fault indication pin for indicating an error type. The power failure management method includes:

[0028] In response to a power good signal of any power chip received being in a fault level state, a processing component obtains a voltage value of a voltage monitoring pin of the extension chip corresponding to the power good signal; the extension chip includes a plurality of voltage monitoring pins, and the voltage monitoring pins are connected to a fault indication pin;

[0029] The control component locates a power failure cause based on the voltage value, wherein the power failure cause is determined based on the error type.

[0030] To solve the above technical problem, the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the power failure management method described above are implemented.

[0031] The present invention provides a power failure management system, which comprehensively monitors the fault indication pin of the power chip of the server through an extension chip, automatically monitors the cause of the power failure, obtains the voltage value of the voltage monitoring pin on the extension chip when power supply abnormality occurs, and determines the fault type indicated by the abnormal fault indication pin based on the voltage value, so as to quickly locate the cause of the power failure, simplify the diagnosis process, improve the problem cause location capability, speed up the later debugging efficiency, and improve the reliability and operation and maintenance efficiency of the server.

[0032] The present invention also provides a power failure management method, a server and a computer-readable storage medium, which have the same beneficial effects as the above-mentioned power failure management system. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 A schematic diagram of the structure of a power failure management system provided by the present invention;

[0035] Figure 2 A processing flow chart of a processing component provided by the present invention;

[0036] Figure 3 A flow chart of the steps of a power failure management method provided by the present invention. DETAILED DESCRIPTION

[0037] The core of the present invention is to provide a power supply fault management method, system, server and readable storage medium, which can quickly locate the cause of the power supply fault, simplify the diagnosis process, improve the ability to locate the cause of the problem, speed up the efficiency of later debugging, and improve the reliability and operation and maintenance efficiency of the server.

[0038] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] In a first aspect, the present invention provides a power supply fault management system, which is applied to a server. The server further includes at least one power supply chip 0, and the power supply chip 0 has at least one fault indication pin for indicating an error type. The power supply fault management system includes:

[0040] At least one extension chip 1, the extension chip 1 comprises a plurality of voltage monitoring pins, and the voltage monitoring pins are connected to the fault indication pins;

[0041] Processing component 2, for obtaining a voltage value of a voltage monitoring pin of expansion chip 1 corresponding to the power good signal in response to a power good signal of any power chip 0 being received in a fault level state;

[0042] The control component 3 is used to locate the cause of the power failure based on the voltage value, and the cause of the power failure is determined based on the error type.

[0043] In this embodiment, each power chip 0 selects a power chip 0 having at least one fault indication pin, and the fault indication pin is used to send a signal when a fault corresponding to a certain error type occurs in the power supply. The extension chip 1 can select an ADC extension chip, and the extension chip 1 includes multiple voltage monitoring pins, which are connected to the fault indication pins of the power chip 0. Specifically, the fault indication pins of all N (N is a positive integer greater than 1) power chips 0 on the board are respectively connected to M ADC extension chips, where M is a positive integer greater than 1, and is determined by the number of fault cause indication pins of the power chip 0 actually selected. Generally speaking, an ADC extension chip that supports 8 voltage monitoring pins can be connected to 2-4 power chips 0. It can be understood that by connecting the fault indication pin of the power chip 0 to multiple ADC extension chips, the state of each power chip 0 can be accurately monitored, thereby improving the accuracy of fault detection.

[0044] Processing component 2 may select CPLD, which can quickly respond to changes in the power good signal and trigger the acquisition of the voltage value in time, thereby shortening the fault response time. Processing component 2 is used to process the power good signal PWRGD, and when the signal is in a fault level state, such as when the PWRGD signal is low, it indicates that the power supply may have a fault, triggering the acquisition of the voltage value of the voltage monitoring pin on the expansion chip 1 connected to the power chip 0 with the PWRGD signal at a low level, including but not limited to triggering the ADC expansion chip to start converting the voltage value of the voltage monitoring pin corresponding to the power good signal. After the ADC expansion chip completes the conversion, the CPLD reads the converted digital voltage value. Control component 3 may select BMC, and control component 3 determines the fault indication pin with abnormality based on the voltage value on each voltage monitoring pin, and determines the cause of the power fault based on the error type indicated by the fault indication pin. Due to the programmability of CPLD and BMC, system maintenance and upgrade become easier, and can quickly adapt to new fault detection requirements or changes in the power chip 0.

[0045] The interface between the CPLD and the ADC expansion chip may use parallel or serial communication, such as SPI or I2C, and the communication between the BMC and the CPLD may be carried out through the system bus and / or a dedicated interface. The system design supports multiple communication interfaces (such as SPI or I2C), so that the system can be compatible with different types of power chip 0 and expansion chip 1, and it is also convenient for future system expansion.

[0046] It can be seen that in this embodiment, the fault indication pin of the power chip 0 of the server is fully monitored by the extension chip 1, and the cause of the power failure is automatically monitored. When a power supply abnormality occurs, the voltage value of the voltage monitoring pin on the extension chip 1 is obtained, and the fault type indicated by the abnormal fault indication pin is determined based on the voltage value. The cause of the power failure can be quickly located, the diagnosis process is simplified, the ability to locate the cause of the problem is improved, the efficiency of later debugging is accelerated, and the reliability and operation and maintenance efficiency of the server are improved.

[0047] The power failure management system is based on the above embodiment:

[0048] In an exemplary embodiment, the processing component 2 is specifically configured to obtain voltage values ​​of all voltage monitoring pins on the expansion chip 1 corresponding to the power good signal in response to the received power good signal being in a fault level state.

[0049] In this embodiment, the power good signal is monitored: the CPLD continuously monitors the power good signal (PWRGD) sent by the power chip 0. When the CPLD detects that the power good signal is in a fault level state (for example, the signal is low), the CPLD responds to the fault level state, starts the ADC expansion chip, obtains the voltage values ​​of all voltage monitoring pins on the expansion chip 1, and after the ADC expansion chip completes the conversion of the voltage value, the CPLD reads these digital voltage values ​​and transmits the data to the control component 3 (BMC) for further processing. This method ensures that when there is a problem with the power supply, the system can obtain the voltage values ​​of all relevant voltage monitoring pins, so as to conduct a comprehensive analysis. Since all voltage values ​​are obtained, the control component 3 can more easily compare and diagnose to find the fault point. In an exemplary embodiment, the processing component 2 is specifically used to determine the voltage value of the target monitoring pin on the expansion chip 1 corresponding to the power good signal in response to the received power good signal being in a fault level state; the target monitoring pin is the voltage monitoring pin on the expansion chip 1 corresponding to the power chip 0 whose power good signal is in a fault level state.

[0050] In this embodiment, similar to the previous embodiment, the CPLD monitors the power good signal. When the power good signal is in a fault level state, the CPLD identifies the specific power chip 0. The CPLD determines the corresponding target monitoring pins based on the faulty power chip 0, and these pins are located on the ADC expansion chip. The CPLD only triggers the ADC expansion chip to convert the voltage value of the target monitoring pin. After the ADC expansion chip completes the conversion, the CPLD reads the digital voltage value of the target monitoring pin and transmits it to the BMC. The solution of this embodiment directly targets the faulty power chip 0, and only obtains the voltage value of the voltage monitoring pin related to it, reducing unnecessary data processing. Since only specific monitoring pins are focused on, faults can be located more quickly, improving the efficiency of fault handling.

[0051] In an exemplary embodiment, all fault indication pins on the power chip 0 are connected to the voltage monitoring pins on the same extension chip 1 in a one-to-one correspondence.

[0052] In this embodiment, when the fault cause indication pin is connected to the ADC expansion chip, all fault cause indication pins of the same power chip 0 are connected to the same ADC expansion chip. Since each fault indication pin has a unique corresponding voltage monitoring pin, when the power chip 0 reports a fault, the specific fault indication pin can be quickly located, so as to quickly determine the fault type. The one-to-one connection reduces the possibility of misdiagnosis caused by pin multiplexing or sharing, and the state of each fault indication pin can be independently monitored and analyzed. By connecting all fault indication pins to the same ADC expansion chip, all potential fault causes of the power chip 0 can be centrally monitored, which is convenient for unified management and analysis. Using a single ADC expansion chip to monitor all fault indication pins of a power chip 0 can reduce the number of ADC interfaces required by the system, thereby reducing the complexity and cost of the system. Since the information of all fault indication pins is processed by the same ADC expansion chip, the control component 3 (such as BMC) can obtain and analyze data faster, improve the efficiency of fault diagnosis, and when a fault occurs, since all relevant signals pass through the same ADC expansion chip, technicians can more easily track and analyze the cause of the fault.

[0053] In an exemplary embodiment, the processing component 2 is also used to establish a corresponding relationship between the address of the extension chip 1 and the power chip 0;

[0054] The processing component 2 is specifically used to respond to the power good signal of any power chip 0 received being in a fault level state, determine the address of the expansion chip 1 corresponding to the power chip 0 whose power good signal is in a fault level state based on the corresponding relationship, and read the voltage value of the voltage monitoring pin according to the address.

[0055] In this embodiment, each ADC expansion chip has 3 address bits, allowing 8 different I2C address settings. When the system is initialized, a unique address is assigned to each ADC expansion chip, and a corresponding relationship between the power chip 0 and the ADC expansion chip address is established. The corresponding relationship can be stored in the memory of the processing component 2, or configured through the system BIOS / firmware. When the processing component 2 detects that the power good signal is in a fault level state, the ADC expansion chip address corresponding to the faulty power chip 0 will be determined according to the preset corresponding relationship. The processing component 2 sends a read command to the ADC expansion chip according to the determined address to obtain the voltage value of the corresponding voltage monitoring pin. Of course, if more power chips 0 need to be monitored, an ADC expansion chip with more address settings and voltage monitoring pins can be selected.

[0056] Through address mapping, the processing component 2 can quickly determine which ADC expansion chip needs to be read, simplifying the data acquisition process. It can be understood that because communication protocols such as I2C support multiple devices sharing the same bus, the need for additional hardware can be reduced through address setting, and the address of the ADC expansion chip can be flexibly set and adjusted according to the number and layout of the power chip 0 on the board. By adopting the solution of this embodiment, the power failure management system can effectively monitor the status of a large number of power chips 0, and quickly locate and read the relevant voltage value when a fault occurs, so as to quickly diagnose and solve the problem.

[0057] In an exemplary embodiment, the processing component 2 is also used to obtain the fault power supply name corresponding to the power good signal in the fault level state, transmit the fault power supply name and voltage value to the control component 3, and control the power supply of the powered device corresponding to the power chip 0 to shut down, so that the server enters the shutdown state.

[0058] In this embodiment, when the power good signal (PWRGD) of the power chip 0 is in a fault level state, the processing component 2 identifies a power failure, and the processing component 2 determines the fault power supply name, such as "3V3 failure", according to the power chip 0 corresponding to the power good signal in the fault level state. The processing component 2 transmits the fault power supply name and voltage value to the control component 3 (BMC), and shuts down the power supply of the powered device corresponding to the faulty power chip 0, so that the server enters the shutdown state. Among them, the fault power supply name provides a clear fault indication, so that the technician can quickly understand the nature of the fault. By automatically shutting down the affected power supply, the power supply fault can be responded to quickly to prevent the fault from spreading or damaging the hardware. In the event of a power failure, safe shutdown can protect the internal data of the server from damage.

[0059] Combined with the above, the processing flow of processing component 2 refers to Figure 2 shown.

[0060] In an exemplary embodiment, the control component 3 includes:

[0061] A processor, used for storing the voltage value and the name of the faulty power supply into a device abnormality record file;

[0062] The display is used to prompt the abnormal record file and the alarm information corresponding to the faulty power supply name, so as to determine and locate the cause of the power supply failure based on the abnormal record file.

[0063] In this embodiment, the processor is responsible for storing the acquired voltage value and faulty power supply name in the device abnormality record file. These data are usually stored in non-volatile memory (NVRAM) to ensure that the data will not be lost after the system is restarted. The display is used to display the contents of the abnormality record file, so that the technician can intuitively view the fault information and perform fault analysis and location. The display can also prompt the alarm information corresponding to the faulty power supply name so that the technician can quickly understand the nature and severity of the fault. Through the cooperation of the processor and the display, the power supply fault management system can provide a comprehensive and intuitive fault management solution to help technicians quickly locate and solve power supply faults, thereby ensuring the stable operation of the server.

[0064] In an exemplary embodiment, the process of locating the cause of a power failure based on a voltage value includes:

[0065] Read the configuration information of each power chip 0;

[0066] Determine an error type indication mode of a fault indication pin of each power chip 0 based on the configuration information;

[0067] determining at least one error type based on a voltage value of each fault indication pin, a preset voltage range of each fault indication pin, and an error type indication mode;

[0068] Associating at least one error type with a record in a fault cause database, and obtaining at least one power supply fault cause based on the error type and the association rule;

[0069] Outputting at least one power failure reason to a server management interface and / or triggering an alarm mechanism;

[0070] The error type indication mode includes at least one of a first indication mode, a second indication mode and a third indication mode. The first indication mode is that multiple fault indication pins indicate multiple error types in a one-to-one correspondence. The second indication mode is that a combination of multiple fault indication pins indicates one error type. The third indication mode includes multiple voltage values ​​of a fault indication pin indicating multiple error types in a one-to-one correspondence.

[0071] In this embodiment, during the system startup or configuration phase, the control component 3 will first read the configuration information of the power chip 0 to determine which error type indication mode is adopted by the fault indication pin of each power chip 0. The control component 3 may identify the error type indication mode in the following ways: hardware configuration: determining the indication mode by reading the hardware configuration register on the power chip 0; software configuration: determining the indication mode by setting the system firmware or software; automatic detection: the control component 3 can automatically detect the response mode of the power chip 0 to infer the error type indication mode.

[0072] When the power supply ready signal indicates a fault, the control component 3 immediately reads the voltage value of the voltage monitoring pin connected to the fault indication pin. Error type mapping is performed according to the voltage value, and three indication modes are described. The first indication mode: each fault indication pin directly corresponds to an error type. For example, the voltage change of pin 1 may indicate "overvoltage", while the voltage change of pin 2 may indicate "undervoltage". The second indication mode: the combined voltage value of multiple fault indication pins indicates an error type. For example, pin 1 and pin 2 are high at the same time, which may indicate "power module failure". The third indication mode: different voltage values ​​of a single fault indication pin indicate different error types. For example, 0V of pin 1 may indicate "no fault", 1V may indicate "overtemperature", and 2V may indicate "short circuit". The determined error type is associated with the record in the fault cause database, and the specific power supply fault cause is inferred according to the error type and association rules. The fault cause, error type, occurrence time and other information are output to the management interface of the server, or the fault information is recorded in the system log for subsequent analysis and audit, or the alarm mechanism is triggered to notify the management personnel through email, SMS or system notification.

[0073] It is understandable that the preset voltage range of the fault indication pin can be adjusted according to different power chip 0 and system requirements. Further, to prevent power supply noise interference, the fault indication pin may be electrically isolated by an optical coupler or a magnetic coupler, and to prevent false triggering, the signal of the fault indication pin may be de-jittered. The control component 3 may also include a fault recovery process, such as automatically trying to restart the power module or switching to a backup power supply.

[0074] As another optional embodiment, the control component 3 sets the priority of the fault response to ensure that the most serious fault type can be handled first. Specifically, the control component 3 divides the fault type into multiple levels, such as serious, medium, and minor, according to the records in the fault cause database. Each level represents the urgency and impact range of the fault. When multiple faults are detected to occur at the same time, the control component 3 evaluates the priority of each fault. The evaluation may be based on factors such as the fault type, the fault impact range, and the frequency of the fault. The control component 3 prioritizes the faults according to the evaluation results and determines the order of fault handling. Faults with high priority will be handled first to reduce the impact of the fault. The control component 3 controls the power supply of the power chip 0 according to the fault response priority and shuts down the affected power supply to prevent the fault from spreading or damaging the hardware. At the same time, the alarm mechanism can also be triggered to notify the technician of the occurrence and handling of the fault. By setting the priority of the fault response, the power fault management system can ensure that the most urgent and serious faults can be handled in a timely manner in the case of multiple faults, thereby reducing the impact and loss caused by the fault and ensuring the stable operation of the server and other key equipment.

[0075] In a second aspect, the present invention further provides a server, comprising at least one power chip, the power chip having at least one fault indication pin for indicating an error type, and a power fault management system as described in any one of the above.

[0076] In a third aspect, the present invention further provides a power failure management method, which is applied to a server, wherein the server includes at least one power chip, and the power chip has at least one fault indication pin for indicating an error type. The power failure management method includes:

[0077] In response to a power good signal of any power chip received being in a fault level state, the processing component obtains a voltage value of a voltage monitoring pin of an extension chip corresponding to the power good signal; the extension chip includes a plurality of voltage monitoring pins, and the voltage monitoring pins are connected to the fault indication pin;

[0078] The cause of the power failure is located by the control component based on the voltage value, and the cause of the power failure is determined based on the error type.

[0079] Reference Figure 3 , Figure 3 A flow chart of a power failure management method is shown.

[0080] In a fourth aspect, the present invention further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the power failure management method as described above are implemented.

[0081] For an introduction to a computer-readable storage medium provided by the present invention, please refer to the above embodiments, and the present invention will not be described in detail here.

[0082] A computer-readable storage medium provided by the present invention has the same beneficial effects as the above power failure management method.

[0083] In a fifth aspect, the present invention further provides a computer program product, comprising a computer program / instruction, which, when executed by a processor, implements the steps of the power management method for a server as described in any one of the above items.

[0084] For an introduction to a computer program product provided by the present invention, please refer to the above embodiments, and the present invention will not be described in detail here.

[0085] A computer program product provided by the present invention has the same beneficial effects as the above power failure management method.

[0086] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0087] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A power failure management system, characterized in that: Applied to a server, the server further includes at least one power chip, the power chip has at least one fault indication pin for indicating an error type, and the power fault management system includes: at least one extension chip, the extension chip comprising a plurality of voltage monitoring pins, the voltage monitoring pins being connected to the fault indication pins; a processing component, configured to, in response to a received power good signal of any of the power chips being in a fault level state, obtain a voltage value of a voltage monitoring pin of the expansion chip corresponding to the power good signal; A control component is used to locate a cause of a power failure based on the voltage value, wherein the cause of the power failure is determined based on the error type.

2. The power failure management system according to claim 1, characterized in that: The processing component is specifically used for obtaining voltage values ​​of all voltage monitoring pins on the extension chip corresponding to the power good signal in response to the received power good signal being in a fault level state; or, The processing component is specifically configured to determine, in response to the received power good signal being in a fault level state, a voltage value of a target monitoring pin on the extension chip corresponding to the power good signal; The target monitoring pin is a voltage monitoring pin on the expansion chip corresponding to the power chip whose power good signal is in a fault level state.

3. The power failure management system according to claim 1, characterized in that: All fault indication pins on the power chip are connected to the voltage monitoring pins on the same expansion chip in a one-to-one correspondence.

4. The power failure management system according to claim 1, characterized in that: The processing component is also used to establish a corresponding relationship between the address of the expansion chip and the power chip; The processing component is specifically used to respond to the power good signal of any of the power chips received being in a fault level state, determine the address of the expansion chip corresponding to the power chip whose power good signal is in a fault level state based on the corresponding relationship, and read the voltage value of the voltage monitoring pin according to the address.

5. The power failure management system according to claim 1, characterized in that: The processing component is also used to obtain the fault power supply name corresponding to the power good signal in the fault level state, transmit the fault power supply name and the voltage value to the control component, and control the power supply of the powered device corresponding to the power chip to shut down, so that the server enters the shutdown state.

6. The power failure management system according to claim 5, characterized in that: The control component comprises: A processor, configured to store the voltage value and the faulty power supply name in a device abnormality record file; The display is used to prompt the abnormal record file and the alarm information corresponding to the faulty power supply name, so as to determine and locate the cause of the power supply failure based on the abnormal record file.

7. The power failure management system according to any one of claims 1 to 6, characterized in that: The process of locating the cause of the power failure based on the voltage value includes: Reading configuration information of each of the power chips; Determine an error type indication mode of a fault indication pin of each of the power supply chips based on the configuration information; Determine at least one error type based on the voltage value of each of the fault indication pins, the preset voltage range of each of the fault indication pins, and the error type indication mode; Associating at least one error type with a record in a fault cause database, wherein the error type and the association rule obtain at least one power supply fault cause; Outputting at least one of the power failure reasons to a server management interface and / or triggering an alarm mechanism; The error type indication mode includes at least one of a first indication mode, a second indication mode and a third indication mode. The first indication mode is that multiple fault indication pins correspond one-to-one to indicate multiple error types. The second indication mode is that a combination of multiple fault indication pins indicates one error type. The third indication mode includes multiple voltage values ​​of one fault indication pin corresponding one-to-one to indicate multiple error types.

8. A server, characterized in that: The invention comprises at least one power supply chip having at least one fault indication pin for indicating an error type, and a power supply fault management system as claimed in any one of claims 1 to 7.

9. A power failure management method, characterized in that: Applied to a server, the server includes at least one power chip, the power chip has at least one fault indication pin for indicating an error type, and the power fault management method includes: In response to a power good signal of any power chip received being in a fault level state, a processing component obtains a voltage value of a voltage monitoring pin of the extension chip corresponding to the power good signal; the extension chip includes a plurality of voltage monitoring pins, and the voltage monitoring pins are connected to a fault indication pin; The control component locates a power failure cause based on the voltage value, wherein the power failure cause is determined based on the error type.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the power failure management method according to claim 9 are implemented.

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