Chip pin multiplexing system, SOC chip and method

Abstract

The invention relates to a chip pin multiplexing system, an SOC chip and a method, a PINMUX component is designed and a PINMUX mode pin is added, so that when the chip is started, the value of the PINMUX mode pin is automatically locked in a pin mode register, hardware reads the value in the pin mode register to determine the configuration mode of the PINMUX register, and the configuration mode of pin multiplexing can be flexibly selected. Meanwhile, the pin multiplexing configuration of each component is combined with the gated clock of the component, the hardware automatically configures the pin multiplexing configuration register of the corresponding component while the gated clock of the component is switched on and off, the pin multiplexing configuration process can be saved in a hardware configuration mode, and the hardware configuration efficiency is improved. The technical problems that multiplexing pin configuration is complex and manual configuration is wrong are solved from the hardware level, errors and the like caused by hot switching of components in the using process are avoided, the post-silicon testing efficiency is improved, and the chip pin multiplexing use efficiency is greatly improved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit design, and relates to a chip pin multiplexing system, a SOC chip and a method. Background Art

[0002] With the advancement of process technology, while the performance of SOC (System on Chip) continues to improve, the circuit area continues to shrink, which limits the number of chip pins. Therefore, in the case of limited number of full chip pins and package size, in order to allow as many components as possible in the chip to have channels for interaction with the outside of the chip, in complex on-chip system designs, multiplexers are often used to multiplex signals on chip pins to optimize resource usage to adapt to different operating scenarios and improve chip resource utilization through flexible resource allocation.

[0003] Clock gating technology is a common low-power control technology and is very common in digital circuit design. It is one of the most successful and widely used methods to reduce power consumption by shutting down the clock of the idle or non-useful parts of the design through clock gating. The goal of clock gating technology is to shut down the temporarily unused chip parts (such as triggers, clock networks, and logic gates, etc.) through clock gating circuits under certain conditions. The power consumption saved is mainly the reduction of switch capacitance and the reduction of switching coefficient. The reason is that when the clock frequency is idle, some non-essential transistors will be turned off.

[0004] At present, some traditional technologies related to pin multiplexing have also emerged, such as object-oriented chip-level port interconnection circuits and port interconnection methods, and customized integrated circuits that contain one or more sets of hard-wired connections and allow communication between any input / output (I / O) pins and on-board peripheral devices. Or for example, a chip pin multiplexing communication method and a chip using the same, a pin multiplexing circuit automatic generation method based on a scripting language, and a chip pin function multiplexing circuit generation method. However, the above traditional technologies still have the technical problem of low pin multiplexing efficiency. Summary of the invention

[0005] In view of the problems existing in the above-mentioned traditional technologies, the present invention proposes a chip pin multiplexing system, a SOC chip and a chip pin multiplexing method, which can greatly improve the efficiency of chip pin multiplexing.

[0006] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a chip pin multiplexing system is provided, comprising a PINMUX register module and a pin control module, wherein the PINMUX register module is used to connect an internal host and a clock gating of a chip respectively, and to output a valid value to the pin control module, and the pin control module is used to connect a PAD of the chip and a component that interacts with the outside via the chip pin multiplexing system; When the chip is started, the value of the PINMUX mode pin of the PINMUX register module is automatically locked in the pin mode register; the value in the pin mode register is used to determine the configuration mode of the PINMUX register module after being read by the hardware, and the configuration mode includes a software configuration mode and a hardware configuration mode; In software configuration mode, the valid values ​​output by the PINMUX register module select the values ​​configured by the internal host through software. In hardware configuration mode, the valid values ​​output by all PINMUX registers in the PINMUX register module automatically select the pre-configured values ​​of the PINMUX registers corresponding to the target component based on the clock gating enable of the target component; The pin control module adopts a one-hot encoding method to control the pin behavior of the chip's PAD and the components that interact with the outside through the chip pin multiplexing system according to the effective value output by the PINMUX register module; the pin control module is provided with an input isolation signal, which is used to ensure that the data and control signals input by the components that are not currently configured with the PINMUX register selection are in an invalid state.

[0007] On the other hand, a SOC chip is also provided, including an internal host, clock gating, PAD and the above-mentioned chip pin multiplexing system.

[0008] On the other hand, a chip pin multiplexing method is provided, which is applied to a chip pin multiplexing system, wherein the chip pin multiplexing system includes a PINMUX register module and a pin control module, wherein the PINMUX register module is used to connect the internal host and clock gating of the chip respectively, and to output a valid value to the pin control module, and the pin control module is used to connect the PAD of the chip and a component that interacts with the outside via the chip pin multiplexing system; When the chip is started, the value of the PINMUX mode pin of the PINMUX register module is automatically locked in the pin mode register; the value in the pin mode register is used to determine the configuration mode of the PINMUX register module after being read by the hardware, and the configuration mode includes a software configuration mode and a hardware configuration mode; In software configuration mode, the valid values ​​output by the PINMUX register module select the values ​​configured by the internal host through software. In hardware configuration mode, the valid values ​​output by all PINMUX registers in the PINMUX register module automatically select the pre-configured values ​​of the PINMUX registers corresponding to the target component based on the clock gating enable of the target component; The pin control module uses a one-hot encoding method to control the pin behavior of the chip's PAD and the components that interact with the outside through the chip pin multiplexing system according to the effective value output by the PINMUX register module; the pin control module is provided with an input isolation signal, which is used to ensure that the data and control signals input by the components that are not currently configured with the PINMUX register selection are in an invalid state; The chip pin multiplexing method comprises the steps of: Determine the configuration mode of the PINMUX register in the PINMUX register module; When the current PINMUX register is in software configuration mode, the PINMUX register is read and written through the internal host of the chip to route the signal corresponding to the target component to the corresponding pin.

[0009] One of the above technical solutions has the following advantages and beneficial effects: The chip pin multiplexing system, SOC chip and method are designed to add a PINMUX mode pin by designing a PINMUX component consisting of a PINMUX register module and a pin control module, so that the value of the PINMUX mode pin is automatically locked in the PINMODE register when the chip is started, and the hardware reads the value in the PINMODE register to determine the configuration mode of the PINMUX register, so that the configuration mode of the pin multiplexing can be flexibly selected. At the same time, the pin multiplexing configuration of each component is combined with the gated clock of the component. When the gated clock of the switch component is switched, the hardware automatically configures the pin multiplexing configuration register of the corresponding component. In the hardware configuration mode, the multiplexing pin configuration process can be saved, and the technical problems of complex multiplexing pin configuration and manual configuration errors can be solved from the hardware level, avoiding errors caused by hot switching of components during use, etc., improving the efficiency of post-silicon testing, and combining with clock gating technology can also effectively optimize power consumption and reduce unnecessary signal flips. In addition, for each multiplexed pin, an input isolation signal is added to the pin control module based on the valid state of the multiplexed signal, so as to ensure that the input data and control signals are in an invalid state when the PINMUX register is not configured, thereby avoiding functional abnormalities caused by external inputs from the hardware level and greatly improving the efficiency of chip pin multiplexing. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0011] Figure 1 A schematic diagram of the overall structure of a chip pin multiplexing system in one embodiment; Figure 2 Schematic diagram of the implementation structure of a PINMUX register module in one embodiment; Figure 3 A schematic diagram of input and output signals of a single pin control module in one embodiment; Figure 4 A schematic diagram of the use process of a chip pin multiplexing system in one embodiment; Figure 5 The figure is a schematic diagram of the software configuration mode workflow of a chip pin multiplexing method in one embodiment. DETAILED DESCRIPTION

[0012] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0013] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification of the present invention and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0014] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0015] In complex system-on-chip designs, multiplexers are used to multiplex signals on chip pins. When using the target component, the corresponding pin multiplexing selection (PINMUX) register needs to be configured through software to select the pin multiplexing as the signal of the target component. In large-scale system-on-chip designs, the multiplexing situation is often more complicated, which will lead to complex pin multiplexing configuration and only support software configuration but not hardware control. If the pin multiplexing configuration is wrong, the target component will not work properly, and the resulting abnormalities will be difficult to troubleshoot. When performing post-silicon testing on components with complex multiplexing situations, configuration or use errors are often caused by human factors, which in turn leads to slow chip debugging progress and affects the project development cycle.

[0016] However, in the object-oriented chip-level port interconnection circuit and its port interconnection method, the pin multiplexing configuration mode is fixed and does not support automatic configuration. If the connection path between the PAD module in the control circuit and each IP (Intellectual Property Core) core is to be controlled, the IOCTRL control unit of the PINMUX unit needs to be configured through the CPU, and there is a cumbersome configuration process. This method is actually a widely applicable pin multiplexing design method, which is used to quickly and high-quality complete the interconnection requirements between various IP core ports in the chip development process, but does not consider the realization of automatic configuration of the connection path between the PAD module and each IP core in the logic design to reduce the cumbersome configuration process. However, traditional technologies such as custom integrated circuits that contain one or more sets of hard-wired connections and allow communication between any input / output (I / O) pins and on-board peripheral devices, chip pin multiplexing communication methods, and chips using the same, do not involve pin multiplexing configuration methods. The focus is on solving various problems caused by pin multiplexing, such as the limited use of various peripheral combinations caused by pin multiplexing conflicts and the problem that the existing pins of the chip cannot be directly reused due to the limitations of the chip's pin working environment and chip performance requirements, and do not consider pin multiplexing configuration methods. Traditional technologies such as the automatic generation method of pin multiplexing circuits based on scripting languages ​​and the chip pin function multiplexing circuit generation method require manual configuration of pin multiplexing according to the pin function correspondence, and cannot realize the automatic configuration of the pin multiplexing control module, thus failing to take into account the convenience of the pin multiplexing configuration process.

[0017] In one embodiment, Figure 1As shown, a chip pin multiplexing system is provided, including a PINMUX register module and a pin control module. The PINMUX register module is used to connect the internal host and clock gating of the chip respectively, and to output a valid value to the pin control module. The pin control module is used to connect the PAD of the chip and the components that interact with the outside via the chip pin multiplexing system. When the chip is started, the value of the PINMUX mode pin of the PINMUX register module is automatically locked in the pin mode register; the value in the pin mode register is used to determine the configuration mode of the PINMUX register module after being read by the hardware, and the configuration mode includes a software configuration mode and a hardware configuration mode.

[0018] In software configuration mode, the valid value output by the PINMUX register module selects the value configured by the internal host through software. In hardware configuration mode, the valid value output by all PINMUX registers in the PINMUX register module is based on the clock gating enable of the target component to automatically select the pre-configured value of the PINMUX register corresponding to the target component. The pin control module uses a one-hot encoding method to control the pin behavior of the chip's PAD and the components that interact with the outside through the chip pin multiplexing system according to the valid value output by the PINMUX register module. The pin control module is provided with an input isolation signal, which is used to ensure that the data and control signals input by the component that is not currently configured with the PINMUX register gating are in an invalid state.

[0019] It can be understood that this embodiment proposes a chip pin multiplexing design scheme that supports flexible configuration (hereinafter referred to as PINMUX component). Pin multiplexing supports software configuration mode or hardware configuration mode. In software configuration mode, the multiplexing of each pin can be flexibly configured through software; in hardware configuration mode, by combining clock gating technology with pin multiplexing, the pin multiplexing system can support hardware configuration mode. By enabling clock gating, the hardware automatically completes the pin multiplexing configuration, eliminating the complex pin multiplexing configuration process in traditional technology, and solving the technical problems of complex pin multiplexing configuration and configuration or use errors caused by human factors at the hardware level, avoiding errors caused by hot switching of components during use, etc., improving the efficiency of post-silicon testing, and combining with clock gating technology can effectively optimize system power consumption.

[0020] Specifically, the designed PINMUX component consists of two parts: the PINMUX register module and the pin control module. The overall structure is as follows: Figure 1As shown, the PINMUX component serves as an intermediate component for communication between the chip and the outside. It connects all components that interact with the outside via the PINMUX internally, and interacts with external devices externally through PAD (such as PAD0 to PADn, n is the total number of pins). Among them, PAD refers to the pin on the silicon wafer, which is packaged inside the chip. The PAD type is determined by the wafer process. There can be multiple pin control modules, such as pin control 0 to pin control n.

[0021] The above chip pin multiplexing system adds a PINMUX mode pin by designing a PINMUX component consisting of a PINMUX register module and a pin control module, so that the value of the PINMUX mode pin is automatically locked in the PINMODE register when the chip is started, and the hardware reads the value in the PINMODE register to determine the configuration mode of the PINMUX register, so that the configuration mode of the pin multiplexing can be flexibly selected. At the same time, the pin multiplexing configuration of each component is combined with the gated clock of the component. When the gated clock of the switch component is switched, the hardware automatically configures the pin multiplexing configuration register of the corresponding component. In the hardware configuration mode, the multiplexing pin configuration process can be saved, and the technical problems of complex multiplexing pin configuration and manual configuration errors can be solved from the hardware level, avoiding errors caused by hot switching of components during use, etc., improving the efficiency of post-silicon testing, and combining with clock gating technology can also effectively optimize power consumption and reduce unnecessary signal flips. In addition, for each multiplexed pin, an input isolation signal is added to the pin control module based on the valid state of the multiplexed signal, so as to ensure that the input data and control signals are in an invalid state when the PINMUX register is not configured, thereby avoiding functional abnormalities caused by external inputs from the hardware level and greatly improving the efficiency of chip pin multiplexing.

[0022] In one embodiment, Figure 2 As shown, the PINMUX register module includes a pin mode register (i.e., PINMODE register), a PINMUX register corresponding to the software configuration mode (which can be recorded as RG1), a PINMUX register corresponding to the hardware configuration mode (which can be recorded as RG2), and an output register (which can be recorded as RG3). The input end of the pin mode register is connected to the PINMUX mode pin, the output end of the pin mode register is connected to the control end of the output register, and the PINMUX register corresponding to the software configuration mode stores the value configured by the internal host through software and is connected to the first input channel of the output register.

[0023] The PINMUX register corresponding to the hardware configuration mode is used to store the PINMUX register pre-configuration value corresponding to the target component and is connected to the second input channel of the output register. The output end of the output register is connected to the pin control module. When the value in the pin mode register corresponds to the software configuration mode, the output end of the output register is connected to the first input channel. When the value in the pin mode register corresponds to the hardware configuration mode, the output end of the output register is connected to the second input channel.

[0024] It can be understood that the PINMUX register module is used to implement the selection of the PINMUX configuration mode, process register read and write requests from an internal host (such as a CPU or other processor), and the PINMUX register effective value output control logic.

[0025] The implementation structure of the PINMUX register module can be as follows Figure 2 The configuration mode of the PINMUX register module is selected by the PINMUX mode pin (external pin of the chip). When the chip starts, the value of the PINMUX mode pin is automatically locked in the PINMODE (pin mode) register. The hardware reads the value in the PINMODE register to determine the configuration mode of the PINMUX register module. The setting description of the PINMODE register can be shown in Table 1 below: Table 1

[0026] In Table 1, the domain control R represents read-only.

[0027] The PINMUX register module supports read and write requests from internal hosts such as the CPU. The value of the PINMUX register can be arbitrarily configured by the CPU, such as Figure 2 The CPU reads and writes the PINMUX register, and the PINMUX register here is called the PINMUX register RG1 corresponding to the software configuration mode. The effective value output by the PINMUX register module is controlled by the value of the read PINMODE register. If the value read from the PINMODE register is a high level (i.e., level 1), the software configuration mode is selected. In this mode, the effective value output by all PINMUX register modules selects the value configured by the software (i.e., the PINMUX register value configured by the CPU).

[0028] If the value read from the PINMODE register is low (i.e., level 0), the hardware configuration mode is selected. In this mode, the hardware pre-configures the PINMUX registers in units of components. All PINMUX registers automatically select the PINMUX register pre-configured value corresponding to the target component based on the clock gating enable of each target component (i.e., each functional component that currently needs to use pin multiplexing). The clock gating enable of each target component comes from the module-level clock gating controller, which is used to control the shutdown and enable of the gated clock transmitted to each target component. For example, when the clock gating enable of component A is turned on, the value of the PINMUX register used by component A is rewritten to the PINMUX register pre-configured value corresponding to component A at the same time. At this time, these PINMUX registers used are called the PINMUX register RG2 corresponding to the hardware configuration mode.

[0029] In one embodiment, optionally, the configuration mode of the PINMUX register corresponding to the value read from the PINMODE register may be opposite to the above-mentioned implementation mode. For example, if the value read from the PINMODE register is a high level, the hardware configuration mode is selected; if the value read from the PINMODE register is a low level, the software configuration mode is selected, as long as it can be used to achieve the above-mentioned required control effect.

[0030] In one embodiment, the pin control module includes a plurality of pin control modules, each of which includes: The judgment signal comes from the PINMUX register module and is used to control the function of multiplexing pin selection; The pad_c signal comes from PAD and indicates the data received from the pin inside the chip; Input isolation signal, access fixed value according to signal polarity, used to ensure that the data and control signals input by the components that are not currently configured with PINMUX register selection are in invalid state; The signal_ren signal comes from the PINMUX register module and is used to enable the pull-up and pull-down resistors of the corresponding PAD of the switch multiplexing pin; The signal_x_en signal comes from all components that interact with the outside world through the chip pin multiplexing system and is used to indicate the signal transmission direction of each component; The signal_x_u2p signal comes from all components that interact with the outside world through the chip pin multiplexing system and is used to indicate the data that each component needs to send to the pin; x is a positive integer; pad_i signal is the signal output to PAD, indicating the data that the target component needs to send to the pin; The pad_ren signal is a signal output to the PAD, indicating that the pull-up and pull-down resistors of the switch multiplexing pin corresponding to the PAD are enabled; The signal_x_p2u signal represents the data input to all components that interact with the outside world via the chip pin multiplexing system.

[0031] It can be understood that the pin control module is used to control the behavior of multiplexed pins. The effective value output by the collected PINMUX register module is used as the judgment signal of the multiplexer to select the signal used by each multiplexed pin of the chip at the current moment. The input and output signal diagram of a single pin control module is shown in Figure 3 As shown, the multiplexer to be used is flexibly determined based on the number of pin multiplexing signals.

[0032] Taking a 5-to-1 multiplexer as an example, a one-hot encoding method is used, and each 4 bits of the PINMUX register controls a multiplexed pin. Figure 3 In the PINMUX register module, the judgment signal pin pinmux[3:0] is derived from the PINMUX register module, indicating the judgment signal that controls which function the multiplexed pin selects. pad_c is derived from the PAD, indicating the data received from the pin to the inside of the chip. pad_effect[4:0] is connected to a fixed value, indicating the effective value of the five multiplexed signals. signal_ren is derived from the PINMUX register module, indicating that the pull-up and pull-down resistors of the PAD corresponding to the multiplexed pin are enabled. signal_x_en and signal_x_u2p (where x=0 / 1 / 2 / 4 / 8) are derived from all components that interact with the outside through PINMUX, respectively indicating the signal transmission direction signal of each component at the moment and the data to be sent to the pin. pad_i is the signal output to the PAD, indicating the data to be sent to the pin by the target component. pad_oen is the signal output to the PAD, indicating the signal transmission direction of the target component. pad_ren is the signal output to the PAD, indicating that the pull-up and pull-down resistors of the PAD corresponding to the multiplexed pin are enabled. signal_x_p2u (x=0 / 1 / 2 / 4 / 8) represents the data input to all components that interact with the outside world via PINMUX.

[0033] When the multiplexed pin is used as an output, the output signal of the target component (such as signal_x_u2p) is routed to the multiplexed pin (pad_i); when the multiplexed pin is used as an input, the signal input from the pin (such as pad_c) is routed to the input signal of the target component (such as signal_x_p2u), and the input isolation signal (pad_effect) is added. For the components that are not currently configured with the PINMUX register selection, ensure that the input data and control signals are in an invalid state to avoid functional abnormalities caused by external input at the hardware level. That is, when pinmux[3:0] is configured to 0, signal_0_p2u comes from pad_c, and the remaining signal_x_p2u (x=1 / 2 / 4 / 8) comes from the inversion of the corresponding bits of pad_effect.

[0034] In some embodiments, the workflow of the chip pin multiplexing system can be as follows: Figure 4 As shown: Step 1, determine the configuration mode of the PINMUX register in the PINMUX register module. When the chip starts, the value of the PINMUX mode pin is automatically locked in the PINMODE register. The hardware reads the value in the PINMODE register to determine the configuration mode of the PINMUX register. If the read value is a high level, the software configuration mode is selected and the process goes to step 2. If the read value is a low level, the hardware configuration mode is selected and the process goes to step 3. Step 2: The current PINMUX register is in software configuration mode. The PINMUX register is read and written through the chip's internal host. The programmer needs to configure the corresponding PINMUX register through the internal host according to the pin multiplexing situation to route the signal corresponding to the target component to the corresponding pin. Assuming that a pin has 5 multiplexed signals, the functional description and usage of the PINMUX register are shown in Table 2. Each 4 bits controls a multiplexed pin. A 32-bit PINMUX register can control 8 multiplexed pins. Take PINMUX0[3:0] as an example. When the value of these 4 bits is 0x2, function B is selected; Table 2

[0035] Step 3. The current PINMUX register is in hardware configuration mode. With a single component as the smallest unit, the hardware automatically configures the PINMUX register of the target component based on the switch status of the component's clock gating enable. When the clock gating enable is turned on, all PINMUX registers automatically select the PINMUX register pre-configured value corresponding to the component based on the component's clock gating enable. All multiplexed pins involving the component are selected as the component function.

[0036] In one embodiment, a SOC chip is further provided, comprising an internal host, clock gating, a PAD and the above-mentioned chip pin multiplexing system.

[0037] It can be understood that the description of the internal host, clock gating and PAD components in this embodiment can be understood by referring to the same components in the SOC in the field, and will not be described in detail in this specification. For the specific explanation of the chip pin multiplexing system, please refer to the corresponding limitations of the chip pin multiplexing system in each embodiment above, which will not be repeated here.

[0038] The SOC chip can effectively improve the post-silicon test efficiency and optimize the system power consumption by applying the chip pin multiplexing system.

[0039] In one embodiment, a chip pin multiplexing method is also provided, which is applied to a chip pin multiplexing system. The chip pin multiplexing system includes a PINMUX register module and a pin control module. The PINMUX register module is used to connect the internal host and clock gating of the chip respectively, and to output a valid value to the pin control module. The pin control module is used to connect the PAD of the chip and the components that interact with the outside via the chip pin multiplexing system. When the chip is started, the value of the PINMUX mode pin of the PINMUX register module is automatically locked in the pin mode register. The value in the pin mode register is used to determine the configuration mode of the PINMUX register module after being read by the hardware, and the configuration mode includes a software configuration mode and a hardware configuration mode.

[0040] In software configuration mode, the effective value output by the PINMUX register module selects the value configured by the internal host through software. In hardware configuration mode, the effective value output by all PINMUX registers in the PINMUX register module is the pre-configured value of the PINMUX register corresponding to the target component that is automatically selected based on the clock gating enable of the target component.

[0041] The pin control module adopts a one-hot encoding method to control the pin behavior of the chip's PAD and the components that interact with the outside through the chip pin multiplexing system according to the effective value output by the PINMUX register module; the pin control module is provided with an input isolation signal, which is used to ensure that the data and control signals input by the components that are not currently configured with the PINMUX register selection are in an invalid state.

[0042] like Figure 5 As shown, the chip pin multiplexing method may include the following processing steps S10 and S12: S10, determining a configuration mode of a PINMUX register in a PINMUX register module; S12, when the current PINMUX register is in software configuration mode, the PINMUX register is read and written through the internal host of the chip to route the signal corresponding to the target component to the corresponding pin.

[0043] In one embodiment, the chip pin multiplexing method may further include the following steps: When the current PINMUX register is in hardware configuration mode, with a single component as the smallest unit, when the clock gating enable of the target component is turned on, the PINMUX register corresponding to the target component automatically selects the pre-configured value of the PINMUX register corresponding to the target component; all multiplexed pins involving the target component are selected as the target component function.

[0044] The above chip pin multiplexing method adds a PINMUX mode pin by designing a PINMUX component consisting of a PINMUX register module and a pin control module, so that the value of the PINMUX mode pin is automatically locked in the PINMODE register when the chip is started, and the hardware reads the value in the PINMODE register to determine the configuration mode of the PINMUX register, so that the configuration mode of the pin multiplexing can be flexibly selected. At the same time, the pin multiplexing configuration of each component is combined with the gated clock of the component. When the gated clock of the switch component is switched, the hardware automatically configures the pin multiplexing configuration register of the corresponding component. In the hardware configuration mode, the multiplexing pin configuration process can be saved, and the technical problems of complex multiplexing pin configuration and manual configuration errors can be solved from the hardware level, avoiding errors caused by hot switching of components during use, etc., improving the efficiency of post-silicon testing, and combining with clock gating technology can also effectively optimize power consumption and reduce unnecessary signal flips. In addition, for each multiplexed pin, an input isolation signal is added to the pin control module based on the valid state of the multiplexed signal, so as to ensure that the input data and control signals are in an invalid state when the PINMUX register is not configured, thereby avoiding functional abnormalities caused by external inputs from the hardware level and greatly improving the efficiency of chip pin multiplexing.

[0045] In one embodiment, the PINMUX register module includes a pin mode register, a PINMUX register corresponding to a software configuration mode, a PINMUX register corresponding to a hardware configuration mode, and an output register; The input end of the pin mode register is connected to the PINMUX mode pin, the output end of the pin mode register is connected to the control end of the output register, and the PINMUX register corresponding to the software configuration mode stores the value configured by the internal host through the software and is connected to the first input channel of the output register; The PINMUX register corresponding to the hardware configuration mode is used for the PINMUX register pre-configuration value corresponding to the target component and is connected to the second input channel of the output register. The output end of the output register is connected to the pin control module. When the value in the pin mode register corresponds to the software configuration mode, the output end of the output register is connected to the first input channel. When the value in the pin mode register corresponds to the hardware configuration mode, the output end of the output register is connected to the second input channel.

[0046] In one embodiment, the pin control module includes a plurality of pin control modules, each of which includes: The judgment signal comes from the PINMUX register module and is used to control the function of multiplexing pin selection; The pad_c signal comes from PAD and indicates the data received from the pin inside the chip; Input isolation signal, access fixed value according to signal polarity, used to ensure that the data and control signals input by the components that are not currently configured with PINMUX register selection are in invalid state; The signal_ren signal comes from the PINMUX register module and is used to enable the pull-up and pull-down resistors of the corresponding PAD of the switch multiplexing pin; The signal_x_en signal comes from all components that interact with the outside world through the chip pin multiplexing system and is used to indicate the signal transmission direction of each component; The signal_x_u2p signal comes from all components that interact with the outside world through the chip pin multiplexing system and is used to indicate the data that each component needs to send to the pin; x is a positive integer; pad_i signal is the signal output to PAD, indicating the data that the target component needs to send to the pin; The pad_ren signal is a signal output to the PAD, indicating that the pull-up and pull-down resistors of the switch multiplexing pin corresponding to the PAD are enabled; The signal_x_p2u signal represents the data input to all components that interact with the outside world via the chip pin multiplexing system.

[0047] For the specific explanation and limitation of the above-mentioned chip pin multiplexing method, please refer to the corresponding limitation of the chip pin multiplexing system in the above text, which will not be repeated here.

[0048] It should be understood that although Figure 5 The steps in the method are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figure 5At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0049] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (RambusDRAM, referred to as RDRAM) and interface dynamic random access memory (DRDRAM).

[0050] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0051] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A chip pin multiplexing system, characterized in that: It includes a PINMUX register module and a pin control module, wherein the PINMUX register module is used to connect the internal host and clock gating of the chip respectively, and to output a valid value to the pin control module, and the pin control module is used to connect the PAD of the chip and the components that interact with the outside via the chip pin multiplexing system; When the chip is started, the value of the PINMUX mode pin of the PINMUX register module is automatically locked in the pin mode register; the value in the pin mode register is used to determine the configuration mode of the PINMUX register module after being read by hardware, and the configuration mode includes a software configuration mode and a hardware configuration mode; In the software configuration mode, the valid value output by the PINMUX register module selects the value configured by the internal host through software, and in the hardware configuration mode, the valid value output by all PINMUX registers in the PINMUX register module automatically selects the pre-configured value of the PINMUX register corresponding to the target component based on the clock gating enable of the target component; The pin control module adopts a one-hot encoding method to control the pin behavior multiplexed between the chip's PAD and the components that interact with the outside through the chip pin multiplexing system according to the effective value output by the PINMUX register module; the pin control module is provided with an input isolation signal, and the input isolation signal is used to ensure that the data and control signals input by the components that are not currently configured with the PINMUX register selection are in an invalid state.

2. The chip pin multiplexing system according to claim 1, characterized in that: The PINMUX register module includes a pin mode register, a PINMUX register corresponding to a software configuration mode, a PINMUX register corresponding to a hardware configuration mode, and an output register; The input end of the pin mode register is connected to the PINMUX mode pin, the output end of the pin mode register is connected to the control end of the output register, and the PINMUX register corresponding to the software configuration mode stores the value configured by the internal host through software and is connected to the first input channel of the output register; The PINMUX register corresponding to the hardware configuration mode is used to store the PINMUX register pre-configuration value corresponding to the target component and is connected to the second input channel of the output register. The output end of the output register is connected to the pin control module. When the value in the pin mode register corresponds to the software configuration mode, the output end of the output register is connected to the first input channel. When the value in the pin mode register corresponds to the hardware configuration mode, the output end of the output register is connected to the second input channel.

3. The chip pin multiplexing system according to claim 1 or 2, characterized in that: The pin control module includes a plurality of pin control modules, each of which includes: A judgment signal, which is derived from the PINMUX register module and is used to control the function of multiplexing pin selection; The pad_c signal comes from PAD and indicates the data received from the pin inside the chip; Input isolation signal, access fixed value according to signal polarity, used to ensure that the data and control signals input by the components that are not currently configured with PINMUX register selection are in invalid state; The signal_ren signal comes from the PINMUX register module and is used to enable the pull-up and pull-down resistors of the PAD corresponding to the switch multiplexing pin; The signal_x_en signal comes from all components that interact with the outside through the chip pin multiplexing system and is used to indicate the signal transmission direction of each component; The signal_x_u2p signal comes from all components that interact with the outside through the chip pin multiplexing system and is used to indicate the data that each component needs to send to the pin; x is a positive integer; pad_i signal is the signal output to PAD, indicating the data that the target component needs to send to the pin; The pad_ren signal is a signal output to the PAD, indicating that the pull-up and pull-down resistors of the switch multiplexing pin corresponding to the PAD are enabled; The signal_x_p2u signal represents the data input to all components that interact with the outside world via the chip pin multiplexing system.

4. A SOC chip, characterized in that: The invention comprises an internal host, a clock gating, a PAD and the chip pin multiplexing system as claimed in any one of claims 1 to 3.

5. A chip pin multiplexing method, characterized in that: Applied to a chip pin multiplexing system, the chip pin multiplexing system includes a PINMUX register module and a pin control module, the PINMUX register module is used to connect the internal host and clock gating of the chip respectively, and to output a valid value to the pin control module, the pin control module is used to connect the PAD of the chip and the components interacting with the outside via the chip pin multiplexing system; When the chip is started, the value of the PINMUX mode pin of the PINMUX register module is automatically locked in the pin mode register; the value in the pin mode register is used to determine the configuration mode of the PINMUX register module after being read by hardware, and the configuration mode includes a software configuration mode and a hardware configuration mode; In the software configuration mode, the valid value output by the PINMUX register module selects the value configured by the internal host through software, and in the hardware configuration mode, the valid value output by all PINMUX registers in the PINMUX register module automatically selects the pre-configured value of the PINMUX register corresponding to the target component based on the clock gating enable of the target component; The pin control module adopts a one-hot encoding method to control the pin behavior of the chip PAD and the components that interact with the outside through the chip pin multiplexing system according to the effective value output by the PINMUX register module; the pin control module is provided with an input isolation signal, and the input isolation signal is used to ensure that the data and control signals input by the components that are not currently configured with the PINMUX register selection are in an invalid state; The chip pin multiplexing method comprises the steps of: Determining a configuration mode of a PINMUX register in the PINMUX register module; When the current PINMUX register is in software configuration mode, the PINMUX register is read and written through the internal host of the chip to route the signal corresponding to the target component to the corresponding pin.

6. The chip pin multiplexing method according to claim 5, characterized in that: Also includes the steps: When the current PINMUX register is in hardware configuration mode, with a single component as the smallest unit, when the clock gating enable of the target component is turned on, the PINMUX register corresponding to the target component automatically selects the pre-configured value of the PINMUX register corresponding to the target component; all multiplexed pins involving the target component are selected as the target component function.

7. The chip pin multiplexing method according to claim 5 or 6, characterized in that: The PINMUX register module includes a pin mode register, a PINMUX register corresponding to a software configuration mode, a PINMUX register corresponding to a hardware configuration mode, and an output register; The input end of the pin mode register is connected to the PINMUX mode pin, the output end of the pin mode register is connected to the control end of the output register, and the PINMUX register corresponding to the software configuration mode stores the value configured by the internal host through software and is connected to the first input channel of the output register; The PINMUX register corresponding to the hardware configuration mode is used to store the PINMUX register pre-configuration value corresponding to the target component and is connected to the second input channel of the output register. The output end of the output register is connected to the pin control module. When the value in the pin mode register corresponds to the software configuration mode, the output end of the output register is connected to the first input channel. When the value in the pin mode register corresponds to the hardware configuration mode, the output end of the output register is connected to the second input channel.

8. The chip pin multiplexing method according to claim 7, characterized in that: The pin control module includes a plurality of pin control modules, each of which includes: A judgment signal, which is derived from the PINMUX register module and is used to control the function of multiplexing pin selection; The pad_c signal comes from PAD and indicates the data received from the pin inside the chip; Input isolation signal, access fixed value according to signal polarity, used to ensure that the data and control signals input by the components that are not currently configured with PINMUX register selection are in invalid state; The signal_ren signal comes from the PINMUX register module and is used to enable the pull-up and pull-down resistors of the PAD corresponding to the switch multiplexing pin; The signal_x_en signal comes from all components that interact with the outside through the chip pin multiplexing system and is used to indicate the signal transmission direction of each component; The signal_x_u2p signal comes from all components that interact with the outside through the chip pin multiplexing system and is used to indicate the data that each component needs to send to the pin; x is a positive integer; pad_i signal is the signal output to PAD, indicating the data that the target component needs to send to the pin; The pad_ren signal is a signal output to the PAD, indicating that the pull-up and pull-down resistors of the switch multiplexing pin corresponding to the PAD are enabled; The signal_x_p2u signal represents the data input to all components that interact with the outside world via the chip pin multiplexing system.

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