Data path group leveling method based on clock tree synthesis
By creating clocks and setting balance points in data path groups, and using electronic design automation tools to synthesize clock trees, the problem of inconsistent delays during the time sequence convergence of data path groups is solved, and efficient and accurate data path groups are achieved. Improve chip performance and development efficiency.
Patent Information
- Application Number
- CN202411592891.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-08
- Publication Date
- 2025-02-18
AI Technical Summary
In deep submicron and nanoscale chip design, during the time sequence convergence of data path groups, the delay of data paths is inconsistent, resulting in the timing of data path groups being affected, and it is difficult for the existing technology to achieve accurate and efficient data path groups to level. .
Using a clock tree synthesis method, by creating clocks in the data path group and setting balance points, using electronic design automation tools to synthesize clock trees to achieve leveling of data path groups.
This method avoids the timing reports of unnecessary violations and errors in electronic design automation tools, enhances design controllability, reduces chip delay, improves chip performance, and reduces design difficulty and scripts for digital backend engineers The difficulty of writing shortens the chip development cycle.
Smart Images
Figure CN119476154A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a data path group leveling method based on clock tree synthesis. Background Art
[0002] As chip design enters deep submicron and nanometer advanced process nodes, chip design becomes more and more complex. Digital backend engineers spend a lot of time on physical implementation of chips, among which timing convergence is the top priority of physical implementation. In digital chips, the above timing convergence process often requires that the delays of multiple data paths in the data path group be consistent. The skew between different data paths is a key factor affecting the timing of the data path group. Therefore, how to accurately and efficiently flatten the data path group has become a technical problem that needs to be solved urgently.
[0003] The current method of flattening a data path group is to use the timing constraint command to constrain the data path endpoints, and use the electronic design automation tool to flatten the data path. The disadvantages of this method are: 1. Constraining the data path will produce unnecessary violations, affecting the normal timing report of the electronic design automation tool; 2. When a data path endpoint corresponds to multiple data path starting points, it is impossible to constrain multiple data paths on a data path endpoint; 3. The process of constraining the data path requires digital backend engineers to spend a lot of time analyzing and manually writing script files, which increases the chip development cycle. Summary of the invention
[0004] In order to solve the above technical problems, the present invention provides a data path group leveling method based on clock tree synthesis, comprising:
[0005] Step 1: Determine the number N of target data paths and create a data path group;
[0006] Step 2: Determine N registers at the data transmitting end of the N data paths in the data path group, and an output Q pin of each data transmitting end register;
[0007] Step 3: Create a clock on the output Q pin of each data transmitter register, create a total of N clocks, and add these clocks to the same internal balanced clock group;
[0008] Step 4: Determine N registers at the data capture end of the N data paths in the data path group, and an input D pin of each data capture end register;
[0009] Step 5: Set the input D pin of each data capture end register as a balance point, and set N balance points in total;
[0010] Step 6: Use electronic design automation tools to perform clock tree synthesis on all clocks in the internal balanced clock group with balance as the goal, and achieve balancing of N data paths in the data path group from the starting point of the clock tree to the balance point.
[0011] Beneficial effects of the present invention:
[0012] The present invention applies the idea of clock tree synthesis to the design of data path group flattening, and uses the clock tree synthesis function in the electronic design automation tool to complete the design, thereby avoiding the electronic design automation tool from generating unnecessary violations and erroneous timing reports and enhancing the controllability in the design.
[0013] The present invention creates a clock and sets a balance point on each data path in the data path group. The starting point and the end point of each path correspond one to one. This deterministic constraint enables electronic design automation tools to continuously optimize the design, reduce chip delay, and improve chip performance.
[0014] Each data path of the present invention adopts consistent operation, which reduces the design difficulty of digital back-end engineers, reduces the difficulty of script writing, and shortens the chip development cycle.
[0015] The present invention utilizes electronic design automation tools to perform clock tree synthesis with balance as the goal, thereby achieving balancing of data path groups. The report documents generated by the tool are complete, which is convenient for digital back-end engineers to check errors and reduces the possibility of errors caused by human participation. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 A schematic diagram of a flow chart of a method for leveling data path groups based on clock tree synthesis provided in an embodiment of the present invention;
[0017] Figure 2 A schematic diagram of the circuit structure of a data path group provided by an embodiment of the present invention;
[0018] Figure 3 A schematic diagram of the output pins of the data path group at the data transmitting end register group provided by an embodiment of the present invention;
[0019] Figure 4 A schematic diagram of creating a clock at an output pin of a data transmitting end register group provided by an embodiment of the present invention;
[0020] Figure 5 A schematic diagram of input pins of a data path group at a data capture end register group provided by an embodiment of the present invention;
[0021] Figure 6 A schematic diagram of setting a balance point at an input pin of a data capture end register group provided by an embodiment of the present invention;
[0022] Figure 7 A schematic diagram of an implementation of a data path group leveling method based on clock tree synthesis provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0024] like Figure 1 As shown, an embodiment of the present invention provides a data path group leveling method based on clock tree synthesis, comprising the following steps:
[0025] S101: Figure 2 As shown, the number N of target data paths is determined and a data path group is created;
[0026] Specifically, the data path includes: a data path from the input port to the data capture end register, a data path from the data transmitter end register to the data capture end register, and a data path from the data transmitter end register to the output port; in the embodiment of the present invention, the data path refers to the timing path from the above-mentioned data transmitter end register to the data capture end register, such as Figure 2 As shown, 201 represents N data paths from register to register, and the N data paths are sent from the data transmitting end register of the previous stage, pass through different combinational logics, and reach the data capturing end register of the next stage.
[0027] S102: Figure 3 As shown, N registers of N data paths at the data transmitting end and the output Q pin of each register are determined;
[0028] Specifically, in the data path from the input port to the data capture end register, there is no output Q pin of the data transmitter end register, then the proposed input port is connected to the output Q pin of the data transmitter end register in the previous chip; in the embodiment of the present invention, the data path is the data path from the data transmitter end register to the data capture end register, and there is an output Q pin of the data transmitter end register, such as Figure 3 As shown, 301 represents N data transmitting end registers, and 302 represents the output Q pins of the N data transmitting end registers.
[0029] S103: Figure 4 As shown, a clock is created at the output Q pin of each data transmitter register, a total of N clocks are created, and these clocks are added to the same internal balanced clock group;
[0030] Specifically, in the data path from the input port to the data capture end register, the proposed input port is connected to the output Q pin of the data transmitter end register in the previous chip, and a clock is created at the output Q pin of the data transmitter end register in the previous chip, which is equivalent to creating a clock on the input port, and these clocks are added to the same internal balanced clock group; in an embodiment of the present invention, the data path is a data path from the data transmitter end register to the data capture end register, and there is an output Q pin of the data transmitter end register, a clock is created at the output Q pin of the data transmitter end register, and these clocks are added to the same internal balanced clock group, such as Figure 4 As shown, 401 represents N clocks created at the output Q pin of the data transmitter register, and these N clocks are added to the same internal balanced clock group.
[0031] S104: Figure 5 As shown, N registers of N data paths at the data capture end and the input D pin of each register are determined;
[0032] Specifically, in the data path from the data transmitting end register to the output port, there is no input D pin of the data capturing end register, and the proposed output port is connected to the input D pin of the data capturing end register in the subsequent chip; in the embodiment of the present invention, the data path is the data path from the data transmitting end register to the data capturing end register, and there is an input D pin of the data capturing end register, such as Figure 5 As shown, 501 represents N data capture end registers, and 502 represents input D pins of the N data capture end registers.
[0033] S105: Figure 6 As shown, a balance point is set at the input D pin of each data capture end register;
[0034] Specifically, in the data path from the data transmitting end register to the output port, it is proposed that the output port is connected to the input D pin of the data capture end register in the subsequent chip, and a balance point is set on the input D pin of the data capture end register in the subsequent chip, which is equivalent to setting a balance point on the output port; in the embodiment of the present invention, the data path is the data path from the data transmitting end register to the data capture end register, and there is an input D pin of the data capture end register, and the input D pin of the data capture end register is set to the balance point, such as Figure 6 As shown, 601 represents setting the balance point at the input D pin of the data capture end register.
[0035] S106: Using electronic design automation tools, perform clock tree synthesis with balance as the goal to achieve leveling of the data path group;
[0036] Specifically, the data path group leveling method based on clock tree synthesis is implemented, such as Figure 7 As shown, 701, 702, and 703 represent the delays when different data paths pass through different combinational logics. The electronic design automation clock tree synthesis tool inserts different numbers of buffer units represented by 704, 705, and 706 inside the combinational logic to reduce the skew of N data paths and flatten the data path group.
[0037] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.
Claims
1. A data path group leveling method based on clock tree synthesis, characterized in that: include: Step 1: Determine the number N of target data paths and create a data path group; Step 2: Determine N registers at the data transmitting end of the N data paths in the data path group, and an output Q pin of each data transmitting end register; Step 3: Create a clock on the output Q pin of each data transmitter register, create a total of N clocks, and add these clocks to the same internal balanced clock group; Step 4: Determine N registers at the data capture end of the N data paths in the data path group, and an input D pin of each data capture end register; Step 5: Set the input D pin of each data capture end register as a balance point, and set N balance points in total; Step 6: Use electronic design automation tools to perform clock tree synthesis on all clocks in the internal balanced clock group with balance as the goal, and achieve balancing of N data paths in the data path group from the starting point of the clock tree to the balance point.
2. The method for leveling data path groups based on clock tree synthesis according to claim 1, characterized in that: The data path includes: a data path from the input port to the data capture end register, a data path from the data transmission end register to the data capture end register, and a data path from the data transmission end register to the output port.
3. The method for leveling data path groups based on clock tree synthesis according to claim 2, characterized in that: In the data path from the input port to the data capture register, the input port does not have a data transmitter register. The proposed input port is connected to the output Q pin of the data transmitter register in the previous chip. Creating a clock on the output Q pin of the data transmitter register in the previous chip is equivalent to creating a clock on the input port, and adding these clocks to the same internal balanced clock group.
4. The method for leveling data path groups based on clock tree synthesis according to claim 2, characterized in that: The step 5 includes: in the data path from the data transmitting end register to the output port, the output port does not have a data capturing end register, and the output port is planned to be connected to the data capturing end register in the subsequent chip. The input D pin of the device is connected to the data capture end register in the subsequent chip, and the input D pin of the data capture end register is set to the balance point. This is equivalent to setting the output port to the balance point.