Chip circuit layout method, device and equipment based on EDA tool and medium

Abstract

The invention provides a chip circuit layout method and device based on an EDA tool, equipment and a medium, and the method comprises the steps: determining an initial placement rectangular region, sorting rectangular blocks of a circuit module according to the height from large to small, and obtaining a rectangular block sequence; dividing the initial placement rectangular area based on a first rectangular block in the rectangular block sequence, and determining a strip-shaped area; the rectangular blocks conforming to the strip-shaped areas are placed, and the strip-shaped areas are divided into a plurality of sub-areas; traversing the free areas in each sub-area, placing the remaining rectangular blocks in the free areas, determining a new strip-shaped area based on the rectangular block with the maximum height in the rectangular blocks which are not placed after the strip-shaped areas are filled, continuously placing the remaining rectangular blocks, and then placing the remaining rectangular blocks in the new strip-shaped area. And carrying out corresponding region placement on the hierarchical circuit under each circuit module to generate a circuit module layout of the chip to be arranged. Therefore, a larger space utilization rate is provided, and a better stock layout effect is finally obtained.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a chip circuit layout method, device, equipment and medium based on EDA tools. Background Art

[0002] Layout planning occupies an important position in chip design. Its rationality is directly related to the chip's timing convergence, smooth routing, power supply stability and yield rate. In the traditional design process, layout planning may take up 10% to 20% of the total chip back-end design time, or even more. A visual view is usually provided in the digital back-end electronic design automation (EDA) tool. The built-in algorithm of EDA automatically generates visual rectangular blocks for each circuit module in the chip and optimizes the layout. Designers can directly drag and adjust the position of the module in the view, and preview the layout effect in real time, helping designers to quickly and accurately complete the first step of physical design and lay the foundation for subsequent steps. The existing visual view alignment algorithm distributes the circuit modules on both sides of the chip and linearly aligns and displays them separately, such as Figure 1 As shown in , this arrangement has low space utilization and cannot display the hierarchical relationship of each circuit module in the chip. The existing visualization view "cut glass" algorithm can display the hierarchical relationship of circuit modules, but the actual area of ​​the circuit modules cannot be accurately displayed. At the same time, when encountering some smaller circuit modules, their areas will be cut into very narrow strips, which is not beautiful and not conducive to editing operations. In addition, the algorithm cannot support the display of visualization views. Therefore, how to improve the space utilization of chip circuit layout has become a technical issue that cannot be underestimated. Summary of the invention

[0003] In view of this, the purpose of the present application is to provide a chip circuit layout method, device, equipment and medium based on EDA tools, which can not only place different types of circuit modules together while following the circuit hierarchy relationship, but also reuse the idle areas generated during the placement process, so that more circuit modules can be placed in the idle areas, thereby providing greater space utilization and ultimately obtaining a better layout effect.

[0004] The embodiment of the present application provides a chip circuit layout method based on an EDA tool, and the chip circuit layout method includes: Determine an initial placement rectangular area based on the area of ​​the chip to be laid out, and sort the rectangular blocks of multiple different types of circuit modules of the chip to be laid out from large to small according to height to obtain a rectangular block sequence; Dividing the initial placement rectangular area based on the first rectangular block in the rectangular block sequence to determine a strip area; Arranging the rectangular blocks in the rectangular block sequence that match the strip area, and dividing the strip area into a plurality of sub-areas based on the widths of the rectangular blocks already arranged in the strip area; Traverse the free areas in each of the sub-areas, place the remaining rectangular blocks in the rectangular block sequence into the free areas, and after filling the strip areas, determine a new strip area in the remaining initial placement rectangular area based on the rectangular block with the largest height among the unplaced rectangular blocks, and after the remaining rectangular blocks are placed, place the hierarchical circuits under each circuit module in the corresponding areas to generate the circuit module layout of the chip to be laid out.

[0005] In a possible implementation manner, placing the rectangular blocks in the rectangular block sequence that conform to the strip area includes: Based on the arrangement order from left to right, the rectangular blocks with decreasing heights in the rectangular block sequence are arranged at the bottom of the strip area at preset intervals, and the rectangular blocks are stopped from being arranged when reaching the rightmost side of the strip area.

[0006] In a possible implementation manner, traversing the free area in each of the sub-areas and placing the remaining rectangular blocks in the rectangular block sequence into the free area includes: Based on the arrangement order from bottom to top and from left to right, the remaining rectangular blocks are arranged in the idle area in the order of small to large height; Detect whether there are multiple top idle areas in the idle area; If so, multiple top idle areas are merged to generate a new idle area, and the new idle area is continuously arranged into rectangular blocks.

[0007] In a possible implementation manner, for the first idle area, placing the remaining rectangular blocks in the idle area in ascending order of height based on the arrangement order from bottom to top and from left to right includes: Detecting whether the rectangular block with the smallest height among the remaining rectangular blocks is suitable for being placed at the lower left corner of the first free area; If not, stop placing the rectangular blocks in the first free area; If so, after arranging the rectangular block with the smallest height, the next rectangular block among the remaining rectangular blocks is placed above the rectangular block with the smallest height, until the height of the rectangular blocks can no longer be placed in the first free area, then the first free area is cut vertically to determine the column space area, and the rectangular blocks continue to be arranged in the column space area.

[0008] In a possible implementation manner, stopping placing rectangular blocks in the first idle area includes: If the height of the first idle area does not meet the height of the rectangular block with the smallest height, then the traversal of the plurality of idle areas ends; If the width of the first idle area does not satisfy the width of the rectangular block with the smallest height, the placement of the first idle area is terminated and the placement of the rectangular block in the next idle area is switched.

[0009] In a possible implementation manner, the hierarchical circuits under each circuit module are arranged in corresponding areas, including: Determine a rectangular block of hierarchical circuits under the circuit module; The rectangular blocks of the hierarchical circuit are placed in the rectangular block area where the circuit module is located. If each rectangular block of the hierarchical circuit cannot be placed in the rectangular block area where the circuit module is located, the area of ​​the rectangular block where the circuit module is located is enlarged proportionally.

[0010] In a possible implementation manner, after generating the circuit module layout of the chip to be laid out, the chip circuit layout method further includes: In response to the user's request to display the hierarchical circuit under the circuit module, the background color of the rectangular block corresponding to the circuit module is controlled to be transparent to display the rectangular block of the hierarchical circuit, and the rectangular blocks located on the right and upper sides of the circuit module are shifted.

[0011] The embodiment of the present application further provides a chip circuit layout device based on an EDA tool, the chip circuit layout device comprising: An initial setting module, used to determine an initial placement rectangular area based on the area of ​​the chip to be laid out, and sort the rectangular blocks of multiple different types of circuit modules of the chip to be laid out from large to small according to height to obtain a rectangular block sequence; A region division module, used for dividing the initial placement rectangular region based on the first rectangular block in the rectangular block sequence to determine a strip region; A rectangular block placement module, used for placing the rectangular blocks in the rectangular block sequence that are in line with the strip area, and dividing the strip area into a plurality of sub-areas based on the width of the rectangular blocks already placed in the strip area; The module for filling the free area is used to traverse the free area in each of the sub-areas, place the remaining rectangular blocks in the rectangular block sequence into the free area, and after filling the strip area, determine the new strip area in the remaining initial placement rectangular area based on the rectangular block with the largest height among the unplaced rectangular blocks, and after continuing to place the remaining rectangular blocks, place the hierarchical circuits under each circuit module in the corresponding area to generate the circuit module layout of the chip to be laid out.

[0012] An embodiment of the present application also provides an electronic device, comprising: a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the memory through the bus, and when the machine-readable instructions are executed by the processor, the steps of the chip circuit layout method based on the EDA tool as described above are performed.

[0013] An embodiment of the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the chip circuit layout method based on the EDA tool as described above are executed.

[0014] The embodiment of the present application provides a chip circuit layout method, device, equipment and medium based on EDA tools. The chip circuit layout method includes: determining an initial placement rectangular area based on the area of ​​the chip to be laid out, and sorting the rectangular blocks of multiple different types of circuit modules of the chip to be laid out from large to small according to height to obtain a rectangular block sequence; dividing the initial placement rectangular area based on the first rectangular block in the rectangular block sequence to determine a strip area; placing the rectangular blocks in the rectangular block sequence that meet the strip area, and dividing the strip area into multiple sub-areas based on the width of the rectangular blocks already placed in the strip area; traversing the free area in each of the sub-areas, placing the remaining rectangular blocks in the rectangular block sequence into the free area, and after filling the strip area, determining the remaining new strip area in the initial placement rectangular area based on the rectangular block with the largest height among the unplaced rectangular blocks, and after continuing to place the remaining rectangular blocks, placing the hierarchical circuits under each circuit module in the corresponding area to generate the circuit module layout of the chip to be laid out. Not only can different types of circuit modules be placed together in accordance with the circuit hierarchy, but the idle areas generated during the placement process can also be reused, so that more circuit modules can be placed in the idle areas, thereby providing greater space utilization and ultimately achieving better layout effects.

[0015] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 It is a schematic diagram of the arrangement effect of chip circuit layout in the prior art; Figure 2 A flowchart of a chip circuit layout method based on an EDA tool provided in an embodiment of the present application; Figure 3 This is one of the schematic diagrams of the layout effect of the chip circuit layout provided in the embodiment of the present application; Figure 4 The second schematic diagram of the layout effect of the chip circuit layout provided in the embodiment of the present application; Figure 5 One of the structural schematic diagrams of a chip circuit layout device based on an EDA tool provided in an embodiment of the present application; Figure 6 A second structural schematic diagram of a chip circuit layout device based on an EDA tool provided in an embodiment of the present application; Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0018] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application usually described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, each other embodiment obtained by those skilled in the art without making creative work belongs to the scope of protection of the present application.

[0019] First, the application scenarios to which the present application is applicable are introduced. The present application can be applied in the field of chip technology.

[0020] Layout planning occupies an important position in chip design. Its rationality is directly related to the chip's timing convergence, smooth routing, power supply stability and yield rate. In the traditional design process, layout planning may take up 10% to 20% of the total chip back-end design time, or even more. A visual view is usually provided in the digital back-end electronic design automation (EDA) tool. The built-in algorithm of EDA automatically generates visual rectangular blocks for each circuit module in the chip and optimizes the layout. Designers can directly drag and adjust the position of the module in the view, and preview the layout effect in real time, helping designers to quickly and accurately complete the first step of physical design and lay the foundation for subsequent steps. The existing visual view alignment algorithm distributes the circuit modules on both sides of the chip and linearly aligns and displays them separately, such as Figure 1 As shown in , this arrangement has low space utilization and cannot display the hierarchical relationship of each circuit module in the chip. The existing visualization view "cut glass" algorithm can display the hierarchical relationship of circuit modules, but the actual area of ​​the circuit modules cannot be accurately displayed. At the same time, when encountering some smaller circuit modules, their areas will be cut into very narrow strips, which is not beautiful and not conducive to editing operations. In addition, the algorithm cannot support the display of visualization views. Therefore, how to improve the space utilization of chip circuit layout has become a technical issue that cannot be underestimated.

[0021] Based on this, the embodiment of the present application provides a chip circuit layout method based on EDA tools, which can not only place different types of circuit modules together while following the circuit hierarchy relationship, but also reuse the idle areas generated during the placement process, so that more circuit modules can be placed in the idle areas, thereby providing greater space utilization and ultimately obtaining a better layout effect.

[0022] See also Figure 2 , Figure 2 The following is a flow chart of a chip circuit layout method based on EDA tools provided in an embodiment of the present application. Figure 2 As shown in , the chip circuit layout method provided by the embodiment of the present application includes: S201: determining an initial placement rectangular area based on the area of ​​the chip to be laid out, and sorting rectangular blocks of a plurality of different types of circuit modules of the chip to be laid out from large to small according to height to obtain a rectangular block sequence.

[0023] In this step, an initial placement rectangular area is determined according to the area of ​​the chip to be laid out, and rectangular blocks of multiple different types of circuit modules of the chip to be laid out are sorted in descending order according to height to obtain a rectangular block sequence.

[0024] The rectangular block of the circuit module is a circumscribed rectangle of the circuit module.

[0025] S202: Divide the initial placement rectangular area based on the first rectangular block in the rectangular block sequence to determine strip areas.

[0026] In this step, the initial placement rectangular area is divided according to the first rectangular block in the rectangular block sequence to determine the strip area.

[0027] Here, the rectangular block with the highest height is selected from the rectangular blocks placed in the rectangular block sequence, and is placed at the lower left corner of the rectangular area where the rectangle can be placed, and a strip area is determined with its height as the limit and the width of the rectangular area where the rectangle can be placed.

[0028] S203: Arrange the rectangular blocks in the rectangular block sequence that match the strip area, and divide the strip area into a plurality of sub-areas based on the widths of the rectangular blocks that have been arranged in the strip area.

[0029] In this step, the rectangular blocks in the rectangular block sequence that are in line with the strip area are placed, and the strip area is divided into a plurality of sub-areas according to the widths of the rectangular blocks that have been placed in the strip area. Here, the strip region is divided into sub-regions according to the width of the rectangular block in the strip region, and each sub-region has only one rectangular block.

[0030] The rectangular block that conforms to the strip region is a rectangular block that satisfies the height and width of the strip region.

[0031] In a possible implementation manner, placing the rectangular blocks in the rectangular block sequence that conform to the strip area includes: Based on the arrangement order from left to right, the rectangular blocks with decreasing heights in the rectangular block sequence are arranged at the bottom of the strip area at preset intervals, and the rectangular blocks are stopped from being arranged when reaching the rightmost side of the strip area.

[0032] Here, rectangular blocks of decreasing height in the rectangular block sequence are sequentially placed at the bottom of the strip area at preset intervals according to the placement order from left to right, and the placement of rectangular blocks in the strip area is stopped when the rectangular blocks reach the rightmost side of the strip area.

[0033] S204: traverse the free areas in each of the sub-areas, place the remaining rectangular blocks in the rectangular block sequence into the free areas, and after filling the strip areas, determine a new strip area in the remaining initial placement rectangular area based on the rectangular block with the largest height among the unplaced rectangular blocks, and after the remaining rectangular blocks are placed, place the hierarchical circuits under each circuit module in the corresponding areas to generate the circuit module layout of the chip to be laid out.

[0034] In this step, the free areas in each sub-area are traversed, and the remaining rectangular blocks in the rectangular block sequence are placed in the free areas. After the strip area is filled, the unplaced rectangular blocks are placed in the remaining initial placement rectangular areas according to the above-mentioned rectangular block placement rules, and the hierarchical circuits under each circuit module are placed in the corresponding areas to generate the circuit module layout of the chip to be laid out.

[0035] Here, after the strip-shaped area is filled with rectangular blocks, the remaining initially placed rectangular areas are continuously filled with rectangular blocks according to a filling method consistent with the strip-shaped area.

[0036] In a possible implementation manner, traversing the free area in each of the sub-areas and placing the remaining rectangular blocks in the rectangular block sequence into the free area includes: A: Based on the arrangement order from bottom to top and from left to right, the remaining rectangular blocks are arranged in the idle area in the order of height from small to large.

[0037] Here, the free areas in the above sub-areas are traversed, and for each free area, the rectangular blocks are placed in the free area in order from bottom to top and from left to right according to the order of height from small to large.

[0038] Among them, in this solution, in addition to the arrangement rule from bottom to top and from left to right, the rectangular blocks can also be arranged according to the arrangement rule from bottom to top and from right to left.

[0039] In a possible implementation manner, for the first idle area, placing the remaining rectangular blocks in the idle area in ascending order of height based on the arrangement order from bottom to top and from left to right includes: (1): Detect whether the rectangular block with the smallest height among the remaining rectangular blocks is suitable for being placed at the lower left corner of the first free area.

[0040] Here, it is detected whether the rectangular block with the smallest height among the remaining rectangular blocks is suitable for being placed at the lower left corner of the first free area.

[0041] (2): If not, stop placing the rectangular blocks in the first free area.

[0042] In a possible implementation manner, stopping placing rectangular blocks in the first idle area includes: If the height of the first idle area does not meet the height of the rectangular block with the smallest height, the traversal of the multiple idle areas is terminated; if the width of the first idle area does not meet the width of the rectangular block with the smallest height, the placement of the first idle area is terminated and the rectangular block placement of the next idle area is switched.

[0043] Here, when the rectangular block with the smallest height among the remaining rectangular blocks cannot be placed in the first free area, if the rectangular block cannot be placed due to insufficient height, the traversal of all free areas is terminated; if the rectangular block cannot be placed due to insufficient width, the placement is switched to the free area of ​​the next sub-area in the sub-area sequence.

[0044] (3): If yes, after placing the rectangular block with the smallest height, place the next rectangular block among the remaining rectangular blocks above the rectangular block with the smallest height, until the first free area is no longer able to accommodate the height of the rectangular blocks, then cut the first free area vertically to determine the column space area, and continue to place the rectangular blocks in the column space area.

[0045] Here, if, after arranging the rectangular block with the smallest height, the next rectangular block among the remaining rectangular blocks is placed above the rectangular block with the smallest height, until the height of the rectangular blocks cannot be placed in the first free area, the first free area is cut vertically to determine the column space area, and the rectangular blocks are continued to be arranged in the column space area.

[0046] Among them, the next rectangular block in the current queue is placed above the previous rectangular block, and this step is repeated until a rectangular block cannot be placed; if it cannot be placed due to insufficient width, the placement in the current sub-area is ended and the next one in the aforementioned sub-area sequence is switched; if it cannot be placed due to insufficient height, a column space is cut vertically from the sub-area with the maximum width of the rectangular blocks currently placed in the sub-area as the boundary, and the rectangular block is placed at the bottom of the remaining space on the right side of the column space, and the above steps are repeated. B: Detect whether there are multiple top idle areas in the idle area; if so, merge the multiple top idle areas to generate a new idle area, and continue to arrange rectangular blocks in the new idle area.

[0047] Here, it is detected whether there are multiple top idle areas in the idle area; if so, the multiple top idle areas are merged to generate a new idle area, and the rectangular blocks are continuously placed in the new idle area.

[0048] After each column is placed, the top free area of ​​the column and the top free area of ​​the left column are merged into a new free area. For rectangular free areas spanning multiple columns, the next rectangular block is placed into the new free area first. If the rectangular block cannot be placed due to insufficient height, the merged free area is discarded; if the rectangular block cannot be placed due to insufficient width, it is left to be merged with the top free area of ​​the subsequent column. Here, after the strip area is placed, it is cut off from the placeable area, and the above placement steps are repeated until all rectangular blocks are placed successfully, or there is no remaining space; if there is no remaining space in the placeable area, but there are still rectangular blocks that have not been placed, the initial placement area is expanded proportionally, and all rectangular blocks are rearranged according to the above placement steps. The heuristic algorithm used is to place the remaining rectangular blocks in the free area in the order of height from small to large based on the order of placement from bottom to top and from left to right.

[0049] In a possible implementation manner, the hierarchical circuits under each circuit module are arranged in corresponding areas, including: a: Determine the rectangular blocks of the hierarchical circuits under the circuit module.

[0050] Here, a rectangular block of hierarchical circuits under the circuit module is determined.

[0051] b: Place the rectangular blocks of the hierarchical circuit in the rectangular block area where the circuit module is located. If each rectangular block of the hierarchical circuit cannot be placed in the rectangular block area where the circuit module is located, the area of ​​the rectangular block where the circuit module is located is proportionally enlarged. Here, according to the above placement rules, the rectangular blocks of the hierarchical circuits are placed in the rectangular block area where the circuit module is located. If the rectangular blocks of each hierarchical circuit cannot be placed in the rectangular block area where the circuit module is located, the area of ​​the rectangular block where the circuit module is located is expanded proportionally.

[0052] In a possible implementation manner, after generating the circuit module layout of the chip to be laid out, the chip circuit layout method further includes: In response to the user's request to display the hierarchical circuit under the circuit module, the background color of the rectangular block corresponding to the circuit module is controlled to be transparent to display the rectangular block of the hierarchical circuit, and the rectangular blocks located on the right and upper sides of the circuit module are shifted.

[0053] Here, in response to the user's request to display the hierarchical circuit under the circuit module, the background color of the rectangular block corresponding to the circuit module is controlled to be transparent to display the rectangular block of the hierarchical circuit, and the rectangular blocks located on the right and upper sides of the circuit module are shifted.

[0054] Among them, after the hierarchical circuit under the circuit module is folded, the rectangular blocks located on the right and upper side of the circuit module are regressed to the positions before the offset, and other circuit modules are dynamically translated to avoid cross occlusion.

[0055] In this application, not only can different types of circuit modules be placed together while following the circuit hierarchy, but the idle area reuse algorithm can also be used to significantly improve the space utilization of the visualization view, and ultimately achieve a better layout effect. The advantage of this algorithm is that it can intuitively display the hierarchical relationship between the various circuit modules, and at the same time, it can also record the idle areas generated by the circuit modules during the placement process, and merge the idle areas generated during the placement process based on certain rules, so that more circuit modules can be placed in the idle areas, thereby providing greater space utilization.

[0056] In a specific embodiment, an initial placement rectangular area is set, and the circuit rectangular blocks to be placed are sorted from large to small according to height; the first rectangular block (the rectangular block with the highest height) is selected from the rectangular blocks that have not yet been placed, and it is placed in the lower left corner of the rectangular area that can be placed, and a strip area is determined based on its height; in the order of the height of the rectangular blocks from large to small, the rectangular blocks are placed at the bottom of the above strip area at a certain interval from left to right until they reach the rightmost side of the strip area, and the last rectangular block placed in the strip area is marked. Based on the width of the rectangular blocks in the above strip area, the strip area is divided into sub-areas, and each sub-area has and only has one rectangular block; the idle areas in the above sub-areas are traversed, and for each idle area, according to the principle of from bottom to top, from left to right, and in the order of the height of the rectangular blocks from small to large, they are placed in the idle area in sequence. The specific steps are as follows: place the first rectangular block in the current queue in the lower left corner. If the rectangular block cannot be placed due to insufficient height, end the traversal of all the above sub-areas; if the rectangular block cannot be placed due to insufficient width, switch to the next one in the aforementioned sub-area sequence; place the next rectangular block in the current queue above the previous rectangular block, and repeat this step until a rectangular block cannot be placed; if it cannot be placed due to insufficient width, end the placement in the current sub-area and switch to the next one in the aforementioned sub-area sequence; if it cannot be placed due to insufficient height, use the maximum width of the rectangular blocks currently placed in the sub-area as the boundary, cut a column space vertically from the sub-area, and place the rectangular block at the bottom of the remaining space on the right side of this column space; repeat the above steps of placing in the free area. After each column is placed, merge the top free area and the top free area of ​​the left column into a new free area. For rectangular free areas spanning multiple columns, the next rectangular block is placed in this free area first. If the rectangular block cannot be placed due to insufficient height, the merged free area is discarded; if the rectangular block cannot be placed due to insufficient width, it is left and merged with the top free area of ​​the subsequent column. The above strip area is cut from the placeable area, and the above steps are repeated until all rectangular blocks are successfully placed or there is no remaining space; if there is no remaining space in the placeable area, but there are still rectangular blocks that have not been placed, the initial placement area is expanded in proportion, and all rectangular blocks are rearranged according to the above steps.

[0057] For further information, see Figure 3 , Figure 3 This is one of the schematic diagrams of the layout effect of the chip circuit layout provided in the embodiment of the present application. Figure 3As shown in the figure, the chips to be laid out include m1, m2, m3, m4, m5, m6, m7, m8, m9 and IP1, IP2, IP3, IP4, IP5, IP6, IP7, IP8, IP9, a total of 18 circuit modules. By using the rectangular block layout optimization algorithm of this scheme, we can get Figure 2 The arrangement effect.

[0058] For further information, see Figure 4 , Figure 4 This is a second schematic diagram of the layout effect of the chip circuit layout provided in the embodiment of the present application. Figure 3 When m4 observes or edits its subcircuit module, Figure 2 The visualization of Figure 3 As shown in the schematic diagram. It can be seen from the figure that the background color of the rectangular block corresponding to the m4 circuit module becomes transparent, and the rectangular modules corresponding to m4_a, m4_b and m4_c are included in the rectangular block corresponding to m4. Since the area of ​​the rectangular block corresponding to m4 will change during the expansion or folding process, at this time, it is only necessary to offset the other rectangular blocks on the right and upper sides of m4 to ensure that all circuit rectangular blocks will not cross or overlap. At the same time, the relative positions of all rectangular blocks have not changed, ensuring good consistency.

[0059] In this application, the following conventions are adopted in the process of placing circuit modules: ① Determine the visual rectangular blocks of each circuit module; ② To ensure the aesthetics of the overall placement view, all circuit modules are close to each other and separated by a given distance; ③ When placing the first layer of circuit modules of the chip for the first time, determine an initial placement area with a determined height and width based on the area of ​​the current die. The placement of each sub-circuit module follows the principle of being placed from left to right and from bottom to top in this area, that is, the first circuit module is placed in the lower left corner of the given area, and the remaining circuit modules are placed from left to right and from bottom to top in turn to find an available free area and place them. If all sub-circuit modules of this level cannot be placed in a given area, the area is expanded proportionally until all sub-circuit modules of this level can be placed; ④ When a placed circuit module is expanded, its sub-circuit modules are placed using an algorithm consistent with ③. When the area of ​​the expanded circuit module increases, other circuit modules are translated to ensure that all circuit modules do not overlap and their relative positions remain unchanged.

[0060] The embodiment of the present application provides a chip circuit layout method based on an EDA tool, the chip circuit layout method comprising: determining an initial placement rectangular area based on the area of ​​a chip to be laid out, and sorting rectangular blocks of multiple different types of circuit modules of the chip to be laid out from large to small according to height to obtain a rectangular block sequence; dividing the initial placement rectangular area based on the first rectangular block in the rectangular block sequence to determine a strip area; placing the rectangular blocks in the rectangular block sequence that meet the strip area, and dividing the strip area into multiple sub-areas based on the width of the rectangular blocks already placed in the strip area; traversing the free area in each of the sub-areas, placing the remaining rectangular blocks in the rectangular block sequence into the free area, and after filling the strip area, determining a new strip area in the remaining initial placement rectangular area based on the rectangular block with the largest height among the unplaced rectangular blocks, and after continuing to place the remaining rectangular blocks, placing the hierarchical circuits under each circuit module in the corresponding area to generate the circuit module layout of the chip to be laid out. Not only can different types of circuit modules be placed together in accordance with the circuit hierarchy, but the idle areas generated during the placement process can also be reused, so that more circuit modules can be placed in the idle areas, thereby providing greater space utilization and ultimately achieving better layout effects.

[0061] See also Figure 5 , Figure 6 , Figure 5 One of the structural schematic diagrams of a chip circuit layout device based on an EDA tool provided in an embodiment of the present application; Figure 6 The second structural diagram of a chip circuit layout device based on an EDA tool provided in an embodiment of the present application. Figure 5 As shown in , the chip circuit layout device 500 includes: The initial setting module 510 is used to determine the initial placement rectangular area based on the area of ​​the chip to be laid out, and sort the rectangular blocks of multiple different types of circuit modules of the chip to be laid out from large to small according to height to obtain a rectangular block sequence; A region division module 520, configured to divide the initial placement rectangular region based on the first rectangular block in the rectangular block sequence to determine a strip region; A rectangular block placement module 530, configured to place the rectangular blocks in the rectangular block sequence that are in accordance with the strip region, and divide the strip region into a plurality of sub-regions based on the widths of the rectangular blocks that have been placed in the strip region; The free area filling module 540 is used to traverse the free areas in each of the sub-areas, place the remaining rectangular blocks in the rectangular block sequence into the free areas, and after filling the strip area, determine a new strip area in the remaining initial placement rectangular area based on the rectangular block with the largest height among the unplaced rectangular blocks, and after continuing to place the remaining rectangular blocks, place the hierarchical circuits under each circuit module in the corresponding area to generate the circuit module layout of the chip to be laid out.

[0062] Furthermore, when the rectangular block placement module 530 is used to place the rectangular blocks in the rectangular block sequence that conform to the strip area, the rectangular block placement module 530 is specifically used to: Based on the arrangement order from left to right, the rectangular blocks with decreasing heights in the rectangular block sequence are arranged at the bottom of the strip area at preset intervals, and the rectangular blocks are stopped from being arranged when reaching the rightmost side of the strip area.

[0063] Furthermore, when the idle area filling module 540 is used to traverse the idle area in each of the sub-areas and place the remaining rectangular blocks in the rectangular block sequence into the idle area, the idle area filling module 540 is specifically used to: Based on the arrangement order from bottom to top and from left to right, the remaining rectangular blocks are arranged in the idle area in the order of small to large height; Detect whether there are multiple top idle areas in the idle area; If so, multiple top idle areas are merged to generate a new idle area, and the new idle area is continuously arranged into rectangular blocks.

[0064] Further, when the idle area filling module 540 is used for placing the remaining rectangular blocks in the idle area in the order of height from small to large based on the arrangement order from bottom to top and from left to right for the first idle area, the idle area filling module 540 is specifically used to: Detecting whether the rectangular block with the smallest height among the remaining rectangular blocks is suitable for being placed at the lower left corner of the first free area; If not, stop placing the rectangular blocks in the first free area; If so, after arranging the rectangular block with the smallest height, the next rectangular block among the remaining rectangular blocks is placed above the rectangular block with the smallest height, until the height of the rectangular blocks can no longer be placed in the first free area, then the first free area is cut vertically to determine the column space area, and the rectangular blocks continue to be arranged in the column space area.

[0065] Furthermore, when the idle area filling module 540 is used to stop placing the rectangular blocks in the first idle area, the idle area filling module 540 is specifically used to: If the height of the first idle area does not meet the height of the rectangular block with the smallest height, then the traversal of the plurality of idle areas ends; If the width of the first idle area does not satisfy the width of the rectangular block with the smallest height, the placement of the first idle area is terminated and the placement of the rectangular block in the next idle area is switched.

[0066] Furthermore, when the module 540 for filling the idle area is used to arrange the hierarchical circuits under each circuit module in a corresponding area, the module 540 for filling the idle area is specifically used to: Determine a rectangular block of hierarchical circuits under the circuit module; The rectangular blocks of the hierarchical circuit are placed in the rectangular block area where the circuit module is located. If each rectangular block of the hierarchical circuit cannot be placed in the rectangular block area where the circuit module is located, the area of ​​the rectangular block where the circuit module is located is enlarged proportionally.

[0067] Further, such as Figure 6 As shown, the chip circuit layout device 500 further includes a display module 550, and the display module 550 is used to: In response to the user's request to display the hierarchical circuit under the circuit module, the background color of the rectangular block corresponding to the circuit module is controlled to be transparent to display the rectangular block of the hierarchical circuit, and the rectangular blocks located on the right and upper sides of the circuit module are shifted. The embodiment of the present application provides a chip circuit layout device based on an EDA tool, and the chip circuit layout device includes: an initial setting module, which is used to determine an initial placement rectangular area based on the area of ​​a chip to be laid out, and to sort rectangular blocks of multiple different types of circuit modules of the chip to be laid out from large to small according to height to obtain a rectangular block sequence; an area division module, which is used to divide the initial placement rectangular area based on the first rectangular block in the rectangular block sequence to determine a strip area; and a rectangular block placement module, which is used to place the rectangular blocks in the rectangular block sequence that meet the strip area. The strip area is divided into multiple sub-areas based on the width of the rectangular blocks already placed in the strip area; a free area filling module is used to traverse the free areas in each sub-area, place the remaining rectangular blocks in the rectangular block sequence into the free area, and after the strip area is filled, determine the new strip area in the remaining initial placement rectangular area based on the rectangular block with the largest height among the unplaced rectangular blocks, and after the remaining rectangular blocks are placed, place the hierarchical circuits under each circuit module in the corresponding area to generate the circuit module layout of the chip to be laid out. Not only can different types of circuit modules be placed together while following the circuit hierarchy relationship, but the free areas generated during the placement process can also be reused, so that more circuit modules can be placed in the free area, thereby providing greater space utilization and ultimately obtaining a better layout effect.

[0068] See also Figure 7 , Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Figure 7 As shown in , the electronic device 700 includes a processor 710 , a memory 720 and a bus 730 .

[0069] The memory 720 stores machine-readable instructions executable by the processor 710. When the electronic device 700 is running, the processor 710 communicates with the memory 720 via the bus 730. When the machine-readable instructions are executed by the processor 710, the above-mentioned Figure 2 The specific implementation of the steps of the chip circuit layout method based on the EDA tool in the method embodiment shown can be found in the method embodiment, which will not be repeated here.

[0070] The present application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the computer program can execute the above-mentioned Figure 1 The specific implementation of the steps of the chip circuit layout method based on the EDA tool in the method embodiment shown can be found in the method embodiment, which will not be repeated here.

[0071] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0072] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0073] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0074] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0075] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0076] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-mentioned embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A chip circuit layout method based on EDA tools, characterized in that: The chip circuit layout method comprises: Determine an initial placement rectangular area based on the area of ​​the chip to be laid out, and sort the rectangular blocks of multiple different types of circuit modules of the chip to be laid out from large to small according to height to obtain a rectangular block sequence; Dividing the initial placement rectangular area based on the first rectangular block in the rectangular block sequence to determine a strip area; Arranging the rectangular blocks in the rectangular block sequence that match the strip area, and dividing the strip area into a plurality of sub-areas based on the widths of the rectangular blocks already arranged in the strip area; Traverse the free areas in each of the sub-areas, place the remaining rectangular blocks in the rectangular block sequence into the free areas, and after filling the strip areas, determine a new strip area in the remaining initial placement rectangular area based on the rectangular block with the largest height among the unplaced rectangular blocks, and after the remaining rectangular blocks are placed, place the hierarchical circuits under each circuit module in the corresponding areas to generate the circuit module layout of the chip to be laid out.

2. The chip circuit layout method according to claim 1, characterized in that: Placing the rectangular blocks in the rectangular block sequence that are in conformity with the strip area comprises: Based on the arrangement order from left to right, the rectangular blocks with decreasing heights in the rectangular block sequence are arranged at the bottom of the strip area at preset intervals, and the rectangular blocks are stopped from being arranged when reaching the rightmost side of the strip area.

3. The chip circuit layout method according to claim 1, characterized in that: The traversing the free area in each of the sub-areas and placing the remaining rectangular blocks in the rectangular block sequence into the free area includes: Based on the arrangement order from bottom to top and from left to right, the remaining rectangular blocks are arranged in the idle area in the order of small to large height; Detect whether there are multiple top idle areas in the idle area; If so, multiple top idle areas are merged to generate a new idle area, and the new idle area is continuously arranged into rectangular blocks.

4. The chip circuit layout method according to claim 3, characterized in that: For the first idle area, placing the remaining rectangular blocks in the idle area in ascending order of height based on the order of placement from bottom to top and from left to right includes: Detecting whether the rectangular block with the smallest height among the remaining rectangular blocks is suitable for being placed at the lower left corner of the first free area; If not, stop placing the rectangular blocks in the first free area; If so, after arranging the rectangular block with the smallest height, the next rectangular block among the remaining rectangular blocks is placed above the rectangular block with the smallest height, until the height of the rectangular blocks can no longer be placed in the first free area, then the first free area is cut vertically to determine the column space area, and the rectangular blocks continue to be arranged in the column space area.

5. The chip circuit layout method according to claim 4, characterized in that: The step of stopping placing the rectangular blocks in the first idle area includes: If the height of the first idle area does not satisfy the height of the rectangular block with the smallest height, then the traversal of the plurality of idle areas ends; If the width of the first idle area does not satisfy the width of the rectangular block with the smallest height, the placement of the first idle area is terminated and the placement of the rectangular block in the next idle area is switched.

6. The chip circuit layout method according to claim 1, characterized in that: The hierarchical circuits under each circuit module are arranged in corresponding areas, including: Determine a rectangular block of hierarchical circuits under the circuit module; The rectangular blocks of the hierarchical circuit are placed in the rectangular block area where the circuit module is located. If each rectangular block of the hierarchical circuit cannot be placed in the rectangular block area where the circuit module is located, the area of ​​the rectangular block where the circuit module is located is enlarged proportionally.

7. The chip circuit layout method according to claim 1, characterized in that: After generating the circuit module layout of the chip to be laid out, the chip circuit layout method further includes: In response to the user's request to display the hierarchical circuit under the circuit module, the background color of the rectangular block corresponding to the circuit module is controlled to be transparent to display the rectangular block of the hierarchical circuit, and the rectangular blocks located on the right and upper sides of the circuit module are shifted.

8. A chip circuit layout device based on EDA tools, characterized in that: The chip circuit layout device comprises: An initial setting module, used to determine an initial placement rectangular area based on the area of ​​the chip to be laid out, and sort the rectangular blocks of multiple different types of circuit modules of the chip to be laid out from large to small according to height to obtain a rectangular block sequence; A region division module, used for dividing the initial placement rectangular region based on the first rectangular block in the rectangular block sequence to determine a strip region; A rectangular block placement module, used for placing the rectangular blocks in the rectangular block sequence that are in line with the strip area, and dividing the strip area into a plurality of sub-areas based on the width of the rectangular blocks already placed in the strip area; The module for filling the free area is used to traverse the free area in each of the sub-areas, place the remaining rectangular blocks in the rectangular block sequence into the free area, and after filling the strip area, determine the new strip area in the remaining initial placement rectangular area based on the rectangular block with the largest height among the unplaced rectangular blocks, and after continuing to place the remaining rectangular blocks, place the hierarchical circuits under each circuit module in the corresponding area to generate the circuit module layout of the chip to be laid out.

9. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate through the bus, and the machine-readable instructions are executed by the processor to execute the steps of the chip circuit layout method based on the EDA tool as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the chip circuit layout method based on an EDA tool as claimed in any one of claims 1 to 7 are executed.

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