Register resource management method and device for GPU and medium

Abstract

The invention provides a register resource management method and device for a GPU and a medium, and belongs to the technical field of electric digital data processing. According to the method, a first memory space corresponding to an actual calculation task can be applied to GPU equipment based on a pre-compiled first executable file; the first memory space is used for storing corresponding calculation parameters and a second executable file; the second executable file is used for the GPU equipment to execute the actual calculation task based on the calculation parameters and the preset register; generating a calculation parameter mapping binary tree according to the memory address of the calculation parameter in the first memory space, and writing a root node pointer of the calculation parameter mapping binary tree into a GPU initialization parameter structural body of the GPU equipment to obtain a corresponding GPU initialization parameter; and writing a memory head address of the GPU device for storing the GPU initialization parameters into the preset register so as to enable the GPU device to execute the second executable file.

Description

Technical Field

[0001] The present application relates to the technical field of electronic digital data processing, and in particular to a register resource management method, device and medium for a graphics processing unit (GPU). Background Art

[0002] As computing demands continue to increase, GPUs play an important role in many fields by using a large number of threads to improve the parallelism of operations. However, their performance is limited by storage resources.

[0003] Specifically, taking NVIDIA V100 GPU as an example, its hardware specifications limit the maximum size of registers that each streaming multiprocessor (SM) can control to 256KB, and each SM is allowed to run up to 2048 threads simultaneously. After conversion, it is equivalent to each thread occupying up to 32 32-bit register resources.

[0004] The inventors found that in actual operations, if the computing tasks processed by each thread require more registers, the number of threads running simultaneously will have to be reduced, which will in turn reduce the number of schedulable threads and ultimately reduce the parallelism of the threads, affecting the full utilization of the overall computing performance of the GPU. Summary of the invention

[0005] The embodiments of the present application provide a register resource management method, device and medium for a GPU, which are used to solve the technical problem that threads consume register resources unreasonably, resulting in reduced thread parallelism in the system, in a computing environment where the GPU is limited by storage resources.

[0006] On the one hand, an embodiment of the present application provides a register resource management method for a GPU, the method comprising: Based on the pre-compiled first executable file, apply to the GPU device for a first memory space corresponding to the actual computing task; the first memory space is used to store corresponding computing parameters and a second executable file; the second executable file is used by the GPU device to execute the actual computing task based on the computing parameters and preset registers; Generate a computing parameter mapping binary tree according to the memory address of the computing parameter in the first memory space, and write the root node pointer of the computing parameter mapping binary tree into the GPU initialization parameter structure of the GPU device to obtain the corresponding GPU initialization parameter; The first memory address of the GPU device storing the GPU initialization parameters is written into the preset register so that the GPU device executes the second executable file; wherein the preset register is used to pass the pre-stored parameters when the GPU device executes the kernel function corresponding to the actual computing task.

[0007] In one implementation of the present application, based on a pre-compiled first executable file, applying to a GPU device for a first memory space corresponding to an actual computing task specifically includes: Determine, through the first executable file, various computing parameters corresponding to the actual computing task and the second executable file; wherein the parameter type of the computing parameter includes one or more of the following: source operation data, destination operation data; Generate a memory request according to the number of parameters of the calculation parameter and the second executable file, and send the request to the GPU device, so that the GPU device allocates video memory according to the memory request to generate the first memory space; After applying for a first memory space corresponding to an actual computing task from a GPU device based on a pre-compiled first executable file, the method further includes: The source operation data and the second executable file are stored in the first memory space, and the memory address corresponding to the data stored in the first memory space is recorded.

[0008] In one implementation of the present application, a computing parameter mapping binary tree is generated according to the memory address of the computing parameter in the first memory space, and a root node pointer of the computing parameter mapping binary tree is written into a GPU initialization parameter structure of the GPU device to obtain the corresponding GPU initialization parameter, specifically including: Constructing a binary tree data structure according to the parameter type and parameter quantity corresponding to the calculation parameters; Storing each of the memory addresses of the calculation parameters in the first memory space into corresponding nodes of the binary tree data structure to generate a calculation parameter mapping binary tree; The root node pointer of the computing parameter mapping binary tree is written into a preset position of the GPU initialization parameter structure to obtain the GPU initialization parameter.

[0009] In one implementation of the present application, writing the first memory address of the GPU device storing the GPU initialization parameters into the preset register specifically includes: After obtaining the GPU initialization parameters, applying for a second memory space from the GPU device; Writing the GPU initialization parameters into the second memory space, and obtaining the memory first address of the second memory space; The memory first address is written into the preset register.

[0010] In one implementation of the present application, the GPU device executes the second executable file, specifically including: The GPU device reads the parameters pre-stored in the preset register through a pre-written startup program file to determine the memory first address of the GPU initialization parameter; The GPU device uses the memory first address as a base address and reads a corresponding preset offset address to determine the root node pointer; wherein the preset offset address read using the memory first address as a base address is a write position of the GPU initialization parameter; The GPU device traverses the computing parameter mapping binary tree according to the root node pointer and the parameter type and parameter quantity of the actual computing task, obtains the node data value corresponding to each binary tree node, and determines the computing parameter corresponding to each node data value based on the correspondence between the binary tree nodes and the computing parameters, and then executes the actual computing task.

[0011] In one implementation of the present application, generating a computing parameter mapping binary tree according to the memory address of the computing parameter in the first memory space specifically includes: Determine the memory addresses corresponding to the source operation data and the second executable file in the first memory space, and add the corresponding memory addresses to the first linked list according to the memory application order; Adding the memory address corresponding to the target operation data in the first memory space to the second linked list according to the memory application order; Based on the spatial locality principle of the program and the second executable file in the first linked list, the root node data of the calculation parameter mapping binary tree is determined, and the memory addresses corresponding to the remaining source operation data in the first linked list are used as left subtree node data and added to the binary tree in sequence; The memory address of the target operation data in the second linked list is added to the binary tree in sequence as the right subtree node data to obtain the calculation parameter mapping binary tree; wherein the number of binary tree nodes of the calculation parameter mapping binary tree is equal to the number of parameters of the calculation parameters.

[0012] In one implementation of the present application, based on the spatial locality principle of the program and the second executable file in the first linked list, the root node data of the calculation parameter mapping binary tree is determined, and the memory addresses corresponding to the remaining source operation data in the first linked list are used as left subtree node data and added to the binary tree in sequence, specifically including: Based on the spatial locality principle of the program, determining the memory address of the second executable file in the first linked list; Determine, in the first linked list, a memory address with the shortest storage address distance from the memory address of the second executable file as the root node data, and remove the memory address of the second executable file and the root node data from the first linked list; wherein the storage address distance is the difference between the two memory addresses; Determine the memory address in the first linked list that has the shortest distance from the storage address of the root node data, which is the first left subtree node data, and remove the first left subtree node data from the first linked list until the first linked list is empty, thereby obtaining the root node and each left subtree node of the calculation parameter mapping binary tree; wherein the first left subtree node data is the node data of the left subtree node of the root node.

[0013] In one implementation of the present application, when the GPU device executes the second executable file, the calculation parameter mapping binary tree is traversed by a pre-order traversal algorithm.

[0014] On the other hand, an embodiment of the present application further provides a register resource management device for a GPU, the device comprising: At least one processor; and a memory in communication with the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute a register resource management method for a GPU as described above.

[0015] On the other hand, an embodiment of the present application further provides a non-volatile computer storage medium storing computer executable instructions, wherein the computer executable instructions can execute a register resource management method for a GPU as described above.

[0016] Compared with the prior art, the present invention has the following significant effects: (1) This application applies for memory space through a pre-compiled first executable file and constructs a binary tree for computing parameter mapping, thereby achieving fast access and efficient management of computing parameters. At the same time, the memory first address of the GPU initialization parameter is written into a preset register, so that the GPU device can flexibly access the required parameters when executing the kernel function. This design not only improves memory utilization efficiency and reduces memory fragmentation, but also significantly enhances the flexibility of register use, reduces the direct dependence of computing tasks on register resources, and enables the GPU to meet the needs of complex computing tasks for register resources while maintaining high thread parallelism.

[0017] (2) The first memory space of the GPU device stores the calculation parameters and the second executable file, which helps to ensure that the GPU device has sufficient video memory resources before executing the calculation task, avoiding resource shortage or improper allocation. The binary tree structure helps to quickly find and access the calculation parameters, thereby improving the calculation efficiency. In the computing environment where the GPU is limited by storage resources, the technical problem of unreasonable consumption of register resources by threads, which leads to a decrease in the system's thread parallelism, is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 A flowchart of a method for managing register resources for a GPU in an embodiment of the present application is shown; Figure 2 A schematic diagram of a system structure corresponding to a register resource management method for a GPU in an embodiment of the present application; Figure 3 A schematic diagram of a GPU memory in a register resource management method for a GPU in an embodiment of the present application; Figure 4 A schematic diagram of a second linked list in a register resource management method for a GPU in an embodiment of the present application; Figure 5 A schematic diagram of a binary tree for mapping calculation parameters in a register resource management method for a GPU in an embodiment of the present application; Figure 6 A schematic diagram of a program design flow of an executable file in a register resource management method for a GPU in an embodiment of the present application; Figure 7 This is a structural diagram of a register resource management device for a GPU in an embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0020] The heterogeneous programming model divides executable programs into device-side (GPU) programs and host-side programs, with the host side being the central processing unit (CPU). The current mainstream heterogeneous programming frameworks, such as the Compute Unified Device Architecture (CUDA) and the Open Computing Language (OpenCL), require the host-side program to explicitly apply for device-side memory in the programming model, and write the data to be processed and the bin file executed on the device side into the applied device-side memory; then write the parameters such as the address and data length of each parameter in the device-side memory into the GPU register, and each thread completes the execution of the computing task in the bin file according to the data passed into the register. When the number of parameters required for the computing task on the device side is too large, a large amount of register resources will be required.

[0021] The embodiments of the present application provide a register resource management method, device and medium for a GPU, which are used to solve the technical problem that threads consume register resources unreasonably, resulting in reduced thread parallelism in the system, in a computing environment where the GPU is limited by storage resources.

[0022] The following describes in detail various embodiments of the present application in conjunction with the accompanying drawings.

[0023] The embodiment of the present application provides a register resource management method for a GPU, which is applied to an electronic device including a GPU and a CPU, such as Figure 1 As shown, the method may include steps S101-S103: S101, based on a pre-compiled first executable file, applying to a GPU device for a first memory space corresponding to an actual computing task.

[0024] The first memory space is used to store corresponding calculation parameters and a second executable file; the second executable file is used by the GPU device to perform actual calculation tasks based on the calculation parameters and preset registers.

[0025] It should be noted that the register resource management method for GPU in the present application is described with the CPU as the execution subject. The execution subject is not limited to the CPU but may also be other types of devices, and the present application does not make any specific limitation on this.

[0026] The first executable file is generated by compiling a host-side program using a compiler for the CPU host side. When the GPU is required to participate in the actual computing task, the CPU will execute the first executable file to complete steps S101-S103. When the CPU executes the first executable file, it will configure the GPU parameters. The CPU can use the GPU driver application programming interface (Application Programming Interface, API), such as (CUDA Runtime API or OpenCL API), to apply for the memory of the GPU device and generate a first memory space in the video memory DDR of the GPU device. Among them, the system structure diagram composed of the host side (CPU) and the device side (GPU device), such as Figure 2 As shown, the device side includes a GPU and DDR, and the host side and the device side are connected via a PCIe bus.

[0027] In the embodiment of the present application, applying for the first memory space corresponding to the actual computing task from the GPU device based on the pre-compiled first executable file specifically includes: The first executable file is used to determine the various computing parameters and the second executable file corresponding to the actual computing task. The parameter types of the computing parameters include one or more of the following: source operation data and destination operation data. According to the number of parameters of the computing parameters and the second executable file, a memory request is generated and sent to the GPU device, so that the GPU device allocates video memory according to the memory request and generates a first memory space.

[0028] In other words, the CPU can determine the calculation parameters involved in the actual calculation task, and the calculation parameters include the source operation data, the destination operation data, and the parameter type of the combination of the two. For example, the actual calculation task of the vector addition kernel function: the vector addition kernel function vecadd (__global const uint32_t *a, __global const uin32_t *b, __globaluint32_t *c), this function includes two source operation data and one destination operation data, the parameter type is 2, and the number of parameters is three. At the same time, the CPU can also determine the pre-compiled second executable file of the GPU, which can be understood as a bin file on the GPU device side, which enables the GPU to perform the actual calculation task in a reasonable way of consuming register resources. Subsequently, the CPU will apply for memory in the GPU device according to the number of calculation parameters and the second executable file, so that the memory applied for can store the calculation parameters and the second executable file.

[0029] In layman's terms, source operation data is the data required by the GPU to perform actual computing tasks, and destination operation data is the data obtained or generated after performing the actual computing tasks.

[0030] In another embodiment of the present application, after applying for a first memory space corresponding to an actual computing task from a GPU device based on a pre-compiled first executable file, the method further includes: The source operation data and the second executable file are stored in the first memory space, and the memory address corresponding to the data stored in the first memory space is recorded.

[0031] That is to say, when the CPU enables the GPU to perform the actual computing task, it needs to first write the source operation data and the second executable file into the first memory space. Figure 3 The GPU memory shown, the code segment from start through kernel_func to end, corresponds to the memory address of the second executable file, the kernel parameter node data corresponds to the binary tree node of the calculation parameter mapping binary tree of this application, and the kernel parameter root node data corresponds to the binary tree root node. In the figure, the number and letter combinations such as 0x9000_3000, 0x9000_3004, 0x9000_3008 are memory addresses.

[0032] In addition, the destination operation data also has a memory address on the device side (GPU). For example, an addition calculation task contains destination operation data, which can be understood as the calculation result of the addition. A memory address must be allocated in advance for storage.

[0033] For example, the above vector addition kernel function requires three operands in total. The CPU applies for memory from the device, and obtains the storage addresses of the three parameters, arg1_addr, arg2_addr, and arg3_addr, respectively.

[0034] S102, generating a computing parameter mapping binary tree according to the memory address of the computing parameter in the first memory space, and writing the root node pointer of the computing parameter mapping binary tree into the GPU initialization parameter structure of the GPU device to obtain corresponding GPU initialization parameters.

[0035] In an embodiment of the present application, a calculation parameter mapping binary tree is generated according to the memory address of the calculation parameter in the first memory space, and the root node pointer of the calculation parameter mapping binary tree is written into the GPU initialization parameter structure of the GPU device to obtain the corresponding GPU initialization parameters, specifically including: According to the parameter type and parameter quantity corresponding to the calculation parameters, a binary tree data structure is constructed. Each memory address of the calculation parameters in the first memory space is stored in the corresponding node of the binary tree data structure to generate a calculation parameter mapping binary tree. The root node pointer of the calculation parameter mapping binary tree is written into the preset position of the GPU initialization parameter structure to obtain the GPU initialization parameter.

[0036] In other words, the CPU can determine the memory addresses allocated for all computing parameters in the first memory space, and then construct a binary tree according to the parameter type and parameter quantity, and generate binary tree nodes for the above-mentioned source operation data and destination operation data respectively. The node data in the binary tree node is the memory address to which the computing parameter is allocated. For example, the CPU can preset a correspondence list between parameter types and parameter quantities and binary tree nodes, such as a correspondence list in which the parameter type is the source operation data for the left subtree node, the destination operation data for the right subtree node, and the number of binary tree nodes is equal to the number of parameters of the computing parameters. The binary tree is constructed through the correspondence list to obtain a computing parameter mapping binary tree. Subsequently, the root node pointer of the computing parameter mapping binary tree is written to the preset position of the GPU initialization parameter structure. Figure 3 In the example, the root node pointer of 0x9000_3000, that is, the storage address of the root node, is written into the GPU initialization parameters. The preset position can be set during actual use, and this application does not make specific restrictions on this.

[0037] In another embodiment of the present application, generating a computing parameter mapping binary tree according to the memory address of the computing parameter in the first memory space specifically includes: Determine the memory addresses corresponding to the source operation data and the second executable file in the first memory space, and add the corresponding memory addresses to the first linked list in the order of memory application. Add the memory addresses corresponding to the destination operation data in the first memory space to the second linked list in the order of memory application. Based on the spatial locality principle of the program and the second executable file in the first linked list, determine the root node data of the calculation parameter mapping binary tree, and use the memory addresses corresponding to the remaining source operation data in the first linked list as the left subtree node data, and add them to the binary tree in sequence. Use the memory address of the destination operation data in the second linked list as the right subtree node data, and add them to the binary tree in sequence to obtain the calculation parameter mapping binary tree. Among them, the number of binary tree nodes of the calculation parameter mapping binary tree is equal to the number of parameters of the calculation parameters.

[0038] That is, the present application can group the memory addresses corresponding to the source operation data and the second executable file into a group to generate a first linked list, and group the memory addresses corresponding to the destination operation data into a group to generate a second linked list (such as Figure 4 When generating the linked list, the memory addresses may be arranged in the order of application, or in other orders, which is not specifically limited in this application.

[0039] This application searches for root node data based on the spatial locality principle of the program, then generates the left subtree node of the binary tree through the first linked list, obtains the right subtree node through the second linked list, and then constructs a calculation parameter mapping binary tree.

[0040] More specifically, based on the spatial locality principle of the program and the second executable file in the first linked list, the root node data of the calculation parameter mapping binary tree is determined, and the memory addresses corresponding to the remaining source operation data in the first linked list are used as the left subtree node data, and are sequentially added to the binary tree, specifically including: Based on the principle of spatial locality of the program, the memory address of the second executable file in the first linked list is determined. The memory address in the first linked list with the smallest storage address distance to the memory address of the second executable file is determined as the root node data, and the memory address of the second executable file and the root node data are removed from the first linked list. Among them, the storage address distance is the difference between the two memory addresses. The memory address in the first linked list with the smallest storage address distance to the root node data is determined as the first left subtree node data, and the first left subtree node data is removed from the first linked list until the first linked list is empty, and the root node and each left subtree node of the calculation parameter mapping binary tree are obtained. Among them, the first left subtree node data is the node data of the left subtree node of the root node.

[0041] That is to say, in accordance with the principle of spatial locality of the program, the present application takes the memory address of the second executable file as a reference, first calculates the memory address in the first linked list with the smallest storage address distance from the reference memory address, that is, finds the source operation data closest to the storage address of the second executable file. For example, the memory address of the second executable file is addr_bin in the first linked list, and the memory address of the source operation data with the smallest storage address distance is addr_src_7 in the first linked list, then the memory address corresponding to addr_src_7 is used as the root node data to create a binary tree. Then addr_bin and addr_src_7 in the first linked list are deleted from the first linked list List_order_SRC. Next, search the remaining source operation data in the first linked list, find the memory address with the smallest distance to the storage address of addr_src_7, such as addr_src_5 in the first linked list, get the left subtree node of the root node, and remove addr_src_5 from the first linked list; then find the memory address with the smallest distance to the storage address of addr_src_5... until the first linked list is empty, and get the root node and left subtree of the binary tree.

[0042] According to the above execution process, the second linked list is searched, so that each memory address in the second linked list is used as the right subtree node. For example, read the second linked list List_order_DST, and insert addr_dst_1 corresponding to the memory address of the destination operation data in the linked list into the binary tree as the right subtree node of the binary tree root node. And delete addr_dst_1 from List_order_DST, and repeat this step until the List_order_DST linked list is empty. At this time, all the memory addresses of the destination operation data are stored in the binary tree. The generated binary tree is as follows: Figure 5 shown.

[0043] In the embodiment of the present application, after constructing the calculation parameter mapping binary tree by the above binary tree generation rule, in order to improve the efficiency and calculation speed of GPU traversal of the binary tree, when the GPU device of the present application executes the second executable file, the above calculation parameter mapping binary tree is traversed by the pre-order traversal algorithm. Thus, the source operation data and the destination operation data can be obtained efficiently and orderly.

[0044] S103, writing the first address of the memory storing the GPU initialization parameters of the GPU device into a preset register, so that the GPU device executes the second executable file.

[0045] The preset register is used to transfer pre-stored parameters when the GPU device executes the kernel function corresponding to the actual computing task, for example, the preset memory transfers the first memory address of the GPU initialization parameter.

[0046] In the embodiment of the present application, the first memory address of the GPU device storing the GPU initialization parameters is written into the preset register, specifically including: After obtaining the GPU initialization parameters, apply for the second memory space from the GPU device, write the GPU initialization parameters into the second memory space, obtain the memory first address of the second memory space, and write the memory first address into the preset register.

[0047] In other words, after obtaining the GPU initialization parameters after writing the root node pointer, the CPU can further apply to the GPU device for a second memory space for storing the GPU initialization parameters. In addition, the application also configures other conventional startup parameters, such as grid and block size, to start the GPU kernel function. The application writes the memory first address of the second memory space storing the GPU initialization parameters into the preset register. The memory first address is as follows: Figure 30x9002_4000 in the second executable file, write the GPU initialization parameters to the 0x9002_4000 position, and write 0x9002_4000 to the gpu_args register. When the GPU executes the assembly startup program in the second executable file, it will first read the preset gpu_args register to obtain the content of the GPU initialization parameter structure.

[0048] Furthermore, the GPU device executes the second executable file, specifically including: The GPU device reads the parameters pre-stored in the preset register through a pre-written startup program file to determine the memory first address of the GPU initialization parameters. The GPU device uses the memory first address as the base address and reads the corresponding preset offset address to determine the root node pointer. Among them, the preset offset address read with the memory first address as the base address is the write location of the GPU initialization parameter. The GPU device traverses the calculation parameter mapping binary tree according to the root node pointer and the parameter type and number of the actual calculation task, obtains the node data value corresponding to each binary tree node, and determines the calculation parameters corresponding to each node data value based on the correspondence between the binary tree nodes and the calculation parameters, and then executes the actual calculation task.

[0049] That is to say, the GPU device determines the calculation parameters corresponding to the actual calculation task through the second executable file, including the parameter type and the number of parameters. Execute the startup program file such as start.S, and obtain the storage address of the GPU initialization parameter as 0x9002_4000 by reading the data of the gpu_agrs register, and then use this storage address as the base address to read the preset offset address 0x9002_4004, which corresponds to the root node pointer of the binary tree of the calculation parameter mapping, and obtains the memory address of the root node pointer as 0x9000_3000. Then, the GPU device performs the traversal operation of the binary tree of the calculation parameter mapping through the pre-order traversal algorithm to obtain the data values ​​of each node. At the same time, the GPU of this application presets the corresponding relationship between the binary tree nodes and the calculation parameters, such as the root node and the left subtree node as the source operation data, and the right subtree node as the destination operation data, to obtain each calculation parameter, and then the GPU kernel function performs the actual calculation task according to the obtained calculation parameters.

[0050] Furthermore, after waiting for the GPU to complete the computing task and read the output data, the CPU can release the memory resources applied for on the GPU device so that subsequent computing tasks can reasonably utilize the GPU register resources.

[0051] Through the above scheme, when the CPU host program runs, completes the GPU initialization parameter configuration and starts the GPU kernel function, the GPU kernel function assembly startup program can address the binary tree root node of the storage device calculation parameters through the base address of the GPU initialization parameter storage space during execution, and obtain the storage address of all calculation parameters by traversing, so as to obtain all calculation parameter data and pass it to the device program for calculation. Since the parameter address of this application is obtained by indirect addressing (i.e., binary tree traversal) instead of being directly stored in registers, the consumption of register resources by calculation parameters is reduced. And more register resources of this application can be used for other purposes (such as temporary variables and index calculations), thereby improving the computing efficiency of the GPU and the parallelism of threads.

[0052] This application applies for memory space through a pre-compiled first executable file and constructs a binary tree of computing parameter mapping, thereby achieving fast access and efficient management of computing parameters. At the same time, the memory first address of the GPU initialization parameter is written into a preset register, so that the GPU device can flexibly access the required parameters when executing the kernel function. This design not only improves memory utilization efficiency and reduces memory fragmentation, but also significantly enhances the flexibility of register use, reduces the direct dependence of computing tasks on register resources, and enables the GPU to meet the needs of complex computing tasks for register resources while maintaining high thread parallelism.

[0053] In addition, the first memory space of the GPU device stores the calculation parameters and the second executable file, which helps to ensure that the GPU device has sufficient video memory resources before executing the calculation task, avoiding resource shortage or improper allocation. The binary tree structure helps to quickly find and access the calculation parameters, improving the calculation efficiency. In the computing environment where the GPU is limited by storage resources, it solves the technical problem that the thread consumes register resources unreasonably, resulting in a reduction in the system's thread parallelism.

[0054] Figure 6 The flowchart of the programming method for generating a first executable file and a second executable file respectively on the host side (CPU) and the device side (GPU device) of the embodiment of the present application is as follows: Figure 6 As shown: Host side: S601, write a host-side program to implement device-side memory application, and write source operands and device-side bin file data into the applied device-side memory; S602, store the device-side memory addresses of all calculation parameters applied for in a binary tree data structure. Write the root node pointer of the binary tree to the preset position of the GPU initialization parameter structure. S603, the host program applies to the device side for memory space to store GPU initialization parameters, and writes GPU initialization parameters into the applied device-side memory, and writes the applied memory first address into the register gpu_args specified by the device side. Then configure other regular startup parameters to start GPU kernel function execution. S604, use the compiler for the CPU host side to compile the host-side program to generate a second executable file.

[0055] Device side: S701, write the GPU device side program, determine the parameter type and number of the source operands and destination operands involved in the calculation, and design the calculation task. S702, write the start.S assembly startup program, implement the pre-order traversal of the binary tree in the assembly program, and obtain the corresponding number of source operation data and destination operation data from the parameter storage area according to the parameter type and parameter number determined in S701 and the binary tree root node pointer provided by the host side. S703, use the compiler for the GPU device to compile the source files designed in S701 and S702 to generate a second executable file.

[0056] Figure 7 A schematic diagram of a register resource management device for a GPU provided in an embodiment of the present application is shown in FIG. Figure 7 As shown, the device includes: At least one processor; and a memory in communication with the at least one processor. The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to: Based on the pre-compiled first executable file, apply to the GPU device for the first memory space corresponding to the actual computing task. The first memory space is used to store the corresponding computing parameters and the second executable file. The second executable file is used for the GPU device to perform the actual computing task based on the computing parameters and the preset register. According to the memory address of the computing parameters in the first memory space, a computing parameter mapping binary tree is generated, and the root node pointer of the computing parameter mapping binary tree is written into the GPU initialization parameter structure of the GPU device to obtain the corresponding GPU initialization parameters. The first memory address of the GPU device storing the GPU initialization parameters is written into the preset register so that the GPU device executes the second executable file. Among them, the preset register is used for the GPU device to pass the pre-stored parameters when executing the kernel function corresponding to the actual computing task.

[0057] The embodiment of the present application further provides a non-volatile computer storage medium storing computer executable instructions, wherein the computer executable instructions are configured as follows: Based on the pre-compiled first executable file, apply to the GPU device for the first memory space corresponding to the actual computing task. The first memory space is used to store the corresponding computing parameters and the second executable file. The second executable file is used for the GPU device to perform the actual computing task based on the computing parameters and the preset register. According to the memory address of the computing parameters in the first memory space, a computing parameter mapping binary tree is generated, and the root node pointer of the computing parameter mapping binary tree is written into the GPU initialization parameter structure of the GPU device to obtain the corresponding GPU initialization parameters. The first memory address of the GPU device storing the GPU initialization parameters is written into the preset register so that the GPU device executes the second executable file. Among them, the preset register is used for the GPU device to pass the pre-stored parameters when executing the kernel function corresponding to the actual computing task.

[0058] Each embodiment in this application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device and medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0059] The devices and media provided in the embodiments of the present application correspond one-to-one to the methods. Therefore, the devices and media also have similar beneficial technical effects as the corresponding methods. Since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the devices and media will not be repeated here.

[0060] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0061] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A register resource management method for a GPU, characterized in that: The method comprises: Based on the pre-compiled first executable file, apply to the GPU device for a first memory space corresponding to the actual computing task; the first memory space is used to store corresponding computing parameters and a second executable file; the second executable file is used by the GPU device to execute the actual computing task based on the computing parameters and preset registers; Generate a computing parameter mapping binary tree according to the memory address of the computing parameter in the first memory space, and write the root node pointer of the computing parameter mapping binary tree into the GPU initialization parameter structure of the GPU device to obtain the corresponding GPU initialization parameter; The first memory address of the GPU device storing the GPU initialization parameters is written into the preset register so that the GPU device executes the second executable file; wherein the preset register is used to pass the pre-stored parameters when the GPU device executes the kernel function corresponding to the actual computing task.

2. A register resource management method for a GPU according to claim 1, characterized in that: Based on the pre-compiled first executable file, applying to the GPU device for a first memory space corresponding to the actual computing task specifically includes: Determine, through the first executable file, various computing parameters corresponding to the actual computing task and the second executable file; wherein the parameter type of the computing parameter includes one or more of the following: source operation data, destination operation data; Generate a memory request according to the number of parameters of the calculation parameter and the second executable file, and send the request to the GPU device, so that the GPU device allocates video memory according to the memory request to generate the first memory space; After applying for a first memory space corresponding to an actual computing task from a GPU device based on a pre-compiled first executable file, the method further includes: The source operation data and the second executable file are stored in the first memory space, and the memory address corresponding to the data stored in the first memory space is recorded.

3. The register resource management method for a GPU according to claim 1, characterized in that: Generate a computing parameter mapping binary tree according to the memory address of the computing parameter in the first memory space, and write the root node pointer of the computing parameter mapping binary tree into the GPU initialization parameter structure of the GPU device to obtain the corresponding GPU initialization parameter, specifically including: Constructing a binary tree data structure according to the parameter type and parameter quantity corresponding to the calculation parameters; Storing each of the memory addresses of the calculation parameters in the first memory space into corresponding nodes of the binary tree data structure to generate a calculation parameter mapping binary tree; The root node pointer of the computing parameter mapping binary tree is written into a preset position of the GPU initialization parameter structure to obtain the GPU initialization parameter.

4. The method for managing register resources for a GPU according to claim 1, characterized in that: Writing the first memory address of the GPU device storing the GPU initialization parameters into the preset register specifically includes: After obtaining the GPU initialization parameters, applying for a second memory space from the GPU device; Writing the GPU initialization parameters into the second memory space, and obtaining the memory first address of the second memory space; The memory first address is written into the preset register.

5. The method for managing register resources for a GPU according to claim 1, characterized in that: The GPU device executes the second executable file, specifically including: The GPU device reads the parameters pre-stored in the preset register through a pre-written startup program file to determine the memory first address of the GPU initialization parameter; The GPU device uses the memory first address as a base address and reads a corresponding preset offset address to determine the root node pointer; wherein the preset offset address read using the memory first address as a base address is a write position of the GPU initialization parameter; The GPU device traverses the computing parameter mapping binary tree according to the root node pointer and the parameter type and parameter quantity of the actual computing task, obtains the node data value corresponding to each binary tree node, and determines the computing parameter corresponding to each node data value based on the correspondence between the binary tree nodes and the computing parameters, and then executes the actual computing task.

6. The method for managing register resources for a GPU according to claim 2, characterized in that: Generating a computing parameter mapping binary tree according to the memory address of the computing parameter in the first memory space specifically includes: Determine the memory addresses corresponding to the source operation data and the second executable file in the first memory space, and add the corresponding memory addresses to the first linked list according to the memory application order; Adding the memory address corresponding to the target operation data in the first memory space to the second linked list according to the memory application order; Based on the spatial locality principle of the program and the second executable file in the first linked list, the root node data of the calculation parameter mapping binary tree is determined, and the memory addresses corresponding to the remaining source operation data in the first linked list are used as left subtree node data and added to the binary tree in sequence; The memory address of the target operation data in the second linked list is added to the binary tree in sequence as the right subtree node data to obtain the calculation parameter mapping binary tree; wherein the number of binary tree nodes of the calculation parameter mapping binary tree is equal to the number of parameters of the calculation parameters.

7. A register resource management method for a GPU according to claim 6, characterized in that: Based on the spatial locality principle of the program and the second executable file in the first linked list, determining the root node data of the calculation parameter mapping binary tree, and using the memory addresses corresponding to the remaining source operation data in the first linked list as left subtree node data, and sequentially adding them to the binary tree, specifically includes: Based on the spatial locality principle of the program, determining the memory address of the second executable file in the first linked list; Determine, in the first linked list, a memory address with the shortest storage address distance from the memory address of the second executable file as the root node data, and remove the memory address of the second executable file and the root node data from the first linked list; wherein the storage address distance is the difference between the two memory addresses; Determine the memory address in the first linked list that has the shortest distance from the storage address of the root node data, which is the first left subtree node data, and remove the first left subtree node data from the first linked list until the first linked list is empty, thereby obtaining the root node and each left subtree node of the calculation parameter mapping binary tree; wherein the first left subtree node data is the node data of the left subtree node of the root node.

8. The method for managing register resources for a GPU according to claim 7, characterized in that: When the GPU device executes the second executable file, the calculation parameter mapping binary tree is traversed by a pre-order traversal algorithm.

9. A register resource management device for a GPU, characterized in that: The device comprises: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute a register resource management method for a GPU as described in any one of claims 1 to 8.

10. A non-volatile computer storage medium storing computer executable instructions, characterized in that: The computer executable instructions can execute a register resource management method for a GPU as described in any one of claims 1 to 8.

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