Pixel circuit and driving method thereof, array substrate and display panel

Abstract

The invention discloses a pixel circuit and a driving method thereof, an array substrate and a display panel. The pixel circuit comprises a driving module, wherein the first end of the driving module is connected with a first power line; wherein in each driving period, the voltages of the first power supply signal on the first power line are different in at least two driving stages; the threshold value compensation module is connected between the second end of the driving module and the control end of the driving module, and the threshold value compensation module is used for performing resetting and threshold value compensation on the driving module in a time-sharing manner; the first power supply signal comprises a second reset voltage and a first power supply voltage; the first power line is used for transmitting the second reset voltage and the first power voltage to the first end of the driving module in a time-sharing manner. According to the technical scheme, the use performance of the display panel is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, an array substrate, and a display panel. Background Art

[0002] With the rapid development of display technology, the application of display products using organic light emitting devices (OLED) is becoming more and more widespread.

[0003] However, the performance of current OLED display panels needs to be improved. Summary of the invention

[0004] The present invention provides a pixel circuit and a driving method thereof, an array substrate, and a display panel, so as to improve the performance of the display panel.

[0005] According to one aspect of the present invention, a pixel circuit is provided, the pixel circuit comprising:

[0006] A driving module, wherein a first end of the driving module is connected to a first power line; wherein in each driving cycle, a first power signal on the first power line has different voltages in at least two driving stages;

[0007] A threshold compensation module, wherein the threshold compensation module is connected between the second end of the driving module and the control end of the driving module, and the threshold compensation module is used to reset and threshold compensate the driving module in a time-sharing manner; the first power supply signal includes a second reset voltage and a first power supply voltage; and the first power supply line is used to transmit the second reset voltage and the first power supply voltage to the first end of the driving module in a time-sharing manner.

[0008] Optionally, in a reset phase of one of the driving cycles, the first power signal is the second reset voltage, and in the remaining phases of the driving cycle, the first power signal is the first power voltage.

[0009] Optionally, the voltage of the first power signal jumps from the first power voltage to a second reset voltage in a first sub-phase of the reset phase;

[0010] Preferably, the threshold compensation module is used to transmit the second reset voltage to the control end of the driving module in the second sub-stage of the reset stage to reset the control end of the driving module;

[0011] Preferably, the second sub-stage is located after the first sub-stage;

[0012] Preferably, the threshold compensation module is further used to perform threshold compensation on the driving module in the threshold compensation stage, and the voltage of the first power supply signal jumps from the second reset voltage to the first power supply voltage in the threshold compensation stage;

[0013] Preferably, the pixel circuit further comprises a data writing module and a coupling module; the first end of the data writing module is connected to the data voltage or the first reset voltage, and the coupling module is connected between the second end of the data writing module and the control end of the driving module; the data writing module is used to transmit the data voltage and the first reset voltage to the coupling module in a time-sharing manner;

[0014] Preferably, the data writing module is used to transmit the first reset voltage to the coupling module in the third sub-stage of the reset stage, so as to reset the control end of the driving module through the coupling module;

[0015] Preferably, the third sub-stage is located after the second sub-stage;

[0016] Preferably, in one of the reset phases, the duration of the second sub-phase is longer than the duration of the third sub-phase;

[0017] Preferably, in one of the reset phases, the duration of the second sub-phase is longer than the duration of the first sub-phase.

[0018] Optionally, the data writing module includes a data writing transistor, a first electrode of the data writing transistor is connected to the data voltage and / or the first reset voltage, and a second electrode of the data writing transistor is connected to the coupling module; a control electrode of the data writing transistor is connected to a first scanning line; and the data writing transistor is used to transmit the data voltage and the first reset voltage to the coupling module in a time-sharing manner;

[0019] Preferably, the data writing transistor is used to transmit the data voltage to the coupling module in the data writing phase, and transmit the first reset voltage to the coupling module in at least a part of the time period of the reset phase;

[0020] Preferably, the data writing transistor is used to transmit the first reset voltage to the coupling module in a third sub-phase of the reset phase.

[0021] Optionally, the data writing module includes a data writing transistor and a reset transistor;

[0022] The control electrode of the data writing transistor is connected to the first scanning line, the first electrode of the data writing transistor is connected to the data voltage, and the second electrode of the data writing transistor is connected to the coupling module; the data writing transistor is used to transmit the data voltage to the coupling module in the data writing stage, and the coupling module is used to couple the data voltage to the control end of the driving module;

[0023] The first electrode of the reset transistor is connected to the first reset voltage, and the second electrode of the reset transistor is connected to the coupling module; the reset transistor is used to transmit the first reset voltage to the coupling module during at least part of the reset phase;

[0024] Preferably, the reset transistor is used to transmit the first reset voltage to the coupling module in a third sub-phase of the reset phase.

[0025] Optionally, the control electrode of the reset transistor is connected to the second scan line;

[0026] Preferably, the threshold compensation module comprises a threshold compensation transistor, the control electrode of the threshold compensation transistor is connected to the third scan line; the threshold compensation transistor is connected between the second end of the driving module and the control end of the driving module;

[0027] Preferably, the type of the threshold compensation transistor is the same as the type of the reset transistor;

[0028] Preferably, the threshold compensation transistor and the reset transistor are both of N-type or P-type;

[0029] Preferably, the start time of the effective level of the second scanning signal on the second scanning line is delayed by one line time relative to the start time of the effective level of the third scanning signal on the third scanning line; the second scanning signal has the same period as the third scanning signal, and the second scanning signal has the same waveform as the third scanning signal;

[0030] Preferably, the second scan line and the third scan line extend along the first direction, and in two adjacent pixel circuits in the second direction, the third scan line corresponding to one pixel circuit is connected to the second scan line corresponding to the other pixel circuit; wherein the first direction intersects the second direction.

[0031] Optionally, the second reset voltage is lower than the first reset voltage.

[0032] Optionally, the driving module includes a driving transistor, a control electrode of the driving transistor is connected to the coupling module, a first electrode of the driving transistor is connected to the first power supply signal, and a second electrode of the driving transistor is connected to the threshold compensation module;

[0033] Preferably, the coupling module comprises a coupling capacitor, a first electrode of the coupling capacitor is connected to the control electrode of the driving transistor, and a second electrode of the coupling capacitor is connected to the data writing module;

[0034] Preferably, the pixel circuit further includes a storage module;

[0035] The first end of the storage module is connected to the first power signal, and the second end of the storage module is connected to the second end of the coupling module or the control end of the driving module;

[0036] The first end of the coupling module is connected to the control end of the driving module;

[0037] Preferably, the pixel circuit further comprises a light emitting control module, a control end of the light emitting control module is connected to a light emitting control line, and the light emitting control module is connected between the second end of the driving module and the light emitting element;

[0038] Preferably, the storage module comprises a storage capacitor, a first electrode of the storage capacitor is connected to the first power supply signal, and a second electrode of the storage capacitor is connected to the second end of the coupling module;

[0039] Preferably, the light emitting control module comprises a light emitting control transistor, a control electrode of the light emitting control transistor is connected to the light emitting control line, and the light emitting control transistor is connected between the second end of the driving module and the light emitting element.

[0040] Optionally, the driving module comprises a driving transistor, and an active layer material of the driving transistor and the data writing transistor is different;

[0041] Preferably, the active layer of the driving transistor includes a polysilicon semiconductor material, and the active layer of the data writing transistor includes an oxide semiconductor material.

[0042] According to another aspect of the present invention, an array substrate is provided, the array substrate comprising:

[0043] substrate;

[0044] A first active layer, located on one side of the substrate, the first active layer comprising a first active region, the first active region being provided with a channel region of a driving transistor and a channel region of a threshold compensation transistor;

[0045] a first conductive layer, located on a side of the first active layer away from the substrate, the first conductive layer comprising a first metal block forming a control electrode of the driving transistor and a third scan line forming a control electrode of the threshold compensation transistor, the third scan line extending along a first direction, a channel region of the driving transistor located at an orthographic projection of the first metal block on the first active region, a channel region of the threshold compensation transistor located at an orthographic projection of the third scan line on the first active region, the first metal block connected to a first electrode of the threshold compensation transistor through a first connecting portion, and a second electrode of the driving transistor connected to a second electrode of the threshold compensation transistor through the first active region;

[0046] a second conductive layer, located on a side of the first conductive layer away from the substrate, the second conductive layer comprising a second metal block forming a second electrode of a coupling capacitor, the first metal block being reused as a first electrode of the coupling capacitor, and an orthographic projection of the second metal block on the substrate covering an orthographic projection of the first metal block on the substrate;

[0047] A second active layer, located on a side of the second conductive layer away from the substrate, the second active layer comprising a third active region, wherein the third active region is provided with a channel region of a data writing transistor;

[0048] a fourth conductive layer, located on a side of the second active layer away from the substrate, the fourth conductive layer comprising a first scan line forming a control electrode of the data writing transistor, the first scan line extending along the first direction, a channel region of the data writing transistor located at a positive projection of the first scan line on the third active region, and a second electrode of the data writing transistor connected to the second metal block via a second connecting portion;

[0049] The first active layer and the second active layer are made of different materials.

[0050] Optionally, the first active layer further includes a second active region, the second active region includes a channel region of a reset transistor, and a second electrode of the reset transistor is connected to a second electrode of the coupling capacitor;

[0051] The first conductive layer further includes a second scan line extending along the first direction, and the channel region of the reset transistor is located at a positive projection of the second scan line on the second active region;

[0052] Preferably, the extension direction of the channel region of the threshold compensation transistor is perpendicular to the extension direction of the channel region of the reset transistor;

[0053] Preferably, in the second direction, the threshold compensation transistor channel region and the reset transistor channel region are distributed on both sides of the channel region of the driving transistor, and the first direction intersects with the second direction;

[0054] Preferably, the first metal block comprises a first protrusion, the first protrusion is located at one end of the first metal block facing the threshold compensation transistor, and the first electrode of the threshold compensation transistor is connected to the first protrusion;

[0055] Preferably, the second metal block comprises a second protrusion, the second protrusion is located at one end of the second metal block facing the reset transistor, and the second electrode of the reset transistor is electrically connected to the second protrusion.

[0056] Optionally, the second active layer further includes a fourth active region, the fourth active region includes a channel region of the light emitting control transistor, the third active region and the fourth active region are arranged at intervals, and both extend along the second direction;

[0057] Preferably, the orthographic projection of the third active region on the substrate and the orthographic projection of the fourth active region on the substrate partially overlap with the orthographic projection of the first active region on the substrate;

[0058] The fourth conductive layer further includes a light emitting control line extending along the first direction, and a channel region of the light emitting control transistor is located at a positive projection of the light emitting control line on the fourth active region;

[0059] Preferably, the channel region of the driving transistor is in an X-shape, and the third active region is in an L-shape.

[0060] Optionally, the array substrate further includes a third conductive layer located between the second conductive layer and the second active layer;

[0061] The third conductive layer includes a third metal block forming a first electrode of the storage capacitor, the orthographic projection of the third metal block on the substrate covers the orthographic projection of the second metal block on the substrate, and the second metal block is reused as the second electrode of the storage capacitor;

[0062] In the first direction, the adjacent third metal blocks are connected to each other, the third metal blocks connected to each other are reused as a first power line to transmit a first power signal, and the first electrode of the storage capacitor is connected to the first electrode of the driving transistor;

[0063] Preferably, the third metal block comprises a third protrusion, and the third protrusion extends toward the third active area;

[0064] Preferably, the first connecting portion and the second connecting portion are both located in the third conductive layer;

[0065] Preferably, the orthographic projections of the third active region and the fourth active region on the substrate are located within the orthographic projection range of the third metal block on the substrate;

[0066] Preferably, the third scan line comprises a main body portion and an extension portion, the main body portion and the channel region of the threshold compensation transistor extend in the same direction, the extension direction of the extension portion is perpendicular to the extension direction of the main body portion, and the channel region of the threshold compensation transistor is located at the orthographic projection of the extension portion on the first active region;

[0067] Preferably, the width of the main body portion is the same as that of the first scanning line.

[0068] Optionally, the second conductive layer further includes a plurality of reset power signal lines extending along the first direction, the orthographic projection of the reset power signal lines on the substrate partially overlaps with the orthographic projection of the first electrode of the reset transistor on the substrate, and the first electrode of the reset transistor is connected to the reset power signal lines; or

[0069] The third conductive layer further comprises a plurality of reset power signal lines, the orthographic projections of the reset power signal lines on the substrate partially overlap with the orthographic projections of the first electrode of the reset transistor on the substrate, and the first electrode of the reset transistor is connected to the reset power signal lines;

[0070] The reset power signal line extends along the first direction, and one end of the second active region away from the second metal block is electrically connected to one of the reset power signal lines.

[0071] Optionally, the array substrate further includes a first insulating layer located between the first active layer and the first conductive layer, a second insulating layer located between the first conductive layer and the second conductive layer, and a third insulating layer located between the second conductive layer and the third conductive layer;

[0072] The second electrode of the reset transistor is connected to the second metal block through a first via hole penetrating the first insulating layer and the second insulating layer, the first electrode of the reset transistor is connected to the reset power signal line through a second via hole, and the second via hole penetrates the first insulating layer and the second insulating layer, or the second via hole penetrates the first insulating layer, the second insulating layer and the third insulating layer;

[0073] Preferably, the first electrode of the driving transistor is connected to the third metal block through a third via hole, and the third via hole passes through the first insulating layer, the second insulating layer and the third insulating layer;

[0074] Preferably, the control electrode of the driving transistor is connected to the first connecting portion through a fourth via hole, and the first connecting portion is further connected to the first electrode of the threshold compensation transistor through a fifth via hole;

[0075] The fourth via hole penetrates the second insulating layer and the third insulating layer, and the fifth via hole sequentially penetrates the third insulating layer, the second insulating layer and the first insulating layer.

[0076] Optionally, the array substrate further includes a fourth conductive layer and a fifth conductive layer located on a side of the third conductive layer away from the substrate; the array substrate further includes a fourth insulating layer located between the third conductive layer and the second active layer, a fifth insulating layer located between the second active layer and the fourth conductive layer, and a sixth insulating layer located on a side of the fourth conductive layer away from the substrate;

[0077] The fifth conductive layer includes a plurality of data transmission lines extending along the second direction, and the first electrode of the data writing transistor is connected to the data transmission line through a sixth via hole penetrating the sixth insulating layer and the fifth insulating layer;

[0078] Preferably, the fifth conductive layer further includes a third connection portion extending along the first direction and a fourth connection portion extending along the second direction, the second electrode of the data writing transistor is connected to the third connection portion through a seventh via hole, an end of the third connection portion away from the seventh via hole is connected to the second connection portion through an eighth via hole, and the second connection portion is connected to the second electrode of the coupling capacitor through a ninth via hole;

[0079] The eighth via hole sequentially penetrates the sixth insulating layer, the fifth insulating layer and the fourth insulating layer, the seventh via hole penetrates the sixth insulating layer and the fifth insulating layer, and the ninth via hole penetrates the third insulating layer;

[0080] Preferably, the ninth via hole overlaps with the orthographic projection of the first via hole on the substrate;

[0081] Preferably, the first electrode of the light emitting control transistor is connected to the fourth connecting portion through a tenth via hole, and an end of the fourth connecting portion away from the tenth via hole is connected to the fifth connecting portion through an eleventh via hole;

[0082] The tenth via hole sequentially penetrates the sixth insulating layer and the fifth insulating layer, and the eleventh via hole sequentially penetrates the sixth insulating layer, the fifth insulating layer and the fourth insulating layer;

[0083] Preferably, the second electrode of the light emitting control transistor is electrically connected to the first electrode of the light emitting element through a twelfth via hole penetrating the sixth insulating layer and the fifth insulating layer.

[0084] According to another aspect of the present invention, a method for driving a pixel circuit is provided, for driving the pixel circuit according to any embodiment of the present invention, the method comprising:

[0085] In the reset stage, the threshold compensation module transmits the first power supply signal to the control end of the driving module;

[0086] In the threshold compensation stage, the threshold compensation module performs threshold compensation on the driving module based on the first power supply signal;

[0087] Among them, the voltage of the first power signal in the reset stage and the remaining stages is different, and the first power signal includes a second reset voltage and a first power voltage; the first power line is used to transmit the second reset voltage and the first power voltage to the first end of the driving module in a time-sharing manner.

[0088] Optionally, in the reset phase, the first power signal is the second reset voltage, and in other phases, the first power signal is the first power voltage;

[0089] In the reset stage, the threshold compensation module transmits the first power supply signal to the control end of the driving module, including:

[0090] In the reset phase, the threshold compensation module transmits the second reset voltage to the control terminal of the driving module;

[0091] In the threshold compensation stage, the threshold compensation module performs threshold compensation on the driving module based on the first power supply signal, including:

[0092] In the threshold compensation stage, the threshold compensation module performs threshold compensation on the driving module based on the first power supply voltage.

[0093] Optionally, in the reset stage, the threshold compensation module transmits the first power supply signal to the control end of the driving module, and the data writing module transmits the first reset voltage to the coupling module, including:

[0094] In a first sub-stage of the reset stage, the voltage of the first power signal jumps from the first power voltage to the second reset voltage;

[0095] In the second sub-stage of the reset stage, the threshold compensation module transmits the second reset voltage to the control end of the driving module to reset the control end of the driving module;

[0096] In a third sub-phase of the reset phase, the data writing module transmits the first reset voltage to the coupling module;

[0097] Preferably, the second reset voltage is less than the first reset voltage;

[0098] Preferably, in one of the reset phases, the duration of the second sub-phase is longer than the duration of the third sub-phase;

[0099] Preferably, in one of the reset phases, the duration of the second sub-phase is longer than the duration of the first sub-phase.

[0100] According to another aspect of the present invention, a display panel is provided. The display panel includes the array substrate described in any embodiment of the present invention.

[0101] The technical solution of the embodiment of the present invention is to set the voltage of the first power signal to be different in at least two driving stages, so that the first power line can transmit different voltages in time. When the first power signal is the second reset voltage, the second reset voltage is transmitted to the control end of the driving module through the driving module and the threshold compensation module, and the threshold compensation module resets the driving module. When the first power signal is the first power voltage, the voltage of the control end of the driving module can be made to be a voltage related to the first power voltage and the threshold voltage of the transistor in the driving module, and the threshold compensation module performs threshold compensation on the driving module. In this way, the threshold compensation module resets and compensates the threshold of the driving module in time. Therefore, there is no need to set more modules to achieve compensation and reset, which reduces the number of transistors, which is conducive to improving the pixel density of the display panel corresponding to the pixel circuit. Therefore, on the basis of ensuring that the pixel density of the display panel is large, the normal operation of the pixel circuit is guaranteed, and the performance of the display panel is improved.

[0102] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0103] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0104] Figure 1 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0105] Figure 2 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0106] Figure 3 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0107] Figure 4 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0108] Figure 5 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0109] Figure 6 is a schematic structural diagram of a display panel corresponding to a pixel circuit provided in an embodiment of the present invention;

[0110] Figure 7 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0111] Figure 8 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0112] Fig. 9 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0113] Fig.10 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0114] Fig.11 is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0115] Fig.12 is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0116] Fig.13 is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0117] Fig.14 is a schematic diagram of a top view structure of an array substrate provided by an embodiment of the present invention;

[0118] Fig.15 It is a schematic diagram of the layout structure of a first active layer and a first conductive layer of an array substrate provided by an embodiment of the present invention;

[0119] Fig.16 It is a schematic diagram of the layout structure of a second conductive layer and a third conductive layer of an array substrate provided by an embodiment of the present invention;

[0120] Fig.17 It is a schematic diagram of the layout structure of a second active layer and a fourth conductive layer of an array substrate provided by an embodiment of the present invention;

[0121] Fig.18 It is a schematic structural diagram of a first active layer, a first conductive layer, a second conductive layer and a third conductive layer of an array substrate provided by an embodiment of the present invention;

[0122] Fig.19It is a schematic diagram of the layout structure of a second conductive layer, a third conductive layer, a second active layer and a fourth conductive layer of an array substrate provided by an embodiment of the present invention;

[0123] Fig. 20 is a schematic diagram of a top view structure of another array substrate provided by an embodiment of the present invention;

[0124] Fig.21 yes Fig.14 Cross-sectional view along the direction a1-a2;

[0125] Fig. 22 It is a schematic diagram of the layout structure of a first active layer, a first conductive layer and a third active layer of an array substrate provided by an embodiment of the present invention;

[0126] Fig.23 yes Fig.18 Cross-sectional view along the b1-b2 direction;

[0127] Fig.24 yes Fig.18 Cross-sectional view along the direction e1-e2;

[0128] Fig.25 yes Fig.19 Cross-sectional view along the f1-f2 direction;

[0129] Fig.26 It is a schematic diagram of the layout structure of a third conductive layer, a second active layer and a sixth insulating layer of an array substrate provided by an embodiment of the present invention;

[0130] Fig. 27 is a schematic diagram of the layout structure of a fifth conductive layer of an array substrate provided by an embodiment of the present invention;

[0131] Fig.28 yes Fig.14 Cross-sectional view along the h1-h2 direction;

[0132] Fig.29 yes Fig.14 Cross-sectional view along the h3-h4 direction;

[0133] Fig.30 is a flow chart of a driving method of a pixel circuit provided by an embodiment of the present invention;

[0134] Fig.31 It is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0135] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0136] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0137] As mentioned in the background technology, the existing display panel has the problem that the performance needs to be improved. The inventor has found that the reason for this problem is that with the development of display technology, the application of display panels is becoming more and more extensive, but the display panel is affected by the array process and the film layer structure, and cannot achieve a higher pixel density (Pixels Per Inch, PPI), so it is impossible to display images at a higher density. The lower the display density, the lower the realism, so that the display device cannot achieve a higher realism, so that the display effect of the display device is poor, affecting the performance of the display device. The display panel of the display device includes a plurality of pixel circuits and light-emitting elements. The pixel circuit can generate a driving current to drive the light-emitting element to emit light. In order to achieve a higher pixel density, the number of transistors used in the pixel circuit is reduced in the related art, for example, the pixel circuit is a 2T1C pixel circuit, but the reduction in the number of transistors reduces the function of the pixel circuit, for example, it is impossible to complete the initialization or threshold compensation functions, resulting in residual charge and threshold drift causing the driving current to change, so that the luminous brightness of the light-emitting element is much different from the target brightness, so that the picture display effect of the display panel is poor, affecting the performance of the display panel.

[0138] In view of the above technical problem, an embodiment of the present invention provides a pixel circuit. Figure 1 is a schematic diagram of a pixel circuit provided by an embodiment of the present invention, with reference to Figure 1 , the pixel circuit includes:

[0139] A driving module 110, wherein a first end of the driving module 110 is connected to a first power line VDD; wherein in each driving cycle, a first power signal on the first power line VDD has different voltages in at least two driving stages;

[0140] A threshold compensation module 120 is connected between the second end of the driving module 110 and the control end of the driving module. The threshold compensation module 120 is used to reset and threshold compensate the driving module 110 in a time-sharing manner; the first power supply signal includes a second reset voltage and a first power supply voltage; and the first power supply line VDD is used to transmit the second reset voltage and the first power supply voltage to the first end of the driving module 110 in a time-sharing manner.

[0141] Among them, a driving cycle of the pixel circuit is a display frame of the display panel formed by the pixel circuit. A driving cycle of the pixel circuit includes multiple driving stages, such as a reset stage, a data writing stage, a compensation stage and a light-emitting stage, etc., which are not limited here. The pixel circuit can be connected to the light-emitting element 200 to drive the corresponding light-emitting element 200 to emit light. For example, the second end of the driving module 110 is connected to the first end of the light-emitting element 200, and the second end of the light-emitting element 200 is connected to the second power line VSS. The driving module 110 can generate a driving current so that the light-emitting element 200 emits light in response to the driving current. Among them, the first power supply signal includes a first power supply voltage, for example, the first power supply voltage is a positive voltage, and the second power supply voltage on the second power line VSS is a negative voltage or zero; or the first power supply voltage is a negative voltage or zero, and the second power supply voltage on the second power line VSS is a positive voltage, which is not limited in this embodiment.

[0142] Specifically, the first power line VDD can transmit the first power signal, and by setting the voltage of the first power signal to be different in at least two driving stages, the first power line VDD can transmit different voltages in time-sharing. The first power signal includes a second reset voltage and a first power voltage, and the second reset voltage is less than the first power voltage. When the first power signal is the second reset voltage, the second reset voltage is transmitted to the control end of the driving module 110 through the driving module 110 and the threshold compensation module 120, so as to achieve the reset of the control end of the driving module 110, that is, the threshold compensation module 120 resets the driving module 110. When the first power signal is the first power voltage, the first power voltage charges the control end of the driving module 110 through the driving module 110 and the threshold compensation module 120, so that the voltage of the control end of the driving module 110 is a voltage related to the first power voltage and the threshold voltage of the transistor in the driving module 110, so as to achieve the threshold compensation of the driving module 110, that is, the threshold compensation module 120 performs the threshold compensation on the driving module 110. In this way, the threshold compensation module 120 resets and compensates the driving module 110 in time. Therefore, it is not necessary to set up more modules to achieve compensation and reset, and the number of transistors is reduced, which is conducive to improving the pixel density of the display panel corresponding to the pixel circuit. Therefore, on the basis of fewer devices in the pixel circuit, it is ensured that the pixel circuit can be reset and compensated, that is, on the basis of ensuring a high pixel density of the display panel, the normal operation of the pixel circuit is guaranteed, and the performance of the display panel is improved.

[0143] Furthermore, the second reset voltage can be transmitted to the first end of the light emitting element 200 through the driving module 110 to achieve the reset of the light emitting element 200. It is not necessary to separately set a corresponding reset device for the light emitting element 200, thereby further improving the pixel density of the display panel corresponding to the pixel circuit. Moreover, when the first power supply signal is the first power supply voltage, the first power supply voltage, the driving module 110, the light emitting element 200 and the second power supply voltage can form a current path, so that the driving module 110 generates a driving current, and the light emitting element 200 can emit light in response to the driving current.

[0144] The technical solution of this embodiment is to set the voltage of the first power signal to be different in at least two driving stages, so that the first power line can transmit different voltages in time-sharing. When the first power signal is the second reset voltage, the second reset voltage is transmitted to the control end of the driving module through the driving module and the threshold compensation module, and the threshold compensation module resets the driving module. When the first power signal is the first power voltage, the voltage of the control end of the driving module can be made to be a voltage related to the first power voltage and the threshold voltage of the transistor in the driving module, and the threshold compensation module performs threshold compensation on the driving module. In this way, the threshold compensation module resets and compensates the threshold of the driving module in time-sharing. There is no need to set more modules to achieve compensation and reset, which reduces the number of transistors and is conducive to improving the pixel density of the display panel corresponding to the pixel circuit. Therefore, on the basis of ensuring that the pixel density of the display panel is large, the normal operation of the pixel circuit is guaranteed, and the performance of the display panel is improved.

[0145] Based on the above technical solution, optionally, in a reset phase of a driving cycle, the first power signal is the second reset voltage, and in the remaining phases of the driving cycle, the first power signal is the first power voltage.

[0146] Specifically, a driving cycle of a pixel circuit refers to the time from the end of the light emission of the light-emitting element of the pixel circuit in the previous frame to the end of the light emission in this frame, which specifically includes a reset stage, and may also include a compensation stage, a data writing stage, and a light-emitting stage, etc. By setting it in the reset stage, the first power supply signal is the second reset voltage, and the second reset voltage is transmitted to the control end of the driving module 110 through the driving module 110 and the threshold compensation module 120, so as to achieve the reset of the control end of the driving module 110 in the reset stage. In the remaining stages, the first power supply signal is the first power supply voltage, so that the threshold compensation module 120 uses the first power supply voltage to perform threshold compensation on the driving module 110, so that the first power supply voltage, the driving module 110, the light-emitting element 200 and the second power supply voltage can form a current path, so that the driving module 110 can generate a driving current.

[0147] On the basis of the above technical solutions, optionally, the voltage of the first power supply signal jumps from the first power supply voltage to the second reset voltage in the first sub-stage of the reset stage. In this way, at the beginning of the reset stage, the first power supply signal becomes the second reset voltage, so that the driving module 110 is reset according to the second reset voltage, eliminating the influence of the light-emitting voltage of the previous frame on the driving module 110.

[0148] Optionally, the threshold compensation module 120 is used to transmit a second reset voltage to the control end of the driving module 110 in the second sub-stage of the reset stage, so as to reset the control end of the driving module 110 .

[0149] Specifically, the second sub-stage is located after the first sub-stage. After the first power supply signal becomes the second reset voltage, the threshold compensation module 120 transmits the second reset voltage to the control end of the driving module 110 in the second sub-stage of the reset stage, that is, the second reset voltage is transmitted to the control end of the driving module 110 through the driving module 110 and the threshold compensation module 120, which can clear the residual voltage of the first end and the control end of the driving module 110, thereby resetting the driving module 110.

[0150] Optionally, the threshold compensation module 120 is further used to perform threshold compensation on the driving module 110 in the threshold compensation stage, and the voltage of the first power supply signal jumps from the second reset voltage to the first power supply voltage in the threshold compensation stage.

[0151] Specifically, in the threshold compensation stage, the voltage of the first power supply signal jumps from the second reset voltage to the first power supply voltage, and the first power supply voltage charges the control end of the driving module 110 through the driving module 110 and the threshold compensation module 120, so that the voltage of the control end of the driving module 110 is a voltage related to the first power supply voltage and the threshold voltage of the transistor in the driving module 110, thereby realizing threshold compensation for the driving module 110, that is, the threshold compensation module 120 performs threshold compensation on the driving module 110.

[0152] On the basis of the above technical solutions, Figure 2 is a schematic diagram of a structure of another pixel circuit provided by an embodiment of the present invention. Figure 2 The pixel circuit also includes a data writing module 130 and a coupling module 140; the first end of the data writing module 130 is connected to the data voltage Vdata or the first reset voltage Vini, and the coupling module 140 is connected between the second end of the data writing module 130 and the control end of the driving module 110; the data writing module 130 is used to transmit the data voltage Vdata and the first reset voltage Vini to the coupling module 140 in a time-sharing manner.

[0153] For example, a first end of the coupling module 140 is connected to the control end of the driving module 110 , and a second end of the coupling module 140 is connected to the second end of the data writing module 130 .

[0154] Specifically, the first end of the data writing module 130 can be connected to the data voltage Vdata and the first reset voltage Vini in time division, so that the data writing module 130 can transmit the data voltage Vdata and the first reset voltage Vini to the second end of the coupling module 140 in time division. The coupling module 140 can couple the first reset voltage Vini and the data voltage Vdata to the control end of the driving module 110 in time division to achieve the reset and data writing of the control end of the driving module 110. For example, in the reset stage, the data writing module 130 transmits the first reset voltage Vini to the second end of the coupling module 140, and the coupling module 140 couples the first reset voltage Vini to the control end of the driving module 110 to achieve the reset of the driving module 110. In the data writing stage, the data writing module 130 transmits the data voltage Vdata to the second end of the coupling module 140, and the coupling module 140 couples the data voltage Vdata to the control end of the driving module 110, so that in the light-emitting stage, the driving module 110 can generate a driving current according to the data voltage Vdata, so that the light-emitting element 200 can emit light in response to the driving current.

[0155] Optionally, the data writing module 130 is used to transmit the first reset voltage Vini to the coupling module 140 in the third sub-stage of the reset stage, so as to reset the control end of the driving module 110 through the coupling module 140. In this way, through the coupling effect of the coupling module 140, the control end of the driving module 110 can be reset in the reset stage, so as to realize the control of the potential of the control end of the driving module 110.

[0156] Optionally, the third sub-stage is located after the second sub-stage.

[0157] Specifically, in the second sub-stage, after the threshold compensation module 120 resets the control end of the driving module 110, the first end and the control end of the driving module 110 are at the second reset voltage. By setting the third sub-stage after the second sub-stage, and the data writing module 130 transmitting the first reset voltage Vini to the coupling module 140 in the third sub-stage of the reset stage, for example, the driving module 110 requires a lower voltage for reset, and the first reset voltage Vini is greater than the second reset voltage, then in the third sub-stage, through the coupling effect of the coupling module 140, the voltage of the control end of the driving module 110 is slightly pulled up, but still at a lower voltage, to achieve the reset of the control end of the driving module 110. For example, if the driving module 110 requires a higher voltage for reset, and the first reset voltage Vini is less than the second reset voltage, then in the third sub-stage, through the coupling effect of the coupling module 140, the voltage of the control end of the driving module 110 is slightly pulled down, but still at a higher voltage, to achieve the reset of the control end of the driving module 110.

[0158] Optionally, in a reset phase, the duration of the second sub-phase is longer than the duration of the third sub-phase. In this way, the time for resetting the driver module 110 using the second reset voltage is longer, so that the potential of the control end of the driver module 110 is closer to the second reset voltage, and the control end of the driver module 110 is better reset.

[0159] Optionally, in a reset phase, the duration of the second sub-phase is longer than that of the first sub-phase. The first sub-phase is mainly a phase of voltage jump, which is shorter, and the second sub-phase is longer, so that the second reset voltage can be more fully written to the control end of the driving module 110, so that the potential of the control end of the driving module 110 is closer to the second reset voltage, and the control end of the driving module 110 is better reset.

[0160] Based on the above technical solution, the possible structure of the data writing module 130 is described below, but it is not intended to limit the present application.

[0161] In one embodiment, Figure 3 is a schematic diagram of a structure of another pixel circuit provided by an embodiment of the present invention. Figure 3 The data writing module 130 includes a data writing transistor T1, a first electrode of the data writing transistor T1 is connected to the data voltage Vdata and / or the first reset voltage Vini, and a second electrode of the data writing transistor T1 is connected to the coupling module 140; a control electrode of the data writing transistor T1 is connected to the first scanning line S1; the data writing transistor T1 is used to transmit the data voltage Vdata and the first reset voltage Vini to the coupling module 140 in a time-sharing manner.

[0162] Specifically, the data writing transistor T1 can transmit the data voltage Vdata and the first reset voltage Vini to the second end of the coupling module 140 in a time-sharing manner according to the first scanning signal of the first scanning line S1. The coupling module 140 can couple the first reset voltage Vini and the data voltage Vdata to the control end of the driving module 110 in a time-sharing manner to achieve the reset and data writing of the control end of the driving module 110. The data writing transistor T1 can be an N-type transistor or a P-type transistor. Figure 3 The case where the data writing transistor T1 is an N-type transistor is shown in the figure, but this is not limited to the above.

[0163] Optionally, refer to Figure 3 The data writing transistor T1 is used to transmit the data voltage Vdata to the coupling module 140 in the data writing phase, and transmit the first reset voltage Vini to the coupling module 140 in at least a part of the reset phase.

[0164] Specifically, in the data writing stage, the data writing transistor T1 transmits the data voltage Vdata to the second end of the coupling module 140, and the coupling module 140 couples the data voltage Vdata to the control end of the driving module 110, so that in the light emitting stage, the driving module 110 can generate a driving current according to the data voltage Vdata, so that the light emitting element 200 can emit light in response to the driving current.

[0165] During at least part of the reset phase, the data writing transistor T1 transmits the first reset voltage Vini to the coupling module 140, for example, to the second end of the coupling module 140, so as to reset the second end of the coupling module 140. The coupling module 140 can couple the first reset voltage Vini to the control end of the driving module 110, so as to reset the driving module 110.

[0166] Optionally, refer to Figure 3 The data writing transistor T1 is used to transmit the first reset voltage Vini to the coupling module 140 in the third sub-phase of the reset phase.

[0167] Specifically, in the second sub-stage, after the threshold compensation module 120 resets the control end of the driving module 110, the control end of the driving module 110 is at the second reset voltage. In the third sub-stage of the reset stage, the data writing transistor T1 transmits the first reset voltage Vini to the coupling module 140. For example, if the driving module 110 requires a lower voltage for reset, and the first reset voltage Vini is greater than the second reset voltage, then in the third sub-stage, through the coupling effect of the coupling module 140, the voltage of the control end of the driving module 110 is slightly raised, but still at a lower voltage, so as to achieve the reset of the control end of the driving module 110.

[0168] In another embodiment, Figure 4 is a schematic diagram of a structure of another pixel circuit provided by an embodiment of the present invention. Figure 4 , the data writing module 130 includes a data writing transistor T1 and a reset transistor T2;

[0169] The control electrode of the data writing transistor T1 is connected to the first scanning line S1, the first electrode of the data writing transistor T1 is connected to the data voltage Vdata, and the second electrode of the data writing transistor T1 is connected to the coupling module 140; the data writing transistor T1 is used to transmit the data voltage Vdata to the coupling module 140 in the data writing stage, and the coupling module 140 is used to couple the data voltage Vdata to the control end of the driving module 110;

[0170] The first electrode of the reset transistor T2 is connected to the first reset voltage Vini, and the second electrode of the reset transistor T2 is connected to the coupling module 140; the reset transistor T2 is used to transmit the first reset voltage Vini to the coupling module 140 during at least part of the reset phase.

[0171] Specifically, during at least a portion of the reset phase, the reset transistor T2 is turned on, and the first reset voltage Vini is transmitted to the coupling module 140, for example, to the second end of the coupling module 140, so as to reset the second end of the coupling module 140. The coupling module 140 can couple the first reset voltage Vini to the control end of the driving module 110, so as to reset the driving module 110.

[0172] In the data writing stage, the first scanning signal on the first scanning line S1 controls the data writing transistor T1 to turn on, and the data writing transistor T1 transmits the data voltage Vdata to the second end of the coupling module 140. The coupling module 140 couples the data voltage Vdata to the control end of the driving module 110, so that in the light emitting stage, the driving module 110 can generate a driving current according to the data voltage Vdata, so that the light emitting element 200 can emit light in response to the driving current.

[0173] Optionally, refer to Figure 4 The reset transistor T2 is used to transmit the first reset voltage Vini to the coupling module 140 in the third sub-phase of the reset phase.

[0174] Specifically, in the second sub-stage, after the threshold compensation module 120 resets the control end of the driving module 110, the control end of the driving module 110 is at the second reset voltage. In the third sub-stage of the reset stage, the reset transistor T2 transmits the first reset voltage Vini to the coupling module 140. For example, if the driving module 110 requires a lower voltage for reset, and the first reset voltage Vini is greater than the second reset voltage, in the third sub-stage, through the coupling effect of the coupling module 140, the voltage of the control end of the driving module 110 is slightly raised, but still at a lower voltage, so as to achieve the reset of the control end of the driving module 110.

[0175] On the basis of the above technical solution, optionally, refer to Figure 4 , the control electrode of the reset transistor T2 is connected to the second scan line S2. In this way, the reset transistor T2 can be turned on or off according to the second scan signal on the second scan line S2, so that when the reset transistor T2 is turned on in response to the second scan signal, the second end of the coupling module 140 and the control end of the driving module 110 can be reset.

[0176] Optionally, refer to Figure 4The threshold compensation module 120 includes a threshold compensation transistor T3 , the control electrode of the threshold compensation transistor T3 is connected to the third scan line S3 ; the threshold compensation transistor T3 is connected between the second end of the driving module 110 and the control end of the driving module 110 .

[0177] Specifically, when the first power signal is the second reset voltage, the third scan signal on the third scan line S3 controls the threshold compensation transistor T3 to turn on, and the second reset voltage is transmitted to the control end of the driving module 110 through the driving module 110 and the threshold compensation transistor T3, so as to achieve the reset of the control end of the driving module 110, that is, the threshold compensation transistor T3 resets the driving module 110. When the first power signal is the first power voltage, when the third scan signal on the third scan line S3 controls the threshold compensation transistor T3 to turn on, the first power voltage charges the control end of the driving module 110 through the driving module 110 and the threshold compensation transistor T3, so that the voltage at the control end of the driving module 110 is a voltage related to the first power voltage and the threshold voltage of the transistor in the driving module 110, so as to achieve the threshold compensation of the driving module 110, that is, the threshold compensation transistor T3 performs the threshold compensation on the driving module 110. In this way, the threshold compensation transistor T3 achieves the reset and threshold compensation of the driving module 110 in a time-sharing manner.

[0178] Optionally, refer to Figure 4 , the type of the threshold compensation transistor T3 is the same as the type of the reset transistor T2.

[0179] Specifically, the display panel corresponding to the pixel circuit includes a shift register, and the shift register includes a plurality of cascade-connected gate drive circuits, and the gate drive circuit can provide a scan signal for the pixel circuit. By setting the type of the threshold compensation transistor T3 to be the same as the type of the reset transistor T2, the second scan line S2 and the third scan line S3 can be connected to the same shift register, for example, different levels of gate drive circuits in the same shift register are connected, thereby reducing the number of shift registers, which is conducive to reducing the frame size.

[0180] In one embodiment, optionally, reference Figure 4 , the type of the threshold compensation transistor T3 and the reset transistor T2 are both P-type. In this way, when the third scanning signal is at a low level, the threshold compensation transistor T3 is turned on, and the third scanning signal can pull down the control end coupling of the driving module 110, and can better reset the control end of the driving module 110. In addition, the volume of the threshold compensation transistor T3 and the reset transistor T2 is small, which is conducive to improving the pixel density of the display panel.

[0181] In another embodiment, Figure 5 is a schematic diagram of a structure of another pixel circuit provided by an embodiment of the present invention. Figure 5 , the types of the threshold compensation transistor T3 and the reset transistor T2 are both N-type. In this way, the leakage current of the control end of the driving module 110 can be reduced, thereby avoiding the driving current fluctuation generated by the driving module 110, so that the light-emitting element 200 can emit light stably, thereby improving the display quality of the display panel.

[0182] Optionally, refer to Figure 4 , the starting time of the effective level of the second scanning signal on the second scanning line S2 is delayed by one line time relative to the starting time of the effective level of the third scanning signal on the third scanning line S3; the second scanning signal has the same period as the third scanning signal, and the second scanning signal has the same waveform as the third scanning signal. In this way, the second scanning signal and the third scanning signal can be provided by gate driving circuits of different levels in the same shift register. For example, the m-th level gate driving circuit outputs the third scanning signal corresponding to the m-th row pixel circuit; the m+1-th level gate driving circuit outputs the third scanning signal corresponding to the m+1-th row pixel circuit, which is also the second scanning signal corresponding to the m-th row pixel circuit, so that the second scanning line S2 and the third scanning line S3 can be connected to the same shift register, thereby reducing the number of shift registers, which is conducive to reducing the frame size. Wherein, m is a positive integer.

[0183] Among them, one row time is the time interval between the start time of the effective level of the third scanning signal S3 corresponding to two adjacent rows of pixel circuits. One row time can be calculated according to the resolution and refresh rate of the display panel. The number of rows of pixel circuits (that is, the number of rows of light-emitting elements) can be determined according to the resolution. Then, one row time is

[0184] Figure 6 is a schematic diagram of the structure of a display panel corresponding to the pixel circuit provided in an embodiment of the present invention. Figure 6 The second scan line S2 and the third scan line S3 extend along the first direction X. In two adjacent pixel circuits 10 in the second direction Y, the third scan line S3 corresponding to one pixel circuit 10 is connected to the second scan line S2 corresponding to the other pixel circuit 10; wherein the first direction X intersects the second direction Y.

[0185] like Figure 6As shown, the display panel corresponding to the pixel circuit includes a shift register 300, and the shift register 300 includes a plurality of gate driving circuits 310 connected in cascade, the input end of the first-stage gate driving circuit 310 is connected to the input voltage SIN, and the input end of the m+1-stage gate driving circuit 310 is connected to the output end of the m-stage gate driving circuit 310. The first clock end SCK1 of the m-stage gate driving circuit 310 is connected to the first clock signal CLK1, the second clock end SCK2 of the m-stage gate driving circuit 310 is connected to the second clock signal CLK2, the first clock end SCK1 of the m+1-stage gate driving circuit 310 is connected to the second clock signal CLK2, and the second clock end SCK2 of the m+1-stage gate driving circuit 310 is connected to the first clock signal CLK1.

[0186] The output terminal OUT(m+1) of the m+1th level gate driving circuit is connected to the third scan line S3 corresponding to the m+1th row of pixel circuits 10, and is also connected to the second scan line S2 corresponding to the mth row of pixel circuits, so that the second scan line S2 and the third scan line S3 can be connected to the same shift register, thereby reducing the number of shift registers, which is beneficial to reducing the frame size.

[0187] On the basis of the above technical solution, optionally, the second reset voltage is less than the first reset voltage Vini.

[0188] Specifically, in the second sub-stage, after the threshold compensation module 120 resets the control terminal of the driving module 110, the control terminal of the driving module 110 is at the second reset voltage. In the third sub-stage, through the coupling effect of the coupling module 140, the voltage of the control terminal of the driving module 110 is slightly raised, but still at a relatively low voltage, so that the control terminal of the driving module 110 is reset.

[0189] Optionally, refer to Figure 3 , Figure 4 or Figure 5 The light emitting element 200 includes an organic light emitting diode D1, wherein the first pole of the organic light emitting diode D1 is the first end of the light emitting element 200, and the second pole of the organic light emitting diode D1 is the second end of the light emitting element 200. The first pole of the organic light emitting diode D1 is the anode, and the second pole of the organic light emitting diode D1 is the cathode; or the first pole of the organic light emitting diode D1 is the cathode, and the second pole of the organic light emitting diode D1 is the anode.

[0190] Optionally, refer to Figure 3 , Figure 4 or Figure 5 The driving module 110 includes a driving transistor T4 , a control electrode of the driving transistor T4 is connected to the coupling module 140 , a first electrode of the driving transistor T4 is connected to the first power supply signal, and a second electrode of the driving transistor T4 is connected to the threshold compensation module 120 .

[0191] Specifically, when the first power signal is the second reset voltage, the threshold compensation module 120 transmits the second reset voltage to the control electrode of the driving transistor T4 to reset the control electrode of the driving transistor T4. When the first power signal is the first power voltage, the threshold compensation module 120 transmits a voltage related to the first power voltage and the threshold voltage of the driving transistor T4 to the control electrode of the driving transistor T4 to perform threshold compensation on the driving transistor T4.

[0192] Optionally, refer to Figure 3 , Figure 4 or Figure 5 The coupling module 140 includes a coupling capacitor C1 , a first electrode of the coupling capacitor C1 is connected to the control electrode of the driving transistor T4 , and a second electrode of the coupling capacitor C1 is connected to the data writing module 130 .

[0193] Specifically, when the data writing module 130 transmits the first reset voltage Vini to the second electrode of the coupling capacitor C1, the coupling capacitor C1 couples the first reset voltage Vini to the control electrode of the driving transistor T4 to reset the driving transistor T4. When the data writing module 130 transmits the data voltage Vdata to the second electrode of the coupling capacitor C1, the coupling capacitor C1 couples the data voltage Vdata to the control electrode of the driving transistor T4, so that the driving transistor T4 can generate a driving current according to the data voltage Vdata.

[0194] On the basis of the above technical solutions, Figure 7 is a schematic diagram of a structure of another pixel circuit provided by an embodiment of the present invention. Figure 7 , the pixel circuit further includes a storage module 150;

[0195] A first end of the storage module 150 is connected to a first power signal, and a second end of the storage module 150 is connected to a second end of the coupling module 140 or a control end of the driving module 110;

[0196] A first end of the coupling module 140 is connected to a control end of the driving module 110 .

[0197] Specifically, the second end of the storage module 150 is connected to the second end of the coupling module 140, so that the potential of the second end of the coupling module 140 can be maintained, and then the potential of the control end of the driving module 110 can be maintained. The second end of the storage module 150 is connected to the control end of the driving module 110, so that the potential of the control end of the driving module 110 can be maintained. In this way, the potential of the control end of the driving module 110 can be relatively stable, and the driving module 110 can generate a stable driving current, so that the light-emitting element 200 can emit light stably.

[0198] It should be noted that Figure 7 FIG. 1 shows a situation where the second end of the storage module 150 is connected to the second end of the coupling module 140 , but this is not a limitation.

[0199] Optionally, refer to Figure 7 The pixel circuit further includes a light emitting control module 160 , a control end of the light emitting control module 160 is connected to the light emitting control line EM, and the light emitting control module 160 is connected between the second end of the driving module 110 and the light emitting element 200 .

[0200] Specifically, the light emitting control module 160 can control whether the driving current generated by the driving module 110 is transmitted to the light emitting element 200, thereby controlling whether the light emitting element 200 emits light. When the light emitting control signal on the light emitting control line EM is at an effective level, the light emitting control module 160 is turned on, so that the first power line VDD, the driving module 110, the light emitting control module 160, the light emitting element 200 and the second power line VSS can form a current path, so that the driving module 110 generates a driving current, and the light emitting element 200 emits light in response to the driving current.

[0201] Figure 8 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention, Fig. 9 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention, Fig.10 is a schematic diagram of a structure of another pixel circuit provided by an embodiment of the present invention. Figure 8 , Fig. 9 or Fig.10 The storage module 150 includes a storage capacitor C2, a first electrode of the storage capacitor C2 is connected to the first power signal, and a second electrode of the storage capacitor C2 is connected to the second end of the coupling module 140. In this way, the storage capacitor C2 can maintain the voltage of the second end of the coupling module 140, thereby maintaining the potential of the control electrode of the driving transistor T4, so that the driving transistor T4 can generate a stable driving current.

[0202] Optionally, refer to Figure 8 , Fig. 9 or Fig.10 The light control module 160 includes a light control transistor T5, the control electrode of the light control transistor T5 is connected to the light control line EM, and the light control transistor T5 is connected between the second end of the driving module 110 and the light emitting element 200. In this way, the light control transistor T5 can control whether the driving current generated by the driving transistor T4 is transmitted to the light emitting element 200, thereby controlling whether the light emitting element 200 emits light. Figure 8 and Fig. 9 As shown, the light emitting control transistor T5 may be an N-type transistor, such as Fig.10As shown, the light emission control transistor T5 may be a P-type transistor, and this embodiment does not limit the type of the light emission control transistor T5.

[0203] On the basis of the above technical solutions, optionally, the driving module 110 includes a driving transistor T4, and the active layer material of the driving transistor T4 is different from that of the data writing transistor T1. That is, the driving transistor T4 and the data writing transistor T1 are of different types, so that the active layer of the driving transistor T4 and the active layer of the data writing transistor T1 can be stacked, that is, different types of transistors are stacked, which can reduce the occupied area of ​​the pixel circuit, thereby improving the pixel density of the display panel.

[0204] Optionally, refer to Figure 8 , Fig. 9 or Fig.10 , the active layer of the driving transistor T4 includes polysilicon semiconductor material, and the active layer of the data writing transistor T1 includes oxide semiconductor material. That is, the driving transistor T4 is a P-type transistor, and the data writing transistor T1 is an N-type transistor. Different types of transistors can be stacked, thereby reducing the occupied area of ​​the pixel circuit.

[0205] The pixel circuit provided in this embodiment has a small number of transistors, and the pixel circuit can complete the functions of reset, data writing and threshold compensation. It can ensure the normal operation of the pixel circuit on the basis of improving the pixel density of the display panel, which is beneficial to improving the accuracy and stability of the driving current generated by the pixel circuit, thereby improving the display quality of the display panel.

[0206] The working process of the pixel circuit is described below in combination with the structure of the pixel circuit and the driving timing of the pixel circuit, but it is not intended to limit the present application.

[0207] In one embodiment, Fig.11 is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention. Optionally, refer to Figure 8 and Fig.11 ,The driving process of the pixel circuit (i.e., a driving cycle) includes the following stages.

[0208] In the first sub-phase t11 of the reset phase t1, the first power signal Vdd on the first power line VDD changes from the first power voltage to the second reset voltage. Fig.11 FIG. 4 shows a case where the second reset voltage is less than the first power supply voltage, but this is not a limitation. Thus, the control electrode g of the driving transistor T4 and the second electrode n1 of the coupling capacitor C1 can be coupled downward.

[0209] In the second sub-stage t12 of the reset stage t1, the third scan signal Scan3 on the third scan line S3 is at a low level, the threshold compensation transistor T3 is turned on, the control electrode g of the driving transistor T4 is short-circuited with the second electrode of the driving transistor T4, and after a period of leakage, the voltage Vg of the control electrode g of the driving transistor T4 and the voltage of the second electrode of the driving transistor T4 are the second reset voltage Vdd1, and Vg=Vdd1. The control electrode g of the driving transistor T4 is reset. In addition, the light control signal Em on the light control line EM is at a high level, the light control transistor T5 is turned on, and the light control transistor T5 transmits the second reset voltage to the first end of the light emitting element 200 to reset the first end of the light emitting element 200.

[0210] In the third sub-stage t13 of the reset stage t1, the third scan signal Scan3 on the third scan line S3 is at a low level, and the threshold compensation transistor T3 is turned on. The first scan signal Scan1 on the first scan line S1 is at a high level, and the data writing transistor T1 is turned on. At this time, the data writing transistor T1 is connected to the first reset voltage Vini, and the data writing transistor T1 transmits the first reset voltage Vini to the second electrode n1 of the coupling capacitor C1, and resets the second electrode n1 of the coupling capacitor C1. In addition, the coupling capacitor C1 couples the control electrode of the driving transistor T4, so that the potential of the control electrode g of the driving transistor T4 is slightly raised, but the voltage of the control electrode g of the driving transistor T4 is still a relatively low voltage, so as to achieve the reset of the control electrode of the driving transistor T4.

[0211] In the threshold compensation stage t2, the third scan signal Scan3 on the third scan line S3 is at a low level, and the threshold compensation transistor T3 is turned on. The first scan signal Scan1 on the first scan line S1 is at a high level, and the data write transistor T1 is turned on. At this time, the data write transistor T1 is connected to the first reset voltage Vini. The light control signal Em on the light control line EM is at a low level, and the light control transistor T5 is not turned on. The first power signal Vdd on the first power line VDD becomes the first power voltage Vdd2. The first power voltage Vdd2 charges the first electrode of the coupling capacitor C1 through the driving transistor T4 and the threshold compensation transistor T3 until the voltage of the first electrode of the coupling capacitor C1 is Vdd2+Vth (Vth is the threshold voltage of the driving transistor T4), that is, the voltage of the control electrode g of the driving transistor T4 is Vdd2+Vth. The data write transistor T1 transmits the first reset voltage Vini to the second electrode n1 of the coupling capacitor C1, and the voltage of the second electrode n1 of the coupling capacitor C1 is maintained at the first reset voltage Vini. In this way, the threshold compensation transistor T3 performs threshold compensation on the driving transistor T4.

[0212] In the data writing stage t3, the first scanning signal Scan1 on the first scanning line S1 is at a high level, and the data writing transistor T1 is turned on. At this time, the data writing transistor T1 is connected to the data voltage Vdata. The third scanning signal Scan3 on the third scanning line S3 is at a high level, and the threshold compensation transistor T3 is not turned on. The data writing transistor T1 transmits the data voltage Vdata to the second electrode n1 of the coupling capacitor C1, and the voltage change of the first electrode of the coupling capacitor C1 is k*(Vdata-Vini), where, Wherein, C1 is the capacitance of the coupling capacitor C1, and Cother is other capacitance of the control electrode of the driving transistor T4. Then the potential of the control electrode of the driving transistor T4 becomes Vdd2+Vth+k*(Vdata-Vini). For example, if the other capacitance of the control electrode of the driving transistor T4 is small and can be ignored, then k is 1, and the potential of the control electrode of the driving transistor T4 is Vdd2+Vth+(Vdata-Vini).

[0213] In the light-emitting stage t4, the light-emitting control signal Em on the light-emitting control line EM is at a high level, the light-emitting control transistor T5 is turned on, the first power line VDD, the driving transistor T4, the light-emitting control transistor T5, the light-emitting element 200 and the second power line VSS form a current path, and the voltage difference between the control electrode of the driving transistor T4 and the first electrode of the driving transistor T4 is Vth+(Vdata-Vini), then the driving current generated by the driving transistor T4 is Wherein, μ is the electron mobility of the driving transistor T4 in the driving module 110, Cox is the channel capacitance per unit area of ​​the driving transistor T4, W is the channel width of the driving transistor T4, and L is the channel length of the driving transistor T4. In this way, the driving current generated by the driving module 110 is only related to the data voltage Vdata and the first reset voltage Vini, and has nothing to do with the threshold voltage of the driving transistor T4 in the driving module 110, and has nothing to do with the first power supply voltage and the second power supply voltage, so that the fluctuation of the driving current caused by the fluctuation of the threshold voltage of the driving transistor T4 can be avoided, and the fluctuation of the driving current caused by the voltage drop on the first power line VDD or the second power line VSS can be avoided, thereby ensuring the stability and accuracy of the driving current, which is conducive to improving the display effect of the display panel, and further improving the display performance of the display panel.

[0214] In another embodiment, Fig.12 is another driving timing diagram of a pixel circuit provided by an embodiment of the present invention. Optionally, refer to Fig. 9 and Fig.12 ,The driving process of the pixel circuit (i.e., a driving cycle) includes the following stages.

[0215] In the first sub-phase t11 of the reset phase t1, the first power signal Vdd on the first power line VDD changes from the first power voltage to the second reset voltage, so that the control electrode g of the driving transistor T4 and the second electrode n1 of the coupling capacitor C1 can be coupled downward.

[0216] In the second sub-stage t12 of the reset stage t1, the third scan signal Scan3 on the third scan line S3 is at a low level, the threshold compensation transistor T3 is turned on, the control electrode g of the driving transistor T4 is short-circuited with the second electrode of the driving transistor T4, and after a period of leakage, the voltage Vg of the control electrode g of the driving transistor T4 and the voltage of the second electrode of the driving transistor T4 are the second reset voltage Vdd1, and Vg=Vdd1. The control electrode g of the driving transistor T4 is reset, and the first electrode s of the driving transistor T4 can be reset at the same time. In addition, the light control signal Em on the light control line EM is at a high level, the light control transistor T5 is turned on, and the light control transistor T5 transmits the second reset voltage to the first end of the light emitting element 200 to reset the first end of the light emitting element 200.

[0217] In the third sub-stage t13 of the reset stage t1, the third scan signal Scan3 on the third scan line S3 is at a low level, and the threshold compensation transistor T3 is turned on. The first scan signal Scan1 on the first scan line S1 is at a low level, and the data writing transistor T1 is not turned on. The second scan signal Scan2 on the second scan line S2 is at a low level, the reset transistor T2 is turned on, and the reset transistor T2 transmits the first reset voltage Vini to the second electrode n1 of the coupling capacitor C1, and resets the second electrode n1 of the coupling capacitor C1. In addition, the coupling capacitor C1 couples the control electrode of the driving transistor T4, so that the potential of the control electrode g of the driving transistor T4 is slightly raised, but the voltage of the control electrode g of the driving transistor T4 is still a relatively low voltage, so as to achieve the reset of the control electrode of the driving transistor T4.

[0218] In the threshold compensation stage t2, the third scanning signal Scan3 on the third scanning line S3 is at a low level, and the threshold compensation transistor T3 is turned on. The first scanning signal Scan1 on the first scanning line S1 is at a low level, the data writing transistor T1 is not turned on, the second scanning signal Scan2 on the second scanning line S2 is at a low level, and the reset transistor T2 is turned on. The light-emitting control signal Em on the light-emitting control line EM is at a low level, and the light-emitting control transistor T5 is not turned on. The first power supply signal Vdd on the first power supply line VDD becomes the first power supply voltage Vdd2. The first power supply voltage Vdd2 charges the first electrode of the coupling capacitor C1 through the driving transistor T4 and the threshold compensation transistor T3 until the voltage of the first electrode of the coupling capacitor C1 is Vdd2+Vth (Vth is the threshold voltage of the driving transistor T4), that is, the voltage of the control electrode g of the driving transistor T4 is Vdd2+Vth. The reset transistor T2 transmits the first reset voltage Vini to the second electrode n1 of the coupling capacitor C1, and the voltage of the second electrode n1 of the coupling capacitor C1 is maintained at the first reset voltage Vini. In this way, the threshold compensation transistor T3 performs threshold compensation on the driving transistor T4.

[0219] In the data writing stage t3, the first scanning signal Scan1 on the first scanning line S1 is at a high level, and the data writing transistor T1 is turned on. The third scanning signal Scan3 on the third scanning line S3 and the second scanning signal Scan2 on the second scanning line S2 are at a high level, and the reset transistor T2 and the threshold compensation transistor T3 are not turned on. The data writing transistor T1 transmits the data voltage Vdata to the second electrode n1 of the coupling capacitor C1, and the voltage change of the first electrode of the coupling capacitor C1 is k*(Vdata-Vini), where, Wherein, C1 is the capacitance of the coupling capacitor C1, and Cother is other capacitance of the control electrode of the driving transistor T4. Then the potential of the control electrode of the driving transistor T4 becomes Vdd2+Vth+k*(Vdata-Vini). For example, if the other capacitance of the control electrode of the driving transistor T4 is small and can be ignored, then k is 1, and the potential of the control electrode of the driving transistor T4 is Vdd2+Vth+(Vdata-Vini).

[0220] In the light-emitting stage t4, the light-emitting control signal Em on the light-emitting control line EM is at a high level, the light-emitting control transistor T5 is turned on, the first power line VDD, the driving transistor T4, the light-emitting control transistor T5, the light-emitting element 200 and the second power line VSS form a current path, and the voltage difference between the control electrode of the driving transistor T4 and the first electrode of the driving transistor T4 is Vth+(Vdata-Vini), then the driving current generated by the driving transistor T4 is Wherein, μ is the electron mobility of the driving transistor T4 in the driving module 110, Cox is the channel capacitance per unit area of ​​the driving transistor T4, W is the channel width of the driving transistor T4, and L is the channel length of the driving transistor T4. In this way, the driving current generated by the driving module 110 is only related to the data voltage Vdata and the first reset voltage Vini, and has nothing to do with the threshold voltage of the driving transistor T4 in the driving module 110, and has nothing to do with the first power supply voltage and the second power supply voltage, so that the fluctuation of the driving current caused by the fluctuation of the threshold voltage of the driving transistor T4 can be avoided, and the fluctuation of the driving current caused by the voltage drop on the first power line VDD or the second power line VSS can be avoided, thereby ensuring the stability and accuracy of the driving current, which is conducive to improving the display effect of the display panel, and further improving the display performance of the display panel.

[0221] In yet another embodiment, Fig.13 is another driving timing diagram of a pixel circuit provided by an embodiment of the present invention. Optionally, refer to Fig.10 and Fig.13 ,The driving process of the pixel circuit (i.e., a driving cycle) includes the following stages.

[0222] In the first sub-phase t11 of the reset phase t1, the first power signal Vdd on the first power line VDD changes from the first power voltage to the second reset voltage, so that the control electrode g of the driving transistor T4 and the second electrode n1 of the coupling capacitor C1 can be coupled downward.

[0223] In the second sub-stage t12 of the reset stage t1, the third scan signal Scan3 on the third scan line S3 is at a high level, the threshold compensation transistor T3 is turned on, the control electrode g of the driving transistor T4 is short-circuited with the second electrode of the driving transistor T4, and after a period of leakage, the voltage Vg of the control electrode g of the driving transistor T4 and the voltage of the second electrode of the driving transistor T4 are the second reset voltage Vdd1, and Vg=Vdd1. The control electrode g of the driving transistor T4 is reset. In addition, the light-emitting control signal Em on the light-emitting control line EM is at a low level, the light-emitting control transistor T5 is turned on, and the light-emitting control transistor T5 transmits the second reset voltage to the first end of the light-emitting element 200 to reset the first end of the light-emitting element 200.

[0224] In the third sub-stage t13 of the reset stage t1, the third scan signal Scan3 on the third scan line S3 is at a high level, and the threshold compensation transistor T3 is turned on. The first scan signal Scan1 on the first scan line S1 is at a low level, and the data writing transistor T1 is not turned on. The second scan signal Scan2 on the second scan line S2 is at a high level, the reset transistor T2 is turned on, and the reset transistor T2 transmits the first reset voltage Vini to the second electrode n1 of the coupling capacitor C1, and resets the second electrode n1 of the coupling capacitor C1. In addition, the coupling capacitor C1 couples the control electrode of the driving transistor T4, so that the potential of the control electrode g of the driving transistor T4 is slightly raised, but the voltage of the control electrode g of the driving transistor T4 is still a relatively low voltage, so as to achieve the reset of the control electrode of the driving transistor T4.

[0225] In the threshold compensation stage t2, the third scanning signal Scan3 on the third scanning line S3 is at a high level, and the threshold compensation transistor T3 is turned on. The first scanning signal Scan1 on the first scanning line S1 is at a low level, the data writing transistor T1 is not turned on, the second scanning signal Scan2 on the second scanning line S2 is at a high level, and the reset transistor T2 is turned on. The light-emitting control signal Em on the light-emitting control line EM is at a high level, and the light-emitting control transistor T5 is not turned on. The first power supply signal Vdd on the first power supply line VDD becomes the first power supply voltage Vdd2. The first power supply voltage Vdd2 charges the first electrode of the coupling capacitor C1 through the driving transistor T4 and the threshold compensation transistor T3 until the voltage of the first electrode of the coupling capacitor C1 is Vdd2+Vth (Vth is the threshold voltage of the driving transistor T4), that is, the voltage of the control electrode g of the driving transistor T4 is Vdd2+Vth. The reset transistor T2 transmits the first reset voltage Vini to the second electrode n1 of the coupling capacitor C1, and the voltage of the second electrode n1 of the coupling capacitor C1 is maintained at the first reset voltage Vini. In this way, the threshold compensation transistor T3 performs threshold compensation on the driving transistor T4.

[0226] In the data writing stage t3, the first scanning signal Scan1 on the first scanning line S1 is at a high level, and the data writing transistor T1 is turned on. The third scanning signal Scan3 on the third scanning line S3 and the second scanning signal Scan2 on the second scanning line S2 are at a low level, and the reset transistor T2 and the threshold compensation transistor T3 are not turned on. The data writing transistor T1 transmits the data voltage Vdata to the second electrode n1 of the coupling capacitor C1, and the voltage change of the first electrode of the coupling capacitor C1 is k*(Vdata-Vini), where Wherein, C1 is the capacitance of the coupling capacitor C1, and Cother is other capacitance of the control electrode of the driving transistor T4. Then the potential of the control electrode of the driving transistor T4 becomes Vdd2+Vth+k*(Vdata-Vini). For example, if the other capacitance of the control electrode of the driving transistor T4 is small and can be ignored, then k is 1, and the potential of the control electrode of the driving transistor T4 is Vdd2+Vth+(Vdata-Vini).

[0227] In the light-emitting stage t4, the light-emitting control signal Em on the light-emitting control line EM is at a low level, the light-emitting control transistor T5 is turned on, the first power line VDD, the driving transistor T4, the light-emitting control transistor T5, the light-emitting element 200 and the second power line VSS form a current path, and the voltage difference between the control electrode of the driving transistor T4 and the first electrode of the driving transistor T4 is Vth+(Vdata-Vini), then the driving current generated by the driving transistor T4 is Wherein, μ is the electron mobility of the driving transistor T4 in the driving module 110, Cox is the channel capacitance per unit area of ​​the driving transistor T4, W is the channel width of the driving transistor T4, and L is the channel length of the driving transistor T4. In this way, the driving current generated by the driving module 110 is only related to the data voltage Vdata and the first reset voltage Vini, and has nothing to do with the threshold voltage of the driving transistor T4 in the driving module 110, and has nothing to do with the first power supply voltage and the second power supply voltage, so that the fluctuation of the driving current caused by the fluctuation of the threshold voltage of the driving transistor T4 can be avoided, and the fluctuation of the driving current caused by the voltage drop on the first power line VDD or the second power line VSS can be avoided, thereby ensuring the stability and accuracy of the driving current, which is conducive to improving the display effect of the display panel, and further improving the display performance of the display panel.

[0228] An embodiment of the present invention further provides an array substrate, which includes the pixel circuit provided by any implementation scheme of the present invention. Fig.14 is a schematic diagram of a top view of an array substrate provided by an embodiment of the present invention. Fig.15 is a schematic diagram of the layout structure of a first active layer and a first conductive layer of an array substrate provided by an embodiment of the present invention, Fig.16 is a schematic diagram of the layout structure of a second conductive layer and a third conductive layer of an array substrate provided by an embodiment of the present invention, Fig.17 is a schematic diagram of the layout structure of the second active layer and the fourth conductive layer of an array substrate provided by an embodiment of the present invention, with reference to Fig.14 , Fig.15 , Fig.16 and Fig.17 , the array substrate comprises:

[0229] Substrate 101;

[0230] A first active layer 102 is located on one side of the substrate 101. The first active layer 102 includes a first active region 1021. The first active region 1021 is provided with a channel region T41 of the driving transistor T4 and a channel region T31 of the threshold compensation transistor T3.

[0231] The first conductive layer M1 is located on the side of the first active layer 102 facing away from the substrate 101. The first conductive layer M1 includes a first metal block M11 forming a control electrode of the driving transistor T4 and a third scan line S3 forming a control electrode of the threshold compensation transistor T3. The third scan line S3 extends along the first direction X. The channel region T41 of the driving transistor T4 is located at the positive projection of the first metal block M11 on the first active area 1021. The channel region T31 of the threshold compensation transistor T3 is located at the positive projection of the third scan line S3 on the first active area 1021. The first metal block M11 is connected to the first electrode T32 of the threshold compensation transistor T3 through the first connecting portion L1. The driving transistor T4 is connected to the second electrode T33 of the threshold compensation transistor T3 through the first active area 1021.

[0232] The second conductive layer M2 is located on a side of the first conductive layer M1 away from the substrate 101. The second conductive layer M2 includes a second metal block M21 that forms a second electrode C12 of the coupling capacitor C1. The first metal block M21 is reused as the first electrode C11 of the coupling capacitor C1. The orthographic projection of the second metal block M21 on the substrate 101 covers the orthographic projection of the first metal block M11 on the substrate 101.

[0233] The second active layer 103 is located on a side of the second conductive layer M2 away from the substrate 101. The second active layer 103 includes a third active region 1031. The third active region 1031 is provided with a channel region T11 of the data writing transistor T1.

[0234] The fourth conductive layer M4 is located on the side of the second active layer 103 away from the substrate 101, and the fourth conductive layer M4 includes a first scan line S1 forming a control electrode of the data writing transistor T1, the first scan line S1 extends along the first direction X, the channel region T11 of the data writing transistor T1 is located at the positive projection of the first scan line S1 on the third active area 1031, and the second electrode T12 of the data writing transistor T1 is connected to the second metal block M21 through the second connecting portion L2;

[0235] The first active layer 102 and the second active layer 103 are made of different materials.

[0236] The first direction X is the row direction. The overlapped portion of the first scan line S1 and the third active area 1031 forms the control electrode of the data writing transistor T1, and the overlapped portion of the third scan line S3 in the first active area 1021 can form the control electrode of the threshold compensation transistor T3, which can reduce the number of electrodes and improve space utilization.

[0237] Specifically, by stacking active layers (the first active layer 102 and the third active layer 103) made of different materials, different types of transistors can be stacked, thereby maximizing space utilization, so that the pixel density of the display panel formed by the array substrate is relatively high. In addition, the array substrate includes a threshold compensation transistor T3, which can ensure that the pixel circuit can perform threshold compensation and reset functions on the basis of improving the pixel density, thereby ensuring the normal operation of the pixel circuit.

[0238] On the basis of the above technical solution, optionally, refer to Fig.14 and Fig.15 , the first active layer 102 further includes a second active area 1022 , the second active area 1022 includes a channel area T21 of the reset transistor T2 , and a second electrode T22 of the reset transistor T2 is connected to a second electrode C12 of the coupling capacitor C1 ;

[0239] The first conductive layer M1 further includes a second scan line S2 extending along the first direction X. The channel region T21 of the reset transistor T2 is located at the orthographic projection of the second scan line S2 in the second active region 1022 .

[0240] Specifically, the portion where the second scan line S2 overlaps the second active area 1022 forms the control electrode of the reset transistor T2, which can reduce the number of electrodes and improve space utilization. The second electrode T22 of the reset transistor T2 is connected to the second electrode C12 of the coupling capacitor C1, so that the first reset voltage Vini is written to the second electrode C12 of the coupling capacitor C1, so that the coupling capacitor C1 can couple and reset the control electrode of the driving transistor T4.

[0241] Alternatively, if Fig.14 and Fig.15 As shown, the extension direction of the channel region T31 of the threshold compensation transistor T3 is perpendicular to the extension direction of the channel region T21 of the reset transistor T2. In this way, compared with the channel region T31 of the threshold compensation transistor T3 and the channel region T21 of the reset transistor T2 being arranged in sequence along the first direction X, the occupied space in the first direction X can be reduced. Compared with the channel region T31 of the threshold compensation transistor T3 and the channel region T21 of the reset transistor T2 being arranged in sequence along the second direction Y, the occupied space in the second direction Y can be reduced. Thus, the space utilization rate of the array substrate can be improved.

[0242] Alternatively, if Fig.14 and Fig.15As shown, in the second direction Y, the channel region T31 of the threshold compensation transistor T3 and the channel region T21 of the reset transistor T2 are distributed on both sides of the channel region T41 of the driving transistor T4, and the first direction X intersects with the second direction Y. In this way, the occupied space in the first direction X can be reduced, and multiple pixel circuits can be arranged in the first direction X, thereby improving the pixel density of the display panel formed by the array substrate.

[0243] Alternatively, if Fig.14 and Fig.15 As shown, the first metal block M11 includes a first protrusion A1, which is located at one end of the first metal block M11 facing the threshold compensation transistor T3, and the first electrode T32 of the threshold compensation transistor T3 is connected to the first protrusion A1. In this way, the first electrode T32 of the threshold compensation transistor T3 is connected to the first metal block M11 through the first protrusion A1, that is, connected to the control electrode of the driving transistor T4, so that the threshold compensation transistor T3 can perform threshold compensation and reset on the driving transistor T4 in a time-sharing manner.

[0244] Fig.18 is a schematic structural diagram of a first active layer, a first conductive layer, a second conductive layer and a third conductive layer of an array substrate provided by an embodiment of the present invention. Optionally, as Fig.14 , Fig.16 and Fig.18 As shown, the second metal block M21 includes a second protrusion A2, and the second protrusion A2 is located at one end of the second metal block M21 facing the reset transistor T2, and the second electrode T22 of the reset transistor T2 is electrically connected to the second protrusion A2. In this way, it is convenient for the reset transistor T2 to be connected to the second metal block M21, and thus connected to the second electrode C12 of the coupling capacitor C1, and it is convenient to write the first reset voltage Vini to the second electrode C12 of the coupling capacitor C1, so that the coupling capacitor C1 can couple and reset the control electrode of the driving transistor T4.

[0245] On the basis of the above technical solutions, optionally, refer to Fig.17 The second active layer 103 further includes a fourth active region 1032, the fourth active region 1032 includes a channel region T51 of the light emitting control transistor T5, and the third active region 1031 and the fourth active region 1032 are arranged at intervals and both extend along the second direction Y. In this way, the occupied space in the first direction X can be further reduced, and it is convenient to arrange a plurality of pixel circuits in the first direction X, thereby improving the pixel density of the display panel formed by the array substrate.

[0246] Optionally, the orthographic projection of the third active area 1031 on the substrate 101 and the orthographic projection of the fourth active area 1032 on the substrate 101 partially overlap with the orthographic projection of the first active area 1021 on the substrate. In this way, the occupied space in the first direction X and the second direction Y can be reduced, thereby improving space utilization and facilitating the realization of a higher pixel density.

[0247] Optionally, refer to Fig.17 The fourth conductive layer M4 further includes a light emitting control line EM extending along the first direction X, and the channel region T51 of the light emitting control transistor T5 is located at the positive projection of the light emitting control line EM on the fourth active region 1032. In this way, the portion where the light emitting control line EM overlaps with the fourth active region 1032 forms the control electrode of the light emitting control transistor T5, which can reduce the number of electrodes and improve space utilization.

[0248] Optionally, refer to Fig.15 and Fig.17 , the channel region T41 of the driving transistor T4 is an X-type, and the third active region 1031 is an L-type.

[0249] Specifically, the channel region T41 of the driving transistor T4 is an X-shaped region, which facilitates the driving transistor T4 to be connected to the threshold compensation transistor T3 and the reset transistor T2 on both sides thereof. The third active region 1031 is an L-shaped region, which facilitates the data writing transistor T1 to be connected to the second metal block M21.

[0250] On the basis of the above technical solution, optionally, refer to Fig.14 and Fig.16 , the array substrate further includes a third conductive layer M3 located between the second conductive layer M2 and the second active layer 103;

[0251] The third conductive layer M3 includes a third metal block M31 forming a first electrode C21 of the storage capacitor C2, the orthographic projection of the third metal block M31 on the substrate 101 covers the orthographic projection of the second metal block M21 on the substrate 101, and the second metal block M21 is reused as the second electrode C22 of the storage capacitor C2;

[0252] In the first direction X, adjacent third metal blocks M31 are connected to each other. The connected third metal blocks M31 are multiplexed as a first power line VDD to transmit a first power signal. The first electrode C21 of the storage capacitor C2 is connected to the first electrode of the driving transistor T4.

[0253] Specifically, by setting the second metal block M21 to be reused as the second electrode C22 of the storage capacitor C2, the number of metal plates can be reduced, thereby reducing the thickness of the array substrate, which is conducive to a lightweight design. In addition, the third metal block M31 is reused as the first power line VDD to transmit the first power signal, which can reduce the space occupied by the wiring, thereby further improving the space utilization of the array substrate, which is conducive to improving the pixel density of the display panel formed by the array substrate.

[0254] Optionally, refer to Fig.16 The third metal block M31 includes a third protruding portion A3, and the third protruding portion A3 extends toward the third active area 1031. In this way, the third metal block M31 is conveniently extended toward the position of the third active area 1031, so that the formed first power line VDD overlaps with the third active area 1031, thereby reducing space occupation and further improving the space utilization of the array substrate.

[0255] Optionally, refer to Fig.16 , the first connection part L1 and the second connection part L2 are both located in the third conductive layer M3. This arrangement facilitates the first electrode T32 of the threshold compensation transistor T3 located in the third conductive layer M3 to be connected to the coupling capacitor C1 through the first connection part L1 located in the third conductive layer M3, that is, the first connection part L1 plays the role of a jumper. It is convenient for the second electrode T12 of the data writing transistor T1 located on the side of the conductive layer M3 away from the substrate 101 to be connected to the second metal block M21 through the second connection part L2, that is, the second connection part L2 plays the role of a jumper.

[0256] Fig.19 is a schematic diagram of the layout structure of a second conductive layer, a third conductive layer, a second active layer and a fourth conductive layer of an array substrate provided in an embodiment of the present invention. Fig.19 , the orthographic projections of the third active area 1031 and the fourth active area 1032 on the substrate 101 are located within the orthographic projection range of the third metal block M31 on the substrate 101. In this way, the occupied space in the second direction Y can be reduced, so that more pixel circuits can be arranged in the second direction Y, further improving the space utilization of the array substrate, thereby improving the pixel density of the display panel formed by the array substrate, which is beneficial to improving the display quality of the display panel.

[0257] Optionally, refer to Fig.15 The third scan line S3 includes a main body portion S31 and an extension portion S32. The main body portion S31 has the same extension direction as the channel region T31 of the threshold compensation transistor T3. The extension direction of the extension portion S32 is perpendicular to the extension direction of the main body portion S31. The channel region T31 of the threshold compensation transistor T3 is located at the positive projection of the extension portion on the first active area 1021.

[0258] Specifically, by setting the third scan line S3 to include a main portion S31 and an extension portion S32, the main portion S31 extends along the first direction X, and can be connected to the threshold compensation transistors T3 in multiple pixel circuits, so as to facilitate row-by-row driving. In addition, the extension portion S32 can be connected to the corresponding threshold compensation transistor T3. Moreover, the extension portion S32 overlaps with the first active area 1021, thereby forming a control electrode of the threshold compensation transistor T3, reducing the number of electrodes, and further improving space utilization.

[0259] Optionally, the width of the main body S31 is the same as that of the first scan line S1. In this way, it is convenient to prepare the scan line, and the main body S31 and the first scan line S1 can be narrow, which is convenient to save space and improve space utilization. In some embodiments, for example, the width of the main body S31 is the same as that of the second scan line S2.

[0260] On the basis of the above technical solution, the second conductive layer M2 further includes a plurality of reset power signal lines Vin extending along the first direction X, the orthographic projection of the reset power signal line Vin on the substrate 101 partially overlaps with the orthographic projection of the first electrode T23 of the reset transistor T2 on the substrate 101, and the first electrode T23 of the reset transistor T2 is connected to the reset power signal line Vin; or

[0261] Fig. 20 is a schematic diagram of a top view structure of another array substrate provided by an embodiment of the present invention. Fig. 20 The third conductive layer M3 further includes a plurality of reset power signal lines Vin, the orthographic projection of the reset power signal line Vin on the substrate 101 partially overlaps with the orthographic projection of the first electrode T23 of the reset transistor T2 on the substrate 101, and the first electrode T23 of the reset transistor T2 is connected to the reset power signal line Vin;

[0262] The reset power signal line Vin extends along the first direction X, and one end of the second active region 1022 away from the second metal block M21 is electrically connected to a reset power signal line Vin.

[0263] Specifically, the reset power signal line Vin extends along the first direction X, and the reset power signal line Vin can be connected to the reset transistors T2 in the plurality of pixel circuits, thereby providing the first reset voltage Vini for the plurality of pixel circuits. By connecting the reset power signal line Vin to the first electrode T23 of the reset transistor T2, the reset transistor T2 can transmit the first reset voltage Vini on the reset power signal line Vin to the second electrode of the coupling capacitor C1, so as to reset the second electrode of the coupling capacitor C1.

[0264] Fig. 20 FIG. 5 shows a case where the reset power signal line Vin is located in the third conductive layer M3 , but this is not limiting.

[0265] Based on the above technical solutions, Fig.21 yes Fig.14 The cross-sectional view along the direction a1-a2, Fig. 22 is a schematic diagram of the layout structure of a first active layer, a first conductive layer and a third active layer of an array substrate provided in an embodiment of the present invention. Optionally, refer to Fig. 20 , Fig.21 and Fig. 22 , the array substrate further includes a first insulating layer 104 located between the first active layer 102 and the first conductive layer M1, a second insulating layer 105 located between the first conductive layer M1 and the second conductive layer M2, and a third insulating layer 106 located between the second conductive layer M2 and the third conductive layer M3;

[0266] The second electrode of the reset transistor T2 is connected to the second metal block M21 through the first via V1 that penetrates the first insulating layer 104 and the second insulating layer 105, and the first electrode of the reset transistor T2 is connected to the reset power signal line Vin through the second via V2, and the second via V2 penetrates the first insulating layer 104 and the second insulating layer 105, or the second via V2 penetrates the first insulating layer 104, the second insulating layer 105 and the third insulating layer 106. In this way, it is convenient to connect the reset transistor T2 to the reset power signal line Vin, and it is convenient to connect the reset transistor T2 to the second metal block M21 (the second electrode of the coupling capacitor C1). Among them, the first insulating layer 104 can be an organic insulating layer or an inorganic insulating layer. The second insulating layer 105 can be an organic insulating layer or an inorganic insulating layer, for example, an insulating layer formed by silicon dioxide or silicon nitride. The third insulating layer 106 can be an inorganic insulating layer or an organic insulating layer, for example, the material of the third insulating layer 106 is the same as the material of the second insulating layer 105, which is not limited in this embodiment.

[0267] Fig.23 yes Fig.18 A cross-sectional view along the b1-b2 direction, optionally, referring to Fig.18 , Fig. 22 and Fig.23 , the first electrode of the driving transistor T4 is connected to the third metal block M31 through the third via hole V3, and the third via hole V3 penetrates the first insulating layer 104, the second insulating layer 105 and the third insulating layer 106. In this way, it is convenient to connect the first electrode of the driving transistor T4 to the third metal block M31, that is, to connect the driving transistor T4 to the first power line VSS.

[0268] Fig.24 yes Fig.18 A cross-sectional view along the direction e1-e2, optionally, referring to Fig.18 , Fig. 22 and Fig.23, the control electrode of the driving transistor T4 is connected to the first connection portion L1 through the fourth via hole V4, and the first connection portion L1 is also connected to the first electrode of the threshold compensation transistor T3 through the fifth via hole V5;

[0269] The fourth via hole V4 penetrates the second insulating layer 105 and the third insulating layer 106, and the fifth via hole V5 sequentially penetrates the third insulating layer 106, the second insulating layer 105 and the first insulating layer 104. In this way, the control electrode of the driving transistor T4 is connected to the first electrode of the threshold compensation transistor T3 through the first connecting portion L1, so that the threshold compensation transistor T3 can reset and threshold compensate the driving transistor T4.

[0270] Based on the above technical solutions, Fig.25 yes Fig.19 Cross-sectional view along the f1-f2 direction, Fig.26 is a schematic diagram of the layout structure of a third conductive layer, a second active layer and a sixth insulating layer of an array substrate provided in an embodiment of the present invention. Optionally, reference Fig.25 and Fig.26 , the array substrate further includes a fourth conductive layer M4 and a fifth conductive layer M5 located on a side of the third conductive layer M3 away from the substrate 101; the array substrate further includes a fourth insulating layer 107 located between the third conductive layer M3 and the second active layer 103, a fifth insulating layer 108 located between the second active layer 103 and the fourth conductive layer M4, and a sixth insulating layer 109 located on a side of the fourth conductive layer M4 away from the substrate 101;

[0271] The fifth conductive layer M5 includes a plurality of data transmission lines Data extending along the second direction Y, and the first electrode of the data writing transistor T1 is connected to the data transmission line Data through a sixth via hole V6 penetrating the sixth insulating layer 109 and the fifth insulating layer 108. In this way, it is convenient to connect the data writing transistor T1 to the data transmission line Data, so that the data writing transistor T1 can transmit the data voltage Vdata on the data transmission line Data to the control electrode of the driving transistor T4, so that the driving transistor T4 generates a driving current according to the data voltage Vdata.

[0272] Fig. 27 is a schematic diagram of a layout structure of a fifth conductive layer of an array substrate provided by an embodiment of the present invention, Fig.28 yes Fig.14 A cross-sectional view along the h1-h2 direction, optionally, referring to Fig.26 , Fig. 27 and Fig.28, the fifth conductive layer M5 further includes a third connection portion L3 extending along the first direction X and a fourth connection portion L4 extending along the second direction Y, the second electrode of the data writing transistor T1 is connected to the third connection portion L3 through the seventh via hole V7, the end of the third connection portion L3 away from the seventh via hole V7 is connected to the second connection portion L2 through the eighth via hole V8, and the second connection portion L2 is connected to the second electrode of the coupling capacitor C1 through the ninth via hole V9;

[0273] The seventh via hole V7 penetrates the sixth insulating layer 109 and the fifth insulating layer 108; the eighth via hole V8 penetrates the sixth insulating layer 109, the fifth insulating layer 108 and the fourth insulating layer 107; and the ninth via hole V9 penetrates the third insulating layer 106. In this way, the data writing transistor T1 is connected to the second electrode of the coupling capacitor C1.

[0274] Optionally, refer to Fig.28 , the ninth via hole V9 overlaps with the orthographic projection of the first via hole V1 on the substrate 101. In this way, the space utilization rate can be improved, which is beneficial to improving the pixel density of the display panel formed by the array substrate.

[0275] Fig.29 yes Fig.14 A cross-sectional view along the h3-h4 direction, optionally, referring to Fig.26 and Fig.29 , the first electrode of the light emitting control transistor T5 is connected to the fourth connection portion L4 through the tenth via hole V10, and the end of the fourth connection portion L4 away from the tenth via hole V10 is connected to the fifth connection portion L5 through the eleventh via hole V11;

[0276] The tenth via hole V10 sequentially penetrates the sixth insulating layer 109 and the fifth insulating layer 108, and the eleventh via hole V11 sequentially penetrates the sixth insulating layer 109, the fifth insulating layer 108 and the fourth insulating layer 107. In this way, the light emission control transistor T5 is conveniently connected to the driving transistor T4.

[0277] Alternatively, if Fig.29 As shown, the second electrode of the light emitting control transistor T5 is electrically connected to the first electrode 210 of the light emitting element 200 through the twelfth via hole V12 penetrating the sixth insulating layer 109 and the fifth insulating layer 108. In this way, it is convenient to connect the light emitting control transistor T5 to the first electrode 210 of the light emitting element 200. The first electrode 210 of the light emitting element 210 is the first end of the light emitting element 200, and the first electrode 210 of the light emitting element 200 is an anode or a cathode.

[0278] Alternatively, if Fig.29As shown, the array substrate further includes a first planarization layer PLN1 located on the side of the fifth conductive layer M5 away from the substrate 101, a sixth conductive layer M6 located on the side of the first planarization layer PLN1 away from the substrate 101, a second planarization layer PLN2 located on the side of the sixth conductive layer M6 away from the substrate 101, and a pixel definition layer PDL located on the side of the second planarization layer PLN2 away from the substrate 101. The pixel definition layer PDL is used to define the size of the light-emitting element 200, and the first electrode 210 of the light-emitting element 200 is connected to the second electrode of the light-emitting control transistor T5 through a conductive connection portion located on the sixth conductive layer M6.

[0279] An embodiment of the present invention further provides a method for driving a pixel circuit, which is used to drive the pixel circuit provided by any implementation scheme of the present invention. Fig.30 is a flowchart of a driving method of a pixel circuit provided by an embodiment of the present invention, with reference to Fig.30 , the driving method of the pixel circuit includes:

[0280] S1000 , in a reset phase, the threshold compensation module transmits a first power supply signal to a control end of the driving module.

[0281] Specifically, the first power line VDD is used to transmit the first power signal. By setting the voltage of the first power signal to be different in at least two driving stages, the first power line VDD can transmit different voltages in time. The first power signal includes a second reset voltage and a first power voltage. For example, in the reset stage, the first power signal is the second reset voltage, and the second reset voltage is transmitted to the control end of the driving module 110 through the driving module 110 and the threshold compensation module 120 to achieve the reset of the control end of the driving module 110, that is, the threshold compensation module 120 resets the driving module 110.

[0282] S2000: In a threshold compensation stage, the threshold compensation module performs threshold compensation on the driving module based on the first power supply signal;

[0283] Among them, the voltage of the first power signal in the reset stage and the remaining stages is different, and the first power signal includes a second reset voltage and a first power voltage; the first power line is used to transmit the second reset voltage and the first power voltage to the first end of the driving module in a time-sharing manner.

[0284] Specifically, in the threshold compensation stage, the first power supply signal is the first power supply voltage, and the first power supply voltage charges the control end of the driving module 110 through the driving module 110 and the threshold compensation module 120, so that the voltage of the control end of the driving module 110 is a voltage related to the first power supply voltage and the threshold voltage of the transistor in the driving module 110, so as to realize threshold compensation for the driving module 110, that is, the threshold compensation module 120 performs threshold compensation on the driving module 110. In this way, the threshold compensation module 120 resets and threshold compensates the driving module 110 in a time-sharing manner. Therefore, there is no need to set up more modules to realize compensation and reset, and the number of transistors is reduced, which is conducive to improving the pixel density of the display panel corresponding to the pixel circuit. As a result, on the basis of fewer devices in the pixel circuit, it is ensured that the pixel circuit can be reset and compensated, that is, on the basis of ensuring that the pixel density of the display panel is large, the normal operation of the pixel circuit is guaranteed, and the performance of the display panel is improved.

[0285] On the basis of the above technical solution, optionally, in the reset stage, the first power signal is the second reset voltage, and in the remaining stages, the first power signal is the first power voltage;

[0286] In the reset stage, the threshold compensation module transmits the first power supply signal to the control end of the driving module, including:

[0287] In the reset phase, the threshold compensation module transmits the second reset voltage to the control terminal of the driving module.

[0288] Specifically, in the reset stage, the first power signal is the second reset voltage, and the second reset voltage is transmitted to the control end of the driving module 110 through the driving module 110 and the threshold compensation module 120 to achieve the reset of the control end of the driving module 110, that is, the threshold compensation module 120 resets the driving module 110.

[0289] In the threshold compensation stage, the threshold compensation module performs threshold compensation on the driving module based on the first power supply signal, including:

[0290] Optionally, in the threshold compensation stage, the threshold compensation module performs threshold compensation on the driving module based on the first power supply voltage.

[0291] Specifically, in the threshold compensation stage, the first power supply signal is the first power supply voltage, and the first power supply voltage charges the control end of the driving module 110 through the driving module 110 and the threshold compensation module 120, so that the voltage of the control end of the driving module 110 is a voltage related to the first power supply voltage and the threshold voltage of the transistor in the driving module 110, so as to realize the threshold compensation of the driving module 110, that is, the threshold compensation module 120 performs the threshold compensation on the driving module 110. In this way, the threshold compensation module 120 realizes the reset and threshold compensation of the driving module 110 in a time-sharing manner.

[0292] Based on the above technical solution, optionally, in the reset stage, the threshold compensation module transmits the first power supply signal to the control end of the driving module, and the data writing module transmits the first reset voltage to the coupling module, including:

[0293] Step a11: In the first sub-stage of the reset stage, the voltage of the first power supply signal jumps from the first power supply voltage to the second reset voltage;

[0294] Step a12: in the second sub-stage of the reset stage, the threshold compensation module transmits the second reset voltage to the control end of the driving module to reset the control end of the driving module;

[0295] Step a13: In the third sub-phase of the reset phase, the data writing module transmits the first reset voltage to the coupling module.

[0296] Specifically, in the first sub-stage of the reset phase, the voltage of the first power supply signal jumps from the first power supply voltage to the second reset voltage, that is, at the beginning of the reset phase, the first power supply signal becomes the second reset voltage, so that the driving module 110 is reset according to the second reset voltage. After the first power supply signal becomes the second reset voltage, the threshold compensation module 120 transmits the second reset voltage to the control end of the driving module 110 in the second sub-stage of the reset phase, that is, the second reset voltage is transmitted to the control end of the driving module 110 through the driving module 110 and the threshold compensation module 120, which can clear the residual voltage of the control end of the driving module 110 and achieve the reset of the driving module 110. In the third sub-stage, the first reset voltage Vini is transmitted to the coupling module 140. For example, if the driving module 110 needs a lower voltage for reset, and the first reset voltage Vini is greater than the second reset voltage, then in the third sub-stage, through the coupling effect of the coupling module 140, the voltage of the control end of the driving module 110 is slightly raised, but still at a lower voltage, so as to achieve the reset of the control end of the driving module 110.

[0297] Optionally, the second reset voltage is lower than the first reset voltage.

[0298] Optionally, in a reset phase, the duration of the second sub-phase is greater than the duration of the third sub-phase.

[0299] Optionally, in a reset phase, the duration of the second sub-phase is greater than the duration of the first sub-phase.

[0300] An embodiment of the present invention further provides a display panel, Fig.31 is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. Fig.31As shown, the display panel includes the array substrate provided by any of the above embodiments. The display panel can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, etc. The display panel includes the array substrate provided by any embodiment of the present invention, and thus has the same beneficial effects as the array substrate provided by any embodiment of the present invention, which will not be described in detail here.

[0301] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0302] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A pixel circuit, characterized in that: include: A driving module, wherein a first end of the driving module is connected to a first power line; wherein in each driving cycle, a first power signal on the first power line has different voltages in at least two driving stages; A threshold compensation module, the threshold compensation module is connected between the second end of the driving module and the control end of the driving module, and the threshold compensation module is used to reset and threshold compensate the driving module in a time-sharing manner; The first power signal includes a second reset voltage and a first power voltage; the first power line is used to transmit the second reset voltage and the first power voltage to the first end of the driving module in a time-sharing manner.

2. The pixel circuit according to claim 1, characterized in that: In a reset phase of one of the driving cycles, the first power signal is the second reset voltage, and in the remaining phases of the driving cycle, the first power signal is the first power voltage.

3. The pixel circuit according to claim 1, characterized in that: The voltage of the first power signal jumps from the first power voltage to a second reset voltage in a first sub-phase of the reset phase; Preferably, the threshold compensation module is used to transmit the second reset voltage to the control end of the driving module in the second sub-stage of the reset stage to reset the control end of the driving module; Preferably, the second sub-stage is located after the first sub-stage; Preferably, the threshold compensation module is further used to perform threshold compensation on the driving module in a threshold compensation stage, and the voltage of the first power supply signal jumps from the second reset voltage to the first power supply voltage in the threshold compensation stage; Preferably, the pixel circuit further comprises a data writing module and a coupling module; the first end of the data writing module is connected to the data voltage or the first reset voltage, and the coupling module is connected between the second end of the data writing module and the control end of the driving module; the data writing module is used to transmit the data voltage and the first reset voltage to the coupling module in a time-sharing manner; Preferably, the data writing module is used to transmit the first reset voltage to the coupling module in the third sub-stage of the reset stage, so as to reset the control end of the driving module through the coupling module; Preferably, the third sub-stage is located after the second sub-stage; Preferably, in one of the reset phases, the duration of the second sub-phase is longer than the duration of the third sub-phase; Preferably, in one of the reset phases, the duration of the second sub-phase is longer than the duration of the first sub-phase.

4. The pixel circuit according to claim 3, characterized in that: The data writing module comprises a data writing transistor, a first electrode of the data writing transistor is connected to the data voltage and / or the first reset voltage, and a second electrode of the data writing transistor is connected to the coupling module; a control electrode of the data writing transistor is connected to the first scanning line; the data writing transistor is used to transmit the data voltage and the first reset voltage to the coupling module in a time-sharing manner; Preferably, the data writing transistor is used to transmit the data voltage to the coupling module in the data writing phase, and transmit the first reset voltage to the coupling module in at least a part of the time period of the reset phase; Preferably, the data writing transistor is used to transmit the first reset voltage to the coupling module in a third sub-phase of the reset phase.

5. The pixel circuit according to claim 3, characterized in that: The data writing module includes a data writing transistor and a reset transistor; The control electrode of the data writing transistor is connected to the first scanning line, the first electrode of the data writing transistor is connected to the data voltage, and the second electrode of the data writing transistor is connected to the coupling module; the data writing transistor is used to transmit the data voltage to the coupling module in the data writing stage, and the coupling module is used to couple the data voltage to the control end of the driving module; The first electrode of the reset transistor is connected to the first reset voltage, and the second electrode of the reset transistor is connected to the coupling module; the reset transistor is used to transmit the first reset voltage to the coupling module during at least part of the reset phase; Preferably, the reset transistor is used to transmit the first reset voltage to the coupling module in a third sub-phase of the reset phase.

6. The pixel circuit according to claim 5, characterized in that: The control electrode of the reset transistor is connected to the second scan line; Preferably, the threshold compensation module comprises a threshold compensation transistor, the control electrode of the threshold compensation transistor is connected to the third scan line; the threshold compensation transistor is connected between the second end of the driving module and the control end of the driving module; Preferably, the type of the threshold compensation transistor is the same as the type of the reset transistor; Preferably, the threshold compensation transistor and the reset transistor are both of N-type or P-type; Preferably, the start time of the effective level of the second scanning signal on the second scanning line is delayed by one line time relative to the start time of the effective level of the third scanning signal on the third scanning line; the second scanning signal has the same period as the third scanning signal, and the second scanning signal has the same waveform as the third scanning signal; Preferably, the second scan line and the third scan line extend along the first direction, and in two adjacent pixel circuits in the second direction, the third scan line corresponding to one pixel circuit is connected to the second scan line corresponding to the other pixel circuit; wherein the first direction intersects the second direction.

7. The pixel circuit according to claim 3, characterized in that: The second reset voltage is lower than the first reset voltage.

8. The pixel circuit according to claim 3, characterized in that: The driving module comprises a driving transistor, a control electrode of the driving transistor is connected to the coupling module, a first electrode of the driving transistor is connected to the first power supply signal, and a second electrode of the driving transistor is connected to the threshold compensation module; Preferably, the coupling module comprises a coupling capacitor, a first electrode of the coupling capacitor is connected to the control electrode of the driving transistor, and a second electrode of the coupling capacitor is connected to the data writing module; Preferably, the pixel circuit further includes a storage module; The first end of the storage module is connected to the first power signal, and the second end of the storage module is connected to the second end of the coupling module or the control end of the driving module; The first end of the coupling module is connected to the control end of the driving module; Preferably, the pixel circuit further comprises a light emitting control module, a control end of the light emitting control module is connected to a light emitting control line, and the light emitting control module is connected between the second end of the driving module and the light emitting element; Preferably, the storage module comprises a storage capacitor, a first electrode of the storage capacitor is connected to the first power supply signal, and a second electrode of the storage capacitor is connected to the second end of the coupling module; Preferably, the light emitting control module comprises a light emitting control transistor, a control electrode of the light emitting control transistor is connected to the light emitting control line, and the light emitting control transistor is connected between the second end of the driving module and the light emitting element.

9. The pixel circuit according to claim 4 or 5, characterized in that: The driving module comprises a driving transistor, wherein the active layer material of the driving transistor is different from that of the data writing transistor; Preferably, the active layer of the driving transistor includes a polysilicon semiconductor material, and the active layer of the data writing transistor includes an oxide semiconductor material.

10. An array substrate, characterized in that: include: substrate; A first active layer, located on one side of the substrate, the first active layer comprising a first active region, the first active region being provided with a channel region of a driving transistor and a channel region of a threshold compensation transistor; a first conductive layer, located on a side of the first active layer away from the substrate, the first conductive layer comprising a first metal block forming a control electrode of the driving transistor and a third scan line forming a control electrode of the threshold compensation transistor, the third scan line extending along a first direction, a channel region of the driving transistor located at an orthographic projection of the first metal block on the first active region, a channel region of the threshold compensation transistor located at an orthographic projection of the third scan line on the first active region, the first metal block connected to a first electrode of the threshold compensation transistor through a first connecting portion, and a second electrode of the driving transistor connected to a second electrode of the threshold compensation transistor through the first active region; a second conductive layer, located on a side of the first conductive layer away from the substrate, the second conductive layer comprising a second metal block forming a second electrode of a coupling capacitor, the first metal block being reused as a first electrode of the coupling capacitor, and an orthographic projection of the second metal block on the substrate covering an orthographic projection of the first metal block on the substrate; A second active layer, located on a side of the second conductive layer away from the substrate, the second active layer comprising a third active region, wherein the third active region is provided with a channel region of a data writing transistor; a fourth conductive layer, located on a side of the second active layer away from the substrate, the fourth conductive layer comprising a first scan line forming a control electrode of the data writing transistor, the first scan line extending along the first direction, a channel region of the data writing transistor located at a positive projection of the first scan line on the third active region, and a second electrode of the data writing transistor connected to the second metal block via a second connecting portion; The first active layer and the second active layer are made of different materials.

11. The array substrate according to claim 10, characterized in that: The first active layer further includes a second active region, the second active region includes a channel region of a reset transistor, and a second electrode of the reset transistor is connected to a second electrode of the coupling capacitor; The first conductive layer further includes a second scan line extending along the first direction, and the channel region of the reset transistor is located at a positive projection of the second scan line on the second active region; Preferably, the extension direction of the channel region of the threshold compensation transistor is perpendicular to the extension direction of the channel region of the reset transistor; Preferably, in the second direction, the threshold compensation transistor channel region and the reset transistor channel region are distributed on both sides of the channel region of the driving transistor, and the first direction intersects with the second direction; Preferably, the first metal block comprises a first protrusion, the first protrusion is located at one end of the first metal block facing the threshold compensation transistor, and the first electrode of the threshold compensation transistor is connected to the first protrusion; Preferably, the second metal block comprises a second protrusion, the second protrusion is located at one end of the second metal block facing the reset transistor, and the second electrode of the reset transistor is electrically connected to the second protrusion.

12. The array substrate according to claim 11, characterized in that: The second active layer further includes a fourth active region, the fourth active region includes a channel region of the light emitting control transistor, the third active region and the fourth active region are arranged at intervals and both extend along the second direction; Preferably, the orthographic projection of the third active region on the substrate and the orthographic projection of the fourth active region on the substrate partially overlap with the orthographic projection of the first active region on the substrate; The fourth conductive layer further includes a light emitting control line extending along the first direction, and a channel region of the light emitting control transistor is located at a positive projection of the light emitting control line on the fourth active region; Preferably, the channel region of the driving transistor is in an X-shape, and the third active region is in an L-shape.

13. The array substrate according to claim 12, characterized in that: The array substrate further comprises a third conductive layer located between the second conductive layer and the second active layer; The third conductive layer includes a third metal block forming a first electrode of the storage capacitor, the orthographic projection of the third metal block on the substrate covers the orthographic projection of the second metal block on the substrate, and the second metal block is reused as the second electrode of the storage capacitor; In the first direction, the adjacent third metal blocks are connected to each other, the connected third metal blocks are reused as a first power line to transmit a first power signal, and the first electrode of the storage capacitor is connected to the first electrode of the driving transistor; Preferably, the third metal block comprises a third protrusion, and the third protrusion extends toward the third active area; Preferably, the first connecting portion and the second connecting portion are both located in the third conductive layer; Preferably, the orthographic projections of the third active region and the fourth active region on the substrate are located within the orthographic projection range of the third metal block on the substrate; Preferably, the third scan line comprises a main body portion and an extension portion, the main body portion and the channel region of the threshold compensation transistor extend in the same direction, the extension direction of the extension portion is perpendicular to the extension direction of the main body portion, and the channel region of the threshold compensation transistor is located at the orthographic projection of the extension portion on the first active region; Preferably, the width of the main body is the same as that of the first scanning line.

14. The array substrate according to claim 13, characterized in that: The second conductive layer further includes a plurality of reset power signal lines extending along the first direction, the orthographic projections of the reset power signal lines on the substrate partially overlap with the orthographic projections of the first electrode of the reset transistor on the substrate, and the first electrode of the reset transistor is connected to the reset power signal lines; or The third conductive layer further comprises a plurality of reset power signal lines, the orthographic projections of the reset power signal lines on the substrate partially overlap with the orthographic projections of the first electrode of the reset transistor on the substrate, and the first electrode of the reset transistor is connected to the reset power signal lines; The reset power signal line extends along the first direction, and one end of the second active region away from the second metal block is electrically connected to one of the reset power signal lines.

15. The array substrate according to claim 14, characterized in that: The array substrate further includes a first insulating layer located between the first active layer and the first conductive layer, a second insulating layer located between the first conductive layer and the second conductive layer, and a third insulating layer located between the second conductive layer and the third conductive layer; The second electrode of the reset transistor is connected to the second metal block through a first via hole penetrating the first insulating layer and the second insulating layer, the first electrode of the reset transistor is connected to the reset power signal line through a second via hole, and the second via hole penetrates the first insulating layer and the second insulating layer, or the second via hole penetrates the first insulating layer, the second insulating layer and the third insulating layer; Preferably, the first electrode of the driving transistor is connected to the third metal block through a third via hole, and the third via hole passes through the first insulating layer, the second insulating layer and the third insulating layer; Preferably, the control electrode of the driving transistor is connected to the first connecting portion through a fourth via hole, and the first connecting portion is further connected to the first electrode of the threshold compensation transistor through a fifth via hole; The fourth via hole penetrates the second insulating layer and the third insulating layer, and the fifth via hole sequentially penetrates the third insulating layer, the second insulating layer and the first insulating layer.

16. The array substrate according to claim 15, characterized in that: The array substrate further comprises a fourth conductive layer and a fifth conductive layer located on a side of the third conductive layer away from the substrate; the array substrate further comprises a fourth insulating layer located between the third conductive layer and the second active layer, a fifth insulating layer located between the second active layer and the fourth conductive layer, and a sixth insulating layer located on a side of the fourth conductive layer away from the substrate; The fifth conductive layer includes a plurality of data transmission lines extending along the second direction, and the first electrode of the data writing transistor is connected to the data transmission line through a sixth via hole penetrating the sixth insulating layer and the fifth insulating layer; Preferably, the fifth conductive layer further includes a third connection portion extending along the first direction and a fourth connection portion extending along the second direction, the second electrode of the data writing transistor is connected to the third connection portion through a seventh via hole, an end of the third connection portion away from the seventh via hole is connected to the second connection portion through an eighth via hole, and the second connection portion is connected to the second electrode of the coupling capacitor through a ninth via hole; The eighth via hole sequentially penetrates the sixth insulating layer, the fifth insulating layer and the fourth insulating layer, the seventh via hole penetrates the sixth insulating layer and the fifth insulating layer, and the ninth via hole penetrates the third insulating layer; Preferably, the ninth via hole overlaps with the orthographic projection of the first via hole on the substrate; Preferably, the first electrode of the light emitting control transistor is connected to the fourth connecting portion through a tenth via hole, and an end of the fourth connecting portion away from the tenth via hole is connected to the fifth connecting portion through an eleventh via hole; The tenth via hole sequentially penetrates the sixth insulating layer and the fifth insulating layer, and the eleventh via hole sequentially penetrates the sixth insulating layer, the fifth insulating layer and the fourth insulating layer; Preferably, the second electrode of the light emitting control transistor is electrically connected to the first electrode of the light emitting element through a twelfth via hole penetrating the sixth insulating layer and the fifth insulating layer.

17. A method for driving a pixel circuit, characterized in that: Used to drive the pixel circuit according to any one of claims 1 to 9, the method comprising: In the reset stage, the threshold compensation module transmits the first power supply signal to the control end of the driving module; In the threshold compensation stage, the threshold compensation module performs threshold compensation on the driving module based on the first power supply signal; Among them, the voltage of the first power signal in the reset stage and the remaining stages is different, and the first power signal includes a second reset voltage and a first power voltage; the first power line is used to transmit the second reset voltage and the first power voltage to the first end of the driving module in a time-sharing manner.

18. The method according to claim 17, characterized in that In the reset phase, the first power signal is the second reset voltage, and in the remaining phases, the first power signal is the first power voltage; In the reset stage, the threshold compensation module transmits the first power supply signal to the control end of the driving module, including: In the reset phase, the threshold compensation module transmits the second reset voltage to the control terminal of the driving module; In the threshold compensation stage, the threshold compensation module performs threshold compensation on the driving module based on the first power supply signal, including: In the threshold compensation stage, the threshold compensation module performs threshold compensation on the driving module based on the first power supply voltage.

19. The method according to claim 18, characterized in that In the reset stage, the threshold compensation module transmits the first power supply signal to the control end of the driving module, and the data writing module transmits the first reset voltage to the coupling module, including: In a first sub-stage of the reset stage, the voltage of the first power signal jumps from the first power voltage to the second reset voltage; In the second sub-stage of the reset stage, the threshold compensation module transmits the second reset voltage to the control end of the driving module to reset the control end of the driving module; In a third sub-phase of the reset phase, the data writing module transmits the first reset voltage to the coupling module; Preferably, the second reset voltage is less than the first reset voltage; Preferably, in one of the reset phases, the duration of the second sub-phase is longer than the duration of the third sub-phase; Preferably, in one of the reset phases, the duration of the second sub-phase is longer than the duration of the first sub-phase.

20. A display panel, characterized in that: Comprising the array substrate according to any one of claims 10-16.

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