Low-thermal-resistance low-stress multi-chip embedded board-level packaging method and packaging structure thereof

Abstract

The invention belongs to the technical field of chip packaging, and particularly relates to a low-thermal-resistance low-stress multi-chip embedded board-level packaging method and a packaging structure thereof. The chip layout of the multi-chip embedded board-level packaging structure is as follows. The chips and the copper blocks are symmetrically distributed, the copper blocks are respectively arranged at the upper and lower boundaries of the structure, and the z-shaped groove is placed in the middle; the number of the chips is four, every two chips form a group, and the chips in the same group are vertically placed in the longitudinal direction. Eight copper blocks are arranged, four copper blocks form a group, and the copper blocks in the same group are horizontally and tightly placed. The groove, the chip and the copper block are integrally arranged in a central symmetry manner; the chip forms a chip area, and the copper block realizes circuit connection; the chip and the copper block are respectively provided with a plurality of blind holes which are uniformly distributed and are used for realizing a longitudinal electrical connection structure, and the carrier substrate is made of copper; and the grooves are used for realizing electrical insulation and dividing electrode areas. According to the invention, the packaging size of the power device can be reduced, more uniform heat distribution is realized on the basis of low stray sensation and low stress, and the heat-force characteristic of the device is improved.

Description

Technical Field

[0001] The present invention belongs to the field of chip packaging technology, and specifically relates to a low thermal resistance and low stress multi-chip embedded board-level packaging method and a packaging structure thereof. Background Art

[0002] As electronic devices develop towards higher performance and smaller size, traditional single-chip packaging technology can no longer meet the growing power density and heat dissipation requirements. Multi-chip FOPLP has become a development trend due to its excellent electrothermal performance and cost-effectiveness. However, the thermal management and mechanical stress problems caused by the multi-chip layout pose a challenge to the reliability of the packaging structure. At present, the thermomechanical stress distribution of the FOPLP sample with four chips is uneven. The present invention proposes a new layout to even out the thermomechanical properties of the four chips.

[0003] The process of multi-chip board-level packaging is similar to that of single-chip board-level packaging. Both face-up and face-down process flows can be implemented in multi-chip packaging [1]. However, due to the connection of multiple chips in the half-bridge circuit topology and the vertical structure of SiC MOSFET, face-down is usually used in multi-chip board-level packaging [2]. The face-down packaging process starts with the chip being fixed on the substrate. The packaging of the half-bridge topology requires the electrode division of the substrate and the design of the current flow path. The height difference between the source of the upper bridge arm and the drain of the lower bridge arm in the package needs to be eliminated by placing a copper block on the substrate. The copper block is processed in the same way as the chip and is fixed to the substrate by solder at the same time as the chip. The redistribution layer (RDL) is also applied on the copper block to connect the circuit in the half-bridge topology. These technologies have been applied in large-scale production, but there are still problems such as large thermal resistance and severe coupling of heat dissipation paths.

[0004] FOPLP packaging technology can effectively reduce the length of electrical interconnection and the distance of heat conduction, thereby reducing parasitic inductance and thermal resistance. There are already some embedded power module solutions based on copper lead frames and PCBs, but there is still room for further improvement in parasitic parameters and thermal performance optimization. The face-down SiC MOSFET configuration can reduce the common source inductance of the drive circuit and the power circuit, thereby improving the switching performance. The copper connection block can overcome the limitations of the through-hole, achieve double-sided heat dissipation, and improve the current carrying capacity and thermal conductivity. The current research on double-sided heat dissipation packaging of parallel multi-chips mainly focuses on the design of low-inductance and low-thermal resistance packaging [3], and there is not much optimization research on the layout of the chip.

[0005] At present, there are a lot of research contents on the manufacturing process and packaging form of FOPLP, which has obvious improvement in reducing the inductive thermal resistance stress of the whole package. However, in the application of multi-chip modules, the thermal coupling caused by the simultaneous heating of chips will have a bad effect on the temperature and stress characteristics of the device. Therefore, it is very important to reasonably layout the chips in the multi-chip module for uniform temperature and stress distribution. Summary of the invention

[0006] The object of the present invention is to provide a multi-chip board-level packaging method and a packaging structure thereof which have excellent temperature uniformity and stress uniformity and can optimize the FOPLP chip layout.

[0007] The multi-chip board-level packaging process is similar to the single-chip board-level packaging process, and both face-up and face-down assembly processes can be used. However, due to the complex topology of the half-bridge circuit and the vertical structure of the SiC MOSFET, the multi-chip board-level packaging structure usually adopts a face-down process. The present invention adopts a face-down packaging process, and its process is shown in FIG. Figure 1 As shown, the specific steps are:

[0008] Step 1, half-etching the carrier substrate 4; that is, half-etching is performed on the prepared carrier substrate, and the area on the carrier substrate is electrically divided by half-etching, and positioning grooves 5 for the chip 1 and the copper block 2 are formed; since it is used to fix the device during the entire packaging process, it is not completely etched.

[0009] The overall size of the carrier substrate is greater than 200mm*200mm and less than 2m*2m, and the material is pure copper; the size of a single packaging unit is determined according to the design.

[0010] Step 2, install the chip 1 and the copper block 2 on the carrier substrate 4; specifically adopt the reflow process, the material is solder paste / SnSb10 (ES-1100, EarlySun), the temperature rises to above 250°C (the specific value is determined according to the material properties, generally, the temperature rises to 250-290°C), and the entire solder paste curing time lasts for more than 30 minutes (the specific value is determined according to the material properties, generally, the curing time is 30-300 minutes). For half-bridge topology packaging, it is crucial to design the current path and distinguish the electrodes on the substrate. In order to solve the problem of inconsistent source and drain heights, copper blocks need to be placed on the carrier to ensure balanced and effective electrical interconnection.

[0011] Step 3: laminating the plastic encapsulation material and the copper sheet on the carrier in sequence; the plastic encapsulation material is used to provide mechanical support and lay the foundation for the subsequent lamination and packaging of the chip. A copper sheet (layer) is laminated on the plastic encapsulation material to form a redistribution layer (RDL).

[0012] The pressing process in this step is realized by a vacuum fast press. The pressing process requires vacuuming, the temperature is 40-50°C, the time is 1-5min, and the applied pressure is less than 10Kgf / cm 2 (The specific value is determined by the material properties. Generally, the applied pressure is 5-10Kgf / cm 2 After lamination, it needs to be leveled, pre-baked and cured; the leveling process also needs to be vacuumed, the temperature should be higher than the lamination process temperature (for example, the temperature is 100-125℃), and the applied pressure is less than 10Kgf / cm 2 (The specific value is determined by the material properties. Generally, the applied pressure is 5-10Kgf / cm 2 pressure); pre-bake in a nitrogen environment at a temperature of 90-110°C; curing needs to be carried out at a high temperature (e.g. 170-200°C) and last for more than 60 minutes (the specific value is determined according to the properties of the material, generally, the curing time is 60-120 minutes).

[0013] Step 4, making blind holes 3; blind holes are made on the surfaces of the chip 1 and the copper block 2 by combining computer numerical control (CNC) engraving and laser processing, and the blind holes are used to achieve vertical interconnection; the aperture of the blind holes is greater than 0.1 mm and less than 1 mm.

[0014] Step 5, forming an electrical connection structure; specifically, using chemical deposition to deposit a copper layer on the blind hole wall; and then using electroplating to completely fill the blind hole with copper material. This step completes the interconnection process and ensures seamless electrical connection between chip 1 and copper block 2.

[0015] Step 6, etching the circuit pattern; in order to achieve a specific current path, the top redistribution layer (RDL) needs to be divided into several areas. Specifically, the copper layer is complexly etched into a predefined circuit pattern by applying photoresist, photolithography, and etching technology to meet the requirements of the half-bridge topology circuit.

[0016] Step 7, laminating the polypropylene (PP) material and the heat sink: After the etching process is completed, a layer of polypropylene (PP) material and a heat sink are attached to the bottom of the structure to enhance thermal management and structural stability. The laminating process in this step is achieved by a vacuum fast press.

[0017] Step 8: Solder mask lamination: Subsequently, a layer of solder mask is applied on the upper surface of the RDL to provide protection and ensure the reliability of the soldering process. The lamination process in this step is achieved by a vacuum fast press.

[0018] Step 9, developing the solder mask layer; that is, applying photoresist on the top of the solder mask layer to achieve surface patterning for easy connection with external circuits.

[0019] Step 10, patterning; finally, the sample surface is silver-plated to achieve pad formation. Silver plating not only ensures good conductivity, but also helps improve the durability and oxidation resistance of the contact pad.

[0020] After the multi-chip board-level packaging method, a multi-chip board-level packaging structure is obtained, that is, a multi-chip FOPLP half-bridge module. The chip layout of the multi-chip board-level packaging structure is as follows: Figure 2 As shown in the figure, the chip 1 (large square in the figure) and the copper block 2 (small square in the figure) are symmetrically distributed, and the copper blocks 2 are arranged at the upper and lower boundaries of the structure respectively, and the groove 5 is placed in the middle in a "z" shape; there are four chips 1 in total, two in a group, and the chips in the same group are placed vertically, and the minimum spacing between the chips is equal to 0.6mm, and the maximum does not exceed the package size; there are eight copper blocks 2 in total, four in a group, and the copper blocks in the same group are placed horizontally and closely, and the minimum spacing is equal to 0.6mm, and the maximum does not exceed the package size. The groove 5, the four chips 1, and the eight copper blocks 2 are generally arranged in a central symmetrical layout; wherein, the chip 1 constitutes the chip area, and the copper block 2 realizes the circuit connection; the blind hole 3 (the small dot position evenly arranged on the chip and the copper block in the figure) is used to realize the structure of longitudinal electrical connection (through copper deposition on the blind hole wall and copper filling in the blind hole), which is to achieve surface copper deposition and then fill by electroplating. The material of the substrate 4 is copper. The groove 5 (the white area in the figure) is used to realize electrical insulation to divide the electrode area, and the epoxy resin plastic encapsulation material 6 (the black area in the figure) is used for the entire device packaging. The distance between chips has been verified by simulation.

[0021] The board-level fan-out package proposed in the present invention reduces the package size of the power device, realizes a more uniform thermal distribution on the basis of low inductance and low stress, and improves the thermal-mechanical characteristics of the entire device. Among them, under certain conditions, the maximum junction temperature of the chip can be reduced by 3-4°C. The temperature difference between parallel chips is reduced from the original 3°C (0.5°C) to about 1°C (0.3°C). The present invention provides a low thermal resistance, high integration, low thermal resistance board-level half-bridge power module packaging structure, which provides new possibilities for fully releasing the performance of silicon carbide chips through symmetrical chip layout.

[0022] The chip layout proposed in the present invention can achieve uniform temperature distribution and stress distribution, further optimize the thermal performance of FOPLP on the basis of low noise, effectively solve the thermal performance problem caused by chip layout in multi-chip packaging, and provide a new solution for the large-scale application of SiC devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a flowchart of the multi-chip embedded board-level packaging method of the present invention.

[0024] Figure 2It is a schematic diagram of the chip layout in the multi-chip panel-level packaging structure (multi-core half-bridge FOPLP module) of the present invention.

[0025] Figure 3 Schematic diagram of the sliced ​​structure of different layers of the multi-core half-bridge FOPLP.

[0026] Figure 4 Schematic diagram of blind holes in the cross-section of the FOPLP chip layer.

[0027] Figure 5 Temperature and stress distribution of FOPLP after optimization.

[0028] Figure 6 This is the thermal resistance test curve of the double interface method.

[0029] The numbers in the figure are: 1 is a chip, 2 is a copper block, 3 is a blind hole, 4 is a substrate 4, 5 is a groove, and 6 is a filling material. DETAILED DESCRIPTION

[0030] The present invention is further described below by way of embodiments in conjunction with the accompanying drawings.

[0031] The process of the present invention is shown in Figure 1 As shown, the specific steps are:

[0032] (1) Prepare a board-level carrier with a thickness of 230um and an overall size of 508*203*0.1mm. The material is pure copper. The size of a single package unit is 20*20*0.1mm. Perform half etching on the prepared carrier substrate.

[0033] (2) Install the chip and copper block onto the carrier board. The chip and copper block are symmetrically distributed. The copper blocks are arranged at the upper and lower boundaries of the structure, and the grooves are placed in the middle in a "z" shape. There are four chips in total, two in a group, and the chips in the same group are placed vertically. The spacing between the chips is 3.95mm. There are eight copper blocks in total, four in a group, and the copper blocks in the same group are placed horizontally and closely, with a spacing of 0.6mm. Among them, 1 large square is the chip area, and 2 small squares are copper blocks for circuit connection. The small dots 3 in the structure are the positions of blind holes above the chip and copper blocks. Blind holes are structures for realizing longitudinal electrical connections. They are made by electroplating to deposit copper on the surface and then fill them. The black area is the carrier substrate 4, and the material is copper. The white groove 5 realizes the electrical insulation and divides the electrode area. It is filled with plastic packaging material 6 in the entire package. The entire layout is symmetrically distributed, and the distance between the chips has passed the simulation verification. The chip size is: 3.7mm*4.1mm

[0034] The size of the copper block is 2mm*2mm. The reflow process is used, and the material is solder paste / SnSb10 (ES-1100, EarlySun). The temperature rises to 285℃. The entire solder paste curing time lasts 300 minutes.

[0035] (3) Press the plastic encapsulation material on the carrier board with a thickness of 200um+80um. Then press a whole copper layer with a thickness of 70um on the plastic encapsulation material to form a redistribution layer (RDL). The lamination process in this step is achieved by a vacuum fast press. The lamination process requires vacuuming, a temperature of 45°C, a time of 1min, and a pressure of 5Kgf / cm 2 The leveling process also requires vacuuming, temperature 120℃, time 5min, pressure 6Kgf / cm 2 The pre-baking temperature is 100°C in a nitrogen environment for 30 minutes. The curing temperature is 180°C for 120 minutes.

[0036] (4) In order to achieve vertical interconnection, blind holes with a diameter of 200 μm and a depth of 80 μm were made on the surface of the chip and copper block by combining computer numerical control (CNC) engraving and laser processing.

[0037] (5) After cleaning, copper is deposited on the blind hole wall using chemical deposition. The blind hole is then completely filled using an electroplating process.

[0038] (6) In order to realize a specific current path, the top RDL needs to be divided into several areas. Through the application of photoresist, photolithography, and etching technology, the copper layer is complexly etched into a predefined circuit pattern to meet the requirements of the half-bridge topology circuit.

[0039] (7) After the etching process is completed, a layer of polypropylene (PP) material with a thickness of 130um and a heat sink with a thickness of 30um is attached to the bottom of the structure to enhance thermal management and structural stability. The pressing process in this step is achieved by a vacuum fast press. The pressing process requires vacuuming, a temperature of 180°C, a time of 7 minutes, and a pressure of 6Kgf / cm 2 The curing temperature is 160°C and the curing time is 120 minutes.

[0040] (8) Then, a solder mask layer with a thickness of 20 um is applied on the upper surface to provide protection and ensure the reliability of the welding process. The pressing process in this step is achieved by a vacuum fast pressing machine.

[0041] (9) Apply photoresist on the top to achieve surface patterning.

[0042] (10) Finally, the sample surface is silver-plated.

[0043] The cross-sections of the prepared FOPLP samples were examined to determine the structure and thickness of each constituent layer. Figure 3As shown, the different layers can be observed using an Axioscope 5 metallographic microscope. The sample contains four embedded SiC MOSFETs. The chip size is 3.74mm x 4.13mm, and the copper block size is 2mm x 2mm. The overall package size is 20mmx20mm. Considering the insulation between different electrode areas and the filling of the molding material, the spacing between different potential structures needs to be greater than 0.6mm. Figure 4 A cross-sectional perspective view of the blind via layer is shown, where the diameter of the blind via is over 170μm. Although blind vias are very common in this layer, their individual diameters are relatively small. Therefore, the copper area of ​​the blind via located above the chip is much smaller compared to the surface area of ​​the chip.

[0044] Figure 5 The temperature and top surface displacement distribution of the optimized layout are shown under the conditions that the upper and lower bridge arms work alternately at a duty cycle of 50%, the switching frequency is 100kHz, and the on-current is constant at 10A. The maximum junction temperature of the chip is reduced from 82.10℃ to 79.56℃. In addition, the temperature unevenness caused by thermal coupling between chips is also improved. In the original package, the average temperatures of the two parallel chips were 80.15℃ and 76.83℃, respectively. After optimization, the average temperatures of the two parallel chips were 77.41℃ and 76.18℃, respectively, and the temperature difference between the chips was reduced from 3.32℃ to 1.23℃. The displacement in the Z direction was reduced by 6%. In addition, the uniformity was also significantly improved. These improvements confirm the advantages of the optimized layout design.

[0045] like Figure 6 As shown in Figure 1, the thermal resistance of the FOPLP sample was measured using the double interface method. By determining the dividing point of the two curves, the thermal resistance of FOPLP was determined to be 1.15K / W.

[0046] The board-level packaging samples produced by the present invention have excellent thermal mechanical properties, especially the maximum junction temperature of the chip is reduced from 82.10°C to 79.56°C. In addition, the temperature unevenness caused by thermal coupling between chips is also improved. In the original package, the average temperatures of the two parallel chips were 80.15°C and 76.83°C, respectively. After optimization, the average temperatures of the two parallel chips were 77.41°C and 76.18°C, respectively, and the temperature difference between the chips was reduced from 3.32°C to 1.23°C. The displacement in the Z direction was reduced by 6%. In addition, the uniformity was also significantly improved. These improvements confirm the advantages of the optimized layout design. At the same time, the thermal resistance of the FOPLP sample was measured using the double interface method. By determining the dividing point of the two curves, the thermal resistance of FOPLP was determined to be 1.15K / W. The low thermal resistance and low stress characteristics of the proposed packaging structure are demonstrated.

[0047] References:

[0048] [1]J.N.Sharma and R.Kaur,“Flexural response of thermoelastic thinbeamresonators due to thermal and mechanical loads,”International JournalofMechanical Sciences,vol.101–102,pp.170–179,Oct.2015,doi:10.1016 / j.ijmecsci.2015.07.014.

[0050] [2] D. “Forced Vibration Responses of Axially FunctionallyGraded Beamsby using Ritz Method,”Journal of Applied and ComputationalMechanics,vol.7,no.1,pp.109–115,Jan.2021,doi:10.22055 / jacm.2020.34865.2491.

[0052] [3]K.Xie,Y.Wang,X.Fan,and T.Fu,“Nonlinear free vibration analysisoffunctionally graded beams by using different shear deformation theories,”Applied Mathematical Modelling,vol.77,pp.1860–1880,Jan.2020,doi:10.1016 / j.apm.2019.09.024。

Claims

1. A low thermal resistance and low stress multi-chip embedded board-level packaging method, characterized in that: The face-down packaging process is adopted, and the specific steps are as follows: Step 1, half-etching the carrier substrate (4); that is, half-etching is performed on the carrier substrate, and the area on the carrier substrate is electrically divided by half-etching, and positioning grooves (5) for the chip (1) and the copper block (2) are formed; Step 2, mounting the chip (1) and the copper block (2) on a carrier substrate (4); Step 3, laminating a plastic encapsulation material and a copper sheet on the carrier in sequence; the plastic encapsulation material is used to provide mechanical support and lay a foundation for subsequent lamination and packaging of the chip; laminating a copper sheet on the plastic encapsulation material to form a redistribution layer (RDL); Step 4, making blind holes (3); that is, making blind holes on the surface of the chip (1) and the copper block (2) by combining computer numerical control engraving and laser processing, and the blind holes are used to achieve vertical interconnection; Step 5, forming an electrical connection structure; specifically, using a chemical deposition method to deposit a copper layer on the blind hole wall; and then using an electroplating process to completely fill the blind hole with copper material; ensuring seamless electrical connection between the chip (1) and the copper block (2); Step 6, etching a circuit pattern; dividing the top redistribution layer (RDL) into several areas, and etching the copper layer into a predefined circuit pattern by applying photoresist, photolithography, and etching technology to meet the requirements of the half-bridge topology circuit; Step 7, pressing the polypropylene (PP) material and the heat sink; After the etching process is completed, a layer of polypropylene (PP) material and heat sink are attached to the bottom of the structure to enhance thermal management and structural stability; Step 8, solder mask lamination; Apply a solder mask layer on the upper surface of the RDL; Step 9, developing the solder mask layer; That is, photoresist is applied on the top of the solder mask to achieve surface patterning for easy connection with external circuits; Step 10, patterning: silver-plating the surface of the sample to form a pad; The chip layout is as follows: the chip (1) and the copper block 2 are symmetrically distributed, the copper blocks (2) are arranged at the upper and lower boundaries of the structure, and the groove (5) is arranged in the middle in a "z" shape; there are four chips (1) in total, two chips in a group, and the chips in the same group are arranged vertically, and the spacing between the chips is greater than or equal to 0.6 mm; there are eight copper blocks (2) in total, four chips in a group, and the copper blocks in the same group are arranged horizontally and closely, and the spacing is greater than or equal to 0.6 mm; the groove (5), the four chips (1), and the eight copper blocks (2) are generally arranged in a central symmetrical manner; wherein the chip (1) constitutes a chip area, and the copper block (2) realizes circuit connection; the chip (1) and the copper block (2) are respectively provided with a plurality of blind holes (3) arranged evenly, which are used to realize a structure of vertical electrical connection, and the material of the carrier substrate (4) is copper; the groove (5) is used to realize electrical insulation to divide the electrode area, and the filling material (6) is used to encapsulate the entire device.

2. The low thermal resistance and low stress multi-chip embedded board-level packaging method according to claim 1, characterized in that: The overall size of the carrier substrate in step 1 is greater than 200mm*200mm and less than 2m*2m, and the material is pure copper; the size of a single packaging unit is determined according to the design.

3. The low thermal resistance and low stress multi-chip embedded board-level packaging method according to claim 1, characterized in that: In step 2, the chip (1) and the copper block (2) are mounted on the carrier substrate (4), specifically using a reflow soldering process, the material is solder paste / SnSb10, the temperature is raised to above 250° C., and the entire solder paste curing time is more than 30 minutes.

4. The low thermal resistance and low stress multi-chip embedded board-level packaging method according to claim 1, characterized in that: The lamination process described in step 3 is achieved by a vacuum fast press. The lamination process is vacuumed, the temperature is 40-50°C, the time is 1-5 minutes, and the applied pressure is less than 10Kgf / cm 2 After lamination, it is leveled, pre-baked and cured. The leveling process is also vacuumed, the temperature is 100-125℃, and the applied pressure is less than 10Kgf / cm 2 ; Pre-baking is carried out in a nitrogen environment at a temperature of 90-110°C; curing is carried out under high temperature conditions and lasts for more than 60 minutes.

5. The low thermal resistance and low stress multi-chip embedded board-level packaging method according to claim 1, characterized in that: The blind hole diameter in step 4 is greater than 0.1 mm and less than 1 mm.

6. The low thermal resistance and low stress multi-chip embedded board-level packaging method according to claim 1, characterized in that: The pressing process described in step 7 is achieved by a vacuum fast pressing machine.

7. A low thermal resistance and low stress multi-chip embedded board-level packaging structure obtained by the method according to any one of claims 1 to 6.

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