Method, device and equipment for determining offset of wafer

Abstract

The invention provides a method, device and equipment for determining the offset of a wafer, and the method can carry out the on-off testing of a plurality of first links through electrical testing equipment, and determines the on-off states of the plurality of first links, and each first link comprises any one first copper column in the wafer, any one second copper column in the wafer, and any one second copper column in the wafer. The offset of the wafer is determined according to the on-off state of each first link, a first copper column in the wafer, a first rewiring layer corresponding to the first copper column, a second copper column in the wafer, a second rewiring layer corresponding to the second copper column, and a path between the first copper column and the second copper column according to the on-off state of each first link. In the technical scheme, a link is formed between every two redistribution layers, the offsets applied to the redistribution layers on each link are different, and when the link in a non-conducting state is determined, the offset of the actual wafer can be accurately determined according to the offset corresponding to the non-conducting link.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a method, device, chip and electronic device for determining an offset of a chip (English: die). Background Art

[0002] As the semiconductor industry enters the post-Moore era, fan-out package (FOP) packaging technology that can achieve higher integration has been widely used. Among them, chip first FOP has become the packaging form of many chip products due to its excellent cost advantage. However, for chip first FOP packaging, as the number of integrated dies increases, the problem of chip offset (English: die shift) has become an increasingly key bottleneck hindering the evolution of chip first FOP packaging technology. How to test die shift during FOP recon has become an important difficulty faced by the industry.

[0003] In the prior art, a method based on optical measurement of die shift is proposed, that is, sampling detection is performed on the top, bottom, left, right and middle positions of the wafer (recon wafer) after FOP Recon processing, and an optical microscope is used to perform distance analysis on the copper column (Cu stud) profile and the polyimide opening (PI opening) profile under the view of the microscope to obtain the die shift.

[0004] However, the measurement method in the prior art requires manual intervention, and the obtained die shift is inaccurate. Summary of the invention

[0005] The present application provides a method, device and equipment for determining the offset of a chip, so as to solve the problem of inaccurate die shift testing in the prior art.

[0006] In a first aspect, the present application provides a method for determining an offset of a wafer, comprising:

[0007] Performing an on-off test on a plurality of first links by means of an electrical testing device to determine the on-off status of the plurality of first links, wherein each first link comprises: any first copper pillar in a wafer, a first redistribution layer corresponding to the first copper pillar, a second copper pillar in the wafer, a second redistribution layer corresponding to the second copper pillar, and a path between the first copper pillar and the second copper pillar, wherein the second copper pillar is another copper pillar other than the first copper pillar, and preset offsets are applied to the first redistribution layer and the second redistribution layer in each first link, respectively, and the preset offsets in each first link are different;

[0008] The offset of the wafer is determined according to the on / off status of each first link.

[0009] In a possible implementation manner, before performing a continuity test on the plurality of first links by using an electrical testing device to determine the continuity status of the plurality of first links, the method further includes:

[0010] In response to the design operation, a plurality of different copper pillar groups are selected on the wafer, each copper pillar group respectively including the first copper pillar and the second copper pillar;

[0011] For each copper pillar group, the preset offset is applied to the first redistribution layer corresponding to the first copper pillar and the second redistribution layer corresponding to the second copper pillar respectively, and the preset offset corresponding to each copper pillar group is different.

[0012] In a possible implementation manner, determining the offset of the chip according to the on / off status of each first link includes:

[0013] Determine a second link whose on / off state is non-conductive from the on / off states of the first links;

[0014] The offset of the chip is determined according to the preset offset corresponding to the second link.

[0015] In a possible implementation manner, determining the offset of the chip according to a preset offset corresponding to the second link includes:

[0016] Determine a difference between a first threshold and a preset offset corresponding to the second link, the first threshold being a minimum offset at which the same copper pillar and the redistribution layer corresponding to the copper pillar do not contact each other;

[0017] The maximum value among the differences is determined as the offset of the wafer.

[0018] In a possible implementation, the chip includes: a plurality of the wafers;

[0019] Accordingly, the method further includes:

[0020] According to the offset of each chip, an offset map is determined, and the offset map records the offsets of all chips on the entire wafer.

[0021] In a possible implementation manner, the method for determining the first threshold includes:

[0022] The first threshold is determined according to a first diameter length of a same copper pillar in a wafer and a second diameter length of a redistribution layer corresponding to the copper pillar.

[0023] In a second aspect, the present application provides a device for determining an offset of a wafer, comprising: a first determining module and a second determining module;

[0024] The first determination module is used to perform an on / off test on a plurality of first links through an electrical testing device to determine the on / off status of the plurality of first links, each first link comprising: any first copper pillar in a wafer, a first redistribution layer corresponding to the first copper pillar, a second copper pillar in the wafer, a second redistribution layer corresponding to the second copper pillar, and a path between the first copper pillar and the second copper pillar, the second copper pillar being another copper pillar other than the first copper pillar, the first redistribution layer and the second redistribution layer in each first link being respectively applied with a preset offset, and the preset offsets in each first link are different;

[0025] The second determination module is used to determine the offset of the chip according to the on / off status of each first link.

[0026] In a possible implementation manner, before performing a continuity test on the plurality of first links by using an electrical testing device to determine the continuity status of the plurality of first links, the first determining module is further configured to:

[0027] In response to the design operation, a plurality of different copper pillar groups are selected on the wafer, each copper pillar group respectively including the first copper pillar and the second copper pillar;

[0028] For each copper pillar group, the preset offset is applied to the first redistribution layer corresponding to the first copper pillar and the second redistribution layer corresponding to the second copper pillar respectively, and the preset offset corresponding to each copper pillar group is different.

[0029] In a possible implementation manner, the second determining module is used to:

[0030] Determine a second link whose on / off state is non-conductive from the on / off states of the first links;

[0031] The offset of the chip is determined according to the preset offset corresponding to the second link.

[0032] In a possible implementation manner, the second determination module determines the offset of the chip according to a preset offset corresponding to the second link, specifically for:

[0033] Determine a difference between a first threshold and a preset offset corresponding to the second link, the first threshold being a minimum offset at which the same copper pillar and the redistribution layer corresponding to the copper pillar do not contact each other;

[0034] The maximum value among the differences is determined as the offset of the wafer.

[0035] In a possible implementation, the chip includes: a plurality of the wafers;

[0036] Accordingly, the second determining module is further used for:

[0037] According to the offset of each chip, an offset map is determined, and the offset map records the offsets of all chips on the entire wafer.

[0038] In a possible implementation manner, when determining the first threshold, the second determining module specifically:

[0039] The first threshold is determined according to a first diameter length of a same copper pillar in a wafer and a second diameter length of a redistribution layer corresponding to the copper pillar.

[0040] In a third aspect, the present application provides an electronic device, including:

[0041] at least one processor; and

[0042] a memory communicatively coupled to the at least one processor;

[0043] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the electronic device to execute the method in various possible implementation modes involved in the first aspect above.

[0044] In a fourth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions. When a processor executes the computer-executable instructions, the method involved in the first aspect and various possible implementations described above is implemented.

[0045] In a fifth aspect, the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the methods in various possible implementations involved in the first aspect above.

[0046] The present application provides a method, device and equipment for determining the offset of a chip. The method can perform on-off tests on multiple first links through electrical testing equipment to determine the on-off status of multiple first links. Each first link includes: any first copper pillar in the chip, a first redistribution layer corresponding to the first copper pillar, a second copper pillar in the chip, a second redistribution layer corresponding to the second copper pillar, and a path between the first copper pillar and the second copper pillar. The second copper pillar is another copper pillar other than the first copper pillar. The first redistribution layer and the second redistribution layer in each first link are respectively applied with preset offsets. The preset offsets in each first link are different. Then, the offset of the chip is determined according to the on-off status of each first link. In this technical solution, a link is formed between every two redistribution layers, and the offset applied to the redistribution layer on each link is different. When it is determined that there is a link in a non-conducting state, the offset corresponding to this non-conducting link can be used to accurately determine the offset of the actual chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0048] Figure 1 A schematic diagram of a fan-out package (FOP) package structure is shown;

[0049] Figure 2 A schematic diagram showing the offset of a wafer;

[0050] Figure 3 A schematic diagram of a wafer offset testing method is shown;

[0051] Figure 4 A schematic diagram of an application scenario provided for an embodiment of the present application;

[0052] Figure 5 A schematic flow chart of a first embodiment of a method for determining a wafer offset provided by the present application;

[0053] Figure 6 A schematic diagram of multiple first links on a chip provided by the present application;

[0054] Figure 7 A schematic diagram of the structure of one of the first links provided in this application;

[0055] Figure 8 A schematic flow chart of a second embodiment of a method for determining a wafer offset provided by the present application;

[0056] Fig. 9 A schematic diagram of the structure of the first second link provided for this application;

[0057] Fig.10 A schematic diagram of the structure of the second second link provided for this application;

[0058] Fig.11 A schematic diagram of the structure of the third second link provided for this application;

[0059] Fig.12 It is a schematic diagram corresponding to the offset of the wafer in actual situation;

[0060] Fig.13 A schematic diagram of the structure of an embodiment of a device for determining the offset of a wafer provided in the present application;

[0061] Fig.14 A schematic diagram of the structure of an electronic device embodiment provided in the present application.

[0062] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0063] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0064] First, the professional terms and technical background involved in the embodiments of the present application are introduced.

[0065] 1. Professional terms:

[0066] Die: Wafer or chip, refers to each fully functional unit on the wafer;

[0067] Chip First FOP: FOP is the abbreviation of Fan-out package, a packaging form in which the die is reconned first and then a redistributed layer (RDL) is added;

[0068] RDL: Metal layer, which plays the role of electrical extension and interconnection in the XY plane;

[0069] Die shift: refers to the deviation between the actual position and the designed position of the chip during the mounting process;

[0070] FOP Recon: Recon is the abbreviation of reconstruction, which means reconstruction. FOP Recon is the reconstruction process of the front end of the process line;

[0071] Recon wafer: This is the wafer after FOP Recon processing;

[0072] Cu stud: Copper pillar, used to connect the structure between the chip and the substrate. The Cu stud outline describes the shape and size of the copper pillar.

[0073] PI opening: Polyimide opening. PI can be used as an insulating layer between metal layers. That is, PI opening is an opening of an insulating layer. The metal layers are connected through the metal at the PI opening. The metal at the PI opening is also called via.

[0074] Via: via or through hole;

[0075] Rotating: Rotating refers to rotating an object or figure by a certain angle along the center point. In the chip design or manufacturing process, rotation can be used to adjust the direction of components or circuits;

[0076] RD: may refer to the abbreviation of Research and Development, which means research and development activities, including innovation, design, testing, etc.

[0077] AP layer: aluminum pad layer, refers to the metal layer closest to Cu stud on the die;

[0078] Molding: Plastic packaging process. 2. Technical background:

[0080] As the semiconductor industry enters the post-Moore era, fan-out package (FOP) packaging technology that can achieve higher integration has been widely used. Among them, chip first FOP has become the packaging form of many chip products due to its excellent cost advantage.

[0081] The chip first FOP packaging process may include: incoming wafer, wafer bumping, wafer grinding, laser micro-cutting / die sawing, reconstitution / die bond, molding / decarrier removal, backside taping, topside grinding, RDL+C4 Bump, and final assembly.

[0082] Figure 1 A schematic diagram of a FOP packaging structure is shown, such as Figure 1 As shown, a first chip (English: Die), a second Die, a third Die, a package cover (English: lid), and a wiring substrate (English: substrate) are provided.

[0083] During molding, copper pillars are deployed under the die, and layers of redistribution layers are deployed under the copper pillars, for example, redistribution layers (RDL) 1 and RDL2, and polyimide is deployed around the redistribution layers, for example, PI1 and PI2.

[0084] for Figure 1 For the chip first FOP packaging example, as the number of integrated dies increases, the problem of die shift is increasingly becoming a key bottleneck hindering the evolution of chip first FOP packaging technology. That is, in the Recon / DieBond stage, during the Recon wafer process, the die shift in the chip needs to be measured.

[0085] First, the generation and impact of die shift in the Recon process are introduced. Figure 2 A schematic diagram showing the offset of a wafer is shown, Figure 2 As shown, the ideal situation and two deviation situations and their corresponding impacts are exemplified.

[0086] Among them, the position relationship between the chip and the copper pillar is fixed. Due to the inaccurate layout of the redistribution layer, the layout of the polyimide changes. Figure 2Assume that the diameter of the copper pillar is 22um and the diameter of the redistribution layer is 10um (the diameter depends on the actual situation). The die shift can be the same copper pillar in the die (i.e. Figure 1 Cu stud in the diagram) and its corresponding redistribution layer (i.e. Figure 1 The position offset between the centers of RDL1).

[0087] In the ideal case 21, the copper pillar does not rotate, and the displacement with the redistribution layer is 0um, that is, die shift = 0um;

[0088] In the first offset (i.e., Rotation 1) case 22, there is a slight rotation between the copper pillar and the redistribution layer, and the displacement between the copper pillar and the redistribution layer is 6um, i.e., die shift = 6um;

[0089] In the second offset (ie, Rotating 2) case 23, there is a serious rotation between the copper pillar and the redistribution layer, and the displacement between the copper pillar and the redistribution layer is 16 um, ie, die shift = 16 um.

[0090] That is, when the die shift is less than 16um, the copper pillar is connected to the redistribution layer; when the die shift is greater than or equal to 16um, the copper pillar is not connected to the redistribution layer and there is an open.

[0091] It should be understood that: for the convenience of distinction, Figure 2 The markings for the components are universal in all cases, and only one mark is given in the attached figure.

[0092] In one possible case, when the number of packaged dies increases, if the die shift value cannot be measured in time, the displacement between the redistribution layer and the copper pillar may become larger and larger, affecting the packaging and performance of the entire chip.

[0093] Furthermore, in chip first FOP packaging, how to test the die shift value during the FOP recon process has become an important issue facing the industry.

[0094] In traditional die shift testing, it is often necessary to perform sampling inspections at the top, bottom, left, right, and center of the wafer during the wafer recon process and measure using an optical microscope, such as Figure 3 As shown, Figure 3 A schematic diagram of a wafer offset testing method is shown.

[0095] That is, taking a sampling in a wafer as an example, firstly, a copper pillar and the corresponding polyimide in the die to be tested are photographed by an optical microscope. Under ideal conditions (which may be the case where there is no offset), Figure 3 The left side shows the outline of the copper column and the outline of the polyimide. The center points of the two outlines coincide with each other. In actual situations, Figure 3 As shown on the right, there is a certain distance between the center points corresponding to the two contours. At this time, the technicians measure the two distances and obtain a distance S, which is the center distance between the contour of the copper column and the contour of the polyimide.

[0096] The judgment rule is: if S < the offset relative to the expected position (English: shift spec), then the judgment is passed (English: pass); if S > shift spec, then the judgment is failed (English: fail).

[0097] It should be understood that the shift spec is the actual tolerance for the offset.

[0098] The above-mentioned traditional die shift test has the following technical problems:

[0099] 1. Due to human intervention, there are measurement errors; and only pass or fail can be judged, and the offset cannot be accurately measured.

[0100] 2. Sampling detection cannot provide 100% coverage, and some chips with offsets exceeding the spec cannot be intercepted.

[0101] 3. It is impossible to obtain the die shift of different areas on the entire wafer, and it is impossible to understand the impact of molding and other processes on die shift, and thus it is impossible to optimize the process.

[0102] In response to the problems existing in the above-mentioned prior art, the inventors discovered during the study of die shift that if there is an offset between the copper pillar and its corresponding redistribution layer, if the offset is too large, the copper pillar and its corresponding redistribution layer will not be in contact, that is, when current is applied to the redistribution layer, the copper pillar cannot receive the current. Therefore, before the chip is packaged, if different offsets can be designed for different groups (each group includes two copper pillars, and the redistribution layers corresponding to the corresponding copper pillars), after the packaging is completed, the non-conducting link can be determined according to the on-off state of the link formed between the two redistribution layers in each group. Then, the actual offset between the redistribution layer and the corresponding copper pillar, that is, die shift, can be determined based on the offset corresponding to the non-conducting link and the minimum center distance between the same copper pillar and the redistribution layer when it is not conductive.

[0103] Figure 4A schematic diagram of an application scenario provided in an embodiment of the present application, such as Figure 4 As shown, the application scenario diagram includes: electrical testing equipment 41 and electronic equipment 42.

[0104] The electronic device 42 is the execution subject of the embodiment of the present invention, and may be a computing device, a server, a mobile phone, a computer or other equipment; the electrical testing equipment 41 may be an open / short electrical testing machine or other equipment.

[0105] It should be understood that in some possible implementations, the electronic device 42 may also be a device that integrates the relevant functions of the electrical testing device 41 involved in this application, and the execution of its corresponding method will change accordingly. The principles involved are similar and will not be repeated here.

[0106] As an implementation scenario, before chip packaging, technicians divide pairs of copper pillars on the die into a group, and apply a preset offset to the redistribution layer corresponding to each group of copper pillars. The preset offset applied to the redistribution layer corresponding to each group of copper pillars is different. For example, the preset offset of group 1 is 2um, the preset offset of group 2 is 6um, and the preset offset of group 3 is 10um.

[0107] The die is packaged according to the offset. After the packaging is completed, the electronic device 42 controls the electrical testing equipment 41 to perform on-off tests on the links related to each group of copper pillars. For each group of copper pillars, the link is a link formed between two redistribution layers in the group. When it is measured that there is a link non-conduction, the die shift is determined according to the preset offset corresponding to the non-conducting link.

[0108] It should be understood that this scenario embodiment is a possible implementation and is not intended to be a limitation of the embodiment. For details not disclosed in this embodiment, please refer to the following embodiments.

[0109] The technical solution shown in the present application is described in detail below through specific embodiments. It should be noted that the following embodiments can exist independently or in combination with each other, and the same or similar contents will not be described repeatedly in different embodiments.

[0110] Figure 5 The flowchart of the first embodiment of the method for determining the offset of a wafer provided in the present application is as follows: Figure 5 As shown, the method for determining the offset of the wafer includes the following steps:

[0111] Step 51: Perform an on / off test on the plurality of first links by using an electrical testing device to determine the on / off status of the plurality of first links.

[0112] Each first link includes: any first copper pillar in the wafer, a first redistribution layer corresponding to the first copper pillar, a second copper pillar in the die, a second redistribution layer corresponding to the second copper pillar, and a path between the first copper pillar and the second copper pillar, the second copper pillar is another copper pillar other than the first copper pillar, and a preset offset is applied to the first redistribution layer and the second redistribution layer in each first link, respectively, and the preset offsets in each first link are different;

[0113] First, combine Figure 6 , introduce the first link, Figure 6 A schematic diagram of multiple first links on a wafer provided by the present application.

[0114] For example, on a wafer, a die may have Figure 6 (which can be understood as a top view) shows multiple Custuds 61, and RDLs 62 corresponding to each Cu stud 61, then the first link can be understood as being constructed for every two RDLs 62, specifically including: a first RDL, a first Cu stud, a second RDL, a second Cu stud, and a path 63 between the first Cu stud and the second Custud, that is, from a to b, or b to a.

[0115] To explain more clearly, Figure 7 A schematic diagram of the structure of one of the first links provided in this application, Figure 7 For Figure 6 Two adjacent Cu studs randomly selected from the figure, and the cross-sectional view corresponding to the side view or front view of the device involved.

[0116] The first link (indicated by a thick black line, where a points to b, or b points to a) is a link passing through the first RDL 621 , the first Cu stud 611 , the via 63 between the first Cu stud 611 and the second Cu stud 612 , the second Cu stud 612 , and the second RDL 622 .

[0117] For different first links, there are different preset offsets between the first RDL 621 and the first Cu stud 611 (between the second RDL 622 and the second Cu stud 612), for example, Figure 7 In the example, an offset of 0.1 um is applied between the first RDL 621 and the first Cu stud 611 of the first link, and an offset of 0.5 um is applied between the first RDL 621 and the first Cu stud 611 of other first links.

[0118] That is, in the packaged die, each first link has a first RDL 621 and a first Cu stud 611 (a second RDL 622 and a second Cu stud 612) with different preset offsets.

[0119] It should be understood that: Figure 6 The number of copper pillars, the number of redistribution layers, and the copper pillars and redistribution layers involved in each first link can all be determined according to actual conditions, and this is only an example for describing the embodiments of the present application.

[0120] In a possible implementation, the electrical testing device 41 is used to perform a continuity test on each first link. Figure 7 For example, the electrical testing device 41 is controlled to apply current to the side a, and whether there is current on the side b is detected, that is, whether the first link between a and b is connected.

[0121] When current is detected on the b side, the on / off state of the first link is determined to be conductive; when no current is detected on the b side, the on / off state of the first link is determined to be non-conductive.

[0122] Or, in another possible implementation, the electrical testing device 41 is used to perform a continuity test on at least one first link, that is, Figure 7 For example, the electrical testing device 41 is controlled to apply current to the b side, and whether there is current on the a side is detected, that is, whether the first link between a and b is connected.

[0123] When current is detected on the a side, the on / off state of the first link is determined to be conductive; when no current is detected on the a side, the on / off state of the first link is determined to be non-conductive.

[0124] In an actual on-off test, side a actually corresponds to the BGA at the first RDL 621, and side b actually corresponds to the BGA at the second RDL 622, that is, current is applied to the BGA at the first RDL 621, and current detection is performed on the BGA at the second RDL 622; or current is applied to the BGA at the second RDL 622, and current detection is performed on the BGA at the first RDL 621.

[0125] In addition, before step 51, the method for determining the offset of the wafer may also be performed as follows (the following is a design-related operation before packaging the chip):

[0126] Step 1, in response to a design operation, selecting a plurality of different copper pillar groups on a wafer, each copper pillar group comprising a first copper pillar and a second copper pillar;

[0127] The technicians select multiple groups of copper pillars on the die. Figure 6In the illustrated scenario, the copper studs in each first link are a group of copper studs, for example, a first Cu stud 611 and a second Cu stud 612 .

[0128] Step 2: For each copper pillar group, a preset offset is applied to the first redistribution layer corresponding to the first copper pillar and the second redistribution layer corresponding to the second copper pillar, and the preset offset corresponding to each copper pillar group is different.

[0129] The technicians designed different preset offsets for each copper pillar group. For example, for the first copper pillar group, the offset between the redistribution layer and the copper pillar in the copper pillar group is 0.5um; for the second copper pillar group, the offset between the redistribution layer and the copper pillar in the copper pillar group is 1um; for the third copper pillar group, the offset between the redistribution layer and the copper pillar in the copper pillar group is 1.5um. After that, the relevant equipment for chip packaging performs packaging operations according to the design.

[0130] In one possible implementation, the design for the preset offset may cover 0 to the center distance when the copper pillar and the redistribution layer are not in contact (e.g., 0-16um), and the design granularity may be 0.1um, 0.2um, or 0.5um, depending on actual conditions, for example, based on the number of copper pillars.

[0131] The two-step implementation may be that a technician designs the electronic device, and the chip packaging-related equipment executes the design instructions to complete the chip packaging.

[0132] Step 52: Determine the offset of the chip according to the on / off status of each first link.

[0133] In this step, each of the above-mentioned first links is designed with a preset offset for the corresponding redistribution layer before chip packaging, that is, an offset is artificially added between the redistribution layer and the corresponding copper pillar, so that during packaging, the offset will be applied between the redistribution layer and the corresponding copper pillar in the die, and after the preset offset is added, there may be a situation where there is no contact between the redistribution layer and the corresponding copper pillar in the first link, that is, the corresponding first link is not conductive; there may also be a situation where there is contact between the redistribution layer and the corresponding copper pillar in the first link, that is, the corresponding first link is conductive. At this time, the offset of the chip is determined according to the on-off state of each first link.

[0134] Furthermore, if the packaged chip includes: the dies mentioned in multiple embodiments, after determining the offset of each die, an offset map can also be determined based on the offset of each chip.

[0135] The offset map records the offsets of all chips on the entire wafer. In one implementation, the offset map can be used to judge packaging accuracy and packaging quality.

[0136] In one possible implementation, when 4 dies are involved, the offsets are 11, 9, 10, and 9 respectively. When the displacement is greater than 10, it is recorded as red, and when the offset is not greater than 10, it is recorded as green. The color corresponding to each die is displayed on the offset map, which is convenient for technicians to determine which chips have too large offsets and need to be readjusted.

[0137] In another possible implementation, the die shift map can also be generally represented in the form of a two-dimensional matrix, where each element represents the position offset of a die. The specific forms can be as follows:

[0138] Offset value: Each element directly represents the offset value of the die in the x and y directions. For example, the offset map of a 2x2 chip array can be as follows (taking 2 dies as an example):

[0139] [0, 0]

[0140] [1, -1]

[0141] The offset graph shows that the first chip has no offset, and the second chip has an offset of 1 unit in the x direction and -1 unit in the y direction.

[0142] In another possible implementation, XY coordinates: Each element represents the coordinate position of a chip on a two-dimensional plane. For example, the offset map of a 2x2 chip array can be as follows:

[0143] [(0, 0), (1, -1)]

[0144] [(0, 1), (-1, 0)]

[0145] The offset map indicates that the first die is located at coordinates (0, 0), the second die is located at coordinates (1, -1), the third die is located at coordinates (0, 1), and the fourth die is located at coordinates (-1, 0).

[0146] The method for determining the offset of a chip provided in an embodiment of the present application can perform an on-off test on multiple first links through an electrical testing device to determine the on-off status of multiple first links, each first link includes: any first copper pillar in the chip, a first redistribution layer corresponding to the first copper pillar, a second copper pillar in the chip, a second redistribution layer corresponding to the second copper pillar, and a path between the first copper pillar and the second copper pillar, the second copper pillar is another copper pillar outside the first copper pillar, the first redistribution layer and the second redistribution layer in each first link are respectively applied with a preset offset, and the preset offsets in each first link are different, and then the offset of the chip is determined according to the on-off status of each first link. In this technical solution, a link is formed between every two redistribution layers, and the offset applied to the redistribution layer on each link is different. When it is determined that there is a link in a non-conducting state, the offset of the actual chip can be accurately determined by the offset corresponding to this non-conducting link.

[0147] Based on the above embodiments, Figure 8 The flowchart of the second embodiment of the method for determining the offset of the wafer provided in the present application is as follows: Figure 8 As shown, the above step 52 may include the following steps:

[0148] Step 81: Determine a second link whose on / off state is non-conductive from the on / off states of the first links.

[0149] In this step, when the chip is packaged, there may be a certain deviation between the same copper pillar and the corresponding redistribution layer due to the actual packaging. In addition, the preset offset applied as mentioned above may make the same copper pillar and the corresponding redistribution layer not in contact after packaging, that is, there is a situation where the on / off state of the first link is non-conductive. At this time, the non-conductive first link is used as the second link.

[0150] As an example, the second links involved may include: a second link 821, a second link 822, and a second link 823; the preset offset corresponding to each second link may be: the preset offset corresponding to the second link 821 is 8um, the preset offset corresponding to the second link 822 is 9um, and the preset offset corresponding to the second link 823 is 10um.

[0151] Step 82: Determine the offset of the chip according to the preset offset corresponding to the second link.

[0152] In this step, the first link determined to be non-conductive is used as the second link. At this time, the offset of the chip is determined according to the preset offset corresponding to each second link.

[0153] In conjunction with the example in step 81, the second link includes: a second link 821, a second link 822, and a second link 823, then:

[0154] Fig. 9 The structural diagram of the first second link provided in this application is as follows: Fig. 9 As shown, it includes: a second link 821; Fig.10 A schematic diagram of the structure of the second second link provided for this application, such as Fig.10 As shown, it includes: a second link 822; Fig.11 A schematic diagram of the structure of the third second link provided for this application, such as Fig.11 As shown, it includes: a second link 823.

[0155] Depend on Figure 9-11 It can be seen that the second link 821, the second link 822, and the second link 823 are all not conductive, but due to the different preset offsets applied, the copper pillars in the second link 823 deviate greatly from the corresponding redistribution layer, the copper pillars in the second link 822 deviate less from the corresponding redistribution layer, and the copper pillars in the second link 821 are basically close to the corresponding redistribution layer.

[0156] Optionally, determining the offset of the chip based on the preset offset corresponding to the second link may be implemented by performing the following:

[0157] Step 1: Determine the difference between the first threshold and the preset offset corresponding to the second link.

[0158] Among them, the first threshold is the minimum offset between the same copper pillar and the redistribution layer corresponding to the copper pillar without contact. That is, under ideal circumstances, if the die shift of the packaged chip is 0, the redistribution layer is continuously translated until the redistribution layer and the copper pillar are no longer in contact, and the offset between the redistribution layer and the copper pillar is used as the first threshold.

[0159] Optionally, the first threshold may be obtained in the following manner: determining the first threshold according to a first diameter length of a same copper pillar in the wafer and a second diameter length of a redistribution layer corresponding to the copper pillar.

[0160] As an example, Figure 2 Taking the example shown as an example, the first diameter length of Cu stud is 22, the second diameter length of RDL is 10, and the first threshold is (22+10) / 2=16 um.

[0161] Cited above Figure 9-11In the example, the preset offset corresponding to the second link 821 is 8.5um, the preset offset corresponding to the second link 822 is 9um, and the preset offset corresponding to the second link 823 is 10um; then the difference corresponding to the second link 821 is 16-8.5=7.5um, the difference corresponding to the second link 822 is 16-9=7um, and the difference corresponding to the second link 823 is 16-10=6um.

[0162] Step 2: determine the maximum value of the difference as the chip offset.

[0163] Optionally, in each of the above-mentioned second links, due to different preset offsets, the preset offsets corresponding to some second links are assigned larger values ​​during design, so that the center distance between the same copper pillar in the second link and the corresponding redistribution layer is far different, and cannot be used as a condition for determining the offset of the chip; while the preset offsets corresponding to some second links are assigned smaller values ​​during design, so that the center distance between the same copper pillar in the second link and the corresponding redistribution layer is extremely close. At this time, the difference between the first threshold and the offset corresponding to the second link can be used as the offset of the chip.

[0164] Cited above Figure 9-11 For example, the offset of the wafer is determined to be 7.5um.

[0165] That is, the largest difference is taken as the offset of the chip.

[0166] As an example, combining Fig. 9 , Fig.12 This is a schematic diagram corresponding to the offset of the chip in actual conditions, such as Fig.12 As shown, Fig. 9 After removing the preset offset of 8.5um, the die size is 7.5um.

[0167] Specifically, in an ideal case, that is, there is no offset between Cu stud and its corresponding RDL, the offset between the center of Cu stud and the center of RDL is 0 (e.g. Fig.12 The upper part of the package), at this time, an offset of 8.5um is applied to the RDL, and the package is theoretically obtained as follows Fig.12 However, in reality, the packaged RDL is displayed as follows Fig.12 From the lower part, we can get the die shift of 16-8.5=7.5um.

[0168] For easier understanding, Table 1 shows an example table of a die shift test, as shown in Table 1:

[0169] Table 1:

[0170]

[0171]

[0172] The method for determining the offset of a chip provided in an embodiment of the present application determines the second link whose on / off state is non-conductive from the on / off states of each first link, and determines the offset of the chip according to the preset offset corresponding to the second link. In this technical solution, when the first link is non-conductive, the offset of the chip is determined more accurately based on the preset offset corresponding to the non-conductive first link.

[0173] The following are apparatus embodiments, device embodiments, storage medium embodiments, and program product embodiments provided by the present application.

[0174] Fig.13 This is a schematic diagram of the structure of an embodiment of a device for determining the offset of a wafer provided in the present application, as shown in FIG. Fig.13 As shown, the device includes: a first determination module 131 and a second determination module 132;

[0175] A first determination module 131 is used to perform an on / off test on a plurality of first links through an electrical test device to determine the on / off status of the plurality of first links, wherein each first link comprises: any first copper pillar in a wafer, a first redistribution layer corresponding to the first copper pillar, a second copper pillar in the wafer, a second redistribution layer corresponding to the second copper pillar, and a path between the first copper pillar and the second copper pillar, wherein the second copper pillar is another copper pillar other than the first copper pillar, and preset offsets are applied to the first redistribution layer and the second redistribution layer in each first link, respectively, and the preset offsets in each first link are different;

[0176] The second determination module 132 is used to determine the offset of the chip according to the on / off status of each first link.

[0177] In a possible implementation manner, before performing a continuity test on the plurality of first links by using an electrical testing device to determine the continuity status of the plurality of first links, the first determining module 131 is further configured to:

[0178] In response to the design operation, a plurality of different copper pillar groups are selected on the die, each copper pillar group comprising a first copper pillar and a second copper pillar;

[0179] For each copper pillar group, a preset offset is applied to the first redistribution layer corresponding to the first copper pillar and the second redistribution layer corresponding to the second copper pillar, respectively, and the preset offset corresponding to each copper pillar group is different.

[0180] In a possible implementation manner, the second determining module 132 is configured to:

[0181] Determine a second link whose on / off state is non-conductive from the on / off states of the first links;

[0182] The offset of the chip is determined according to the preset offset corresponding to the second link.

[0183] In a possible implementation manner, the second determination module 132 determines the offset of the chip according to the preset offset corresponding to the second link, specifically for:

[0184] Determine a difference between a first threshold and a preset offset corresponding to the second link, the first threshold being a minimum offset at which the same copper pillar and the redistribution layer corresponding to the copper pillar do not contact each other;

[0185] The maximum value among the differences is determined as the offset of the wafer.

[0186] In a possible implementation manner, the chip includes: a plurality of the wafers; accordingly, the second determination module 132 is further configured to:

[0187] According to the offset of each chip, an offset map is determined, and the offset map records the offsets of all chips on the entire wafer.

[0188] In a possible implementation manner, the second determination module 132, when determining the first threshold, specifically:

[0189] The first threshold is determined according to a first diameter length of a same copper pillar in a wafer and a second diameter length of a redistribution layer corresponding to the copper pillar.

[0190] Fig.14 This is a schematic diagram of the structure of an electronic device embodiment provided by the present application. Fig.14 As shown, the electronic device of this embodiment may be the electronic device 42 mentioned above, and may include:

[0191] The processor 141, the memory 142, and the computer program instructions stored in the memory 142 and executable on the processor 141, and the method provided in any of the above-mentioned embodiments is implemented when the processor 141 executes the computer program instructions.

[0192] Optionally, the above-mentioned components of the electronic device may be connected via a system bus.

[0193] The memory 142 may be a separate storage unit or a storage unit integrated in the processor 141. The number of the processor 141 is one or more.

[0194] It should be understood that the processor 141 may be a central processing unit (CPU), or other general-purpose processors 141, digital signal processors 141 (DSP), application-specific integrated circuits (ASIC), etc. The general-purpose processor 141 may be a microprocessor 141 or the processor 141 may be any conventional processor 141, etc. The steps of the method disclosed in the present disclosure may be directly embodied as being executed by the hardware processor 141, or may be executed by a combination of hardware and software modules in the processor 141.

[0195] The system bus may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The system bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus. The memory 142 may include a random access memory 142 (RAM), and may also include a non-volatile memory 142 (NVM), such as at least one disk storage 142.

[0196] All or part of the steps of the above-mentioned method embodiments can be completed by hardware related to program instructions. The above-mentioned program can be stored in a readable memory 142. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the above-mentioned memory 142 (storage medium) includes: read-only memory 142 (ROM), RAM, flash memory 142, hard disk, solid state hard disk, magnetic tape, floppy disk, optical disc and any combination thereof.

[0197] The electronic device provided in this embodiment is used to execute the method in any of the above embodiments. Its implementation principle and technical effects can be found in the above embodiments and will not be described in detail here.

[0198] An embodiment of the present application further provides a computer-readable storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the method of any of the aforementioned embodiments is implemented.

[0199] An embodiment of the present application also provides a computer program product, including a computer program, which implements the method of any of the aforementioned embodiments when executed by a processor.

[0200] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the modules is only a logical function division, and there may be other division methods in actual implementation, such as multiple modules can be combined or integrated into another system, or some features can be ignored or not executed.

[0201] The above-mentioned integrated module implemented in the form of a software function module can be stored in a computer-readable storage medium. The above-mentioned software function module is stored in a storage medium, including a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to perform some steps of the method described in each embodiment of the present application.

[0202] It should be understood that the processor may be a processing unit (Central Processing Unit, referred to as CPU), or other general-purpose processors, digital signal processors (Digital Signal Processor, referred to as DSP), application-specific integrated circuits (Application Specific Integrated Circuit, referred to as ASIC), etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0203] The steps of the method disclosed in the application can be directly embodied as being executed by a hardware processor, or by a combination of hardware and software modules in the processor. The memory may include a high-speed RAM memory, and may also include a non-volatile storage NVM, such as at least one disk memory, and may also be a USB flash drive, a mobile hard disk, a read-only memory, a disk or an optical disk, etc.

[0204] The above-mentioned storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The storage medium can be any available medium that can be accessed by a general or special-purpose computer. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an application-specific integrated circuit (ASIC). Of course, the processor and the storage medium can also exist as discrete components in an electronic device or a main control device.

[0205] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0206] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0207] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0208] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for determining the offset of a wafer, characterized in that: include: Performing an on-off test on a plurality of first links by means of an electrical testing device to determine the on-off status of the plurality of first links, wherein each first link comprises: any first copper pillar in a wafer, a first redistribution layer corresponding to the first copper pillar, a second copper pillar in the wafer, a second redistribution layer corresponding to the second copper pillar, and a path between the first copper pillar and the second copper pillar, wherein the second copper pillar is another copper pillar other than the first copper pillar, and preset offsets are applied to the first redistribution layer and the second redistribution layer in each first link, respectively, and the preset offsets in each first link are different; The offset of the wafer is determined according to the on / off status of each first link.

2. The method according to claim 1, characterized in that Before performing on / off tests on the plurality of first links by means of an electrical testing device to determine the on / off states of the plurality of first links, the method further includes: In response to the design operation, a plurality of different copper pillar groups are selected on the wafer, each copper pillar group respectively including the first copper pillar and the second copper pillar; For each copper pillar group, the preset offset is applied to the first redistribution layer corresponding to the first copper pillar and the second redistribution layer corresponding to the second copper pillar respectively, and the preset offset corresponding to each copper pillar group is different.

3. The method according to claim 1 or 2, characterized in that: The step of determining the offset of the wafer according to the on / off status of each first link includes: Determine a second link whose on / off state is non-conductive from the on / off states of the first links; The offset of the chip is determined according to the preset offset corresponding to the second link.

4. The method according to claim 3, characterized in that The step of determining the offset of the chip according to the preset offset corresponding to the second link includes: Determine a difference between a first threshold and a preset offset corresponding to the second link, the first threshold being a minimum offset at which the same copper pillar and the redistribution layer corresponding to the copper pillar do not contact each other; The maximum value among the differences is determined as the offset of the wafer.

5. The method according to claim 1 or 2, characterized in that: Chips include: a plurality of said wafers; Accordingly, the method further includes: According to the offset of each chip, an offset map is determined, and the offset map records the offsets of all chips on the entire wafer.

6. The method according to claim 4, characterized in that The method for determining the first threshold includes: The first threshold is determined according to a first diameter length of a same copper pillar in the die and a second diameter length of a redistribution layer corresponding to the copper pillar.

7. A device for determining the offset of a wafer, characterized in that: include: a first determining module and a second determining module; The first determination module is used to perform an on / off test on a plurality of first links through an electrical testing device to determine the on / off status of the plurality of first links, each first link comprising: any first copper pillar in a wafer, a first redistribution layer corresponding to the first copper pillar, a second copper pillar in the wafer, a second redistribution layer corresponding to the second copper pillar, and a path between the first copper pillar and the second copper pillar, the second copper pillar being another copper pillar other than the first copper pillar, the first redistribution layer and the second redistribution layer in each first link being respectively applied with a preset offset, and the preset offsets in each first link are different; The second determination module is used to determine the offset of the chip according to the on / off status of each first link.

8. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the electronic device to perform the method described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and when the processor executes the computer-executable instructions, the method according to any one of claims 1 to 6 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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