High-heat-dissipation semiconductor packaging structure and manufacturing method thereof
By using a high heat dissipation substrate in semiconductor packages to contact the chip components, an efficient electrical connection circuit and thermal path is formed, which solves the problem of low heat dissipation efficiency in the prior art, and achieves a more efficient heat dissipation effect and a longer chip service life .
Patent Information
- Application Number
- CN202411583437.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-07
- Publication Date
- 2025-02-18
AI Technical Summary
In the existing semiconductor packaging technology, silicon materials have poor insulation, glass materials have large thermal expansion coefficient and low thermal conductivity, resulting in low heat dissipation efficiency and affecting the stability and service life of the chip.
The high heat dissipation substrate is used to contact the chip assembly. The high heat dissipation substrate has a multi-layer structure, insulation and high thermal conductivity. It fills metal materials in the connection holes to form electrical connection circuits and heat paths to achieve efficient heat dissipation.
It improves heat dissipation efficiency, reduces the temperature of the chip, extends the service life of the chip, and has good insulation, thermal expansion coefficient matching and mechanical properties.
Smart Images
Figure CN119480812A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a high heat dissipation semiconductor packaging structure and a manufacturing method thereof. Background Art
[0002] Semiconductor chips continue to develop towards high-density wiring, high power and miniaturization. Advanced packaging developed in recent years includes 3D IC, chip technology and high-power (GaN, SiC) chips. As the number and power of transistors increase sharply, the heat generated during chip operation affects the stability and service life of the chip.
[0003] At present, advanced packaging mainly uses silicon and glass materials as interposers to achieve electrical connections. However, silicon materials have poor insulation properties and require insulation treatment, which is difficult to process. Glass has a large coefficient of thermal expansion (CTE), which easily causes thermal mismatch problems. At the same time, glass has a low thermal conductivity and is difficult to quickly remove heat from the chip. Not only in advanced packaging, but with the development of high-power devices on vehicles, power semiconductors also have heat dissipation problems.
[0004] Therefore, it is necessary to use heat dissipation materials and packaging structures to quickly conduct the heat inside the chip to achieve the purpose of "cooling" the chip. At the same time, high heat dissipation materials also need to have good insulation, a thermal expansion coefficient similar to that of the chip material, and excellent mechanical properties. Ceramic materials are used as substrate materials in the manufacture of RF devices and power devices, and have recently been used as heat sinks in devices. However, there are usually several layers of materials with low thermal conductivity between the ceramic heat sink and the semiconductor chip, which affects the heat dissipation efficiency. Summary of the invention
[0005] The purpose of the present invention is to provide a high heat dissipation semiconductor packaging structure and a manufacturing method thereof in order to improve the heat dissipation efficiency in view of the above-mentioned technical problems.
[0006] In view of this, the present invention provides a high heat dissipation semiconductor packaging structure comprising:
[0007] A chip assembly, the chip assembly includes at least two;
[0008] A high heat dissipation substrate, wherein the high heat dissipation substrate has insulation properties, comprises an upper surface and a lower surface, wherein the upper surface or the lower surface is in contact with the chip component surface, the high heat dissipation substrate has a multi-layer substrate structure, wherein a circuit pattern is arranged in the multi-layer structure, and a connection hole is opened on the high heat dissipation substrate, wherein the connection hole extends from the surface in contact with the chip component to the circuit pattern, wherein the connection hole is filled with metal material, wherein the chip component, the metal material in the connection hole and the circuit pattern form an electrically connected circuit, wherein the chip component, the connection hole and the high heat dissipation substrate form a thermal path.
[0009] In the present technical solution, the high heat dissipation substrate material includes aluminum oxide, beryllium oxide, aluminum nitride, silicon nitride, polycrystalline diamond, single crystal diamond, etc. The high heat dissipation substrate has a multi-layer substrate structure, such as HTCC, LTCC, DBC, DPC, LAM. The metal materials filled in the connection hole include: gold, silver, platinum, copper, molybdenum, tungsten, etc. The contact surface between the chip assembly and the high heat dissipation substrate is formed by bonding and the like. A graphic circuit is formed by metallization treatments such as electroplating and chemical plating. The chip assembly, the metal material in the connection hole, and the circuit pattern form an electrical connection circuit to facilitate the interconnection of circuits between chips. The heat generated by the chip assembly can be guided out through the high thermal conductivity of the high heat dissipation substrate itself. In addition, the connection hole can also guide the heat of the chip assembly to the external environment. The two high-efficiency heat dissipations work together to improve the heat dissipation efficiency.
[0010] Furthermore, the thermal conductivity of the high heat dissipation substrate is higher than 20 W / (m·K).
[0011] Furthermore, the thickness of the high heat dissipation substrate is less than 0.2 mm, the surface roughness Ra of the high heat dissipation substrate in contact with the chip component is less than 50 nm, and the TTV is less than 20 μm.
[0012] Furthermore, the connection hole has a diameter less than 150 μm.
[0013] Furthermore, there are two high heat dissipation substrates, which are respectively located on the upper and lower surfaces of the chip assembly.
[0014] Furthermore, the chip assembly includes two power semiconductor chips arranged side by side, and there is at least one first connection hole at each position corresponding to the two power semiconductor chips on the high heat dissipation substrate, and the first circuit pattern on the high heat dissipation substrate and the first connection hole form an electrical connection circuit.
[0015] In the present technical solution, this structure realizes the circuit interconnection between two power semiconductor chips. The two power semiconductor chips can be any suitable power chips, such as SiC power chips, GaN chip, Ga2O3 power chips, etc.
[0016] Furthermore, a through hole penetrating the upper surface and the lower surface of the high heat dissipation substrate is provided on the high heat dissipation substrate below the chip assembly, and a plurality of external bumps are provided on the lower surface of the high heat dissipation substrate below the chip assembly.
[0017] In the technical solution, the external bumps can connect the chip assembly to the circuits of an external printed circuit board, such as an external system board, a main board or a module substrate, through a plurality of through holes.
[0018] Furthermore, the chip assembly includes a memory chip module, a logic chip module and a processing chip module. The memory chip module and the logic chip module are stacked up and down and arranged on the same side, and the processing chip module is arranged on the other side. The memory chip module and the logic chip module are passed through. The positions corresponding to the memory chip module and the processing chip module on the high heat dissipation substrate above the chip assembly are respectively provided with at least one second connection hole, and the second circuit pattern on the upper high heat dissipation substrate forms an electrical connection circuit with the second connection hole. The positions corresponding to the logic chip module and the processing chip module on the high heat dissipation substrate below the chip assembly are respectively provided with at least one third connection hole, and the two ends of the third circuit pattern on the lower high heat dissipation substrate respectively form an electrical connection circuit with the third connection hole.
[0019] Furthermore, the storage chip module includes four storage chips stacked in a matrix, the upper two storage chips and the lower two storage chips are stacked through TSV and multiple connection bumps, the processing chip module includes two upper and lower processor chips stacked through TSV and multiple connection bumps, and there is at least one fourth connection hole corresponding to the two storage chip positions on the high heat dissipation substrate above the storage chip module, and the fourth circuit pattern on the upper high heat dissipation substrate forms an electrical connection circuit with the fourth connection hole.
[0020] Furthermore, the manufacturing method of the high heat dissipation semiconductor packaging structure includes:
[0021] A chip component and a high heat dissipation substrate are provided. The high heat dissipation substrate has insulation properties. The high heat dissipation substrate includes an upper surface and a lower surface. The upper surface or the lower surface is in surface contact with the chip component. The high heat dissipation substrate has a multi-layer substrate structure. A circuit pattern is arranged in the multi-layer structure. A connection hole is opened on the high heat dissipation substrate. The connection hole extends from the surface in contact with the chip component to the circuit pattern. The connection hole is filled with metal material. The chip component, the metal material in the connection hole and the circuit pattern form an electrical connection circuit. The chip component, the connection hole and the high heat dissipation substrate form a thermal path.
[0022] The beneficial effects of the present invention are:
[0023] 1. The chip components, the metal materials in the connection holes and the circuit patterns form an electrical connection circuit to facilitate the interconnection of circuits between chips. The heat generated by the chip components can be conducted out through the high thermal conductivity of the high heat dissipation substrate itself. In addition, the connection holes can also conduct the heat of the chip components to the external environment. The two high-efficiency heat dissipation work together to improve the heat dissipation efficiency.
[0024] 2. The external bumps can connect the chip assembly to the circuits of an external printed circuit board, such as an external system board, a main board, or a module substrate, through multiple through holes. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 is a schematic diagram of Embodiment 1 of the present invention;
[0026] Figure 2 is a stereogram of a second embodiment of the present invention;
[0027] Figure 3 yes Figure 2 Half-section of
[0028] Figure 4 yes Figure 3 Sectional view of AA.
[0029] The symbols in the figure are:
[0030] 1. Chip assembly; 2. High heat dissipation substrate; 3. Power semiconductor chip; 4. First connection hole; 5. First circuit pattern; 6. Through hole; 7. External bump; 8. Storage chip module; 9. Logic chip module; 10. Processing chip module; 11. Second connection hole; 12. Second circuit pattern; 13. Third connection hole; 14. Third circuit pattern; 15. Storage chip; 16. Connection bump; 17. Fourth connection hole; 18. Fourth circuit pattern; 19. Processor chip. DETAILED DESCRIPTION
[0031] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.
[0032] In the description of the present application, it should be noted that the terms used herein are only for describing specific embodiments, and are not intended to limit the exemplary embodiments according to the present application. For ease of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship. The technology, methods and equipment known to ordinary technicians in the relevant field may not be discussed in detail, but in appropriate cases, the technology, methods and equipment should be regarded as part of the authorization specification. In all examples shown and discussed here, any specific value should be interpreted as merely exemplary, rather than as a limitation. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that similar numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.
[0033] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.
[0034] It should be noted that, in the description of the present application, the orientation or positional relationship indicated by terms such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Unless otherwise stated, these orientation words do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the scope of protection of the present application; the orientation words "inside and outside" refer to the inside and outside relative to the contour of each component itself.
[0035] It should be noted that, in the present application, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises one..." does not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be noted that the scope of the method and device in the embodiment of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.
[0036] Embodiment 1
[0037] like Figure 1 As shown, a high heat dissipation semiconductor packaging structure includes:
[0038] Chip assembly 1, the chip assembly 1 comprises at least two,
[0039] A high heat dissipation substrate 2, wherein the high heat dissipation substrate 2 has insulation properties, and the high heat dissipation substrate 2 is provided with two pieces, which are respectively located on the upper and lower surfaces of the chip component 1. The thermal conductivity of the high heat dissipation substrate 2 is higher than 20W / (m·K). The thickness of the high heat dissipation substrate 2 is less than 0.2mm, and the high heat dissipation substrate 2 includes an upper surface and a lower surface, and the upper surface or the lower surface is in surface contact with the chip component 1, and the surface roughness Ra of the high heat dissipation substrate 2 in contact with the chip component 1 is less than 50nm, and the TTV is less than 20μm. The high heat dissipation substrate 2 has a multi-layer substrate structure, and a circuit pattern is arranged in the multi-layer structure. A connection hole is opened on the high heat dissipation substrate 2, and the hole diameter of the connection hole is less than 150μm. The connection hole extends from the surface in contact with the chip component 1 to the circuit pattern, and the connection hole is filled with metal material. The chip component 1, the metal material in the connection hole and the circuit pattern form an electrical connection circuit, and the chip component 1, the connection hole and the high heat dissipation substrate 2 form a thermal path.
[0040] In this embodiment, the chip assembly 1 includes two power semiconductor chips 3 arranged side by side. The two power semiconductor chips 3 can be any suitable power chips, such as SiC power chips, GaN power chips, Ga2O3 power chips, etc.
[0041] The chip assembly 1 has at least one first connection hole 4 at positions corresponding to two power semiconductor chips 3 on the high heat dissipation substrate 2, and the first circuit pattern 5 on the high heat dissipation substrate 2 and the first connection hole 4 form an electrical connection circuit.
[0042] The material of the high heat dissipation substrate 2 includes aluminum oxide, beryllium oxide, aluminum nitride, silicon nitride, polycrystalline diamond, single crystal diamond, etc. The high heat dissipation substrate 2 has a multi-layer substrate structure, such as HTCC, LTCC, DBC, DPC, LAM. The metal materials filled in the connection hole include: gold, silver, platinum, copper, molybdenum, tungsten, etc. The contact surface between the chip component 1 and the high heat dissipation substrate 2 is formed by bonding and the like. The graphic circuit is formed by metallization treatments such as electroplating and chemical plating. The chip component 1, the metal material in the connection hole and the circuit pattern form an electrical connection circuit to facilitate the interconnection of circuits between chips. The heat generated by the chip component 1 can be guided out through the high thermal conductivity of the high heat dissipation substrate 2 itself. In addition, the connection hole can also guide the heat of the chip component 1 to the external environment. The two efficient heat dissipations work together to improve the heat dissipation efficiency. This structure realizes the circuit interconnection between two power semiconductor chips 3.
[0043] A through hole 6 penetrating the upper surface and the lower surface of the high heat dissipation substrate 2 is provided on the high heat dissipation substrate 2 below the chip assembly 1, and a plurality of external bumps 7 are provided on the lower surface of the high heat dissipation substrate 2 below the chip assembly 1. The external bumps 7 can connect the chip assembly 1 to the circuit of an external printed circuit board, such as an external system board, a main board or a module substrate, through the plurality of through holes 6.
[0044] Embodiment 2
[0045] like Figure 2-4 As shown, the content of the second embodiment is basically the same as that of the first embodiment, and the difference lies in the number of chips in the chip assembly 1.
[0046] In this embodiment, the chip assembly 1 includes a memory chip module 8, a logic chip module 9 and a processing chip module 10. The memory chip module 8 and the logic chip module 9 are stacked up and down and arranged on the same side, and the processing chip module 10 is arranged on the other side. The memory chip module 8 and the logic chip module 9 pass through each other. The positions corresponding to the memory chip module 8 and the processing chip module 10 on the high heat dissipation substrate 2 above the chip assembly 1 are respectively provided with at least one second connection hole 11, and the second circuit pattern 12 on the upper high heat dissipation substrate 2 forms an electrical connection circuit with the second connection hole 11. The positions corresponding to the logic chip module 9 and the processing chip module 10 on the high heat dissipation substrate 2 below the chip assembly 1 are respectively provided with at least one third connection hole 13, and the two ends of the third circuit pattern 14 on the lower high heat dissipation substrate 2 form an electrical connection circuit with the third connection hole 13.
[0047] The storage chip module 8 includes four storage chips 15 stacked in a matrix, the upper two storage chips 15 and the lower two storage chips 15 are stacked through TSV and multiple connection bumps 16, the processing chip module 10 includes two upper and lower processor chips 19 stacked through TSV and multiple connection bumps 16, and there is at least one fourth connection hole 17 corresponding to the position of the two storage chips 15 on the high heat dissipation substrate 2 above the storage chip module 8, and the fourth circuit pattern 18 on the upper high heat dissipation substrate 2 forms an electrical connection circuit with the fourth connection hole 17.
[0048] The embodiments of the present application are described above in conjunction with the accompanying drawings. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.
Claims
1. A high heat dissipation semiconductor packaging structure, characterized in that ,include: A chip assembly (1), the chip assembly (1) comprising at least two; A high heat dissipation substrate (2), wherein the high heat dissipation substrate (2) has insulating properties, comprises an upper surface and a lower surface, wherein the upper surface or the lower surface is in surface contact with a chip component (1), the high heat dissipation substrate (2) has a multi-layer substrate structure, a circuit pattern is arranged in the multi-layer structure, a connection hole is opened on the high heat dissipation substrate (2), the connection hole extends from the surface in contact with the chip component (1) to the circuit pattern, a metal material is filled in the connection hole, the chip component (1), the metal material in the connection hole and the circuit pattern form an electrical connection circuit, and the chip component (1), the connection hole and the high heat dissipation substrate (2) form a thermal path.
2. A high heat dissipation semiconductor packaging structure according to claim 1, characterized in that: The thermal conductivity of the high heat dissipation substrate (2) is higher than 20 W / (m·K).
3. A high heat dissipation semiconductor packaging structure according to claim 1, characterized in that: The thickness of the high heat dissipation substrate (2) is less than 0.2 mm, the surface roughness Ra of the high heat dissipation substrate (2) in contact with the chip component (1) is less than 50 nm, and the TTV is less than 20 μm.
4. The high heat dissipation semiconductor packaging structure according to claim 1, characterized in that: The connection hole has a diameter less than 150 μm.
5. The high heat dissipation semiconductor packaging structure according to claim 1, characterized in that: There are two high heat dissipation substrates (2), which are respectively located on the upper surface and the lower surface of the chip component (1).
6. A high heat dissipation semiconductor packaging structure according to claim 5, characterized in that: A through hole (6) penetrating the upper surface and the lower surface of the high heat dissipation substrate (2) is provided on the high heat dissipation substrate (2) below the chip assembly (1), and a plurality of external bumps (7) are provided on the lower surface of the high heat dissipation substrate (2) below the chip assembly (1).
7. A high heat dissipation semiconductor packaging structure according to claim 6, characterized in that: The chip assembly (1) comprises two power semiconductor chips (3) arranged side by side, each position on the high heat dissipation substrate (2) corresponding to the two power semiconductor chips (3) is provided with at least one first connection hole (4), and a first circuit pattern (5) on the high heat dissipation substrate (2) and the first connection hole (4) form an electrical connection circuit.
8. The high heat dissipation semiconductor packaging structure according to claim 6, characterized in that: The chip assembly (1) comprises a memory chip module (8), a logic chip module (9) and a processing chip module (10); the memory chip module (8) and the logic chip module (9) are stacked up and down and arranged on the same side, and the processing chip module (10) is arranged on the other side; the memory chip module (8) and the logic chip module (9) are passed through each other; the positions corresponding to the memory chip module (8) and the processing chip module (10) on the high heat dissipation substrate (2) above the chip assembly (1) are each provided with at least one second connection hole (11); the second circuit pattern (12) on the high heat dissipation substrate (2) above forms an electrical connection circuit with the second connection hole (11); the positions corresponding to the logic chip module (9) and the processing chip module (10) on the high heat dissipation substrate (2) below the chip assembly (1) are each provided with at least one third connection hole (13); and the two ends of the third circuit pattern (14) on the high heat dissipation substrate (2) below form an electrical connection circuit with the third connection hole (13).
9. The high heat dissipation semiconductor packaging structure according to claim 8, characterized in that: The memory chip module (8) comprises four memory chips (15) stacked in a matrix, the two upper memory chips (15) and the two lower memory chips (15) being stacked via TSV and a plurality of connection bumps (16), the processing chip module (10) comprising two upper and lower processor chips (19) being stacked via TSV and a plurality of connection bumps (16), the high heat dissipation substrate (2) above the memory chip module (8) having at least one fourth connection hole (17) at the position corresponding to the two memory chips (15), and the fourth circuit pattern (18) on the upper high heat dissipation substrate (2) and the fourth connection hole (17) forming an electrical connection circuit.
10. A method for manufacturing the high heat dissipation semiconductor packaging structure according to claim 1, characterized in that: include: A chip assembly (1) and a high heat dissipation substrate (2) are provided. The high heat dissipation substrate (2) has insulating properties. The high heat dissipation substrate (2) comprises an upper surface and a lower surface. The upper surface or the lower surface is in surface contact with the chip assembly (1). The high heat dissipation substrate (2) has a multi-layer substrate structure. A circuit pattern is arranged in the multi-layer structure. A connection hole is provided on the high heat dissipation substrate (2). The connection hole extends from the surface in contact with the chip assembly (1) to the circuit pattern. A metal material is filled in the connection hole. The chip assembly (1), the metal material in the connection hole and the circuit pattern form an electrical connection circuit. The chip assembly (1), the connection hole and the high heat dissipation substrate (2) form a thermal path.