High-speed pipeline analog-to-digital converter and electronic equipment

Abstract

The invention relates to a high-speed assembly line analog-to-digital converter and electronic equipment, and the high-speed assembly line analog-to-digital converter comprises cascaded multi-stage assembly line processing units, the first-stage assembly line processing unit is used for receiving a differential analog input signal and outputting a differential signal and a corresponding quantized signal, and the second-stage assembly line processing unit is used for receiving the differential analog input signal; the other stages of assembly line processing units are configured to execute differential sampling operation and residual error transmission operation, and the execution of the differential sampling operation comprises the following steps: the Nth stage of assembly line processing unit performs differential sampling to obtain a sampling signal, receives a quantization result quantized and output by the (N-1) th stage of assembly line processing unit, and executes the residual error transmission operation to obtain a residual error signal; comprising the following steps: determining a residual error signal by an Nth-stage assembly line processing unit, performing quantization operation on the residual error signal of the Nth-stage assembly line processing unit to obtain a quantization result, and transmitting the quantization result and the residual error signal to an (N + 1) th-stage assembly line processing unit. The high-speed assembly line analog-to-digital converter provided by the embodiment of the invention has the characteristics of high energy efficiency, low complexity and high-speed conversion.

Description

Technical Field

[0001] The present disclosure relates to the technical field of analog-to-digital conversion, and in particular to a high-speed pipeline analog-to-digital converter and electronic equipment. Background Art

[0002] An analog-to-digital converter (ADC) is an electronic system that converts analog signals into digital signals, usually implemented with an integrated circuit (chip). There are four main indicators of ADC: speed (sampling rate), accuracy (effective number of bits or signal-to-noise ratio), power consumption, and cost (chip area).

[0003] Commonly used high-speed ADC structures mainly include voltage domain ADC and time domain ADC. Time domain ADC can achieve sampling rates higher than 3GS / s, but its quantization accuracy depends on the matching degree of gate circuit delay, so its performance is not stable enough when environmental factors such as process, voltage and temperature (PVT) change. In contrast, voltage domain ADC (flash ADC, pipeline ADC, successive approximation ADC (SAR ADC)) has better PVT robustness. Among them, flash ADC can achieve the highest sampling rate (higher than 5GS / s) in low-precision applications with 4-5 effective bits, but its power consumption and area cost will increase exponentially with the improvement of accuracy, and it cannot be applied to higher-precision applications. SAR ADC has high energy efficiency, but its speed is slow (lower than 1.5GS / s), and requires a large-scale time interleaving structure to achieve high sampling rates, which increases the cost and complexity of the ADC input front end.

[0004] Compared with SAR ADC, pipeline ADC has a faster speed, but the working mode of traditional pipeline ADC includes three serial operation steps: sampling, quantization and amplification. Figure 1a and Figure 1b As shown, its sampling rate usually does not exceed 3GS / s. The specific workflow is as follows. Taking the Nth stage as an example, in the Φ1 phase, the residual signal after amplification in the N-1th stage is sampled; in the Φ2 phase, the sampled signal is quantized to obtain the quantization result D[N] of this stage; in the Φ3 phase, the sampled signal is subtracted from the quantization result to obtain the residual signal, and the residual signal is amplified by the residual amplifier (RA) and sent to the N+1th stage. The N+1th stage samples the residual signal after amplification in the Nth stage in the Φ3 phase, and then continues to complete the two operation steps of quantization and amplification in this stage, thereby forming a pipeline structure.

[0005] In the related art, there are two main methods to improve the speed of pipeline ADC:

[0006] 1. The "forward quantization" method parallelizes sampling and quantization operations;

[0007] 2. The "amplification followed by residual error" method performs quantization and amplification operations in parallel.

[0008] Figure 2a and Figure 2b The working mode of the pipeline ADC using the "forward quantization" method is demonstrated, which performs sampling and quantization operations at each stage simultaneously, reducing the required operation steps from 3 to 2 (sampling & quantization, amplification), thereby improving the speed of the pipeline ADC. The difference between this architecture and the traditional pipeline ADC architecture mainly comes from the input signal of each stage quantizer.

[0009] like Figure 2a and Figure 2b As shown, at the Φ1 phase, the Nth stage samples the residual signal amplified by the N-1th stage. At this time, the input signal of the Nth stage quantizer in the traditional architecture is the signal sampled by the Nth stage ( Figure 2a In this architecture, the input signal of the Nth-stage quantizer is the residual signal of the N-1th stage ( Figure 2a Therefore, in the Φ1 phase, the Nth stage can perform sampling and quantization operations simultaneously.

[0010] like Figure 2a and Figure 2b As shown, in the Φ2 phase, the Nth stage makes a difference between the sampled signal and the quantization result to obtain a residual signal, and amplifies the residual signal through a residual amplifier and sends it to the N+1th stage.

[0011] In this architecture, since the input signal of each quantizer is the residual signal before the previous stage amplification, the quantizers of the two adjacent stages need to form a main quantizer and a sub-quantizer structure so that the residual signal can be quantized normally, that is, the quantizer of the N+1th stage is the sub-quantizer of the Nth stage quantizer. Therefore, the reference voltage of the N+1th stage quantizer needs to be generated by a reference voltage multiplexer ( Figure 2a V th MUX), which is controlled by the quantization result of the Nth stage.

[0012] This pipeline architecture quantizes the residual signal of the previous stage and parallelizes the sampling and quantization operations, thereby improving the overall speed. However, this architecture requires the generation of multiple reference voltages to form a reference voltage multiplexer, which increases the complexity and power consumption of the reference voltage generation module and reduces energy efficiency.

[0013] Figure 3a and Figure 3bThe working mode of the pipeline ADC using the "amplification followed by residual error" method is demonstrated, which performs the quantization and amplification operations of each stage simultaneously, and also reduces the required operation steps from 3 to 2 (sampling, quantization & amplification), thereby improving the speed of the pipeline ADC.

[0014] The difference between this architecture and the traditional pipeline ADC architecture mainly comes from the location where the quantization result is differentiated at each stage.

[0015] like Figure 3a and Figure 3b As shown, in the Φ1 phase, the Nth stage samples the output signal of the N-1th stage residual amplifier.

[0016] like Figure 3a and Figure 3b As shown, in the Φ2 phase, when the Nth level quantizer quantizes the sampled signal, the residual amplifier in the traditional architecture needs to wait for the sampled signal to be subtracted from the quantization result before amplifying ( Figure 1a , Figure 1b Φ3 phase in the Figure 3a and Figure 3b In the architecture shown, the residual amplifier directly quantizes and amplifies the sampled signal at the Φ2 phase. At the same time, the N+1th stage samples the amplified signal and receives the quantization result of the Nth stage, performs a difference at the output end of the residual amplifier, and generates a residual signal.

[0017] Figure 3a and Figure 3b The pipeline architecture shown in the figure parallelizes the quantization and amplification operations by performing a difference operation after amplification to generate a residual signal, thereby improving the overall speed.

[0018] However, with Figure 1a and Figure 1b The traditional architecture shown and Figure 2a and Figure 2b Compared to the architecture using the "forward quantization" method shown, Figure 3a and Figure 3b In the architecture shown, the input signal of the residual amplifier is a large swing signal that is not differentiated from the quantized result, such as Figure 4 The traditional architecture and the architecture using the "forward quantization" method make a difference first and then amplify, so that the input signal swing of the residual amplifier is small, the linearity of the amplifier is good, and the output end will not be saturated; Figure 3a and Figure 3bThe architecture shown in the figure amplifies first and then makes a difference, so the input signal swing of the difference amplifier is large, the linearity of the amplifier is poor, and the output end may have saturation problems, which will seriously affect the performance of the ADC. Therefore, the difference amplifier in this architecture needs to consume more power or use complex linearity improvement technology to ensure its linearity, and it needs to avoid the problem of output saturation, which adds additional design complexity and power consumption.

[0019] It can be seen that the pipeline ADC of the related technology has the disadvantages of slow speed, low energy efficiency, high requirements on the linearity of the residual amplifier, saturation problem at the output of the amplifier, and high complexity of the reference voltage generation module. Summary of the invention

[0020] According to one aspect of the present disclosure, a high-speed pipeline analog-to-digital converter is provided, comprising a cascade of multiple pipeline processing units, wherein the first-stage pipeline processing unit is used to receive a differential analog input signal and output a differential signal and a corresponding quantized signal, and the remaining pipeline processing units except the first-stage pipeline processing unit are configured to perform a differential sampling operation and a residual transfer operation, wherein:

[0021] The differential sampling operation includes: the Nth stage pipeline processing unit performs differential sampling on the residual signal or the differential signal received from the previous stage to obtain a sampling signal, and receives the quantization result of the quantization output of the N-1th stage pipeline processing unit, where N is a positive integer greater than 1;

[0022] The performing of the residual transfer operation includes: the Nth stage pipeline processing unit determines the residual signal between the sampling signal and the quantization result of the previous stage pipeline processing unit, performs a quantization operation on the residual signal of the Nth stage pipeline processing unit to obtain a quantization result, and transfers the quantization result and the residual signal of the Nth stage pipeline processing unit to the N+1th stage pipeline processing unit,

[0023] Wherein, the quantization results of the quantization outputs of the pipeline processing units at each stage are used as the analog-to-digital conversion results of the analog input signal.

[0024] In a possible implementation, each pipeline processing unit is configured to perform a differential sampling operation and a residual transfer operation based on a target clock signal, wherein the target clock signal is set to a first phase and a second phase that periodically alternate, wherein:

[0025] In the first phase, the Nth stage pipeline processing unit performs differential sampling on the residual signal or the differential signal received from the previous stage to obtain a sampling signal, and receives a quantization result of the quantization output of the N-1th stage pipeline processing unit;

[0026] In the second phase, the Nth-stage pipeline processing unit determines the residual signal between the sampling signal and the quantization result of the previous-stage pipeline processing unit, performs a quantization operation on the residual signal of the Nth-stage pipeline processing unit to obtain a quantization result, and transmits the quantization result and the residual signal of the Nth-stage pipeline processing unit to the N+1th-stage pipeline processing unit.

[0027] In one possible implementation, the analog-to-digital converter includes a first input buffer and a second input buffer, the input ends of the first input buffer and the second input buffer are used to input the analog input signal, and the output ends of the first input buffer and the second input buffer are connected to the first-stage pipeline processing unit.

[0028] In a possible implementation, each stage of the pipeline processing unit further includes a unit gain voltage buffer, and the unit gain voltage buffer is used to transmit the residual signal or the differential signal to a sampling circuit of the next stage of the pipeline processing unit, wherein the unit gain voltage buffer includes a first MOS transistor, a second MOS transistor,

[0029] The gate of the first MOS transistor is used to receive the residual signal or the differential signal, the drain of the first MOS transistor is used to receive a power supply voltage, and the source of the first MOS transistor is connected to the drain of the second MOS transistor.

[0030] The gate of the second MOS transistor is used to receive a bias voltage, and the source of the second MOS transistor is grounded.

[0031] The first MOS transistor is configured to be biased in a saturation region, and the source of the first MOS transistor and the drain of the second MOS transistor serve as output ends of the unit gain voltage buffer for outputting a buffered residual signal or a differential signal.

[0032] In a possible implementation manner, the unit gain voltage buffer satisfies the following first condition: V DD ≤V GS +V th , where V DD represents the power supply voltage, V GS represents the gate-source voltage of the first MOS transistor, V th represents the on-threshold voltage of the first MOS transistor,

[0033] Wherein, each stage of the pipeline processing unit is configured to periodically perform pipeline operations under a target clock signal, wherein the target clock signal is set to a form in which a first phase and a second phase are periodically alternating, and when the unit gain voltage buffers in each stage of the pipeline processing unit all meet the first condition, the pipeline processing units at each stage are configured as follows:

[0034] In each first phase, the 2nth pipeline processing unit performs a differential sampling operation, and the 2n-1th pipeline processing unit performs a residual transfer operation, where n is a positive integer;

[0035] In each second phase, the 2nth pipeline processing unit performs a remainder transfer operation, and the 2n-1th pipeline processing unit performs a differential sampling operation.

[0036] In a possible implementation, the first-stage pipeline processing unit includes a first access switch, a second access switch, a first grounding switch, a second grounding switch, a first common-mode switch, a second common-mode switch, a first capacitor, a second capacitor, a first unit-gain voltage buffer, a second unit-gain voltage buffer, and a quantizer, wherein:

[0037] The first end of the first access switch and the first end of the second access switch are respectively used to receive the positive signal and the negative signal of the differential analog input signal.

[0038] The second end of the first access switch is connected to the first end of the first capacitor, the input end of the first unity gain voltage buffer, and the first input end of the quantizer of the first stage pipeline processing unit.

[0039] The second end of the second access switch is connected to the first end of the second capacitor, the input end of the second unity gain voltage buffer, and the second input end of the quantizer of the first stage pipeline processing unit.

[0040] The second end of the first capacitor is grounded through the first grounding switch and connected to the common-mode reference voltage through the first common-mode switch.

[0041] A second end of the second capacitor is grounded through the second grounding switch and connected to the common-mode reference voltage through the second common-mode switch.

[0042] In a possible implementation, the first access switch, the second access switch, the first grounding switch, and the second grounding switch are turned on in a first phase of a clock cycle, the first common-mode switch and the second common-mode switch are turned on in a second phase of the clock cycle, and the quantizer of the first-stage pipeline processing unit is enabled in the second phase of the clock cycle.

[0043] In a possible implementation manner, all pipeline processing units at all levels except the first-level pipeline processing unit include:

[0044] A first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first sampling capacitor, a second sampling capacitor, a third unit gain voltage buffer and a fourth unit gain voltage buffer, and a quantizer, wherein:

[0045] The first end of the first switch and the first end of the second switch are respectively used to receive the positive signal and the negative signal of the differential signal or the residual signal output by the previous stage pipeline processing unit,

[0046] The second end of the first switch is connected to the first end of the first sampling capacitor, the input end of the third unit gain voltage buffer, and the first input end of the quantizer of the pipeline processing unit.

[0047] The second end of the second switch is connected to the first end of the second sampling capacitor, the input end of the fourth unit gain voltage buffer, and the second input end of the quantizer of the pipeline processing unit.

[0048] The second end of the first sampling capacitor receives the negative signal of the differential signal or the residual signal output by the previous stage pipeline processing unit through the third switch, and is connected to the positive reference voltage or the negative reference voltage through the fifth switch.

[0049] The second end of the second sampling capacitor receives the positive signal of the differential signal or the residual signal output by the previous stage pipeline processing unit through the fourth switch, and is connected to the negative reference voltage or the positive reference voltage through the sixth switch.

[0050] Wherein, if the quantization result outputted by the previous stage is a high-level signal, the second end of the first sampling capacitor is connected to the negative reference voltage, and the second end of the second sampling capacitor is connected to the positive reference voltage; conversely, if the quantization result outputted by the previous stage is a low-level signal, the second end of the first sampling capacitor is connected to the positive reference voltage, and the second end of the second sampling capacitor is connected to the negative reference voltage.

[0051] Wherein, the difference between the positive reference voltage and the negative reference voltage is a preset reference voltage.

[0052] In a possible implementation, the first switch, the second switch, the third switch, and the fourth switch are turned on in the second phase of the clock cycle of the previous pipeline processing unit, the fifth switch and the sixth switch are turned on in the first phase of the clock cycle of the next pipeline processing unit, and the quantizer of the pipeline processing unit at this level is enabled in the first phase of the clock cycle of the next pipeline processing unit.

[0053] According to one aspect of the present disclosure, an electronic device is provided, comprising the high-speed pipeline analog-to-digital converter as described above.

[0054] The pipeline processing units at each level of the embodiment of the present disclosure all adopt differential sampling technology to achieve a double gain, and can achieve high-efficiency signal amplification without the need to specially set up an amplifier, saving circuit area and cost compared to related technologies. In addition, since there is no need to specially set up a corresponding amplification process, the sampling and amplification of analog signals are achieved in the differential sampling operation, which can increase the speed of analog-to-digital conversion. Therefore, the high-speed pipeline analog-to-digital converter of the embodiment of the present disclosure has the characteristics of high energy efficiency, low complexity, and high-speed conversion.

[0055] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0057] Figure 1a shows a schematic diagram of a traditional pipeline ADC architecture, Figure 1b A schematic diagram of the working mode of a traditional architecture pipeline ADC is shown.

[0058] Figure 2a shows a schematic diagram of a pipeline ADC using the "forward quantization" method, Figure 2b A schematic diagram showing the working mode of a pipeline ADC using the “forward quantization” method.

[0059] Figure 3a A schematic diagram of a pipeline ADC using the "amplify and generate residual error" method is shown. Figure 3b A schematic diagram showing the working mode of the pipeline ADC of the "amplification followed by residual error generation" method.

[0060] Figure 4 Shows Figure 1a , Figure 2a , Figure 3a The figure shows a comparison of the input and output signal swings of the difference amplifier in the three pipeline architectures.

[0061] Figure 5 A schematic diagram of a high-speed pipeline analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0062] Figure 6a A schematic diagram comparing differential sampling and single-ended sampling circuits is shown.

[0063] Figure 6b A schematic diagram of adjacent pipeline processing units according to an embodiment of the present disclosure is shown.

[0064] Figure 6c A timing diagram of adjacent pipeline processing units according to an embodiment of the present disclosure is shown.

[0065] Figure 7 A schematic diagram of a unity gain voltage buffer according to an embodiment of the present disclosure is shown.

[0066] Figure 8 The working schematic diagrams of not using power gating technology and using existing switch-based power gating technology are shown.

[0067] Figure 9a A schematic diagram of realizing automatic power gating based on the unity gain voltage buffer is shown.

[0068] Figure 9b Shows Figure 9a The total power consumption of the automatic power gating technique shown is Figure 8 Schematic diagram for comparison of the two methods.

[0069] Fig.10a A schematic diagram of a high-speed pipeline analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0070] Fig.10b Shows Fig.10a The execution timing diagram of the high-speed pipeline analog-to-digital converter is shown. DETAILED DESCRIPTION

[0071] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0072] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0073] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0074] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0075] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0076] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0077] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0078] The background technology has introduced the defects of pipeline ADC in related art. Figure 4 It can also be seen that Figure 2a , Figure 3a The two architectures shown retain the residual amplifier module in the traditional architecture. The residual amplifier is usually the bottleneck that limits the performance of the pipeline ADC and is also the module with the largest power consumption. Figure 2a , Figure 3a Both architectures shown suffer from the drawback of being less energy efficient.

[0079] The advantages and disadvantages of the existing high-speed pipeline architecture mentioned above are summarized in Table 1.

[0080]

[0081] Table 1: Comparison of the advantages and disadvantages of existing high-speed pipeline architectures

[0082] See also Figure 5 , Figure 5 A schematic diagram of a high-speed pipeline analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0083] like Figure 5 As shown, the high-speed pipeline analog-to-digital converter includes a cascade of multiple pipeline processing units, the first-stage pipeline processing unit 10 is used to receive a differential analog input signal and output a differential signal and a corresponding quantized signal, and the remaining pipeline processing units 20 except the first-stage pipeline processing unit 10 are configured to perform a differential sampling operation and a residual transfer operation, wherein,

[0084] The differential sampling operation includes: the Nth stage pipeline processing unit performs differential sampling on the residual signal or the differential signal received from the previous stage to obtain a sampling signal, and receives the quantization result of the quantization output of the N-1th stage pipeline processing unit, where N is a positive integer greater than 1;

[0085] The performing of the residual transfer operation includes: the Nth stage pipeline processing unit determines the residual signal between the sampling signal and the quantization result of the previous stage pipeline processing unit, performs a quantization operation on the residual signal of the Nth stage pipeline processing unit to obtain a quantization result, and transfers the quantization result and the residual signal of the Nth stage pipeline processing unit to the N+1th stage pipeline processing unit,

[0086] Wherein, the quantization results of the quantization outputs of the pipeline processing units at each stage are used as the analog-to-digital conversion results of the analog input signal.

[0087] The pipeline processing units at each level of the embodiment of the present disclosure adopt differential sampling technology to achieve twice the gain, and can achieve high-efficiency signal amplification without the need to specially set up an amplifier. Compared with the related technology that must use a residual amplifier, it saves circuit area and cost. In addition, since there is no need to specially set up a corresponding amplification process, the sampling and amplification of the analog signal are realized in the differential sampling operation, which can improve the speed of analog-to-digital conversion. Therefore, the high-speed pipeline analog-to-digital converter of the embodiment of the present disclosure has the characteristics of high energy efficiency, low complexity, and high-speed conversion.

[0088] The embodiments of the present disclosure do not limit the specific implementation methods of the pipeline processing units at each level. Those skilled in the art can set them according to actual conditions and needs. As long as the first-level pipeline processing unit can receive the differential analog input signal and output the differential signal and the corresponding quantization signal, the remaining pipeline processing units at each level can perform differential sampling operations and residual transfer operations.

[0089] Exemplarily, the analog input signal may be any analog signal that needs to be converted into digital form, which is not limited in the embodiments of the present disclosure.

[0090] The following is an introduction to differential sampling and single-ended sampling methods in related technologies.

[0091] See also Figure 6a , Figure 6a A schematic diagram comparing differential sampling and single-ended sampling circuits is shown.

[0092] For example, Figure 6a As shown, the sampling capacitor C in the single-ended sampling circuit S One end is connected to the input voltage signal V IN , the other end is connected to a fixed voltage (usually ground), so after sampling is completed, the capacitor C S The voltage on the input voltage signal V IN .

[0093] For example, Figure 6a As shown, the sampling capacitor C in the differential sampling circuit S The two ends of the positive input signal V IN and negative input signal -V IN , so after sampling is completed, the capacitor C S The voltage on the IN ).

[0094] It can be seen that the differential sampling circuit can achieve double gain without setting up an additional amplifier, which is a highly energy-efficient amplification method. The ADC chip in the disclosed embodiment is a fully differential circuit, and the input signal is a differential signal. Therefore, there is no need to generate an additional negative input signal in the ADC. It is only necessary to connect the two ends of the differential input signal to the sampling capacitor C S Differential sampling can be achieved at both ends.

[0095] In a possible implementation, each pipeline processing unit is configured to perform a differential sampling operation and a residual transfer operation based on a target clock signal, wherein the target clock signal is set to a first phase and a second phase that periodically alternate, wherein:

[0096] In the first phase, the Nth stage pipeline processing unit performs differential sampling on the residual signal or the differential signal received from the previous stage to obtain a sampling signal, and receives a quantization result of the quantization output of the N-1th stage pipeline processing unit;

[0097] In the second phase, the Nth-stage pipeline processing unit determines the residual signal between the sampling signal and the quantization result of the previous-stage pipeline processing unit, performs a quantization operation on the residual signal of the Nth-stage pipeline processing unit to obtain a quantization result, and transmits the quantization result and the residual signal of the Nth-stage pipeline processing unit to the N+1th-stage pipeline processing unit.

[0098] See also Figure 6b , Figure 6b A schematic diagram of adjacent pipeline processing units according to an embodiment of the present disclosure is shown.

[0099] See also Figure 6c , Figure 6c A timing diagram of adjacent pipeline processing units according to an embodiment of the present disclosure is shown.

[0100] For example, Figure 6b As shown, the embodiment of the present disclosure can set corresponding switches between each stage of the pipeline to turn on the switches at different phases to achieve corresponding operations. It should be noted that Figure 6b It is not used to limit the circuit structure of the pipeline processing unit, but is used to exemplify the signal processing process.

[0101] Figure 6b The "×1" and "×2" inside the buffer are used to indicate the corresponding gain. "×2" indicates that the differential sampling can achieve a 2-fold amplification, and "×1" indicates that the amplification factor of the unit gain voltage buffer is 1.

[0102] The embodiments of the present disclosure do not limit the quantization processing method in each stage of the pipeline processing unit. Those skilled in the art can adopt relevant technologies to implement it according to actual conditions and needs. For example, a quantizer in the relevant technology (such as a flash memory quantizer, etc.) can be used to quantize the analog signal (residual signal), and then the quantization result is converted into a digital-to-analog converter DAC to obtain a corresponding analog signal. In this way, the embodiments of the present disclosure can implement "determining the residual signal between the sampled signal and the quantization result of the previous stage of the pipeline processing unit" through a subtractor or other devices. Of course, "determining the residual signal between the sampled signal and the quantization result of the previous stage of the pipeline processing unit" can be achieved through a subtractor or other methods. Those skilled in the art can adopt appropriate technical solutions to achieve it according to actual conditions and needs, and the embodiments of the present disclosure do not limit it.

[0103] For example, Figure 6cAs shown, the target clock signal is set to be in the form of a first phase (Φ1 phase) and a second phase (Φ2 phase) alternating periodically, and each period T S It includes a first phase (Φ1 phase) and a second phase (Φ2 phase), and the Φ1 phase and the Φ2 phase are periodically alternated.

[0104] For example, Figure 6b , Figure 6c As shown, in the Φ1 phase (first phase), the switch between the Nth stage and the N-1th stage can be turned on, and the Nth stage performs differential sampling on the residual signal sent from the N-1th stage (buffer BUF), and sends the sampled signal obtained by the differential sampling to one end of the subtractor, which is similar to the aforementioned architectures ( Figure 1a , Figure 2a , Figure 3a ) is different from the embodiment of the present disclosure, which adopts the differential sampling method to achieve a double gain while sampling. Figure 6b , Figure 6c As shown, in the Φ1 phase, the quantizer of the N-1th level is enabled to perform the quantization operation, so that the Nth level receives the quantization result of the N-1th level, and the digital-to-analog converter in the Nth level performs a digital-to-analog conversion operation on the quantization result to obtain a corresponding analog signal, which is sent to the subtractor.

[0105] For example, Figure 6b , Figure 6c As shown, in the Φ2 phase (second phase), the Nth stage performs a subtraction on the differential sampling and amplification signal and the analog signal corresponding to the quantization result through a subtractor to generate a residual signal, and transmits the residual signal to the N+1th stage through a unit gain voltage buffer (BUF). At the same time, in the Φ2 phase, the quantizer of the Nth stage is enabled to perform the quantization operation, so that the quantizer of the Nth stage quantizes the residual signal and also sends the quantization result D[N] to the N+1th stage.

[0106] The pipeline architecture of the disclosed embodiment parallelizes the sampling and amplification operations through differential sampling, so that the required operation steps are reduced from 3 to 2 (sampling & amplification, quantization & residual transfer), thereby improving the speed of the pipeline ADC. In addition, under the same gain-bandwidth product, the gain of the unity gain voltage buffer is 1, which has a higher bandwidth than the residual amplifier, making the residual transfer faster, further improving the speed of the pipeline ADC.

[0107] The high-speed pipeline ADC architecture of the disclosed embodiment eliminates the residual amplifier module, which accounts for the largest share of power consumption in the traditional architecture, and uses the differential sampling method to achieve gain, which has high energy efficiency. Figure 2aCompared with the pipeline architecture of the "forward quantization" method shown in FIG. 1 , the embodiment of the present disclosure does not need to generate an additional reference voltage, thereby reducing the design complexity and power consumption of the reference voltage module. Figure 3a Compared with the pipeline architecture using the "amplification to generate residual" method shown, the embodiment of the present disclosure uses a unit gain voltage buffer to transmit the amplified residual signal, which improves the linearity compared to the residual amplifier and avoids the problem of output saturation.

[0108] The advantages of the disclosed embodiments compared to the existing high-speed pipeline ADC architecture are summarized in Table 2.

[0109]

[0110] Table 2: Summary of advantages of the disclosed embodiments compared to existing high-speed pipeline ADC architectures

[0111] In a possible implementation, the analog-to-digital converter may include a first input buffer and a second input buffer, the input ends of the first input buffer and the second input buffer are used to input the analog input signal, and the output ends of the first input buffer and the second input buffer are connected to the first-stage pipeline processing unit. In this way, the embodiment of the present disclosure can receive differential input signals through the first input buffer and the second input buffer.

[0112] The embodiments of the present disclosure do not limit the specific implementation of the first input buffer and the second input buffer. Those skilled in the art may implement them using buffer circuits in related technologies according to actual conditions and needs.

[0113] In a possible implementation, Figure 6b As shown, each stage of the pipeline processing unit may further include a unit gain voltage buffer (BUF), and the unit gain voltage buffer is used to transfer the residual signal or the differential signal to the sampling circuit of the next stage of the pipeline processing unit.

[0114] The embodiments of the present disclosure do not limit the specific implementation of the unity gain voltage buffer, and those skilled in the art can use relevant technologies to implement it according to actual conditions and needs. Of course, the aforementioned first input buffer and second input buffer can also use the unity gain voltage buffer introduced in the embodiments of the present disclosure.

[0115] See also Figure 7 , Figure 7 A schematic diagram of a unity gain voltage buffer according to an embodiment of the present disclosure is shown.

[0116] In a possible implementation, Figure 7As shown, the unit gain voltage buffer may include a first MOS transistor M1, a second MOS transistor M2,

[0117] The gate of the first MOS transistor M1 is used to receive the residual signal or the differential signal (represented as V IN1 ), the drain of the first MOS transistor M1 is used to receive the power supply voltage V DD , the source of the first MOS transistor M1 is connected to the drain of the second MOS transistor M2,

[0118] The gate of the second MOS transistor M2 is used to receive a bias voltage, and the source of the second MOS transistor M2 is grounded.

[0119] The first MOS transistor M1 is configured to be biased in a saturation region, and the source of the first MOS transistor M1 and the drain of the second MOS transistor M2 serve as the output end of the unity gain voltage buffer, for outputting a buffered residual signal or a differential signal (V OUT1 ).

[0120] Exemplarily, the first MOS transistor M1 and the second MOS transistor M2 are NMOS transistors.

[0121] The embodiment of the present disclosure does not limit the method for generating the bias voltage. For example, Figure 7 As shown, a bias circuit can be set to generate a corresponding bias voltage and output it to the gate of the second MOS transistor M2. Of course, an external bias voltage can also be received, and the embodiments of the present disclosure are not limited to this. In addition, the embodiments of the present disclosure are not limited to the specific implementation method of the bias circuit, and those skilled in the art can adopt relevant technologies to implement it according to actual conditions and needs.

[0122] In the high-speed pipeline ADC architecture of the embodiment of the present disclosure, the unity gain voltage buffer can be used as follows: Figure 7 The source follower (SF) circuit shown in the figure is implemented with an input signal V IN1 (residual signal or differential signal) is transmitted to the output end through the first MOS transistor M1. It is worth noting that in this process, the first MOS transistor M1 needs to be biased in the saturation region, that is, the gate-source voltage V GS Need to be higher than its threshold voltage V th , at the same time, the output signal V OUT1 Relative to the input signal V IN1 There is a level shift, that is, V OUT1 =V IN1 -V GS .

[0123] See also Figure 8 , Figure 8 The working schematic diagrams of not using power gating technology and using existing switch-based power gating technology are shown.

[0124] like Figure 8 As shown, when the power gating technology is not used, in the Φ2 phase, the voltage buffer of the pipeline processing unit at this stage transmits the residual signal or differential signal to the next stage, consuming the corresponding static power consumption; but in the Φ1 phase, the pipeline at this stage samples the residual signal or differential signal of the previous stage, and the voltage buffer still consumes the same static power consumption, thus wasting about 50% of the static power consumption.

[0125] like Figure 8 As shown in Figure 1, the switch-based power gating technology achieves current shutoff by connecting a switch in series in the source follower. In the Φ2 phase, the switch is closed to allow the voltage buffer to operate normally; in the Φ1 phase, the switch is open, saving about 50% of the static power consumption. However, in advanced processes, the power supply voltage V DD Usually low, so a larger switch size is required to reduce the switch's on-resistance R ON , thereby reducing the voltage space occupied by the switch resistance, and the larger switch size will increase the additional dynamic power consumption used to drive the switch, so this switch-based power gating technology has very limited improvement in energy efficiency.

[0126] In view of this, the embodiment of the present disclosure proposes a new automatic power gating mechanism based on the unit gain voltage buffer, which can realize automatic power gating of various levels without additionally setting switches in the unit gain voltage buffer.

[0127] In a possible implementation, the unity gain voltage buffer may be configured to satisfy the following first condition to implement automatic power gating, where the first condition is: V DD ≤V GS +V th , where V DD represents the power supply voltage, V GS represents the gate-source voltage of the first MOS transistor M1, V th represents the on-threshold voltage of the first MOS transistor M1,

[0128] Wherein, each stage of the pipeline processing unit is configured to periodically perform pipeline operations under a target clock signal, wherein the target clock signal is set to a form in which a first phase and a second phase are periodically alternating, and when the unit gain voltage buffers in each stage of the pipeline processing unit all meet the first condition, the pipeline processing units at each stage are configured as follows:

[0129] In each first phase, the 2nth pipeline processing unit performs a differential sampling operation, and the 2n-1th pipeline processing unit performs a residual transfer operation, where n is a positive integer;

[0130] In each second phase, the 2nth pipeline processing unit performs a remainder transfer operation, and the 2n-1th pipeline processing unit performs a differential sampling operation.

[0131] Among them, the 2nth pipeline processing unit is the even-stage pipeline processing unit in the cascaded pipeline processing units, and the 2n-1th pipeline processing unit is the previous stage pipeline processing unit of the even-stage pipeline processing unit (that is, the odd-stage pipeline processing unit).

[0132] It should be noted that "n" in this embodiment is the label of each level of pipeline processing units after excluding the aforementioned first-level pipeline processing unit, that is, except for the first-level pipeline processing unit, the numbering of the remaining levels of pipeline processing units starts from 1, and the first-level pipeline processing unit can also be numbered as "0", and the second-level pipeline processing unit corresponds to the first odd-level pipeline processing unit (2n-1) with n=1.

[0133] See also Figure 9a , Figure 9a A schematic diagram of realizing automatic power gating based on the unity gain voltage buffer is shown.

[0134] In the high-speed pipeline ADC architecture of the disclosed embodiment, the residual signal transmission between stages is preferably implemented by a voltage buffer with a source follower structure.

[0135] For example, Figure 9a As shown, in the Φ1 phase, the even-numbered (2nth) pipeline processing unit performs differential sampling, and the odd-numbered (2n-1th) pipeline processing unit performs residual transmission. At this time, the input signal of the voltage buffer of the even-numbered pipeline processing unit (that is, the output signal of the odd-numbered voltage buffer) is V R [2n] = V R [2n-1]-V GS , where V R [2n-1] is the input signal of the voltage buffer of the odd-numbered pipeline processing unit (i.e., the residual signal of the odd-numbered stage at this time), V GS is the gate-source voltage of the first MOS transistor M1 in the unit gain voltage buffer of the odd-numbered pipeline processing unit. As can be seen from the foregoing, the gate-source voltage V GS is higher than the threshold voltage V of the first MOS transistor M1 th , and in order to ensure the reliability of the transistor, the gate voltage V R [2n-1] needs to be lower than the power supply voltage V DD, from which we can conclude that V R [2n] <V DD -V GS If the condition V is met DD ≤V GS +V th , then V R [2n] <V DD -V GS ≤V th At this time, the gate voltage V R [2n] is lower than its threshold voltage V th Therefore, the first MOS transistor M1 is in the cut-off region, so that the current of the voltage buffer in the even-numbered stages is 0, thereby realizing power gating.

[0136] For example, Figure 9a As shown, in the Φ2 phase, the even-numbered (2nth) pipeline processing units perform residual transmission, and the odd-numbered (2n-1th) pipeline processing units perform differential sampling. Similarly, the voltage buffers in the odd-numbered stages implement power gating at this time.

[0137] It can be seen from this that in the high-speed pipeline ADC architecture of the disclosed embodiment, an automatic power gating technology can be implemented by the cascade structure of the inter-stage source followers, which reuses the first MOS transistor M1 in the pipeline processing unit as a switch to cut off the current, without the need for additional switches and switch driving power consumption.

[0138] See also Figure 9b , Figure 9b Shows Figure 9a The total power consumption of the automatic power gating technique shown is Figure 8 Schematic diagram for comparison of the two methods.

[0139] like Figure 9b As shown, compared to Figure 8 Without using gating technology, the disclosed embodiment reduces the static power consumption by 50%. Figure 8 The switch-based power gating technology in the embodiment of the present disclosure saves the extra switch driving power consumption. It is worth noting that the automatic power gating technology of the embodiment of the present disclosure is implemented under the condition that V DD ≤V GS +V th , just set the power supply voltage V DD Lower than or equal to the transistor gate-source voltage V GS and threshold voltage V th The sum of the power supply voltage V DDIt is 0.9V, and this can be achieved by selecting a transistor with a threshold voltage higher than 0.45V.

[0140] A possible implementation of the high-speed pipeline analog-to-digital converter of the embodiment of the present disclosure is given below.

[0141] See also Fig.10a , Fig.10a A schematic diagram of a high-speed pipeline analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0142] See also Fig.10b , Fig.10b Shows Fig.10a The execution timing diagram of the high-speed pipeline analog-to-digital converter is shown.

[0143] In a possible implementation, Fig.10a As shown, the first-stage pipeline processing unit may include a first access switch S11, a second access switch S12, a first grounding switch S13, a second grounding switch S14, a first common-mode switch S15, a second common-mode switch S16, a first capacitor C S01 , the second capacitor C S02 , the first unity gain voltage buffer SF 01 and a second unity gain voltage buffer SF 02 , quantizer Qua1, where

[0144] The first end of the first access switch S11 and the first end of the second access switch S12 are respectively used to receive the positive signal (V INP ), negative signal (V INN ),

[0145] The second end of the first access switch S11 is connected to the first capacitor C S01 The first end of the first unity gain voltage buffer SF 01 an input end of the quantizer Qua1 of the first-stage pipeline processing unit,

[0146] The second end of the second access switch S12 is connected to the second capacitor C S02 The first end of the second unity gain voltage buffer SF 02 an input end of the quantizer Qua1 of the first-stage pipeline processing unit,

[0147] The first capacitor C S01 The second end of the first grounding switch S13 is grounded and connected to the common mode reference voltage V through the first common mode switch S15. REFCM ,

[0148] The second capacitor C S02 The second end of the grounded terminal is connected to the common mode reference voltage V via the second grounding switch S14 and connected to the common mode reference voltage V via the second common mode switch S16. REFCM .

[0149] In a possible implementation, Fig.10a As shown, the first access switch S11, the second access switch S12, the first grounding switch S13, and the second grounding switch S14 are turned on in the first phase Φ1 of the clock cycle, the first common-mode switch S15 and the second common-mode switch S16 are turned on in the second phase Φ2 of the clock cycle, and the quantizer Qua1 of the first-stage pipeline processing unit is enabled in the second phase Φ2 of the clock cycle.

[0150] In a possible implementation, Fig.10a As shown, except for the first-stage pipeline processing unit, each stage of pipeline processing unit may include:

[0151] The first switch S21, the second switch S22, the third switch S23, the fourth switch S24, the fifth switch S25, the sixth switch S26, the first sampling capacitor C S11 , the second sampling capacitor C S12 , the third unity gain voltage buffer SF 11 and a fourth unity gain voltage buffer SF 12 , quantizer Qua2, where

[0152] The first end of the first switch S21 and the first end of the second switch S22 are respectively used to receive the positive signal and the negative signal of the differential signal or the residual signal output by the previous stage pipeline processing unit.

[0153] The second end of the first switch S21 is connected to the first sampling capacitor C S11 The first end of the third unit gain voltage buffer SF 11 an input terminal of the pipeline processing unit, a first input terminal of the quantizer Qua2,

[0154] The second end of the second switch S22 is connected to the second sampling capacitor C S12 The first end of the fourth unity gain voltage buffer SF 12 an input terminal of the pipeline processing unit, a second input terminal of the quantizer Qua2,

[0155] The first sampling capacitor C S11 The second end receives the negative signal of the differential signal or the residual signal output by the previous stage pipeline processing unit through the third switch S23, and is connected to the positive reference voltage (V REFP) or negative reference voltage (V REFN ),

[0156] The second sampling capacitor C S12 The second end receives the positive signal of the differential signal or the residual signal output by the previous stage pipeline processing unit through the fourth switch S24, and is connected to the negative reference voltage or the positive reference voltage through the sixth switch S26.

[0157] If the quantization result output by the previous stage is a high level signal, the first sampling capacitor C S11 The second end of the sampling capacitor C S12 The second end of is connected to the positive reference voltage; otherwise, if the quantization result output by the previous stage is a low level signal, the first sampling capacitor C S11 The second end of the sampling capacitor C S12 The second end of is connected to the negative reference voltage,

[0158] The difference between the positive reference voltage and the negative reference voltage is a preset reference voltage (V REF =V REFP -V REFN ), the preset reference voltage may also be referred to as a differential mode reference voltage.

[0159] The embodiments of the present disclosure do not limit the specific values ​​and generation methods of the common mode reference voltage and the preset reference voltage, and those skilled in the art can set them according to actual conditions and needs. REFCM is the common-mode voltage of the reference voltage, which is the input common-mode voltage that enables the unity-gain voltage buffer (source follower) to work properly. For example, V REFCM =0.5*(V REFP +V REFN ) As an example, since the first-stage pipeline processing unit does not have the quantization result of the previous stage, there is no difference step, so the P terminal (positive terminal) and the N terminal (negative terminal) are both connected to the common mode reference voltage V REFCM , the subsequent pipeline processing unit needs to generate a residual voltage by difference, so the P terminal and N terminal should be connected to the positive reference voltage (V REFP ) or negative reference voltage (V REFN ), the common-mode voltage of the two is also V REFCM .

[0160] The embodiment of the present disclosure selects the first sampling capacitor C according to the quantization result outputted by the previous stage. S11 , the second sampling capacitor C S12The specific implementation of the positive and negative reference voltages is not limited. Those skilled in the art can use relevant technologies to implement them according to actual conditions and needs. For example, a multiplexer can be set to select the first sampling capacitor C according to the quantization result. S11 , the second sampling capacitor C S12 Of course, the positive and negative reference voltages can be implemented in other ways.

[0161] It should be noted that Fig.10a The pipeline processing unit shown in the figure selects the first sampling capacitor C according to the quantization result output by the previous stage. S11 , the second sampling capacitor C S12 The positive and negative reference voltages are connected and the first sampling capacitor C is set S11 , the second sampling capacitor C S12 , in order to realize "determining the residual signal between the sampling signal and the quantization result of the previous stage pipeline processing unit", but the embodiments of the present disclosure are not limited to this. As mentioned above, those skilled in the art can also use the subtractor solution to obtain the residual signal between the two.

[0162] In a possible implementation, Fig.10a As shown, the first switch S21, the second switch S22, the third switch S23, and the fourth switch S24 are turned on in the second phase Φ2 of the clock cycle of the previous stage pipeline processing unit, the fifth switch S25 and the sixth switch S26 are turned on in the first phase Φ1 of the clock cycle of the next stage pipeline processing unit, and the quantizer Qua2 of the pipeline processing unit at this stage is enabled in the first phase Φ1 of the clock cycle of the next stage pipeline processing unit.

[0163] In a possible implementation, Fig.10a As shown, the positive signal of the differential analog input signal (V INP ), negative signal (V INN ) through the input buffer (SF IN1 / SF IN2 ) is sent to the first-level pipeline processing unit.

[0164] In a possible implementation, Fig.10b Shown is the timing signal diagram of the first two stages of the pipeline ADC, which highlights the part of the signal from the input to the second stage in one pipeline transmission.

[0165] like Fig.10a , Fig.10b As shown, in the Φ1 phase, the first access switch S11, the second access switch S12, the first grounding switch S13, and the second grounding switch S14 are turned on, and the first-stage pipeline processing unit samples the input signal to obtain a differential signal V RP[0]-V RN [0] = ΔV. Without loss of generality, we assume that ΔV>0.

[0166] like Fig.10a , Fig.10b As shown, in the Φ2 phase, the first common-mode switch S15 and the second common-mode switch S16 are turned on, and the first unit gain voltage buffer SF 01 and a second unity gain voltage buffer SF 02 The input terminal of the circuit is raised to the appropriate input common-mode level, that is, the common-mode reference voltage V REFCM , so that the differential signal ΔV can be transmitted to the second stage.

[0167] From the working mode of the pipeline ADC of the embodiment of the present disclosure described above, it can be known that the second-stage pipeline processing unit performs differential sampling ( Fig.10a The green part in the middle), that is, the sampling capacitor at the P end (positive end) (the first sampling capacitor C S11 ) is ΔV, the sampling capacitor at the N end (negative end) (the second sampling capacitor C S12 )’s sampling voltage is -ΔV.

[0168] At the same time, Fig.10a , Fig.10b As shown, in the Φ2 phase, the quantizer Qua1 of the first-stage pipeline processing unit quantizes the differential signal ΔV and obtains the quantization result D[0] (D[0]=1 because ΔV>0). At the beginning of the next Φ1 phase, the second stage subtracts the differential sampled signal from the quantization result D[0] to generate a residual signal. Specifically, the sampling capacitor (the first sampling capacitor C S11 ) is connected to the negative reference voltage V REFN , that is, V RP [1]=V REFN +ΔV, the sampling voltage is -ΔV N-terminal (negative terminal) sampling capacitor (second sampling capacitor C S12 ) is connected to the positive reference voltage V REFP , that is, V RN [1] = V REFP -ΔV. Therefore, the residual signal of the second-stage pipeline processing unit is V RP [1]-V RN [1] = 2ΔV-V REF , where V REF =V REFP -V REFN , it can be seen that differential sampling achieves a gain of twice, Fig.10a , Fig.10b Corresponding to ΔV = 0.7V REFAfter the residual signal is generated, the second-stage pipeline processing unit converts the residual signal V RP [1]-V RN [1] Through the third unity gain voltage buffer SF 11 and a fourth unity gain voltage buffer SF 12 It is transmitted to the third-stage pipeline processing unit, and the residual signal is quantized to obtain the quantization result D[1], which is also sent to the third-stage pipeline processing unit.

[0169] The structure and working mode of the pipeline processing units of the remaining stages (such as the 3rd to 10th stages) are the same as those of the 2nd stage (the last stage, the 10th stage pipeline processing unit, no longer needs to perform residual transmission, so in order to reduce costs, the corresponding unit gain voltage buffer can be removed), thereby realizing a high-speed single-channel 10-stage pipeline ADC.

[0170] In summary, the high-speed pipeline analog-to-digital converter of the embodiment of the present disclosure has the following advantages over the existing method:

[0171] and Figure 1a Compared with the traditional pipeline ADC shown, the operation steps are reduced and the sampling rate (speed) is improved;

[0172] and Figure 2a , Figure 3a Compared with the two existing methods for improving the speed of pipeline ADC shown in the figure, there is no need for a complex reference voltage generation module, and the problem of poor linearity of the residual amplifier and saturation of the output end is avoided;

[0173] The differential sampling technology is used to achieve double gain, eliminating the residual amplifier module, which accounts for the largest proportion of power consumption in traditional pipeline ADCs, and improving the overall energy efficiency;

[0174] The unit gain voltage buffer is used for residual transmission, which has a larger bandwidth than the residual amplifier used in the related art, further improving the overall speed;

[0175] An automatic power gating mechanism is implemented through a unity-gain voltage buffer, which saves 50% of the static power consumption without the need for additional switches and switch drive power consumption.

[0176] At the application level, the disclosed embodiments can be used as a single-channel ADC in all high-speed (1-5GS / s sampling rate), medium-to-low precision (6-8 bit quantization accuracy) ADC products, and can also be used as a sub-channel of a time-interleaved ADC in ultra-high-speed (higher than 5GS / s sampling rate), medium-to-low precision (6-8 bit quantization accuracy) ADC products. The disclosed embodiments do not limit their application areas. The advantages of the disclosed embodiments will solve the problems of slow speed and low energy efficiency of single-channel or sub-channel ADCs in these products, and reduce the number of interleaved channels, design complexity, and calibration difficulty of ultra-high-speed time-interleaved ADCs.

[0177] The disclosed embodiment adopts differential sampling technology to perform two operation processes of sampling and amplification in parallel, and adopts a unit gain voltage buffer for residual transfer, so that the operation steps of the pipeline ADC are reduced to 2 (sampling & amplification, quantization & residual transfer), thereby improving the overall speed.

[0178] The disclosed embodiment adopts a specific unit gain voltage buffer and utilizes the automatic power gating technology implemented by the inter-stage source follower cascade structure, which reduces the static power consumption by 50% without requiring additional switches and switch driving power consumption.

[0179] According to one aspect of the present disclosure, an electronic device is provided, comprising the high-speed pipeline analog-to-digital converter as described above.

[0180] The embodiments of the present disclosure do not limit the specific types of electronic devices, and the electronic devices may include terminal devices, which may be user equipment (UE), mobile devices, user terminals, terminals, handheld devices, computing devices or vehicle-mounted devices, etc. For example, some examples of terminals are: mobile phones, tablet computers, laptop computers, PDAs, mobile Internet devices (MID), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control (Industrial Control), wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids (Smart Grid), wireless terminals in transportation safety (Transportation Safety), wireless terminals in smart cities (Smart City), wireless terminals in smart homes (Smart Home), wireless terminals in Internet of Vehicles, etc. For example, the server may be a local server or a cloud server.

[0181] Of course, the high-speed pipeline analog-to-digital converter can also be integrated in the processing component to perform the corresponding analog-to-digital conversion operation. In one example, the processing component includes but is not limited to a separate processor, or a discrete component, or a combination of a processor and a discrete component. The processor may include a controller having an execution instruction function in an electronic device, and the processor may be implemented in any appropriate manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components. Inside the processor, the executable instructions can be executed by hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0182] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A high-speed pipeline analog-to-digital converter, characterized in that: The invention comprises a cascaded multi-stage pipeline processing unit, wherein the first stage pipeline processing unit is used to receive a differential analog input signal and output a differential signal and a corresponding quantized signal, and the pipeline processing units at all stages except the first stage pipeline processing unit are configured to perform a differential sampling operation and a residual transfer operation, wherein: The differential sampling operation includes: the Nth stage pipeline processing unit performs differential sampling on the residual signal or the differential signal received from the previous stage to obtain a sampling signal, and receives the quantization result of the quantization output of the N-1th stage pipeline processing unit, where N is a positive integer greater than 1; The performing of the residual transfer operation includes: the Nth stage pipeline processing unit determines the residual signal between the sampling signal and the quantization result of the previous stage pipeline processing unit, performs a quantization operation on the residual signal of the Nth stage pipeline processing unit to obtain a quantization result, and transfers the quantization result and the residual signal of the Nth stage pipeline processing unit to the N+1th stage pipeline processing unit, Wherein, the quantization results of the quantization outputs of the pipeline processing units at each stage are used as the analog-to-digital conversion results of the analog input signal.

2. The high-speed pipeline analog-to-digital converter according to claim 1, characterized in that: Each stage of the pipeline processing unit is configured to perform a differential sampling operation and a residual transfer operation based on a target clock signal, wherein the target clock signal is set to a form in which a first phase and a second phase are periodically alternating, wherein: In the first phase, the Nth stage pipeline processing unit performs differential sampling on the residual signal or the differential signal received from the previous stage to obtain a sampling signal, and receives a quantization result of the quantization output of the N-1th stage pipeline processing unit; In the second phase, the Nth-stage pipeline processing unit determines the residual signal between the sampling signal and the quantization result of the previous-stage pipeline processing unit, performs a quantization operation on the residual signal of the Nth-stage pipeline processing unit to obtain a quantization result, and transmits the quantization result and the residual signal of the Nth-stage pipeline processing unit to the N+1th-stage pipeline processing unit.

3. The high-speed pipeline analog-to-digital converter according to claim 1, characterized in that: The analog-to-digital converter includes a first input buffer and a second input buffer. The input ends of the first input buffer and the second input buffer are used to input the analog input signal. The output ends of the first input buffer and the second input buffer are connected to the first-stage pipeline processing unit.

4. The high-speed pipeline analog-to-digital converter according to claim 1, characterized in that: Each pipeline processing unit at one stage further includes a unit gain voltage buffer, and the unit gain voltage buffer is used to transmit the residual signal or the differential signal to a sampling circuit of the pipeline processing unit at the next stage, wherein the unit gain voltage buffer includes a first MOS transistor, a second MOS transistor, The gate of the first MOS transistor is used to receive the residual signal or the differential signal, the drain of the first MOS transistor is used to receive a power supply voltage, and the source of the first MOS transistor is connected to the drain of the second MOS transistor. The gate of the second MOS transistor is used to receive a bias voltage, and the source of the second MOS transistor is grounded. The first MOS transistor is configured to be biased in a saturation region, and the source of the first MOS transistor and the drain of the second MOS transistor serve as output ends of the unit gain voltage buffer for outputting a buffered residual signal or a differential signal.

5. The high-speed pipeline analog-to-digital converter according to claim 4, characterized in that: The unity gain voltage buffer satisfies the following first condition: V DD ≤V GS +V th , where V DD represents the power supply voltage, V GS represents the gate-source voltage of the first MOS transistor, V th represents the on-threshold voltage of the first MOS transistor, Wherein, each stage of the pipeline processing unit is configured to periodically perform pipeline operations under a target clock signal, wherein the target clock signal is set to a form in which a first phase and a second phase are periodically alternating, and when the unit gain voltage buffers in each stage of the pipeline processing unit all meet the first condition, the pipeline processing units at each stage are configured as follows: In each first phase, the 2nth pipeline processing unit performs a differential sampling operation, and the 2n-1th pipeline processing unit performs a residual transfer operation, where n is a positive integer; In each second phase, the 2nth pipeline processing unit performs a remainder transfer operation, and the 2n-1th pipeline processing unit performs a differential sampling operation.

6. The high-speed pipeline analog-to-digital converter according to claim 1, characterized in that: The first-stage pipeline processing unit includes a first access switch, a second access switch, a first grounding switch, a second grounding switch, a first common-mode switch, a second common-mode switch, a first capacitor, a second capacitor, a first unit-gain voltage buffer, a second unit-gain voltage buffer, and a quantizer, wherein: The first end of the first access switch and the first end of the second access switch are respectively used to receive the positive signal and the negative signal of the differential analog input signal. The second end of the first access switch is connected to the first end of the first capacitor, the input end of the first unity gain voltage buffer, and the first input end of the quantizer of the first stage pipeline processing unit. The second end of the second access switch is connected to the first end of the second capacitor, the input end of the second unity gain voltage buffer, and the second input end of the quantizer of the first stage pipeline processing unit. The second end of the first capacitor is grounded through the first grounding switch and connected to the common-mode reference voltage through the first common-mode switch. A second end of the second capacitor is grounded through the second grounding switch and connected to the common-mode reference voltage through the second common-mode switch.

7. The high-speed pipeline analog-to-digital converter according to claim 6, characterized in that: The first access switch, the second access switch, the first grounding switch, and the second grounding switch are turned on in a first phase of a clock cycle, the first common-mode switch and the second common-mode switch are turned on in a second phase of the clock cycle, and the quantizer of the first-stage pipeline processing unit is enabled in the second phase of the clock cycle.

8. The high-speed pipeline analog-to-digital converter according to any one of claims 1 to 6, characterized in that: Except for the first-stage pipeline processing unit, each stage of pipeline processing unit includes: A first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first sampling capacitor, a second sampling capacitor, a third unit gain voltage buffer and a fourth unit gain voltage buffer, and a quantizer, wherein: The first end of the first switch and the first end of the second switch are respectively used to receive the positive signal and the negative signal of the differential signal or the residual signal output by the previous stage pipeline processing unit, The second end of the first switch is connected to the first end of the first sampling capacitor, the input end of the third unit gain voltage buffer, and the first input end of the quantizer of the pipeline processing unit. The second end of the second switch is connected to the first end of the second sampling capacitor, the input end of the fourth unit gain voltage buffer, and the second input end of the quantizer of the pipeline processing unit. The second end of the first sampling capacitor receives the negative signal of the differential signal or the residual signal output by the previous stage pipeline processing unit through the third switch, and is connected to the positive reference voltage or the negative reference voltage through the fifth switch. The second end of the second sampling capacitor receives the positive signal of the differential signal or the residual signal output by the previous stage pipeline processing unit through the fourth switch, and is connected to the negative reference voltage or the positive reference voltage through the sixth switch. Wherein, if the quantization result outputted by the previous stage is a high-level signal, the second end of the first sampling capacitor is connected to the negative reference voltage, and the second end of the second sampling capacitor is connected to the positive reference voltage; conversely, if the quantization result outputted by the previous stage is a low-level signal, the second end of the first sampling capacitor is connected to the positive reference voltage, and the second end of the second sampling capacitor is connected to the negative reference voltage. Wherein, the difference between the positive reference voltage and the negative reference voltage is a preset reference voltage.

9. The high-speed pipeline analog-to-digital converter according to claim 8, characterized in that: The first switch, the second switch, the third switch, and the fourth switch are turned on in the second phase of the clock cycle of the previous stage pipeline processing unit, the fifth switch and the sixth switch are turned on in the first phase of the clock cycle of the next stage pipeline processing unit, and the quantizer of the pipeline processing unit at this stage is enabled in the first phase of the clock cycle of the next stage pipeline processing unit.

10. An electronic device, characterized in that: The electronic device comprises a high-speed pipeline analog-to-digital converter as described in any one of claims 1-9.

Images