Low-noise short-offset transient electromagnetic receiving and conditioning circuit and receiver

Abstract

The invention relates to a low-noise short-offset transient electromagnetic receiving conditioning circuit and a receiver. The conditioning circuit comprises a first power supply filter circuit, a second power supply filter circuit, an active filter circuit, a power frequency noise suppression circuit and a low-noise amplification circuit, the first power supply filter circuit and the second power supply filter circuit are respectively used for filtering a first power supply and a second power supply so as to reduce noise; the active filter circuit is used for filtering interference signals; the power frequency noise suppression circuit is used for filtering power frequency noise; the low-noise amplifying circuit comprises an input-stage amplifying circuit, an intermediate-stage amplifying circuit and an output-stage amplifying circuit. According to the technical scheme, various filter circuits are arranged, noise is filtered out, and noise reduction is facilitated.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic technology, and in particular to a low-noise short-offset transient electromagnetic receiving conditioning circuit and a receiver. Background Art

[0002] Short-Offset Transient Electromagnetic (SOTEM) has the advantages of large detection depth and strong resolution. As a broadband near-source method, SOTEM needs to break through the bandwidth limitation and achieve large bandwidth at the receiving end to fully tap the detection potential of the method. Under large bandwidth conditions, noise interference is relatively serious. Summary of the invention

[0003] In order to overcome the problems existing in the related art, the present disclosure provides a low-noise short-offset transient electromagnetic receiving conditioning circuit and a receiver to solve the problem of serious noise interference under large bandwidth conditions in the related art.

[0004] According to a first aspect of an embodiment of the present disclosure, a low-noise short-offset transient electromagnetic receiving conditioning circuit is provided, comprising: a first power supply filter circuit, a second power supply filter circuit, an active filter circuit, an industrial frequency noise suppression circuit and a low-noise amplifier circuit. The first power supply filter circuit and the second power supply filter circuit are respectively used to filter the first power supply and the second power supply to reduce noise. The active filter circuit is used to filter out interference signals. The industrial frequency noise suppression circuit is used to filter out industrial frequency noise.

[0005] The above-mentioned low-noise amplifier circuit comprises: an input stage amplifier circuit, an intermediate stage amplifier circuit and an output stage amplifier circuit.

[0006] In one embodiment, the input stage amplifier circuit includes: a first triode, a second triode, a third triode, a fourth triode, a fifth triode, a sixth triode, a seventh triode, an eighth triode, and a ninth triode; a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor.

[0007] The first triode and the second triode form a current mirror. The emitter of the first triode and the emitter of the second triode are respectively connected to a power supply. The base of the first triode is respectively connected to the base of the second triode, the collector of the third triode and the collector of the fourth triode.

[0008] The collector of the first triode is connected to the collector of the fourth triode. The base of the third triode is connected to the first end of the first resistor, and the second end of the first resistor is grounded. The base of the fourth triode is connected to the first end of the second resistor, and the second end of the second resistor is grounded. The emitter of the third triode is connected to the emitter of the fifth triode. The emitter of the fourth triode is connected to the emitter of the sixth triode. The base of the fifth triode is connected to the base of the sixth triode. The collector of the fifth triode is connected to the collector of the seventh triode and the base of the ninth triode respectively. The collector of the sixth triode is connected to the collector of the eighth triode and the base of the twelfth triode in the intermediate stage amplifier circuit respectively. The base of the seventh triode is connected to the base of the eighth triode. The emitter of the seventh triode is connected to the first end of the fourth resistor and the first end of the third resistor respectively. The emitter of the eighth triode is connected to the first end of the fifth resistor and the second end of the third resistor respectively. The second end of the fourth resistor and the second end of the fifth resistor are connected to a negative voltage.

[0009] In one implementation, the intermediate stage amplifier circuit includes: a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a zeroth resistor, an eleventh transistor, an eleventh transistor and a twelfth transistor.

[0010] The first end of the seventh resistor and the first end of the eighth resistor are respectively connected to a positive voltage. The second end of the seventh resistor is respectively connected to the base of the tenth transistor and the eleventh transistor, and is connected to the collector of the eleventh transistor. The emitters of the tenth transistor and the eleventh transistor are connected to a negative voltage. The second end of the eighth resistor is connected to the first end of the ninth resistor, and the second end of the ninth resistor is respectively connected to the second end of the zeroth resistor and the collector of the twelfth transistor. The emitter of the twelfth transistor is connected to the first end of the tenth resistor, and the second end of the tenth resistor is connected to a negative voltage.

[0011] In one embodiment, the output stage amplifier circuit includes: a thirteenth resistor, an eleventh resistor, a twelfth resistor, a fourteenth resistor, a first capacitor, a second capacitor and a third capacitor. The first end of the thirteenth resistor is connected to a positive voltage. The second end of the thirteenth resistor is respectively connected to the first end of the second capacitor and the first end of the operational amplifier. The second end of the second capacitor is respectively connected to the ground and the first end of the eleventh resistor, and the second end of the eleventh resistor is respectively connected to the positive input end of the operational amplifier and the first end of the first capacitor. The second end of the first capacitor is respectively connected to the first end of the zeroth resistor and the second end of the ninth resistor in the intermediate stage amplifier circuit. The first end of the twelfth resistor is connected to the negative input end of the operational amplifier, and the second end is respectively connected to the ground and the first end of the third capacitor. The second end of the third capacitor is respectively connected to the second end of the operational amplifier and the first end of the fourteenth resistor. The second end of the fourteenth resistor is connected to a negative voltage.

[0012] In one embodiment, the first power supply filter circuit includes: a thirteenth transistor, the emitter of the thirteenth transistor is respectively connected to the anode of the eighth diode, the anode of the ninth diode, and the first end of the first filter capacitor. The second end of the first filter capacitor is grounded. The collector of the thirteenth transistor is respectively connected to the cathode of the seventh diode, the first end of the second filter capacitor, the first end of the seventeenth resistor, the cathode of the seventh diode and the input power supply. The second end of the seventeenth resistor, the anode of the seventh diode, the second end of the eighteenth resistor, the first end of the third filter capacitor and the first end of the fourth filter capacitor are connected together. The second end of the third filter capacitor and the second end of the fourth filter capacitor are connected together and grounded. The base of the thirteenth transistor is respectively connected to the cathode of the eighth diode and the first end of the eighteenth resistor.

[0013] In one embodiment, the second power supply filter circuit includes: a fourteenth transistor, the emitter of the fourteenth transistor is respectively connected to the cathode of the eleventh diode, the first end of the fifth filter capacitor, and the cathode of the twelfth diode. The second end of the fifth filter capacitor is grounded. The base of the fourteenth transistor is respectively connected to the first end of the twentieth resistor and the anode of the eleventh diode. The collector of the fourteenth transistor is respectively connected to the first end of the nineteenth resistor, the anode of the tenth diode, the anode of the twelfth diode and the first end of the sixth filter capacitor. The second end of the sixth filter capacitor is grounded. The cathode of the tenth diode is respectively connected to the second end of the twentieth resistor, the second end of the nineteenth resistor, the first end of the seventh filter capacitor and the first end of the eighth filter capacitor; the second end of the seventh filter capacitor and the second end of the eighth filter capacitor are connected together and grounded.

[0014] In one embodiment, the power frequency noise suppression circuit comprises: an amplifier and a voltage follower; The positive input terminal of the amplifier is connected to the first end of the second filter capacitor and the first end of the second filter resistor, respectively. The second end of the second filter capacitor is connected to the first end of the first filter capacitor and the first end of the third filter resistor, respectively. The second end of the second filter resistor is connected to the first end of the third filter capacitor and the first end of the first filter resistor, respectively. The second end of the first filter capacitor and the second end of the first filter resistor are connected together. The second end of the third filter resistor and the second end of the third filter capacitor are connected together and connected to the output terminal of the voltage follower. The positive input terminal of the voltage follower is connected to the first end of the fifth filter resistor and the first end of the fourth filter resistor, respectively. The second end of the fifth filter resistor is grounded, and the second end of the fourth filter resistor is connected to the output terminal of the amplifier.

[0015] In one embodiment, the active filter circuit comprises: a first active filter operational amplifier and a second active filter operational amplifier. The output end of the first active filter operational amplifier is respectively connected to the first end of the first active filter resistor, the first end of the first active filter capacitor and the inverting input end of the first active filter operational amplifier. The second end of the first active filter capacitor is respectively connected to the first end of the first active filter resistor and the first end of the second active filter resistor. The second end of the second active filter resistor is respectively connected to the first end of the second active filter capacitor and the non-inverting input end of the first active filter operational amplifier. The output end of the second active filter operational amplifier is respectively connected to the first end of the third active filter capacitor and the inverting input end of the second active filter operational amplifier. The second end of the third active filter capacitor is respectively connected to the first end of the third active filter resistor and the first end of the fourth active filter resistor. The second end of the fourth active filter resistor is respectively connected to the first end of the fourth active filter capacitor and the non-inverting input end of the second active filter operational amplifier.

[0016] In a second aspect, the present application proposes a receiver, comprising any of the above-mentioned low-noise short-offset transient electromagnetic receiving signal conditioning circuits, and further comprising: a main control board, a connection board, and an analog board. The low-noise short-offset transient electromagnetic receiving signal conditioning circuit is arranged on the analog board.

[0017] The connection board is provided with a magnetic coupling isolation module, which is respectively connected to the digital signal ports of the analog board and the main control board.

[0018] In some embodiments, the main control board is provided with a cascade digital filter sampling device, and the cascade digital filter sampling device includes: The first FIR filtering down-sampling device has an input end that inputs original data, and an output end that outputs first down-sampled data with a frequency twice that of the original data.

[0019] A second FIR filtering down-sampling device, wherein the first down-sampling data is input into the input end of the second FIR filtering down-sampling device, and the second down-sampling data whose frequency is twice the frequency of the first down-sampling data is output from the output end.

[0020] A third FIR filtering and downsampling device, wherein the input end of the third FIR filtering and downsampling device inputs the second downsampling data, and the output end outputs third downsampling data whose frequency is twice the frequency of the second downsampling data.

[0021] A fourth FIR filtering and downsampling device, wherein the input end of the fourth FIR filtering and downsampling device inputs the third downsampling data, and the output end outputs fourth downsampling data whose frequency is twice the frequency of the third downsampling data.

[0022] A data selector, wherein the input ends of the data selector respectively input the original data, the first down-sampled data, the second down-sampled data, the third down-sampled data and the fourth down-sampled data.

[0023] The output end of the data selector outputs the final filtered data.

[0024] The technical solution provided by the embodiments of the present disclosure may have the following beneficial effects: The above technical solution of the present application is a low-noise short-offset transient electromagnetic receiving conditioning circuit and a receiver, wherein the conditioning circuit includes a power supply filtering circuit, an active filtering circuit, a power frequency noise suppression circuit and a low-noise amplification circuit; the above power supply filtering circuit is used to filter the power supply to reduce noise; the above active filtering circuit is used to filter out interference signals; the above power frequency noise suppression circuit is used to filter out power frequency noise. The above technical solution of the present application achieves the filtering of noise.

[0025] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0027] Figure 1 is a schematic diagram of a semi-aerospace frequency domain electromagnetic method according to an exemplary embodiment; Figure 2 is a block diagram of a low-noise short-offset transient electromagnetic receiving signal conditioning circuit according to an exemplary embodiment; Figure 3is a low noise amplifier circuit diagram according to an exemplary embodiment; Figure 4 is a first power supply filter circuit diagram according to an exemplary embodiment; Figure 5 is a second power supply filter circuit diagram according to an exemplary embodiment; Figure 6 is a circuit diagram of power frequency noise suppression according to an exemplary embodiment; Figure 7 is an active filtering circuit diagram according to an exemplary embodiment; Figure 8 is a structural block diagram of a receiver according to an exemplary embodiment; Fig. 9 A cascade digital filter combination is shown according to an exemplary embodiment. DETAILED DESCRIPTION

[0028] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0029] It should be noted that all actions of acquiring signals, information or data in this application are carried out in compliance with the relevant data protection laws and policies of the country where they are located and with the authorization given by the owner of the corresponding device.

[0030] See attached Figure 1Semi-aerial frequency domain electromagnetic method is an artificial active source exploration method. It uses ground transmission and air reception to explore geological structures. Semi-aerial electromagnetic detection is carried out by the cooperation of the transmitting system and the receiving system. The specific detection principle is as follows: the electromagnetic transmitter is located on the ground and provides an alternating current to the grounding wire as an excitation source. The changing current will produce a changing magnetic field, which is called the primary field. Under the action of the primary field, the underground medium generates eddy currents, which will gradually decay over time. The changing eddy currents will produce an induced magnetic field, which is called the secondary field. The drone is equipped with a semi-aerial electromagnetic receiving system in the air, and receives the secondary field data through the magnetic field sensor. The magnetic induction coil can convert the changing magnetic field signal into an induced voltage signal. The receiving system first amplifies and filters the induced voltage signal through the electronic unit, and then collects and stores the data. Based on the electromagnetic differences between abnormal bodies such as underground mineral resources and the earth, the data stored in the semi-aerial electromagnetic receiving system are processed by forward and inverse, and combined with the transmission waveform and geological exploration experience, the underground structure and the location of the abnormal body are interpreted and analyzed, so as to achieve the purpose of detecting deep geological structures. The above receiving system mainly consists of two parts: one is the magnetic induction coil, which is the receiving sensor of the secondary field signal; the other is the receiver, which reduces noise, amplifies and collects the signal from the sensor. Under large bandwidth conditions, the noise interference in the receiver is relatively serious.

[0031] Based on this, the present application proposes a low-noise short-offset transient electromagnetic receiving conditioning circuit 1, see the attached Figure 2 , including: a first power supply filter circuit 11, a second power supply filter circuit 12, an active filter circuit 13, a power frequency noise suppression circuit 14 and a low noise amplifier circuit 15. The first power supply filter circuit 11 and the second power supply filter circuit 12 are respectively used to filter the first power supply and the second power supply to reduce noise. The active filter circuit 13 is used to filter out interference signals. The power frequency noise suppression circuit 14 is used to filter out power frequency noise. The low noise amplifier circuit 15 includes: an input stage amplifier circuit, an intermediate stage amplifier circuit and an output stage amplifier circuit.

[0032] The above-mentioned technical solution of the present application, the first power supply filter circuit, the second power supply filter circuit, the active filter circuit, the power frequency noise suppression circuit and the low-noise amplifier circuit are conducive to eliminating noise.

[0033] In some embodiments, in order to meet the project requirements of large and adjustable gain of the amplifier circuit, the low-noise amplifier circuit is composed of three-stage amplifier circuits, namely, input stage amplifier circuit, intermediate stage amplifier circuit and output stage amplifier circuit. The noise of the multi-stage amplifier circuit is mainly determined by the input stage amplifier circuit. The input stage amplifier circuit is built with independent components, and the internal noise is much lower than that of the integrated operational amplifier. Therefore, the input stage and intermediate stage amplifier circuits are built with low-noise bipolar transistors (BJT) as the core. In addition, in order to reduce the common-mode interference caused by DC coupling, the amplifier circuit adopts the form of differential input, and selects dual-channel PNP matching transistors MAT03 and dual-channel NPN matching transistors MAT12 with extremely low noise power spectrum density and high gain-bandwidth product. The matching transistor contains two transistors with extremely similar parameters, and the difference can be ignored. The high matching of the two can reduce the impact on the circuit caused by the difference in transistors, and better realize the function of the differential circuit.

[0034] See attached Figure 3, the input stage amplifier circuit includes: a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, and a ninth transistor Q9. A first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The first transistor Q1 and the second transistor Q2 form a current mirror. The emitter of the first transistor Q1 and the emitter of the second transistor Q2 are respectively connected to a power supply. The base of the first transistor Q1 is respectively connected to the base of the second transistor Q2, the collector of the third transistor Q3, and the collector of the fourth transistor Q4. The collector of the first transistor Q1 is connected to the collector of the fourth transistor Q4. The base of the third transistor Q3 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is grounded. The base of the fourth transistor Q4 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded; the emitter of the third transistor Q3 is connected to the emitter of the fifth transistor Q5; the emitter of the fourth transistor Q4 is connected to the emitter of the sixth transistor Q6; the base of the fifth transistor Q5 is connected to the base of the sixth transistor Q6. The collector of the fifth transistor Q5 is connected to the collector of the seventh transistor Q7 and the base of the ninth transistor Q9, respectively. The collector of the sixth transistor Q6 is connected to the collector of the eighth transistor Q8 and the base of the twelfth transistor in the intermediate stage amplifier circuit, respectively. The base of the seventh transistor Q7 is connected to the base of the eighth transistor Q8. The emitter of the seventh transistor Q7 is connected to the first end of the fourth resistor R4 and the first end of the third resistor R3, respectively. The emitter of the eighth transistor Q8 is connected to the first end of the fifth resistor R5 and the second end of the third resistor R3, respectively. A second end of the fourth resistor R4 and a second end of the fifth resistor R5 are connected to a negative voltage.

[0035] When the operating current of MAT03 and MAT12 is maintained above 0.01mA, its noise can remain stable. In order to make the transistor work normally and stably, it is necessary to design a reasonable bias circuit. The voltage source bias circuit is susceptible to factors such as temperature and power supply fluctuations, resulting in the drift of the output voltage, thereby reducing the stability of the bias circuit, and the input end of the amplifier circuit designed by the present invention is directly coupled, and the voltage source will introduce a DC voltage component into the signal, limiting the range of variation of the signal. In addition, the voltage source has limited control over the collector current of the transistor, which is not conducive to suppressing the noise of the circuit. Therefore, the present invention selects a current source to design a bias circuit. Transistor Q1, transistor Q2, transistor Q10, and transistor Q11 constitute a mirror current source, and the high matching of MAT12 and MAT03 transistors just solves the problem that the mirror current source circuit has high requirements for transistor matching.

[0036] The input stage amplifier circuit is composed of MAT12 (Q3Q4, Q7Q8) and MAT03 (Q5Q6) as the core. The input signal acts on the base of the third transistor Q3 and the fourth transistor Q4. The common collector amplifier circuit composed of the third transistor Q3 and the fourth transistor Q4 has the characteristics of high input impedance and low output impedance, which enhances the load capacity of the entire circuit. The fifth transistor Q5 and the sixth transistor Q6 form a common base amplifier circuit, which has a higher voltage gain and improves the bandwidth of the circuit. The seventh transistor Q7, the eighth transistor Q8, and the ninth transistor Q9 are active loads, which can transfer the change Δic5 of the collector current of the fifth transistor Q5 to the collector of the sixth transistor Q6, and the signal is output from the collector of the sixth transistor Q6, thereby realizing differential input and single-ended output. The approximate parameters of the transistors are the same. When the differential signal is input, Δie5=−Δie6, and Δib5=Δib6, that is, Δic5=−Δic6. The base current of the transistor Q9 is very small and can be ignored, so Δic5=Δic7. When R4=R5, Δic7=Δic8, so Δio1=Δic6−Δic8=−2Δic5. When the common-mode signal is input, Δic5=Δic6, and by the same token, Δio1=0. This shows that the input stage amplifier circuit can amplify the differential signal and suppress the interference of common-mode signals such as external noise. Adjusting the resistor R3 can eliminate the effects caused by temperature drift and transistor differences.

[0037] In some embodiments, the intermediate stage amplifier circuit includes: a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a zeroth resistor R0, a tenth transistor Q10, an eleventh transistor Q11 and a twelfth transistor Q12. The first end of the seventh resistor R7 and the first end of the eighth resistor R8 are respectively connected to the positive voltage. The second end of the seventh resistor R7 is respectively connected to the base of the tenth transistor Q10 and the eleventh transistor, and is connected to the collector of the eleventh transistor Q11. The emitters of the tenth transistor Q10 and the eleventh transistor Q11 are connected to a negative voltage. The second end of the eighth resistor R8 is connected to the first end of the ninth resistor R9, and the second end of the ninth resistor R9 is respectively connected to the second end of the zeroth resistor R0 and the collector of the twelfth transistor Q12, the emitter of the twelfth transistor Q12 is connected to the first end of the tenth resistor R10, and the second end of the tenth resistor R10 is connected to a negative voltage.

[0038] The intermediate stage amplifier circuit is a common emitter amplifier circuit with the twelfth transistor Q12 as the core. The twelfth transistor Q12 adopts an NPN transistor, model 2N2222. While amplifying the voltage, a negative feedback resistor R0 is introduced, which is connected between the input terminal Ui and the collector of Q12 to control the amplification factor of the circuit. The eighth resistor R8 is a large resistor and the ninth resistor R9 is a small resistor, which are used to coarsely adjust and finely adjust the offset voltage respectively, so that the DC component of the twelfth transistor Q12 is close to zero.

[0039] In some embodiments, the output stage amplifier circuit includes: a thirteenth resistor R13, an eleventh resistor R11, a twelfth resistor R12, a fourteenth resistor R14, a first capacitor C1, a second capacitor C2 and a third capacitor C3.

[0040] The first end of the thirteenth resistor R13 is connected to a positive voltage; wherein the positive voltage is 15V. The second end of the thirteenth resistor R13 is connected to the first end of the second capacitor C2 and the first end of the operational amplifier. The second end of the second capacitor C2 is connected to the ground and the first end of the eleventh resistor R11, respectively, and the second end of the eleventh resistor R11 is connected to the positive input end of the operational amplifier A0 and the first end of the first capacitor C1. The second end of the first capacitor C1 is connected to the first end of the zeroth resistor R0 and the second end of the ninth resistor R9 in the intermediate stage amplifier circuit. The first end of the twelfth resistor R12 is connected to the negative input end of the operational amplifier A0, and the second end is connected to the ground and the first end of the third capacitor C3. The second end of the third capacitor C3 is connected to the second end of the operational amplifier A0 and the first end of the fourteenth resistor R14. The second end of the fourteenth resistor R14 is connected to a negative voltage. wherein the negative voltage is -15V.

[0041] The output stage amplifier circuit is built with the operational amplifier A0 as the core. The integrated operational amplifier chip has excellent low-noise amplification performance and extremely high common-mode rejection ratio, and is particularly suitable for the conditioning of weak signals. Among them, the first capacitor C1 is a decoupling capacitor used to eliminate DC bias. The second capacitor C2 and the third capacitor C3 are filter capacitors to reduce the influence of power supply ripple. The thirteenth resistor R13 and the fourteenth resistor R14 are current limiting resistors to prevent excessive current from damaging the operational amplifier A0 chip. The input bias current of the operational amplifier A0 must have a return path to the ground, and the eleventh resistor R11 and the twelfth resistor R12 provide a return path to the ground. Rg is an adjustment resistor, and changing its resistance value can achieve adjustable gain of the output stage amplifier circuit.

[0042] The stability of the power supply system is equally important. If the power supply noise is too large, it will seriously affect the working performance of the system. The present invention adopts ±15V dual power supply, and an electronic filter circuit is designed to reduce the ripple of ±15V voltage.

[0043] See attached Figure 4The first power supply filter circuit 11 comprises: a thirteenth transistor Q13, the emitter of the thirteenth transistor Q13 is respectively connected to the anode of the eighth diode D8, the anode of the ninth diode D9, and the first end of the first filter capacitor C26. The second end of the first filter capacitor C26 is grounded. The collector of the thirteenth transistor Q13 is respectively connected to the cathode of the seventh diode D7, the first end of the second filter capacitor C23, the first end of the seventeenth resistor R17, the cathode of the seventh diode D7 and the input power supply. The second end of the seventeenth resistor R17, the anode of the seventh diode D7, the second end of the eighteenth resistor R18, the first end of the third filter capacitor C24 and the first end of the fourth filter capacitor C25 are connected together. The second end of the third filter capacitor C24 and the second end of the fourth filter capacitor C25 are connected together and grounded. The base of the thirteenth transistor Q13 is respectively connected to the cathode of the eighth diode and the first end of the eighteenth resistor R18.

[0044] The first power supply is +15V. The first power supply filter circuit consists of two parts: the first part is a π-type filter, which is composed of the second filter capacitor C23, the seventeenth resistor R17, and the third filter capacitor C24, thereby filtering the Vi ripple. The second part is an emitter follower, which is composed of the thirteenth transistor Q13, the seventeenth resistor R17, and the eighteenth resistor R18. The seventeenth resistor R17 and the eighteenth resistor R18 are bias resistors of the thirteenth transistor Q13 to stabilize the base potential. Since the current input to the base of the thirteenth transistor Q13 fluctuates less, the output emitter current is also relatively stable. The emitter follower has the function of current amplification, which enhances the load-carrying capacity of the circuit.

[0045] The thirteenth transistor Q13, the seventeenth resistor R17 and the third filter capacitor C24 form a capacitance multiplier, which can be equivalent to a filter capacitor, and its equivalent capacitance is equivalent to the third filter capacitor C24 multiplied by the current gain of the transistor, which significantly increases the capacitance of the capacitor and improves the filtering effect. The advantage of the capacitance multiplier is that under the same capacitance value, the volume is smaller than the true capacitor, and the power supply ripple noise can be well suppressed when loaded, which is particularly suitable for the occasion where low-noise DC power supply is required when designing the electronic unit of the short offset electromagnetic receiving system.

[0046] See attached Figure 5, the second power supply filter circuit 12 comprises: a fourteenth transistor Q14, the emitter of the fourteenth transistor Q14 is respectively connected to the cathode of the eleventh diode D11, the first end of the fifth filter capacitor C30, and the cathode of the twelfth diode D12. The second end of the fifth filter capacitor C30 is grounded. The base of the fourteenth transistor Q14 is respectively connected to the first end of the twentieth resistor R20 and the anode of the eleventh diode D11. The collector of the fourteenth transistor Q14 is respectively connected to the first end of the nineteenth resistor R19, the anode of the tenth diode D10, the anode of the twelfth diode D12 and the first end of the sixth filter capacitor C27. The second end of the sixth filter capacitor C27 is grounded. The cathode of the tenth diode Q10 is respectively connected to the second end of the twentieth resistor R20. The second end of the nineteenth resistor R19, the first end of the seventh filter capacitor C28 and the first end of the eighth filter capacitor C29. The second end of the seventh filter capacitor C28 and the second end of the eighth filter capacitor C29 are connected together and grounded.

[0047] See attached Figure 6 When using short-offset transient electromagnetic method for actual detection, the magnetic induction coil will also superimpose the noise in the target frequency band into the signal. Since the power grid equipment uses alternating current with a frequency of 50Hz, the target signal is often mixed with 50Hz power frequency noise, which causes great interference to the subsequent signal processing, so it is necessary to filter the single frequency point of 50Hz. The present invention adopts a double T-type band-stop filter to filter out the power frequency interference signal, and introduces voltage-controlled feedback to enable it to have excellent frequency selection characteristics and filtering performance. The filter is mainly composed of three parts: a frequency selection module, an amplification module, and a feedback module.

[0048] The power frequency noise suppression circuit 14 includes: an amplifier and a voltage follower. The positive input terminal of the amplifier A1 is connected to the first end of the second filter capacitor C52 and the first end of the second filter resistor R52 respectively. The output terminal of the amplifier A1 outputs the voltage U0. The second end of the second filter capacitor C52 is connected to the first end of the first filter capacitor C51 and the first end of the third filter resistor R53 respectively. The second end of the second filter resistor R52 is connected to the first end of the third filter capacitor C53 and the first end of the first filter resistor R51 respectively. The first end of the first filter resistor R51 inputs the power supply Ui. The second end of the first filter capacitor C51 and the second end of the first filter resistor R51 are connected together. The second end of the third filter resistor R53 and the second end of the third filter capacitor C53 are connected together and connected to the output terminal of the voltage follower. The positive input end of the voltage follower A2 is connected to the first end of the fifth filter resistor R55 and the first end of the fourth filter resistor R54, respectively. The second end of the fifth filter resistor R55 is grounded, and the second end of the fourth filter resistor R54 is connected to the output end of the amplifier A1. A single T network is composed of R51, R52, and C53, which can be regarded as a low-pass filter. Another single T network is composed of C51, C52, and R53, which can be regarded as a high-pass filter. The value of the center frequency f_0 of the wave limiter is determined by changing the resistance and capacitance values, that is, the frequency value that needs to be filtered out. The output end of the amplifier A1 is the output of the wave limiter, and the output end of the amplifier A1 and the voltage follower A2 form a voltage feedback circuit, which feeds back part of the output signal of the amplifier A1 to the longitudinal arm of the double T network to form a bootstrap, thereby introducing positive feedback. The fourth filter resistor R54 and the fifth filter resistor R55 are used to determine the value of the positive feedback coefficient m.

[0049] The center frequency f_0 of the wave limiter of the present invention is 50Hz. When the input signal is of other frequencies, its gain is 1. The operational amplifier chip AD8602 is selected. The chip has the characteristics of being less affected by temperature and having a large dynamic range. It can stably respond to input signals when powered by low voltage.

[0050] The bandwidth BW and Q value of the limiter are:

[0051] Where BW is the bandwidth, f_H is the upper limit frequency, f_L is the lower limit frequency, f_0 is the center frequency, Q is the ratio of the center frequency to the bandwidth, and m is the positive feedback coefficient.

[0052] If you want the filter performance of the limiter to be good, that is, the bandwidth of the limiter is narrow and the Q value is high, then the m value needs to be close to 1. The bandwidth BW of the limiter is the ratio of the center frequency f_0 to Q. When the center frequency is selected as 50Hz, its bandwidth can be reduced by increasing the Q value.

[0053] In some embodiments, when the electromagnetic receiving system is working, the magnetic induction coil will receive signals of all frequencies in the environment, that is, the target signal is mixed with a lot of noise, including external environmental noise, drone flight noise, working noise of electronic components on the circuit board, ripple noise introduced by the battery and power supply, etc., which increases the difficulty of later data processing and analysis, and even directly affects the detection results. In addition, when signals of various frequencies are superimposed in the time domain, the signal amplitude may exceed the maximum receiving voltage of the receiving system, and the noise generated by the electronic components is also positively correlated with the size of the frequency band. Therefore, it is necessary to design a suitable filter to limit the bandwidth of the signal conditioning circuit in the receiving system and prevent interference signals outside the specific frequency range. The passband cutoff frequency of the active low-pass filter circuit is set to 15kHz, the stopband start frequency is set to 30kHz, the passband attenuation is 3dB, and the stopband attenuation is 30dB. The fourth-order Butterworth low-pass filter circuit is formed in the form of cascading two second-order filters.

[0054] See attached Figure 7 , the active filter circuit 13 comprises: a first active filter operational amplifier A61 and a second active filter operational amplifier A62. The output end of the first active filter operational amplifier A61 is respectively connected to the first end of the first active filter resistor R63, the first end of the first active filter capacitor C61 and the inverting input end of the first active filter operational amplifier. The second end of the first active filter capacitor C61 is respectively connected to the first end of the first active filter resistor R61 and the first end of the second active filter resistor R62. The second end of the second active filter resistor R62 is respectively connected to the first end of the second active filter capacitor C62 and the non-inverting input end of the first active filter operational amplifier A61. The output end of the second active filter operational amplifier A62 is respectively connected to the first end of the third active filter capacitor C63 and the inverting input end of the second active filter operational amplifier A62. The second end of the third active filter capacitor C63 is respectively connected to the first end of the third active filter resistor R61 and the first end of the fourth active filter resistor R64. The second end of the fourth active filter resistor R64 is respectively connected to the first end of the fourth active filter capacitor C64 and the non-inverting input end of the second active filter operational amplifier A62.

[0055] In this embodiment, the chip model of the first active filter operational amplifier A61 and the second active filter operational amplifier A62 is NE5532. The chip integrates two operational amplifiers, has an extremely low noise level and excellent output driving capability, and the high slew rate of the chip makes the output waveform less likely to be distorted.

[0056] Second, see Appendix Figure 8The present application proposes a receiver, comprising the low-noise short-offset transient electromagnetic receiving signal conditioning circuit described in the above item, and also comprising: a main control board, a connection board and an analog board.

[0057] The low-noise short-offset transient electromagnetic receiving signal conditioning circuit is arranged on the analog board.

[0058] The connection board is provided with a magnetic coupling isolation module, which is respectively connected to the digital signal ports of the analog board and the main control board.

[0059] In this embodiment, the interface board is the bridge between the inside and outside of the instrument, integrating a sensor interface, a power interface, a communication interface, and an interactive interface. The sensor interface is mainly a magnetic field sensor interface, and its connection is connected to the analog channel input terminal on the analog board. The power interface is responsible for inputting an external 12V power supply and powering the entire system through a power distribution network. The communication interface and the interactive interface are responsible for the human-computer interaction function, and their internal wiring is connected to a multiprocessor chip (Multiprocessor System-on-Chip, MPSoC) on the main control board. In addition, the interface board also has functions such as overcurrent reverse connection protection and power monitoring. The digital interface of the power monitoring chip and the power control chip on the interface board are also connected to the MPSoC on the main control board.

[0060] The analog board has five analog channels to condition and convert analog signals of magnetic field components. The signal conditioning circuit mainly includes low-noise amplifier circuit, active filter circuit, power frequency noise suppression circuit, etc. The analog-to-digital conversion circuit includes an analog-to-digital converter and its peripheral circuits, and its digital interface is connected to the MPSoC on the main control board through a connection board. The model of the analog-to-digital converter is AD7760, which can output 24-bit precision sampling data at a maximum frequency of 2.5 MSPS.

[0061] The connection board is equipped with a magnetic coupling isolation module, which is connected to the digital signal ports of the analog board and the main control board respectively, and is responsible for isolating the digital part from the analog part, cutting off the electrical connection to reduce the interference of the digital part on the analog signal. The analog-to-digital conversion data enters the main control board through the connection board.

[0062] The main control board uses the MPSoC model ZU3EG as the main control chip, which is divided into two parts, ARM and FPGA. The two parts have different divisions of labor. The FPGA part is mainly responsible for controlling the analog board to perform analog-to-digital conversion, receiving and parsing conversion data, receiving and parsing GPS data, calibrating the constant temperature crystal oscillator, and managing the system power supply. The ARM part is mainly responsible for the process control, human-computer interaction, data storage and other functions of the entire acquisition station. The ARM part communicates with the FPGA part through the AXI bus inside the chip, and configures the acquisition parameters and controls the start and stop of the acquisition by reading and writing FPGA registers. After the analog-to-digital conversion data is parsed by the FPGA part, it is transmitted to the ARM part in the form of a data stream, and the ARM part stores it in an external hard disk.

[0063] In some embodiments, see Appendix Fig. 9 The main control board is provided with a cascade digital filter sampling device, and the cascade digital filter sampling device comprises: The first FIR filtering and downsampling device has an input end that inputs original data and an output end that outputs first downsampling data with a frequency that is twice that of the original data.

[0064] Among them, the original data input at the input end is the data obtained after AD sampling.

[0065] a second FIR filtering down-sampling device, wherein an input end of the second FIR filtering down-sampling device inputs the first down-sampling data, and an output end of the second FIR filtering down-sampling device outputs second down-sampling data with a frequency twice the frequency of the first down-sampling data; a third FIR filtering down-sampling device, wherein the input end of the third FIR filtering down-sampling device inputs the second down-sampling data, and the output end outputs third down-sampling data having a frequency twice that of the second down-sampling data; a fourth FIR filtering down-sampling device, wherein the third down-sampling data is input into the input end of the fourth FIR filtering down-sampling device, and the fourth down-sampling data having a frequency twice that of the third down-sampling data is output from the output end; a data selector, wherein the input ends of the data selector are respectively input with the original data, the first down-sampled data, the second down-sampled data, the third down-sampled data and the fourth down-sampled data; The output end of the data selector outputs the final filtered data.

[0066] See attached Figure 7, where each FIR filter downsampling device is composed of a FIR filter of length 96 and provides 120dB attenuation at the Nyquist frequency. Cascaded digital filter sampling avoids the spectrum aliasing effect during the downsampling process and can suppress the out-of-band quantization noise generated by the analog-to-digital conversion process. Through the cascaded digital filter sampling technology, the original sampling rate range of the analog-to-digital converter from 78 kSPS to 2.5 MSPS is expanded to 4.9 kSPS to 2.5 MSPS, while ensuring the acquisition accuracy after the sampling rate expansion, so that the instrument can be more flexibly applied to electromagnetic exploration in various frequency bands.

[0067] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the present disclosure. This application is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and examples are to be considered as exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0068] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A low-noise short-offset transient electromagnetic receiving signal conditioning circuit, characterized in that: include: A first power supply filter circuit, a second power supply filter circuit, an active filter circuit, a power frequency noise suppression circuit and a low noise amplifier circuit; The first power supply filter circuit and the second power supply filter circuit are used to filter the first power supply and the second power supply respectively to reduce noise; The active filter circuit is used to filter out interference signals; The power frequency noise suppression circuit is used to filter out power frequency noise; The low-noise amplifier circuit comprises: an input-stage amplifier circuit, an intermediate-stage amplifier circuit and an output-stage amplifier circuit.

2. The low-noise short-offset transient electromagnetic receiving signal conditioning circuit according to claim 1, characterized in that: The input stage amplifier circuit comprises: a first triode, a second triode, a third triode, a fourth triode, a fifth triode, a sixth triode, a seventh triode, an eighth triode and a ninth triode; a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor; The first transistor and the second transistor form a current mirror; The emitter of the first triode and the emitter of the second triode are respectively connected to a power supply; The base of the first triode is respectively connected to the base of the second triode, the collector of the third triode and the collector of the fourth triode; The collector of the first triode is connected to the collector of the fourth triode; The base of the third transistor is connected to the first end of the first resistor, and the second end of the first resistor is grounded; The base of the fourth transistor is connected to the first end of the second resistor, and the second end of the second resistor is grounded; The emitter of the third transistor is connected to the emitter of the fifth transistor; The emitter of the fourth triode is connected to the emitter of the sixth triode; The base of the fifth transistor is connected to the base of the sixth transistor; The collector of the fifth triode is connected to the collector of the seventh triode and the base of the ninth triode respectively; The collector of the sixth triode is respectively connected to the collector of the eighth triode and the base of the twelfth triode in the intermediate stage amplifier circuit; The base of the seventh transistor is connected to the base of the eighth transistor; The emitter of the seventh transistor is connected to the first end of the fourth resistor and the first end of the third resistor respectively; The emitter of the eighth transistor is connected to the first end of the fifth resistor and the second end of the third resistor respectively; The second end of the fourth resistor and the second end of the fifth resistor are connected to a negative voltage.

3. The low-noise short-offset transient electromagnetic receiving signal conditioning circuit according to claim 1, characterized in that: The intermediate stage amplifier circuit comprises: a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a zeroth resistor, a tenth transistor, an eleventh transistor and a twelfth transistor; The first end of the seventh resistor and the first end of the eighth resistor are respectively connected to a positive voltage; The second end of the seventh resistor is connected to the base of the tenth transistor and the eleventh transistor, and is connected to the collector of the eleventh transistor; The emitters of the tenth transistor and the eleventh transistor are connected to a negative voltage; The second end of the eighth resistor is connected to the first end of the ninth resistor, the second end of the ninth resistor is respectively connected to the second end of the zeroth resistor and the collector of the twelfth transistor, the emitter of the twelfth transistor is connected to the first end of the tenth resistor, and the second end of the tenth resistor is connected to a negative voltage.

4. The low-noise short-offset transient electromagnetic receiving signal conditioning circuit according to claim 1, characterized in that: The output stage amplifier circuit comprises: a thirteenth resistor, an eleventh resistor, a twelfth resistor, a fourteenth resistor, a first capacitor, a second capacitor and a third capacitor; The first end of the thirteenth resistor is connected to a positive voltage; The second end of the thirteenth resistor is connected to the first end of the second capacitor and the first end of the operational amplifier respectively; The second end of the second capacitor is connected to the ground and the first end of the eleventh resistor respectively, and the second end of the eleventh resistor is connected to the positive input end of the operational amplifier and the first end of the first capacitor respectively; The second end of the first capacitor is connected to the first end of the zeroth resistor and the second end of the ninth resistor in the intermediate stage amplifier circuit respectively; The first end of the twelfth resistor is connected to the negative input terminal of the operational amplifier, and the second end is respectively connected to the ground and the first end of the third capacitor; The second end of the third capacitor is respectively connected to the second end of the operational amplifier and the first end of the fourteenth resistor; The second end of the fourteenth resistor is connected to a negative voltage.

5. The low-noise short-offset transient electromagnetic receiving signal conditioning circuit according to claim 1, characterized in that: The first power supply filter circuit comprises: a thirteenth transistor, the emitter of which is respectively connected to the anode of the eighth diode, the anode of the ninth diode, and the first end of the first filter capacitor; The second end of the first filter capacitor is grounded; The collector of the thirteenth transistor is respectively connected to the cathode of the seventh diode, the first end of the second filter capacitor, the first end of the seventeenth resistor, the cathode of the seventh diode and the input power supply; The second end of the seventeenth resistor, the anode of the seventh diode, the second end of the eighteenth resistor, the first end of the third filter capacitor and the first end of the fourth filter capacitor are connected together; The second end of the third filter capacitor and the second end of the fourth filter capacitor are connected together and grounded; The base of the thirteenth transistor is respectively connected to the cathode of the eighth diode and the first end of the eighteenth resistor.

6. The low-noise short-offset transient electromagnetic receiving signal conditioning circuit according to claim 1, characterized in that: The second power supply filter circuit comprises: a fourteenth transistor, the emitter of which is respectively connected to the cathode of the eleventh diode, the first end of the fifth filter capacitor, and the cathode of the twelfth diode; The second end of the fifth filter capacitor is grounded; The base of the fourteenth transistor is respectively connected to the first end of the twentieth resistor and the anode of the eleventh diode; The collector of the fourteenth triode is respectively connected to the first end of the nineteenth resistor, the anode of the tenth diode, the anode of the twelfth diode and the first end of the sixth filter capacitor; The second end of the sixth filter capacitor is grounded; The cathode of the tenth diode is respectively connected to the second end of the twentieth resistor, the second end of the nineteenth resistor, the first end of the seventh filter capacitor and the first end of the eighth filter capacitor; the second end of the seventh filter capacitor and the second end of the eighth filter capacitor are connected together and grounded.

7. The low-noise short-offset transient electromagnetic receiving signal conditioning circuit according to claim 4, characterized in that: The power frequency noise suppression circuit comprises: an amplifier and a voltage follower; The positive input terminal of the amplifier is connected to the first end of the second filter capacitor and the first end of the second filter resistor respectively; The second end of the second filter capacitor is connected to the first end of the first filter capacitor and the first end of the third filter resistor respectively; The second end of the second filter resistor is connected to the first end of the third filter capacitor and the first end of the first filter resistor respectively; The second end of the first filter capacitor and the second end of the first filter resistor are connected together; The second end of the third filter resistor and the second end of the third filter capacitor are connected together and connected to the output end of the voltage follower; The positive input end of the voltage follower is respectively connected to the first end of the fifth filter resistor and the first end of the fourth filter resistor, the second end of the fifth filter resistor is grounded, and the second end of the fourth filter resistor is connected to the output end of the amplifier.

8. The low-noise short-offset transient electromagnetic receiving signal conditioning circuit according to claim 1, characterized in that: The active filtering circuit comprises: a first active filter operational amplifier and a second active filter operational amplifier; The output end of the first active filter operational amplifier is respectively connected to the first end of the first active filter resistor, the first end of the first active filter capacitor and the inverting input end of the first active filter operational amplifier; The second end of the first active filter capacitor is respectively connected to the first end of the first active filter resistor and the first end of the second active filter resistor; The second end of the second active filter resistor is respectively connected to the first end of the second active filter capacitor and the non-inverting input end of the first active filter operational amplifier; The output terminal of the second active filter operational amplifier is respectively connected to the first terminal of the third active filter capacitor and the inverting input terminal of the second active filter operational amplifier; The second end of the third active filter capacitor is connected to the first end of the third active filter resistor and the first end of the fourth active filter resistor respectively; The second end of the fourth active filter resistor is respectively connected to the first end of the fourth active filter capacitor and the non-inverting input end of the second active filter operational amplifier.

9. A receiver, characterized in that: The low-noise short-offset transient electromagnetic receiving signal conditioning circuit according to any one of claims 1 to 8 further comprises: a main control board, a connection board and an analog board The low-noise short-offset transient electromagnetic receiving signal conditioning circuit is arranged on the analog board; The connection board is provided with a magnetic coupling isolation module, which is respectively connected to the digital signal ports of the analog board and the main control board.

10. The receiver according to claim 9, characterized in that The main control board is provided with a cascade digital filter sampling device, and the cascade digital filter sampling device comprises: A first FIR filtering downsampling device, wherein the input end of the first FIR filtering downsampling device inputs original data, and the output end outputs first downsampling data with a frequency twice that of the original data; a second FIR filtering down-sampling device, wherein an input end of the second FIR filtering down-sampling device inputs the first down-sampling data, and an output end of the second FIR filtering down-sampling device outputs second down-sampling data with a frequency twice the frequency of the first down-sampling data; a third FIR filtering down-sampling device, wherein the input end of the third FIR filtering down-sampling device inputs the second down-sampling data, and the output end outputs third down-sampling data having a frequency twice that of the second down-sampling data; a fourth FIR filtering down-sampling device, wherein the third down-sampling data is input into the input end of the fourth FIR filtering down-sampling device, and the fourth down-sampling data having a frequency twice that of the third down-sampling data is output from the output end; a data selector, wherein the input ends of the data selector are respectively input with the original data, the first down-sampled data, the second down-sampled data, the third down-sampled data and the fourth down-sampled data; The output end of the data selector outputs the final filtered data.

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