Frequency offset calibration method, system and device based on non-signaling test and medium

Abstract

The invention relates to a non-signaling test-based frequency offset calibration method, system and device and a medium, and the method comprises the steps: carrying out the parallel non-signaling frequency offset test of a plurality of target chips, collecting the output waveforms of the target chips, and determining the frequency offset values of the target chips according to the output waveforms; performing deviation analysis on the frequency deviation value, and calculating a corresponding frequency deviation calibration value based on the frequency deviation value and a preset frequency calibration coefficient under the condition that the frequency deviation value reaches a preset frequency limit range; writing the frequency offset calibration value into a corresponding target chip, and performing parallel frequency offset calibration; and carrying out calibration degree verification on the target chip after frequency offset calibration so as to confirm whether the frequency offset value of the target chip accords with a preset standard frequency. The method and the device have the effect of improving the frequency offset calibration efficiency of the chip.

Description

Technical Field

[0001] The present application relates to the technical field of chip frequency calibration, and in particular to a frequency deviation calibration method, system, device and medium based on non-signaling test. Background Art

[0002] At present, chip frequency deviation calibration is widely used in radio frequency equipment, communication equipment and other electronic devices that require precise frequency control. The main purpose of frequency deviation calibration is to adjust the frequency control module inside the chip so that the output frequency of the chip reaches the preset standard frequency to ensure the normal operation of the equipment.

[0003] Existing, traditional frequency offset calibration methods usually rely on dedicated tools such as frequency calibration boxes, and calibrate individual test chips one by one. This is a relatively complex and time-consuming operation, and it is difficult to achieve efficient calibration processing. As a result, when faced with the production and testing needs of a large number of chips, the time cost and equipment cost used for calibration are high, and it is even more unable to meet the needs of fast and efficient frequency calibration in large-scale production in factories.

[0004] The above-mentioned prior art solutions have the following defects: the traditional frequency offset calibration method calibrates individual test chips one by one, which makes it difficult to achieve efficient calibration processing, so there is room for improvement. Summary of the invention

[0005] In order to improve the efficiency of chip frequency offset calibration, the present application provides a frequency offset calibration method, system, device and medium based on non-signaling test.

[0006] The above-mentioned invention objective of the present application is achieved through the following technical solutions: A frequency offset calibration method based on non-signaling test, the frequency offset calibration method based on non-signaling test comprising: Performing non-signaling frequency deviation tests on a plurality of target chips in parallel, thereby collecting output waveforms of the target chips, and determining frequency deviation values ​​of the target chips according to the output waveforms; Performing deviation analysis on the frequency deviation value, and when the frequency deviation value reaches a preset frequency limit range, calculating a corresponding frequency deviation calibration value based on the frequency deviation value and a preset frequency correction coefficient; Writing the frequency offset calibration value into the corresponding target chip to perform parallel frequency offset calibration; The calibration degree of the target chip after the frequency offset calibration is verified to confirm whether the frequency offset value of the target chip meets the preset standard frequency.

[0007] By adopting the above technical solution, by performing non-signaling frequency deviation tests on several target chips in parallel, it is possible to achieve synchronous testing of multiple chips, avoiding the inefficiency of testing one by one in the traditional method, thereby greatly improving the efficiency and test accuracy of the frequency deviation test; by collecting the output waveform of the target chip and calculating the frequency deviation value, the frequency offset information of each chip can be accurately obtained, thereby providing accurate data support for subsequent frequency deviation calibration; by calculating the frequency deviation calibration value through the frequency deviation value and the preset frequency correction coefficient, the frequency of each chip can be automatically adjusted according to its frequency deviation to make it close to the standard frequency, thereby realizing automated and precise frequency deviation calibration, reducing manual intervention and improving the overall calibration accuracy; by calibrating the target chips in parallel, multiple target chips can be calibrated at the same time, thereby improving the efficiency of frequency deviation calibration and reducing the overall test and calibration time; through calibration verification, it can be ensured that the frequency deviation value of each chip meets the preset standard frequency, thereby improving the reliability of the system and ensuring that the frequency finally output by the chip meets the high-precision requirements.

[0008] In one example, the present application may be further configured as follows: performing non-signaling frequency deviation tests on a plurality of target chips in parallel, thereby collecting output waveforms of the target chips, and determining frequency deviation values ​​of the target chips according to the output waveforms, specifically including: Sending a frequency deviation test instruction to each of the target chips to start a non-signaling frequency deviation test; The output waveform of the target chip is collected, and the frequency deviation value of each target chip is calculated using frequency domain analysis technology.

[0009] By adopting the above technical solution, by sending a frequency deviation test instruction to each target chip and starting the non-signaling frequency deviation test, it is possible to ensure that each chip can perform frequency deviation testing according to a unified test standard and time synchronization, thereby reducing the time waste caused by manual test operations and improving the level of test automation; by collecting the output waveform of the target chip and using frequency domain analysis technology to calculate the frequency deviation value, the frequency offset of the chip can be accurately analyzed, and the frequency domain analysis technology is used to reduce the influence of external signal interference, thereby improving the accuracy of frequency deviation value measurement and ensuring that the calibration process is more reliable.

[0010] In one example, the present application may be further configured as follows: the frequency deviation value of each target chip is calculated by using the frequency domain analysis technology, specifically including: Performing Fourier transform on the output waveform to convert the time domain signal in the output waveform into a frequency domain signal; The peak frequency in the frequency domain signal is obtained, the peak frequency is compared with a preset standard frequency, a corresponding deviation value is calculated, and the frequency deviation value of the target chip is obtained.

[0011] By adopting the above technical solution, the time domain signal is converted into a frequency domain signal by performing Fourier transform on the output waveform, which can more clearly analyze the frequency components of the chip, avoid possible noise interference in the time domain signal, and improve the calculation accuracy of the frequency deviation value; by obtaining the peak frequency in the frequency domain signal and comparing it with the preset standard frequency, the chip frequency offset can be accurately identified and converted into a frequency deviation value, thereby providing a reliable basis for subsequent frequency deviation calibration and ensuring the accuracy and consistency of the frequency deviation value.

[0012] In one example, the present application may be further configured as follows: when the frequency offset value reaches a preset frequency limit range, calculating a corresponding frequency offset calibration value based on the frequency offset value and a preset frequency correction coefficient, specifically including: Multiplying the frequency deviation value by the preset frequency correction coefficient to obtain a preliminary calibration value; When the preliminary calibration value is within a preset calibration range, using the preliminary calibration value as the frequency offset calibration value; When the preliminary calibration value is not within the preset calibration range, a secondary calibration is performed based on the preliminary calibration value to obtain the frequency offset calibration value.

[0013] By adopting the above technical solution, by multiplying the frequency deviation value with the preset calibration coefficient, the calibration amplitude of the chip frequency can be adjusted according to the size of the frequency deviation, ensuring that the frequency deviation calibration value has sufficient correction force, thereby achieving efficient frequency deviation correction; by directly using the preliminary calibration value as the frequency deviation calibration value when it is within the preset calibration range, the calibration process can be simplified and unnecessary complex adjustments can be avoided, thereby improving the efficiency of calibration; by performing secondary calibration based on the preliminary calibration value, it is possible to flexibly respond to situations where the frequency deviation value exceeds the preset range, ensuring that the frequency of the chip is adjusted to the standard value, and improving the calibration accuracy through secondary calibration to prevent error accumulation caused by excessive frequency deviation.

[0014] In one example, the present application may be further configured as follows: writing the frequency offset calibration value into the corresponding target chip to perform parallel frequency offset calibration, specifically including: Transmitting the calculated frequency offset calibration value to the corresponding target chip through parallel control; The frequency control module inside the target chip is adjusted according to the frequency offset calibration value to complete the frequency offset calibration.

[0015] By adopting the above technical solution, the calculated frequency deviation calibration value is transmitted to the corresponding target chip through parallel control, so that the calibration of multiple chips can be completed at the same time, avoiding the inefficient traditional method of one-by-one transmission, thereby greatly improving work efficiency; by adjusting the frequency control module inside the target chip according to the frequency deviation calibration value, the frequency of each chip can be accurately adjusted to ensure that its final output frequency meets the standard requirements, thereby improving the overall performance of the chip and system stability, and reducing performance instability and failures caused by excessive frequency deviation.

[0016] In one example, the present application may be further configured as follows: performing calibration verification on the target chip after the frequency offset calibration, and then confirming whether the frequency offset value of the target chip meets the preset standard frequency, specifically includes: After the frequency offset calibration is completed, performing a secondary frequency offset test on each of the target chips, and collecting an output waveform corresponding to the target chip; Perform frequency domain analysis on the collected output waveform and calculate the calibration frequency deviation value after calibration; The calibration frequency deviation value is compared with a preset standard frequency. When the calibration frequency deviation value meets the preset standard frequency, a calibration success message is triggered. When the calibration frequency deviation value does not meet the preset standard frequency, a recalibration instruction is triggered.

[0017] By adopting the above technical solution, by performing a secondary frequency offset test on the target chip after frequency offset calibration and collecting the output waveform corresponding to the target chip, the frequency offset calibration effect of each target chip can be effectively verified to ensure the accuracy and stability of the calibration process; by performing frequency domain analysis on the collected output waveform and calculating the calibrated frequency offset value after calibration, the measurement of the frequency offset value can be further refined to avoid errors caused by external interference, thereby improving the accuracy of the calibrated frequency offset value; by comparing the calibrated frequency offset value with the preset standard frequency and triggering a calibration success message or a recalibration instruction, the recalibration operation can be triggered in time when the calibration does not meet the standard, thereby avoiding frequency errors in system operation, so that the frequency offset calibration can achieve higher accuracy and reliability, and ensure the stability and consistency of the chip in long-term use.

[0018] The second object of the invention is achieved by the following technical solutions: A frequency offset calibration system based on non-signaling test, the frequency offset calibration system based on non-signaling test comprising: A frequency deviation test module, used to perform non-signaling frequency deviation tests on a plurality of target chips in parallel, thereby collecting output waveforms of the target chips, and determining frequency deviation values ​​of the target chips according to the output waveforms; A frequency deviation analysis module, configured to perform deviation analysis on the frequency deviation value, and when the frequency deviation value reaches a preset frequency limit range, calculate a corresponding frequency deviation calibration value based on the frequency deviation value and a preset frequency correction coefficient; A calibration value transmission module, used for writing the frequency offset calibration value into the corresponding target chip to perform parallel frequency offset calibration; The calibration verification module is used to verify the calibration of the target chip after the frequency deviation calibration, and further confirm whether the frequency deviation value of the target chip meets the preset standard frequency.

[0019] By adopting the above technical solution, by performing non-signaling frequency deviation tests on several target chips in parallel, it is possible to achieve synchronous testing of multiple chips, avoiding the inefficiency of testing one by one in the traditional method, thereby greatly improving the efficiency and test accuracy of the frequency deviation test; by collecting the output waveform of the target chip and calculating the frequency deviation value, the frequency offset information of each chip can be accurately obtained, thereby providing accurate data support for subsequent frequency deviation calibration; by calculating the frequency deviation calibration value through the frequency deviation value and the preset frequency correction coefficient, the frequency of each chip can be automatically adjusted according to its frequency deviation to make it close to the standard frequency, thereby realizing automated and precise frequency deviation calibration, reducing manual intervention and improving the overall calibration accuracy; by calibrating the target chips in parallel, multiple target chips can be calibrated at the same time, thereby improving the efficiency of frequency deviation calibration and reducing the overall test and calibration time; through calibration verification, it can be ensured that the frequency deviation value of each chip meets the preset standard frequency, thereby improving the reliability of the system and ensuring that the frequency finally output by the chip meets the high-precision requirements.

[0020] The third objective of the present application is achieved through the following technical solutions: A computer device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned frequency offset calibration method based on non-signaling test when executing the computer program.

[0021] The fourth objective of the present application is achieved through the following technical solutions: A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the frequency offset calibration method based on non-signaling test are implemented.

[0022] In summary, this application includes the following beneficial technical effects: 1. By performing non-signaling frequency deviation tests on several target chips in parallel, it is possible to achieve synchronous testing of multiple chips, avoiding the inefficiency of testing one by one in the traditional method, thereby greatly improving the efficiency and accuracy of frequency deviation testing; by collecting the output waveform of the target chip and calculating the frequency deviation value, the frequency deviation information of each chip can be accurately obtained, thereby providing accurate data support for subsequent frequency deviation calibration; by calculating the frequency deviation calibration value through the frequency deviation value and the preset frequency correction coefficient, the frequency of each chip can be automatically adjusted according to its frequency deviation to make it close to the standard frequency, thereby realizing automated and precise frequency deviation calibration, reducing manual intervention and improving the overall calibration accuracy; by calibrating the target chips in parallel, multiple target chips can be calibrated at the same time, thereby improving the efficiency of frequency deviation calibration and reducing the overall test and calibration time; through calibration verification, it can ensure that the frequency deviation value of each chip meets the preset standard frequency, thereby improving the reliability of the system and ensuring that the frequency output of the chip finally meets the high-precision requirements; 2. By sending a frequency deviation test instruction to each target chip and starting the non-signaling frequency deviation test, it can ensure that each chip can perform frequency deviation test according to the unified test standard and time synchronization, thereby reducing the time waste caused by manual test operation and improving the automation level of the test; by collecting the output waveform of the target chip and using the frequency domain analysis technology to calculate the frequency deviation value, the frequency deviation of the chip can be accurately analyzed. The frequency domain analysis technology is used to reduce the influence of external signal interference, thereby improving the accuracy of frequency deviation value measurement and ensuring that the calibration process is more reliable; 3. By performing Fourier transform on the output waveform and converting the time domain signal into a frequency domain signal, the frequency components of the chip can be analyzed more clearly, the noise interference that may exist in the time domain signal can be avoided, and the calculation accuracy of the frequency deviation value can be improved; by obtaining the peak frequency in the frequency domain signal and comparing it with the preset standard frequency, the chip frequency offset can be accurately identified and converted into a frequency deviation value, thereby providing a reliable basis for subsequent frequency deviation calibration and ensuring the accuracy and consistency of the frequency deviation value. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a flow chart of a frequency offset calibration method based on non-signaling test in an embodiment of the present application; Figure 2 It is a wiring diagram of a frequency calibration device in a frequency deviation calibration method based on non-signaling test in an embodiment of the present application; Figure 3 is a flowchart for implementing step S10 in a frequency offset calibration method based on non-signaling test in an embodiment of the present application; Figure 4 is a flowchart for implementing step S12 in a frequency offset calibration method based on non-signaling test in an embodiment of the present application; Figure 5is a flowchart for implementing step S20 in a frequency offset calibration method based on non-signaling test in an embodiment of the present application; Figure 6 is a flowchart for implementing step S30 in a frequency offset calibration method based on non-signaling test in an embodiment of the present application; Figure 7 is a flowchart for implementing step S40 in a frequency offset calibration method based on non-signaling test in an embodiment of the present application; Figure 8 It is a principle block diagram of a frequency offset calibration system based on non-signaling test in one embodiment of the present application; Fig. 9 It is a schematic diagram of a device in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The present application is further described in detail below in conjunction with the accompanying drawings.

[0025] In one embodiment, if Figure 1 As shown, the present application discloses a frequency offset calibration method based on non-signaling test, which specifically includes the following steps: S10: performing non-signaling frequency deviation tests on a plurality of target chips in parallel, thereby collecting output waveforms of the target chips, and determining frequency deviation values ​​of the target chips according to the output waveforms.

[0026] Specifically, a frequency deviation test instruction is first sent to each target chip to start a non-signaling frequency deviation test. The test instruction is transmitted to each target chip via wireless or wired signals. After receiving the instruction, the target chip automatically starts the frequency deviation test process and uses the frequency control module inside the chip to detect its output frequency. The test is performed through internal response. The entire process does not require external signal exchange and only relies on the chip's own frequency deviation signal for detection. The test is performed in parallel between multiple target chips to improve test efficiency and synchronization.

[0027] S20: performing deviation analysis on the frequency deviation value, and when the frequency deviation value reaches a preset frequency limit range, calculating a corresponding frequency deviation calibration value based on the frequency deviation value and a preset frequency correction coefficient.

[0028] Specifically, the frequency deviation value of each target chip is first calculated and compared with the preset standard frequency. The frequency deviation deviation is obtained by calculating the deviation between the frequency deviation value and the standard frequency. If the frequency deviation value exceeds the preset frequency limit range, the frequency deviation calibration calculation step is entered, and the calculated frequency deviation value is multiplied by the preset frequency correction coefficient to obtain a preliminary frequency deviation calibration value. If the preliminary calibration value is within the preset calibration range, it can be directly used as the frequency deviation calibration value.

[0029] S30: Writing the frequency offset calibration value into the corresponding target chip to perform parallel frequency offset calibration.

[0030] Specifically, the calculated frequency offset calibration value is transmitted to each target chip through an appropriate communication interface such as SPI, I2C, etc. The frequency offset calibration tasks of multiple chips can be performed in parallel, and the frequency offset calibration value is transmitted to multiple target chips at the same time to ensure that each chip can receive its own calibration value in time. Then, based on the received frequency offset calibration value, the frequency control module of the target chip, such as VCO, PLL, etc., will adjust the frequency output of the chip and correct the frequency offset of the chip to reach the standard frequency, such as Figure 2 The calibration equipment wiring diagram shown in the figure shows that a computer and a Bluetooth test instrument can calibrate multiple chips at the same time. At the same time, the computer, Bluetooth test instrument and chip are all controlled by instructions, which is convenient for secondary development.

[0031] S40: Perform calibration verification on the target chip after the frequency offset calibration, and then confirm whether the frequency offset value of the target chip meets the preset standard frequency.

[0032] Specifically, after the frequency deviation calibration is completed, a secondary frequency deviation test is performed to collect the output waveform data of the target chip, and then the output waveform is processed using frequency domain analysis technology to calculate the calibrated frequency deviation value. The calculated result is compared with the preset standard frequency. If the calibrated frequency deviation value is within the preset error range, the calibration is confirmed to be successful and a success signal is triggered.

[0033] In one embodiment, if Figure 3 As shown, in step S10, a non-signaling frequency deviation test is performed on a plurality of target chips in parallel, and then the output waveform of the target chip is collected, and the frequency deviation value of the target chip is determined according to the output waveform, which specifically includes: S11: Send a frequency deviation test instruction to each target chip to start a non-signaling frequency deviation test.

[0034] Specifically, the frequency deviation test instruction is transmitted to each target chip via wireless signals or wired signals. After receiving the signal, the chip starts its internal frequency control module to perform a frequency deviation test. During this process, the target chip does not need to exchange data with external signals, but only tests the frequency deviation through its own response signal. The frequency deviation tests of all target chips can be started simultaneously through parallel processing to ensure that the test process is carried out synchronously and improve efficiency.

[0035] S12: Collect the output waveform of the target chip and calculate the frequency deviation value of each target chip using frequency domain analysis technology.

[0036] Specifically, the output waveform of the target chip is collected by a high-precision sampling instrument, and the collected time domain signal is converted into a frequency domain signal through frequency domain analysis technology, so as to calculate the frequency deviation value. The signal obtained by frequency domain analysis can accurately identify the degree of frequency deviation and provide reliable data for subsequent frequency deviation calibration.

[0037] In one embodiment, if Figure 4 As shown, in step S12, the frequency deviation value of each target chip is calculated using the frequency domain analysis technology, which specifically includes: S121: Perform Fourier transform on the output waveform to convert the time domain signal in the output waveform into a frequency domain signal.

[0038] Specifically, the collected time domain signal is subjected to Fourier transform to convert the signal in the time domain into a frequency domain signal. In the frequency domain, the frequency component and amplitude of the signal will be clearly displayed, and the frequency domain signal can show the distribution of different frequencies. Through this conversion, the frequency change and offset of the output signal of the target chip can be accurately captured.

[0039] S122: Acquire the peak frequency in the frequency domain signal, compare the peak frequency with a preset standard frequency, calculate the corresponding deviation value, and obtain the frequency deviation value of the target chip.

[0040] Specifically, the main frequency component, that is, the peak frequency in the frequency domain, is identified from the frequency domain signal. This is the main frequency output by the chip. By comparing this peak frequency with the preset standard frequency, the frequency offset is calculated. The offset is the frequency deviation value of the target chip.

[0041] In one embodiment, if Figure 5 As shown, in step S20, that is, when the frequency offset value reaches the preset frequency limit range, the corresponding frequency offset calibration value is calculated based on the frequency offset value and the preset frequency correction coefficient, specifically including: S21: Multiply the frequency deviation value by a preset frequency calibration coefficient to obtain a preliminary calibration value.

[0042] Specifically, the calculated frequency deviation value is multiplied by a preset frequency calibration coefficient, which is set according to the characteristics of the chip, the working environment and the required accuracy. A preliminary calibration value is obtained through this calculation.

[0043] S22: When the preliminary calibration value is within a preset calibration range, use the preliminary calibration value as a frequency offset calibration value.

[0044] Specifically, if the calculated preliminary calibration value is within the preset calibration range, such as between the maximum frequency offset correction amount and the minimum frequency offset correction amount, the value is directly used as the frequency offset calibration value. At this time, the calibration process does not need to be further modified, the calibration operation is completed, and the calibration value can be directly transmitted to the target chip for frequency adjustment.

[0045] S23: When the preliminary calibration value is not within the preset calibration range, a secondary calibration is performed based on the preliminary calibration value to obtain a frequency offset calibration value.

[0046] Specifically, if the preliminary calibration value is not within the preset range, the secondary calibration step is entered. At this time, the preliminary calibration value is adjusted through further correction algorithms, such as proportional scaling or deviation adjustment, to ensure that the corrected calibration value meets the standard requirements. The secondary calibration is dynamically adjusted so that the final calibration value is within a reasonable range, ensuring the accuracy of the calibration process.

[0047] In one embodiment, if Figure 6 As shown, in step S30, the frequency offset calibration value is written into the corresponding target chip to perform parallel frequency offset calibration, which specifically includes: S31: Transmitting the calculated frequency offset calibration value to the corresponding target chip through parallel control.

[0048] Specifically, the frequency offset calibration value is transmitted to each target chip through a multi-channel communication interface such as SPI, I2C or parallel bus. Multiple target chips can receive their corresponding frequency offset calibration values ​​at the same time. This process is carried out in parallel, which greatly improves the transmission efficiency and ensures that the frequency offset calibration of all chips is completed in a shorter time.

[0049] S32: Adjust the frequency control module inside the target chip according to the frequency offset calibration value to complete the frequency offset calibration.

[0050] Specifically, after the target chip receives the frequency deviation calibration value, the frequency control modules inside the chip, such as VCO, PLL, etc., will adjust their frequency output according to the transmitted calibration value. Through the built-in feedback mechanism, the frequency control module can accurately adjust the output frequency to ensure that it reaches the standard frequency, thereby completing the frequency deviation calibration.

[0051] In one embodiment, if Figure 7 As shown, in step S40, the calibration degree of the target chip after the frequency offset calibration is verified to confirm whether the frequency offset value of the target chip meets the preset standard frequency, which specifically includes: S41: After the frequency offset calibration is completed, a secondary frequency offset test is performed on each target chip to collect the output waveform corresponding to the target chip.

[0052] Specifically, after the frequency deviation calibration is completed, the frequency deviation test is performed again, and the output waveform of the calibrated target chip is collected by the test equipment in the same way as the initial test to ensure that the deviation between the output signal of the target chip and the preset standard frequency is within an acceptable range, thereby further verifying the calibration result.

[0053] S42: Perform frequency domain analysis on the collected output waveform and calculate the calibrated frequency deviation value after calibration.

[0054] Specifically, the frequency domain analysis technology is used to perform spectrum analysis on the collected output waveform and calculate the calibrated frequency deviation value. By analyzing the frequency components in the frequency domain signal, the calibrated frequency offset can be accurately determined and the calibration effect can be verified.

[0055] S43: Compare the calibration frequency deviation value with the preset standard frequency. If the calibration frequency deviation value meets the preset standard frequency, trigger a calibration success message. If the calibration frequency deviation value does not meet the preset standard frequency, trigger a recalibration instruction.

[0056] Specifically, the calibrated frequency deviation value is compared with the standard frequency. If the calibrated frequency deviation value is within the preset error range, the calibration is considered successful and a success signal is sent. If the calibrated frequency deviation value exceeds the tolerance range, the recalibration instruction is triggered and the calibration process is restarted to ensure that the frequency deviation value of the target chip finally meets the standard requirements.

[0057] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0058] In one embodiment, a frequency offset calibration system based on non-signaling test is provided, and the frequency offset calibration system based on non-signaling test corresponds one-to-one with the frequency offset calibration method based on non-signaling test in the above embodiment. Figure 8 As shown, the frequency offset calibration system based on non-signaling test includes a frequency offset test module, a frequency offset analysis module, a calibration value transmission module, and a calibration verification module. The detailed description of each functional module is as follows: The frequency deviation test module is used to perform non-signaling frequency deviation tests on a plurality of target chips in parallel, thereby collecting the output waveform of the target chip and determining the frequency deviation value of the target chip according to the output waveform; A frequency deviation analysis module, used to perform deviation analysis on the frequency deviation value, and when the frequency deviation value reaches a preset frequency limit range, calculate a corresponding frequency deviation calibration value based on the frequency deviation value and a preset frequency correction coefficient; A calibration value transmission module is used to write the frequency offset calibration value into the corresponding target chip to perform parallel frequency offset calibration; The calibration verification module is used to verify the calibration of the target chip after the frequency deviation calibration, and then confirm whether the frequency deviation value of the target chip meets the preset standard frequency.

[0059] Optionally, the frequency deviation test module specifically includes: A frequency deviation test instruction submodule is used to send a frequency deviation test instruction to each target chip to start a non-signaling frequency deviation test; The waveform acquisition submodule is used to acquire the output waveform of the target chip and calculate the frequency deviation value of each target chip using frequency domain analysis technology.

[0060] Optionally, the waveform acquisition submodule specifically includes: A Fourier transform unit, used for performing Fourier transform on the output waveform, and converting the time domain signal in the output waveform into a frequency domain signal; The frequency calculation unit is used to obtain the peak frequency in the frequency domain signal, compare the peak frequency with the preset standard frequency, calculate the corresponding deviation value, and obtain the frequency deviation value of the target chip.

[0061] Optionally, the frequency deviation analysis module specifically includes: The calibration calculation submodule is used to multiply the frequency deviation value by a preset frequency correction coefficient to obtain a preliminary calibration value; A calibration range determination submodule, configured to use the preliminary calibration value as a frequency offset calibration value when the preliminary calibration value is within a preset calibration range; The secondary calibration submodule is used to perform secondary calibration based on the preliminary calibration value to obtain a frequency offset calibration value when the preliminary calibration value is not within a preset calibration range.

[0062] Optionally, the calibration value transmission module specifically includes: A calibration value transmission submodule, used for transmitting the calculated frequency offset calibration value to the corresponding target chip through parallel control; The frequency adjustment submodule is used to adjust the frequency control module inside the target chip according to the frequency offset calibration value to complete the frequency offset calibration.

[0063] Optionally, the calibration verification module specifically includes: The secondary frequency offset test submodule is used to perform a secondary frequency offset test on each target chip after the frequency offset calibration is completed, and collect the output waveform corresponding to the target chip; The frequency domain analysis submodule is used to perform frequency domain analysis on the collected output waveform and calculate the calibration frequency deviation value after calibration; The calibration verification submodule is used to compare the calibration frequency deviation value with the preset standard frequency. When the calibration frequency deviation value meets the preset standard frequency, a calibration success message is triggered. When the calibration frequency deviation value does not meet the preset standard frequency, a recalibration instruction is triggered.

[0064] For the specific limitations of the frequency offset calibration system based on non-signaling testing, please refer to the limitations of the frequency offset calibration method based on non-signaling testing in the above text, which will not be repeated here. Each module in the above-mentioned frequency offset calibration system based on non-signaling testing can be implemented in whole or in part through software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0065] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Fig. 9 As shown. The computer device includes a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a frequency deviation calibration method based on non-signaling testing is implemented.

[0066] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the following steps when executing the computer program: A non-signaling frequency deviation test is performed on several target chips in parallel, and then the output waveform of the target chip is collected, and the frequency deviation value of the target chip is determined according to the output waveform.

[0067] A deviation analysis is performed on the frequency deviation value, and when the frequency deviation value reaches a preset frequency limit range, a corresponding frequency deviation calibration value is calculated based on the frequency deviation value and a preset frequency correction coefficient.

[0068] The frequency offset calibration value is written into the corresponding target chip to perform parallel frequency offset calibration.

[0069] The calibration degree of the target chip after frequency offset calibration is verified to confirm whether the frequency offset value of the target chip meets the preset standard frequency.

[0070] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented: A non-signaling frequency deviation test is performed on several target chips in parallel, and then the output waveform of the target chip is collected, and the frequency deviation value of the target chip is determined according to the output waveform.

[0071] A deviation analysis is performed on the frequency deviation value, and when the frequency deviation value reaches a preset frequency limit range, a corresponding frequency deviation calibration value is calculated based on the frequency deviation value and a preset frequency correction coefficient.

[0072] The frequency offset calibration value is written into the corresponding target chip to perform parallel frequency offset calibration.

[0073] The calibration degree of the target chip after frequency offset calibration is verified to confirm whether the frequency offset value of the target chip meets the preset standard frequency.

[0074] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0075] Those skilled in the art will clearly understand that for the sake of convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the system can be divided into different functional units or modules to complete all or part of the functions described above.

[0076] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A frequency offset calibration method based on non-signaling test, characterized in that: The frequency offset calibration method based on non-signaling test includes: Performing non-signaling frequency deviation tests on a plurality of target chips in parallel, thereby collecting output waveforms of the target chips, and determining frequency deviation values ​​of the target chips according to the output waveforms; Performing deviation analysis on the frequency deviation value, and when the frequency deviation value reaches a preset frequency limit range, calculating a corresponding frequency deviation calibration value based on the frequency deviation value and a preset frequency correction coefficient; Writing the frequency offset calibration value into the corresponding target chip to perform parallel frequency offset calibration; The calibration degree of the target chip after the frequency offset calibration is verified to confirm whether the frequency offset value of the target chip meets the preset standard frequency.

2. The frequency offset calibration method based on non-signaling test according to claim 1, characterized in that: The performing of non-signaling frequency deviation tests on a plurality of target chips in parallel, thereby collecting output waveforms of the target chips, and determining frequency deviation values ​​of the target chips according to the output waveforms, specifically includes: Sending a frequency deviation test instruction to each of the target chips to start a non-signaling frequency deviation test; The output waveform of the target chip is collected, and the frequency deviation value of each target chip is calculated using frequency domain analysis technology.

3. The frequency offset calibration method based on non-signaling test according to claim 2, characterized in that: The step of calculating the frequency deviation value of each target chip by using the frequency domain analysis technology specifically includes: Performing Fourier transform on the output waveform to convert the time domain signal in the output waveform into a frequency domain signal; The peak frequency in the frequency domain signal is obtained, the peak frequency is compared with a preset standard frequency, a corresponding deviation value is calculated, and the frequency deviation value of the target chip is obtained.

4. The frequency offset calibration method based on non-signaling test according to claim 1, characterized in that: When the frequency offset value reaches a preset frequency limit range, calculating a corresponding frequency offset calibration value based on the frequency offset value and a preset frequency correction coefficient specifically includes: Multiplying the frequency deviation value by the preset frequency correction coefficient to obtain a preliminary calibration value; When the preliminary calibration value is within a preset calibration range, using the preliminary calibration value as the frequency offset calibration value; When the preliminary calibration value is not within the preset calibration range, a secondary calibration is performed based on the preliminary calibration value to obtain the frequency offset calibration value.

5. The frequency offset calibration method based on non-signaling test according to claim 1, characterized in that: Writing the frequency offset calibration value into the corresponding target chip to perform parallel frequency offset calibration specifically includes: Transmitting the calculated frequency offset calibration value to the corresponding target chip through parallel control; The frequency control module inside the target chip is adjusted according to the frequency offset calibration value to complete the frequency offset calibration.

6. The frequency offset calibration method based on non-signaling test according to claim 1, characterized in that: The calibration verification of the target chip after the frequency offset calibration, and then confirming whether the frequency offset value of the target chip meets the preset standard frequency, specifically includes: After the frequency offset calibration is completed, performing a secondary frequency offset test on each of the target chips, and collecting an output waveform corresponding to the target chip; Perform frequency domain analysis on the collected output waveform and calculate the calibration frequency deviation value after calibration; The calibration frequency deviation value is compared with a preset standard frequency. When the calibration frequency deviation value meets the preset standard frequency, a calibration success message is triggered. When the calibration frequency deviation value does not meet the preset standard frequency, a recalibration instruction is triggered.

7. A frequency offset calibration system based on non-signaling test, characterized in that: The frequency offset calibration system based on non-signaling test includes: A frequency deviation test module, used to perform non-signaling frequency deviation tests on a plurality of target chips in parallel, thereby collecting output waveforms of the target chips, and determining frequency deviation values ​​of the target chips according to the output waveforms; A frequency deviation analysis module, configured to perform deviation analysis on the frequency deviation value, and when the frequency deviation value reaches a preset frequency limit range, calculate a corresponding frequency deviation calibration value based on the frequency deviation value and a preset frequency correction coefficient; A calibration value transmission module, used for writing the frequency offset calibration value into the corresponding target chip to perform parallel frequency offset calibration; The calibration verification module is used to verify the calibration of the target chip after the frequency deviation calibration, and further confirm whether the frequency deviation value of the target chip meets the preset standard frequency.

8. The frequency offset calibration system based on non-signaling test according to claim 7, characterized in that: The frequency deviation test module specifically includes: A frequency deviation test instruction submodule, used to send a frequency deviation test instruction to each of the target chips to start a non-signaling frequency deviation test; The waveform acquisition submodule is used to acquire the output waveform of the target chip and calculate the frequency deviation value of each target chip using frequency domain analysis technology.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the frequency offset calibration method based on non-signaling test as described in any one of claims 1 to 6 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the frequency offset calibration method based on non-signaling test as claimed in any one of claims 1 to 6 are implemented.

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