Adaptive programmable packet scheduling system based on access strategy and algorithm thereof

Abstract

The invention discloses a self-adaptive programmable packet scheduling system based on an admission strategy and an algorithm thereof. The system comprises an enqueue logic area, a data buffer area, a dequeue logic area and an optimal filtering level R calculation area. According to the algorithm, an adjustable sliding window is designed to obtain probability distribution of latest data packet levels and adapt to different data packet level distribution conditions; a real-time delay measurement mechanism based on a timestamp is designed and is used for accurately calculating the waiting time of the data packet in the queue so as to reduce the waiting time of the data packet; a factor of considering a lower-level calculation unit in real time is added in the calculation of the optimal filtering level R, so that the arrival time and the priority of a future data packet can be predicted more accurately, and the calculation of the R is optimized; and fourthly, re-consideration of discarded data packets is added. Under the condition that the queue is full, the algorithm reevaluates and processes the discarded data packets.

Description

Technical Field

[0001] The present invention relates to the technical field of programmable network equipment, in particular to an admission strategy-based adaptive programmable packet scheduling system and an algorithm thereof. Background Art

[0002] As an emerging programmable network device, Smart NICs have attracted much attention in the fields of data centers and scientific computing, and have become a key technology for solving network bottleneck problems. FPGA Smart NICs play an important role in network protocol processing offload, network function virtualization, and specific application acceleration due to their excellent performance. In recent years, with the growing demand for multi-tenant networks in data centers, the offload function of Smart NICs is becoming more complex. In this context, efficient multi-tenant load isolation mechanisms have become a hot topic in academic research on Smart NICs, and programmable packet scheduling algorithms play an important role in this.

[0003] The programmable packet scheduling algorithm is an innovative way of thinking that has emerged with the emergence of programmable switches. Because of its scheduling flexibility, it has received attention in the load balancing design of FPGA smart network cards. It can express the results of different scheduling strategies or scheduling algorithms without frequently modifying the original hardware structure of the switch.

[0004] For example, both PANIC and Menshen designs use PIFO for hierarchical allocation. This allocation method is built on the bandwidth sharing strategy, which provides performance guarantees for multi-tenant isolation strategies. PIFO was chosen because of its excellent performance and mature PIFO tree design. However, the hardware consumption of the PIFO tree is very high, and in the FPGA smart network card architecture, hardware resources are limited. The hardware consumption of PIFO will greatly restrict the scalability of this architecture. Therefore, how to reduce the hardware consumption of PIFO while ensuring performance will be an important issue that the industry needs to solve in future work.

[0005] In the prior art, there are several other programmable packet scheduling algorithms with excellent performance and application in hardware, but they also have problems such as complex algorithm structure or excessive consumption of some hardware resources. When they are applied to the specific FPGA smart network card design, they will restrict the scalability of the modular design of the entire network card structure. These common hardware-level programmable packet scheduling algorithms are often designed for programmable switches. When these algorithms are incorporated into the design of FPGA smart network cards, they may not be able to achieve seamless integration with the entire architecture, which will affect the overall performance and efficiency of the smart network card. Summary of the invention

[0006] The purpose of the present invention is to provide an adaptive programmable packet scheduling system and its algorithm based on admission strategy, which collects the cumulative distribution function of the data packet level ID by maintaining a hardware sliding window, and determines the basic FIFO admission parameters based on this, and introduces a timestamp-based congestion control mechanism and a flexible scheduling mechanism based on the needs of the subsequent stage to achieve dynamic adjustment of the admission parameters.

[0007] In order to achieve the above object, the technical solution of the present invention is:

[0008] An adaptive programmable packet scheduling system based on admission policy, comprising:

[0009] Enqueue logic area, including

[0010] Analysis module, receiving data packets and analyzing the data rank of the data packets, performing enqueue(d) operation, pushing data packets that meet the filter rank R into Main_FIFO, and pushing data packets that do not meet the filter rank R into Rethink_FIFO; and

[0011] The timestamp generation module generates an input timestamp when enqueue(d) is idle and adds it to the rank feature of the data packet in Main_FIFO through the enqueue(t) operation; and transmits the data rank to the optimal filtering rank R calculation area.

[0012] Data buffer, including:

[0013] Main_FIFO, receives and stores data packets whose rank is less than filter level R, i.e., whose priority is higher than filter level R; and

[0014] Rethink_FIFO, receives and stores data packets that do not meet the filter level R;

[0015] Dequeue logic area, including:

[0016] A polling module, which schedules the output of data packets in the data buffer according to the polling deficit; and

[0017] An output data module that buffers the data packets and then delivers them to the lower level units in the order in which they leave the buffer; and

[0018] The output timestamp module retrieves the output timestamp from the output data and sends the output timestamp to the calculation area of ​​the optimal filtering level R for delay matching correction;

[0019] The optimal filtration level R calculation area includes:

[0020] A cumulative distribution probability module performs statistical analysis on the level characteristics of scheduled data packets and generates a probability distribution data pool to represent the proportion of different level data packets in the total data packets; and

[0021] A real-time capacity detection module receives capacity feedback from a subsequent computing unit; and

[0022] The delay calculation module calculates the output delay based on two consecutive output timestamps.

[0023] The filter level R correction module corrects the filter level R and transmits the corrected value of the filter level R to the queue entry logic area.

[0024] As an improvement to the above technical solution, the access policy-based adaptive programmable packet scheduling system also includes a RAM module to store the data value of the data packet, and when the polling output module delivers an address, the RAM module reads the data at the corresponding position according to the address and sends it to the next level.

[0025] As an improvement to the above technical solution, the data buffer further includes a first-level FIFO to store data ranks and address information for writing data into the RAM; the dequeuing logic area further includes a second-level FIFO to buffer output data packets.

[0026] As an improvement to the above technical solution, the operation of enqueue(d) is to first push the data packets that meet the optimal filtering level R into Main_FIFO, and then push the data packets that do not meet the requirements into Rethink_FIFO; enqueue(t): and the operation are fixed time intervals, and the timestamp is inserted into Main_FIFO.

[0027] As an improvement to the above technical solution, the dequeue(d) operation is when the polling algorithm opens Main_FIFO or Rethink_FIFO according to the set polling deficit, dequeue(d) outputs high priority data from Main_FIFO, or outputs low priority data from Rethink_FIFO when it is full and there is a data packet; the dequeue(t) operation is when it is detected that the current output position in Main_FIFO is a timestamp signal, this operation sends the timestamp signal to the delay calculation module, so as to avoid sending an empty signal to the buffer of the calculation unit.

[0028] As an improvement to the above technical solution, the drop(d) operation is performed when Rethink_FIFO is full and a data packet needs to enter Rethink_FIFO, in which case the data packet will be discarded, so that the discard operation is performed during the enqueue decision of Main_FIFO.

[0029] As an improvement to the above technical solution, the execution of the enqueue(t) operation needs to be performed in the idle clock interval of enqueue(d).

[0030] As an improvement to the above technical solution, the steps of processing data packets by the adaptive programmable packet scheduling system based on admission policy and its algorithm are as follows:

[0031] S1. Data buffer sets the current occupied space size of Main_FIFO to c, and the total depth of Main_FIFO to C; sets the maximum delay ΔT of scheduling, defining the maximum acceptable delay of a data packet from being pushed into scheduling to being output;

[0032] S2. When enqueue(d) is idle, the Analysis module analyzes the data rank of the new data packet, and the timestamp generation module generates two input timestamps t 1 and t 2 , input timestamp t 1 and t 2 Assign it to the level characteristics of the new incoming data packet to form a new level characteristic and a new scheduling window; the data buffer performs the enqueue(t) operation, and the dequeue logic area obtains the departure time T of the new incoming data packet when it is output 1 and T 2 , the optimal filtering level R calculation area calculates the CDF function value of the new level feature and optimizes the R value;

[0033]

[0034] φ represents the inversion of the CDF function; CDF.rank.pkt represents the CDF function value under the new rank feature; the correction parameter Unit.pkt is a constant between 0 and 1, indicating that a computing unit will refuse to accept data packets when it is close to saturation;

[0035] S3. Repeat step S3 to obtain the optimal R.

[0036] As an improvement to the above technical solution, t 1 -t 2 =ΔT.

[0037] As an improvement to the above technical solution, in step S3, the new scheduling window also includes a Tetris window. The Tetris window refers to when the accumulated data of each rank is converted into a binary number, the rank buffer is regarded as a matrix, and the matrix behavior is the binary bits of the accumulated number of ranks, which are listed as rank labels. Every time when all ranks are valid in the same bit position, that is, 1, all the accumulated values ​​of the ranks are subtracted by 1, or the decimal number corresponding to the current bit position is subtracted.

[0038] Compared with the prior art, the present invention has the following advantages and positive effects:

[0039] One is to introduce a dynamically updateable hardware-level sliding window to obtain the probability distribution of recent packet levels.

[0040] The second is to add time tags, based on the real-time delay measurement mechanism of timestamps, dynamically retrieve the congestion status of the scheduling buffer, accurately calculate the waiting time of data packets in the queue, and dynamically retrieve the congestion status of the scheduling buffer.

[0041] Thirdly, combining programmable packet scheduling with the actual application scenarios of smart network cards, the unloading module capacity is introduced as another reference coefficient for the admission predicate calculation to obtain a faster and more reasonable queue entry logic; the factor of real-time consideration of the lower-level computing units is added to the calculation of the optimal filtering level R. By monitoring the real-time status of the lower-level computing units, the arrival time and priority of future data packets can be more accurately predicted; when the queue is full, the newly arrived data packets are re-evaluated and processed.

[0042] The present invention can more flexibly adapt to the data packet scheduling requirements under different workload conditions, and improve the processing efficiency of the data packet and the overall performance of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0044] Figure 1 A framework diagram of AWAIFO scheduling of the present invention;

[0045] Figure 2 Schematic diagram showing the impact of computing unit capacity on scheduling results;

[0046] Figure 3 This is a schematic diagram of the steps of Algorithm 3-1;

[0047] Figure 4 It is a schematic diagram of the system composition of the present invention;

[0048] Figure 5 This is a working example diagram of the Teris sliding window of the present invention;

[0049] Figure 6 This is a comparison chart of the real CDF and the CDF designed using “Teris” in the example of the present invention. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0051] like Figure 1 and 4 As shown, the framework of the AWAIFO (admission policy-based adaptive programmable packet scheduling system and algorithm thereof) of the present invention mainly includes an entry logic area, a data buffer area, a dequeue logic area and an optimal filtering level R calculation area.

[0052] 1. Basic Operations of AWAIFO Primitive

[0053] In order to achieve the corresponding logical abstraction, AWAIFO supports five basic operations: enqueue(d), enqueue(t), dequeue(d), dequeue(t) and drop(d).

[0054] 1. enqueue(d): This operation mainly includes two tasks. The first is to push the data packets that meet the optimal filtering level R into the Main_FIFO, and the second is to push the data packets that do not meet the requirements into the Rethink_FIFO.

[0055] 2. enqueue(t): This operation inserts timestamps into Main_FIFO at fixed time intervals.

[0056] 3. dequeue(d): When the polling algorithm opens the Main_FIFO or Rethink_FIFO according to the set polling deficit, dequeue(d) outputs high-priority data from the Main_FIFO, or outputs low-priority data from the Rethink_FIFO when it is full and has data packets.

[0057] 4. dequeue(t): When it is detected that the current output position in Main_FIFO is a timestamp signal, this operation sends the timestamp signal to the delay calculation module to avoid sending an empty signal to the buffer of the calculation unit.

[0058] 5. drop(d): When Rethink_FIFO is full and there is a packet that needs to enter Rethink_FIFO, the packet will be dropped. AWAIFO also allows you to close Rethink_FIFO so that the drop operation is performed during the enqueue decision of Main_FIFO.

[0059] enqueue(d) and dequeue(d) inherit some of the primitives of AIFO scheduling. enqueue(t) and dequeue(t) operations are the key to AWAIFO's "adaptive" implementation.

[0060] (I) Enqueue Logic Area

[0061] Figure 1 and 4 The enqueue logic area in contains two sub-modules, namely the Analysis module and the timestamp generation module.

[0062] The Analysis module uses a first-level FIFO as a buffer to receive data packets. These data packets are sent to the logic component that performs the enqueue(d) operation in the order in which they are received. At the same time, the level features carried by the data packets are also extracted and sent to the optimal filter level R calculation area for evaluation. In this way, the Analysis module ensures that the data packets are enqueued in the order in which they are received, and provides a basis for subsequent filter level evaluation. The timestamp generation module is responsible for generating an identification signal within a fixed time period and sending it to the Main_FIFO through the enqueue(t) operation. In order to ensure that the insertion of the timestamp does not affect the data packet, the execution of the enqueue(t) operation needs to be performed in the idle clock interval of enqueue(d). This design can avoid problems such as queue scheduling confusion or data packet loss caused by the insertion of the timestamp.

[0063] Through the collaborative work of the Analysis module and the timestamp generation module, the enqueue logic area can effectively process and schedule data packets while ensuring the accurate insertion of timestamps, thus providing important support for the normal operation of the entire system.

[0064] (II) Data Buffer

[0065] Figure 1 and 4 The data buffer in the system contains three FIFO components, namely, the primary FIFO, Main_FIFO and Rethink_FIFO. These three components have their own characteristics in function and play an important role in the whole system.

[0066] The first-level FIFO is used to store the data rank and the address information of the data written into the RAM, which is the buffer of the Analysis module to receive data packets. These data packets are sent to the logic component that performs the enqueue (d) operation in the order in which they are received.

[0067] In the enqueue logic, Main_FIFO is responsible for receiving data packets and timestamp signals with a level less than R (i.e., a priority higher than R). These data packets and signals will be pushed into Main_FIFO and arranged according to the first-in-first-out principle. Rethink_FIFO is used to store data packets that do not meet the filtering level. Its enqueue and dequeue order strictly follows the scheduling logic of FIFO, i.e., first-in-first-out. When Rethink_FIFO reaches a full state, any data packet that attempts to enter Rethink_FIFO will be discarded. This is the only data discard operation in the entire module. This design ensures that the filtering level of the data packet is effectively controlled and prevents overflow problems caused by a full queue.

[0068] By combining the first-level FIFO, Main_FIFO and Rethink_FIFO, the data buffer can effectively process and schedule packets of different levels and perform reasonable discard operations based on priority, thus ensuring the stability and efficiency of the entire system. In the case of strict buffer resource requirements, the AWAIFO algorithm allows the Rethink_FIFO component to be eliminated.

[0069] (III) Departure Logic Area

[0070] like Figure 1 and 4 As shown, the dequeue logic area covers four sub-modules, namely the polling module, the output data module, the secondary FIFO and the output timestamp module.

[0071] The polling module is responsible for deciding which FIFO is enabled for the current output based on the preset polling deficit. The data output module uses a secondary FIFO as a buffer to buffer the data packets, and then sends them to the lower-level computing units in the order in which the data packets leave the buffer. This order ensures the continuity and integrity of the data during transmission. The timestamp output module focuses on the extraction and transmission of timestamp signals. From the output data, this module can retrieve the timestamp signals and send them to the optimal filtering level R calculation area for delay matching correction, which will play a key role in R optimization.

[0072] Through the collaborative work of these four sub-modules, the dequeue logic area can effectively process and send data while ensuring the accuracy and real-time nature of the data.

[0073] (IV) Optimal filtration level R calculation area

[0074] The optimal filtering level R calculation area is the most important part of the whole design, which ensures the adaptive performance of the AWAIFO algorithm.

[0075] The main function of the cumulative distribution probability module is to count the level characteristics of the data packets that enter the scheduling within a period of time. It analyzes the characteristics of the data packets and generates a probability distribution data pool to represent the proportion of data packets of different levels in the total data packets. The real-time capacity detection module receives capacity feedback from the subsequent computing unit. It evaluates the capacity of the subsequent computing unit based on real-time feedback information in order to make corresponding adjustments to the scheduling of data packets. The delay calculation module calculates the output delay based on two consecutive output timestamps. It can determine the current congestion in Main_FIFO by comparing two consecutive output timestamps with the input timestamp. When the delay is large, it means that there may be congestion in Main_FIFO and corresponding processing is required. The main function of the filter level R correction module is to correct the filter level R and transmit the correction value of the filter level R to the queue entry logic area.

[0076] Among the above four modules, the cumulative distribution probability module is the basis, which provides statistical information of the packet level characteristics. The real-time capacity detection module and the delay calculation module evaluate the congestion in Main_FIFO based on these statistical information, and the filter level R correction module optimizes the scheduling of data packets. When the scheduling starts, the method can first obtain a rough R value through the cumulative distribution probability module. Then, the real-time capacity detection module, the delay calculation module, and the filter level R correction module optimize this R value to obtain the optimal filter level R. This optimal R value can effectively guide the scheduling of data packets, reduce the congestion in Main_FIFO, and improve the overall performance of the system.

[0077] 2. AWAIFO Algorithm Detailed Description

[0078] like Figure 3 As shown in Algorithm 3-1, the pseudo code describes the algorithm framework of AWAIFO by dividing it into two functional areas, namely the entry area (ENQUEUE) and the exit area (DE-QUEUE).

[0079] (I) ENQUEUE Function Area

[0080] Lines 1 to 15 in Algorithm 3-1 are the ENQUEUE functional area.

[0081] In lines 2 and 3, the control method gets the size of the buffer, where c represents the current queue length and C is the effective depth of the buffer set by the scheduler. This means that c represents the size of the space currently occupied by Main_FIFO, and C represents the total depth of Main_FIFO.

[0082] In line 4, the maximum delay ΔT for scheduling is set. This is a key parameter that defines the maximum acceptable delay for a packet from being pushed into scheduling to being output. In practical applications, the value of ΔT is closely related to FCT to ensure that the impact of low-level flows or elephant flows that occasionally enter the Main_FIFO on FCT remains within a controllable range. If this delay is exceeded, the corresponding elephant flow data will be buffered in Rethink_FIFO for processing. From lines 5 to 7, the timestamp generation module inserts timestamps in Main_FIFO based on the above-set ΔT as a fixed time interval. This helps track the entry and exit times of data packets to ensure correct processing and scheduling.

[0083] In line 8, the scheduled sliding window receives the level parameters of the new packet to update the corresponding CDF value. Regardless of whether the data packet is "admission" or "dropped", the sliding window will receive the corresponding level parameters. Line 9 is the most important part of the entire AWAIFO algorithm framework design and is the prerequisite for scheduling decision-making. The algorithm inverts the CDF function near the corresponding point through the fusion value of the spatial margin ratio and delay information to obtain an optimal R, and uses the capacity margin of each unloading unit to accurately correct the corresponding data flow or data packet.

[0084] Finally, lines 10 to 15 perform "admission" or "drop" according to the R value obtained above.

[0085] (II) DEQUEUE Function Area

[0086] Lines 16 to 24 in Algorithm 3-1 are the ENQUEUE functional area.

[0087] Lines 17 to 18 are the timestamps output at the egress. The time difference of the output timestamp will be compared with the ΔT when the timestamp was inserted in the EN-QUEUE function area to correct the R value. Lines 19 to 24 are the output logic part. By default, data packets are output from Main_FIFO first, and when Main_FIFO is empty, the scheduler starts to consider Rethink_FIFO. The data packets in Rethink_FIFO are processed according to the time sequence of their insertion into FIFO, and their packet level is no longer considered. In the polling module, Main_FIFO and Rethink_FIFO can be weighted and given different token information, but excessive consideration of Rethink_FIFO on scheduling performance when Main_FIFO is not empty will be disastrous.

[0088] (III) Detailed description of algorithm access strategy

[0089] In the AIFO algorithm, the method for obtaining the admission threshold is shown in Formula 3-1. Among them, c and C have the same meaning in this method. In the AIFO algorithm, the difference between the arrival rate and the departure rate is mainly detected by whether the queue is idle or not, and then the aggressiveness of the entry is determined. When Cc is smaller, the entry strategy is more aggressive. However, when Cc is extremely small, the buffer's ability to cope with burst flow will become extremely weak, so the parameter k is included to tolerate small bursts. The k value is determined to be a number between 0 and 1. When k approaches 1, the FCT performance of AIFO is close to FIFO. On the contrary, when k approaches 0, the FCT performance of AIFO is close to PIFO.

[0090]

[0091] The method for obtaining the admission threshold in AWAIFO of this method is shown in formula 3-2, where Partially similar to AIFO, the size of the buffer determines the basic entry threshold. In, t 1 -t 2 This is the maximum tolerable delay set by the designer at the beginning. When an intolerable scheduling delay occurs, the control method will discard the data packet with the lowest level in Main_FIFO, and the R value will be further reduced (the level requirement is increased), and so on. Unit.pkt indicates that a computing unit refuses to accept data packets when it is close to saturation. The AWAIFO primitive allows Unit.pkt to be quantized as a constant between 0 and 1, which is given by the control method based on the feedback value of the capacity of the next level computing unit of the current scheduler. A quantized value close to 0 indicates that the computing unit is close to saturation, and the corresponding data packet demand is small. A quantized value close to 1 indicates that the computing unit is close to empty, and the corresponding data packet demand increases.

[0092] Adding calculation unit correction parameters has the following impact on scheduling: Figure 2 As shown. Even if the data packet has a high priority, once the corresponding offload computing unit has reached saturation, the method of using buffer size as the main scheduling basis will still include the data packet in the FIFO. However, when the data packet is taken out from the FIFO head, the target offload computing unit may no longer be able to receive it, causing the data packet to be discarded or waiting for processing, wasting precious processing resources. Correspondingly, if the stored data packet has a low priority, even if the corresponding offload computing unit has reached clearance, the method of using buffer size as the main scheduling basis will still not include the data packet in the FIFO. The addition of the correction parameter Unit.pkt enables AWAIFO to have the ability to reasonably handle such scheduling.

[0093] In summary, unlike AIFO, which uses a single parameter k to rigidly improve the ability to respond to emergencies, AWAIFO will automatically adjust the processing delivery of emergencies and the current scheduling state of the scheduler. Therefore, compared with AIFO, AWAIFO has a more proactive packet management capability.

[0094] Of course, when the dynamic window frequently collects the ranks of data packets to calculate the CDF, and does not perform any processing under a fixed hardware resource, buffer overflow will be inevitable, which will make the CDF value in the sliding window no longer have reference value. In order to deal with the above problems and save the resource consumption of the sliding window for the buffer, the present invention proposes a Tetris sliding window. In the Tetris sliding window, when the cumulative data of each rank is converted into a binary number, the rank buffer can be regarded as a matrix, and the matrix lines are the binary bits of the cumulative number of ranks, which are listed as rank labels. Every time when all ranks are valid in the same bit position, that is, "1", all the cumulative values ​​of the ranks can be subtracted by 1, or the decimal number corresponding to the current bit position can be subtracted.

[0095] Tetri s There are two elimination strategies for sliding windows: one is to directly eliminate the corresponding bit, and the other is to reduce the cumulative value of all ranks by 1. Figure 5The first elimination strategy is mainly demonstrated. This sliding window has the ability to perform hierarchical collection of 8 different levels of data packets or data flows, and its collection depth reaches 256. Assume that after the scheduler has buffered the number of data packet level parameters shown in Formula 3-3, it first receives a data packet with a rank of 5, and then receives three rank 3 data packets in succession. When the level information of these data packets is added to the sliding window, the matrix will be transposed. After the transposition, the system will detect that two rows have been filled, which are the rows where bit1 and bit3 are located. According to the design principle of Tetris, once a row is filled, the control plane will clear the row. Therefore, in this example, the control plane will perform a clearing operation on the rows where bit1 and bit3 are located in the sliding window buffer, thereby completing a data packet level collection and processing process. This mechanism enables Tetris to efficiently process data packet flows of different levels, ensuring the stability and efficient operation of the network.

[0096] {r 1 , r 2 , r 3 ,r 4 ,r 5 , r 6 , r 7 , r 8} = {171,206,55,10,169,156,10} (3-3)

[0097] Figure 6 The comparison between the CDF value generated by the etris design and the real CDF is given, where (a) is the comparison when the row where bit1 is located is eliminated, and (b) is the comparison when the row where bit3 is located is eliminated. The average difference between the probability of Tetris elimination and the real one is less than 0.32%. When the depth of Main_FIFO is 256, this difference will cause an impact of 0.82 depths, which can be basically ignored in actual engineering.

[0098] Impact Analysis of Tetris Design

[0099] The above example fully explains Tetr is Here, we will generalize the Tetris design in principle and explain its different effects on data flows at various levels.

[0100] Assume that the current cumulative value of a Tetris design is as shown in Formula 3-4. At this time, any k-th data level r k The CDF calculation is shown in formula 3-5

[0101] {r 1 , r2 , r 3 ,…,r n}={α 1 , α 1 , α 1 , …, α n} (3-4)

[0102]

[0103] If there exists j such that the jth bit of each level r is 1, the bitj row in the sliding window is full. Therefore, the corresponding row elimination can be performed, and the cumulative value updated in the Tetris design is shown in Formula 3-6. At this time, any kth data level r k The CDF calculation is shown in Formula 3-7.

[0104] {r 1 , r 2 r 3 , ..., r n}={α 1 -2 j , α 1 -2 j , α 1 -2 j , ..., α n -2 j} (3-6)

[0105]

[0106] make Then any k-th data level r k The true CDF value P corresponding to the data Real and the CDF value P in Tetris design Tetris1 , as shown in Equations 3-8 and 3-9.

[0107]

[0108] Define a parameter n that is closer to 1 to measure P Real and P Tetrisl The difference between. Let η = P Real / P Tetris , then any k-th data level r k The data, P Real and P Tetrisl The corresponding η k for:

[0109]

[0110] In this design requirement, we hope that PReal and P Tetris1 The difference between them is smaller, that is, the value of n is closer to 1. When η is less than 1, it means that the CDF value designed by Tetris is too large; when η is greater than 1, it means that the CDF value designed by Tetris is too small; when η is equal to 1, it means that the CDF value designed by Tetris is the same as the true value.

[0111] The following will analyze the impact of Tetris design on the scheduling of higher-level data packets from four aspects.

[0112] 1. r k The number of high-level packets is large: At this time, the most referenced packet level distribution follows the Pareto distribution. In this case, the corresponding j must be a very small integer, so the result shown in formula 3-11 can be obtained. Therefore, η at this time k is necessarily a number close to 1, and the effect of Tetris design on CDF can be ignored. k When it is a higher level packet, Equation 3-12 always holds true. In the Tetris design, the CDF value of higher level packets is larger, while the CDF value of lower level packets is smaller. In short, the subtle impact of this design on CDF leads to the behavioral tendency of the scheduler when processing packets of different levels: for higher level packets, the scheduler shows a more active scheduling attitude; while for lower level packets, the scheduler adopts a relatively conservative or passive scheduling strategy. This influence has a positive impact on the scheduler itself.

[0113] α k β>>n2 j α k , α k β>>2 j β (3-11)

[0114] n αk <<β (3-12)

[0115] 2. r kThe data packets are high-level packets and the number is small: In this case, the data level distribution shows the left half of the normal distribution. At this time, the impact of Tetris design on the CDF of the two data packets is shown in Formula 3-12, that is, the scheduler will be more active in scheduling low-level data packets. This phenomenon causes the optimal admission level R to be significantly higher, so that some data packets with too low levels have the opportunity to enter the Main_FIFO. These low-level data packets may have a negative impact on scheduling, increase latency and reduce overall network performance. The advantages of timestamp detection scheduling delay will be apparent In this case, the advantages of introducing timestamp detection scheduling delay will be apparent. By real-time detection of the enqueue time and processing time of the data packet, it is possible to accurately determine whether there is a delay caused by low-level data packets. Once the delay is detected, the control plane can quickly remove these low-level data packets from the Main_FIFO, thereby optimizing the scheduling process and improving overall network performance.

[0116] 3. r k For high-level data packets, and the number obeys uniform distribution or any irregular distribution: Obviously, ηα in formula 3-10 k and β determine η k The relationship between the value of and 1. First, for uniform distribution, Equation 3-13 is always true, that is, Equation 3-14 is always true, which means that for any data packet that obeys uniform distribution, its P Real and P Tetrisl are always equal, and the Tetris design does not affect its CDF.

[0117] nα k =β (3-13)

[0118]

[0119] 4. For irregular distribution, if ηαk is greater than the statistical mean, that is, Equation 3-15 holds, then ηk is always greater than 0, otherwise ηk is always less than 0. Therefore, at this time, Tetris design will increase the CDF of a large number of data packets and reduce the CDF of a small number of data packets. The impact on high-level data packets will be the same as when "r is a high-level data packet and the number is small".

[0120]

[0121] Observing the above three situations, in order to minimize the interference of Tetris design on CDF, the sliding window starts the row elimination in Tetris design when the total buffer amount is greater than 1 / 3 of the buffer size, that is, when β is greater than 1 / 3 of the buffer space.

[0122] In summary, AWAIFO collects the cumulative distribution function of the packet level ID by maintaining a hardware sliding window, and determines the basic FIFO admission parameters based on this. At the same time, the algorithm introduces a timestamp-based congestion control mechanism to achieve dynamic adjustment of admission parameters. In terms of enqueuing strategy, AWAIFO fully considers the capacity of the computing unit and can flexibly choose to accept or reject the data packets corresponding to a specific computing unit in the enqueuing decision, making it more suitable for the actual scheduling scenarios of smart network cards.

[0123] Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in the field without making any creative work, any modifications, equivalent substitutions, improvements, etc. made should be included in the protection scope of the present invention.

Claims

1. An adaptive programmable packet scheduling system based on admission policy, comprising: Enqueue logic area, including Analysis module, receiving data packets and analyzing the data rank of the data packets, performing enqueue(d) operation, pushing data packets that meet the filter rank R into Main_FIFO, and pushing data packets that do not meet the filter rank R into Rethink_FIFO; and The timestamp generation module generates input timestamps and adds them to the level characteristics of the data packets in Main_FIFO through enqueue(t) operation when enqueue(d) is idle; And the data level rank is transmitted to the optimal filtering level R calculation area Data buffer, including: Main_FIFO, receives and stores data packets whose rank is less than filter level R, i.e., whose priority is higher than filter level R; and Rethink_FIFO, receives and stores data packets that do not meet the filter level R; Dequeue logic area, including: A polling module, which schedules the output of data packets in the data buffer according to the polling deficit; and An output data module that buffers the data packets and then delivers them to the lower level units in the order in which they leave the buffer; and The output timestamp module retrieves the output timestamp from the output data and sends the output timestamp to the calculation area of ​​the optimal filtering level R for delay matching correction; The optimal filtration level R calculation area includes: A cumulative distribution probability module performs statistical analysis on the level characteristics of scheduled data packets and generates a probability distribution data pool to represent the proportion of different level data packets in the total data packets; and A real-time capacity detection module receives capacity feedback from a subsequent computing unit; and The delay calculation module calculates the output delay based on two consecutive output timestamps; The filter level R correction module corrects the filter level R and transmits the corrected value of the filter level R to the queue entry logic area.

2. The adaptive programmable packet scheduling system according to claim 1, characterized in that: The adaptive programmable packet scheduling system based on admission policy also includes a RAM module to store the data value of the data packet, and when the polling output module delivers an address, the RAM module reads the data at the corresponding position according to the address and sends it to the next level.

3. The adaptive programmable packet scheduling system according to claim 2, characterized in that: The data buffer also includes a first-level FIFO to store data ranks and address information for writing data into the RAM module; the dequeuing logic area also includes a second-level FIFO to buffer output data packets.

4. An algorithm based on the adaptive programmable packet scheduling system as claimed in claims 1 to 3, characterized in that: The algorithm processes the data packet in the following steps: S1. Data buffer sets the current occupied space size of Main_FIFO to c, and the total depth of Main_FIFO to C; sets the maximum delay ΔT of scheduling, defining the maximum acceptable delay of a data packet from being pushed into scheduling to being output; S2. When enqueue(d) is idle, the Analysis module analyzes the data rank of the new data packet, and the timestamp generation module generates two input timestamps t1 and t2, and adds the input timestamps t1 and t2 to the rank feature of the new data packet to form a new rank feature and a new scheduling window; the data buffer performs the enqueue(t) operation, the dequeue logic area obtains the departure time T1 and T2 of the new data packet when it is output, and the optimal filtering level R calculation area calculates the CDF function value of the new rank feature and optimizes the R value; φ represents the inversion of the CDF function; CDF.rank.pkt represents the CDF function value under the new rank feature; the correction parameter Unit.pkt is a constant between 0 and 1, indicating that a computing unit will refuse to accept data packets when it is close to saturation; S3. Repeat step S3 to obtain the optimal R.

5. The algorithm according to claim 4, characterized in that: t1-t2=ΔT.

6. The algorithm according to claim 4, characterized in that: In step S3, the new scheduling window also includes a Tetris window. The Tetris window means that when the accumulated data of each rank is converted into a binary number, the rank buffer is regarded as a matrix, and the matrix rows are the binary bits of the accumulated rank numbers, which are listed as rank labels; each time when all ranks are valid at the same bit position, that is, 1, all the accumulated values ​​of the ranks are subtracted by 1, or the decimal number corresponding to the current bit position is subtracted.

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