Manufacturing method of semiconductor structure

Abstract

The embodiment of the invention discloses a manufacturing method of a semiconductor structure. The manufacturing method comprises the steps of providing a substrate structure; wherein the substrate structure comprises a plurality of bit line isolation structures; a groove is formed between every two adjacent bit line isolation structures; executing a first thin film deposition process, and forming a first dielectric layer in the groove; executing a second thin film deposition process to form a second dielectric layer covering the bit line isolation structure and the first dielectric layer; wherein the film coverage rate of the first film deposition process is greater than that of the second film deposition process.

Description

Technical Field

[0001] The disclosed embodiments relate to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor structure. Background Art

[0002] A storage unit of a dynamic random access memory (DRAM) includes a transistor and a capacitor, wherein a gate of the transistor is connected to a word line, a drain is connected to a bit line, and a source is connected to a capacitor.

[0003] As the integration of DRAM increases, the feature size of DRAM becomes smaller and smaller, which makes DRAM manufacturing more difficult and the performance needs to be further improved. Summary of the invention

[0004] The present disclosure provides a method for manufacturing a semiconductor structure, including:

[0005] Providing a substrate structure; wherein the substrate structure includes a plurality of bit line isolation structures; a trench is formed between two adjacent bit line isolation structures;

[0006] performing a first thin film deposition process to form a first dielectric layer in the trench;

[0007] A second thin film deposition process is performed to form a second dielectric layer covering the bit line isolation structure and the first dielectric layer; wherein the film coverage of the first thin film deposition process is greater than the film coverage of the second thin film deposition process.

[0008] In some embodiments, the surface of the first dielectric layer away from the base structure has a first recess; the manufacturing method further includes:

[0009] A portion of the first dielectric layer exposed by the first recess is removed by etching, and a second recess is formed on a surface of the first dielectric layer away from the substrate structure; wherein a bottom opening size of the second recess is larger than a bottom opening size of the first recess.

[0010] In some embodiments, a top opening size of the second recess is larger than a top opening size of the first recess.

[0011] In some embodiments, the forming of a second dielectric layer covering the bit line isolation structure and the first dielectric layer includes:

[0012] The second dielectric layer is formed in the second recess.

[0013] In some embodiments, the first dielectric layer has a greater density than the second dielectric layer.

[0014] In some embodiments, the substrate structure further includes a plurality of active regions and a bit line structure located above the active regions; wherein the bit line structure is connected to the active regions; and the bit line isolation structure covers the active regions, the sidewalls and the top of the bit line structure;

[0015] The production method further comprises:

[0016] Etching the second dielectric layer until the bit line isolation structure is exposed;

[0017] Forming a mask structure having a mask pattern on the bit line isolation structure; wherein the mask pattern is located above a preset formation position of a capacitor contact;

[0018] Etching the first dielectric layer according to the mask pattern to form a contact hole; wherein the bottom of the contact hole exposes the active area;

[0019] The capacitor contact is formed in the contact hole.

[0020] In some embodiments, the mask pattern includes a self-aligned double exposure mask pattern or a self-aligned quadruple exposure mask pattern.

[0021] In some embodiments, the first thin film deposition process includes: an atomic layer deposition process; the second thin film deposition process includes: a spin coating process.

[0022] In some embodiments, the atomic layer deposition process includes: catalytic atomic layer deposition or plasma atomic layer deposition.

[0023] In some embodiments, the reaction temperature of the atomic layer deposition process is less than 100°C.

[0024] In the embodiment of the present disclosure, a first dielectric layer is formed in the groove by performing a first thin film deposition process; then a second thin film deposition process is performed to form a second dielectric layer covering the bit line isolation structure and the first dielectric layer; since the film coverage of the first thin film deposition process is greater than the film coverage of the second thin film deposition process, the first dielectric layer can fill the groove, which is beneficial for the subsequent removal of the first dielectric layer more completely, reducing the residual impurities in the groove, avoiding failure of the semiconductor device, and improving the yield of the semiconductor device; and the manufacturing method provided in the embodiment of the present disclosure has a simple process, which is beneficial to reducing the difficulty of manufacturing semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1A A schematic top view of a semiconductor structure is shown as an exemplary embodiment;

[0026] Figures 1B to 1MA schematic diagram of a manufacturing process of a semiconductor structure is shown as an exemplary embodiment;

[0027] Figure 2 A flowchart of a method for manufacturing a semiconductor structure shown in an embodiment of the present disclosure;

[0028] FIG. 3A to FIG. 3N A schematic diagram of a manufacturing process of a semiconductor structure shown in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0030] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0031] It will be understood that the meaning of “on,” “over,” and “over” of the present disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0032] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0033] In the disclosed embodiments, the term "layer" refers to a material portion including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0034] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0035] Figure 1A FIG. 1 is a schematic top view of a semiconductor structure 100 according to an exemplary embodiment. Figure 1A As shown, the semiconductor structure 100 can be divided into an array area 100a and a peripheral area 100b; the semiconductor structure 100 includes a substrate 101, a plurality of word lines 103 and a plurality of bit lines 104; a plurality of active areas 102 are formed in the substrate 101, and the active areas 102 are located in the array area 100a; a plurality of word lines 103 are arranged in parallel in the array area 100a, and a plurality of bit lines 104 are arranged in parallel in the array area 100a, and the orthographic projections of the plurality of word lines 103 on the substrate 101 and the orthographic projections of the plurality of bit lines 104 on the substrate 101 are arranged crosswise. Figures 1B to 1M The manufacturing process of the semiconductor structure 100 is described. Figures 1B to 1M The structure of the manufacturing process is shown in Figure 1A Schematic diagram of the cross section at the aa' and bb' positions.

[0036] Reference Figure 1B As shown, a first dielectric layer 107 covering the base structure is formed, and the base structure at least includes a substrate 101, multiple active areas 102, multiple isolation structures 105, multiple bit line structures 104, bit line isolation structures 106, and word lines 103. For example, after spin coating an insulating dielectric (Spin on Dielectrics, SOD), an annealing treatment is performed to solidify the liquid insulating dielectric to form the first dielectric layer 107. In a specific example, the material of the first dielectric layer 107 includes silicon oxide, such as silicon oxide.

[0037] Reference Figure 1C As shown, the first dielectric layer 107 is planarized until the bit line isolation structure 106 is exposed. It can be understood that after the planarization, the surface of the first dielectric layer 107 away from the substrate 101 is flush with the surface of the bit line isolation structure 106 away from the substrate 101.

[0038] Reference Figure 1D As shown, a mask structure 109 is formed to cover the bit line isolation structure 106 and the first dielectric layer 107, and the mask structure 109 includes a first mask layer 1091, a second mask layer 1092, a third mask layer 1093 and a fourth mask layer 1094; the first mask layer 1091 includes but is not limited to amorphous carbon, the second mask layer 1092 includes but is not limited to silicon oxynitride, the third mask layer 1093 includes but is not limited to a spin-on hard mask (Spin on Hardmask, SOH), and the fourth mask layer 1094 includes but is not limited to silicon oxynitride; before forming the mask structure 109, an isolation layer 108 may also be formed first.

[0039] Reference Figure 1EAs shown, a patterned photoresist layer 110 is formed on the mask structure 109 , and the photolithography pattern in the photoresist layer 110 exposes a portion of the mask structure 109 , for example, exposes the fourth mask layer 1094 at the position aa′.

[0040] Reference Figure 1F As shown, the fourth mask layer 1094 and the third mask layer 1093 are etched according to the photolithography pattern to form a plurality of mandrels 111 arranged at intervals, and the intervals between two adjacent mandrels 111 expose the second mask layer 1092, for example, the second mask layer 1092 at the position aa' is exposed. The mandrel 111 includes the stacked fourth mask layer 1094 and the third mask layer 1093; after the mandrel 111 is formed, the photoresist layer is removed.

[0041] Reference Figure 1G As shown, a spacer layer 112 is formed to cover the exposed second mask layer, the sidewalls and the top of the mandrel. The spacer layer 112 includes but is not limited to silicon oxide.

[0042] Reference Figure 1H As shown, a capping layer 113 covering the spacer layer is formed, and the capping layer 113 includes but is not limited to a spin-on hard mask.

[0043] Reference Figure 1F As shown, the capping layer 113 and the spacer layer 112 on the top of the mandrel 111 are etched until the mandrel 111 and the spacer layer 112 on the sidewall of the mandrel 111 are exposed. Fig. 1I As shown; removing the spacer layer 112 on the side wall of the mandrel 111 to form a plurality of openings; etching the first dielectric layer 107 according to the opening to form a plurality of first contact holes 114, as shown Figure 1J shown.

[0044] Reference Figure 1K As shown, a filling layer 115 is formed to fill the first contact hole 114 . The filling layer 115 also covers the remaining isolation layer 108 . The material of the filling layer 115 includes but is not limited to silicon nitride.

[0045] Reference Figure 1L As shown, the filling layer 115 is etched until the remaining isolation layer 108 is exposed.

[0046] Reference Figure 1M As shown, the remaining isolation layer 108 and the first dielectric layer below the isolation layer 108 are removed to form a second contact hole 116. The first contact hole 114 and the second contact hole 116 are used to subsequently fill a conductive material to form a node contact (NC), such as a word line contact or a capacitor contact, etc. Here, wet etching can be used to remove the first dielectric layer.

[0047] However, during the annealing process of the liquid insulating medium, it is difficult for the liquid insulating medium to be completely converted into the first dielectric layer, resulting in residual impurities when the first dielectric layer is subsequently removed to form the second contact hole. The residual impurities will affect the electrical performance of the subsequent node contacts and even cause the semiconductor device to fail.

[0048] In view of this, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure.

[0049] Figure 2 This is a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Figure 2 As shown, the manufacturing method at least comprises the following steps:

[0050] S210: providing a substrate structure; wherein the substrate structure includes a plurality of bit line isolation structures; and forming a trench between two adjacent bit line isolation structures;

[0051] S220: performing a first thin film deposition process to form a first dielectric layer in the trench;

[0052] S230: performing a second thin film deposition process to form a second dielectric layer covering the bit line isolation structure and the first dielectric layer; wherein the film coverage of the first thin film deposition process is greater than the film coverage of the second thin film deposition process.

[0053] In the embodiment of the present disclosure, a first dielectric layer is formed in the groove by performing a first thin film deposition process; then a second thin film deposition process is performed to form a second dielectric layer covering the bit line isolation structure and the first dielectric layer; since the film coverage of the first thin film deposition process is greater than the film coverage of the second thin film deposition process, the first dielectric layer can fill the groove, which is beneficial for the subsequent removal of the first dielectric layer more completely, reducing the residual impurities in the groove, avoiding failure of the semiconductor device, and improving the yield of the semiconductor device; and the manufacturing method provided in the embodiment of the present disclosure has a simple process, which is beneficial to reducing the difficulty of manufacturing semiconductor devices.

[0054] It should be noted that Figure 2 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 2 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0055] FIG. 3A to FIG. 3N This is a schematic diagram of a semiconductor structure manufacturing process shown in an embodiment of the present disclosure. Figure 2 , FIG. 3A to FIG. 3N The method for manufacturing the semiconductor structure provided by the embodiment of the present disclosure is described in detail. It should be noted that: FIG. 3A to FIG. 3N Only the structure in the production process is shown in Figure 1A The cross-sectional diagram at the bb' position in the middle shows the structure during the manufacturing process. Figure 1A The cross-sectional diagram at the aa' position can be found in Figures 1B to 1M .

[0056] In step S210 , a substrate structure is provided; wherein the substrate structure includes a plurality of bit line isolation structures 305 ; and a trench is formed between two adjacent bit line isolation structures 305 .

[0057] Reference Figure 3A As shown, providing a base structure includes: providing a substrate 301; forming a plurality of isolation structures 303 arranged at intervals in the substrate 301, the plurality of isolation structures 303 separating the substrate 301 into a plurality of active areas 302; forming a bit line structure 304 on the active area 302; forming a bit line isolation structure 305 covering the active area 302, the sidewall and the top of the bit line structure 304, forming a groove between two adjacent bit line isolation structures 305, the groove being used to be filled in a subsequent process to form a first dielectric layer 306.

[0058] It can be understood that the base structure in the embodiment of the present disclosure at least includes a substrate 301, a plurality of active regions 302, a plurality of isolation structures 303, a plurality of bit line structures 304 and a bit line isolation structure 305. Figure 3A Not shown in the figure, the substrate structure may further include other film layer structures. For example, the substrate structure may further include a gate structure, and the word line is connected to the gate structure.

[0059] The material of the substrate 301 includes a semiconductor material, for example, a single-element semiconductor material (for example, silicon (Si) or germanium (Ge), etc.), a III-V compound semiconductor material (for example, gallium nitride (GaN), gallium arsenide (GaAs) or indium phosphide (InP), etc.), a II-VI compound semiconductor material (for example, zinc sulfide (ZnS), cadmium sulfide (CdS) or cadmium telluride (CdTe), etc.), an organic semiconductor material or other semiconductor materials known in the art.

[0060] In a specific embodiment, the active region 302 and the isolation structure 303 can be used to form a memory cell array in a dynamic random access memory. The active region 302 includes a source, a drain, and a channel between the source and the drain. The formation process of the active region 302 includes an ion implantation process or an ion diffusion process. The material of the isolation structure 303 includes at least one of silicon oxide (e.g., silicon oxide), silicon nitride (e.g., silicon nitride), or silicon oxynitride (silicon oxynitride).

[0061] The bit line structure 304 is located above the active area 302 and connected to the active area 302. The bit line structure 304 can be a single film layer or a composite film layer composed of multiple film layers. In a specific embodiment, the bit line structure 304 includes a bit line contact 3041, a connection layer 3042 and a bit line 3043. The material of the bit line contact 3041 includes polysilicon or doped polysilicon, the material of the connection layer 3042 includes tungsten silicide or titanium silicide, etc. The connection layer 3042 is used to reduce the contact resistance between the bit line contact 3041 and the bit line 3043, and the material of the bit line 3043 includes tungsten, etc.

[0062] The bit line isolation structure 305 is used to isolate two adjacent bit line structures 304. The material of the bit line isolation structure 305 includes an insulating material, such as silicon oxide, silicon nitride or silicon oxynitride, etc. In a specific embodiment, the bit line isolation structure 305 is a composite film layer composed of silicon nitride-silicon oxide-silicon nitride (NON).

[0063] In step S220, a first thin film deposition process is performed to form a first dielectric layer 306 in the trench. Figure 3A As shown, the material of the first dielectric layer 306 includes silicon oxide, for example, silicon oxide.

[0064] In some embodiments, the first thin film deposition process includes: an atomic layer deposition process, a physical vapor deposition process, or a chemical vapor deposition process, etc. In the embodiments of the present disclosure, the first thin film deposition process is described as an atomic layer deposition process.

[0065] It should be noted that the trenches between the bit line isolation structures 305 usually have a large aspect ratio. Since the atomic layer deposition process has excellent step coverage, the trenches between the bit line isolation structures 305 can be filled, and the reaction precursor of the first dielectric layer 306 is completely converted, so that when the first dielectric layer 306 in the trench is subsequently removed, almost no impurities remain, ensuring that the electrical performance of the node contact (for example, word line contact or capacitor contact) formed at the position where the first dielectric layer is removed is good.

[0066] In some embodiments, the atomic layer deposition process includes: catalytic atomic layer deposition or plasma atomic layer deposition.

[0067] In a specific embodiment, catalytic atomic layer deposition may be used to form the first dielectric layer 306. For example, pyridine may be used as a catalyst, the reaction temperature may be controlled between 10°C and 25°C, and the flow rate of the reaction precursor may be controlled between 0.5L and 5L.

[0068] In another specific embodiment, plasma atomic layer deposition may be used to form the first dielectric layer 306. For example, bis(diethylamino)silane (also known as SAM-24), diisopropylaminosilane (also known as LTO-520) or bis(tert-butylamino)silane (also known as 2-NTE) may be used as raw materials, the reaction temperature may be controlled between 50° C. and 85° C., the flow rate of the reaction precursor may be controlled between 1 L and 10 L, and the reaction power may be controlled between 20 W and 1000 W.

[0069] It should be noted that the above values ​​are only exemplary and can be reasonably set according to specific process requirements in actual applications.

[0070] In some embodiments, the reaction temperature of the atomic layer deposition process is less than 100° C. It should be noted that before forming the first dielectric layer 306, ion implantation is required to form the active region 302 on the substrate 301. By controlling the reaction temperature of the atomic layer deposition process to be less than 100° C., the influence of the ions implanted in the active region 302 can be reduced, for example, the diffusion of the ions implanted in the active region 302 can be avoided.

[0071] In other embodiments, the first dielectric layer may be formed by a physical vapor deposition process, for example, tetraethoxysilane (TEOS) is used as a raw material for high-temperature filling. It is worth noting that during the high-temperature filling process, the depth of ion implantation needs to be considered.

[0072] In some embodiments, the surface of the first dielectric layer 306 away from the substrate structure has a first recess 3061; the above-mentioned manufacturing method also includes: etching and removing a portion of the first dielectric layer 306 exposed by the first recess 3061, and forming a second recess 3062 on the surface of the first dielectric layer 306 away from the substrate structure; wherein the bottom opening size of the second recess 3062 is larger than the bottom opening size of the first recess 3061.

[0073] Reference Figure 3A and Figure 3B As shown, the first recess 3061 on the surface of the first dielectric layer 306 is in a "V" shape. By etching away a portion of the first dielectric layer 306, a second recess 3062 can be formed on the surface of the first dielectric layer 306. The second recess 3062 is in a "U" shape, that is, the bottom opening size of the second recess 3062 is larger than the bottom opening size of the first recess 3061, which is more conducive to the subsequent deposition of the second dielectric layer 307. In a specific embodiment, the second recess 3062 can be formed by dry etching.

[0074] In some embodiments, the top opening size of the second recess 3062 is larger than the top opening size of the first recess 3061. It can be understood that etching can not only widen the bottom of the first recess 3061, but also widen the top of the first recess 3061, forming a second recess 3062 with a bottom opening size and a top opening size larger than the first recess 3061, which is more conducive to the subsequent deposition of the second dielectric layer 307.

[0075] In step S230, a second thin film deposition process is performed to form a second dielectric layer 307 covering the bit line isolation structure 305 and the first dielectric layer 306; wherein the film coverage of the first thin film deposition process is greater than the film coverage of the second thin film deposition process. The material of the second dielectric layer 307 includes silicon oxide, for example, silicon oxide.

[0076] In some embodiments, the second thin film deposition process includes a spin coating process, for example, after spin coating the insulating medium, an annealing process is performed to solidify the liquid insulating medium to form the second dielectric layer 307 .

[0077] Since the trenches between the bit line isolation structures 305 have a large aspect ratio, the liquid insulating medium is difficult to be completely converted into the first dielectric layer 306 during the annealing process when the trenches are filled with spin-coating insulating dielectric, resulting in poor film coverage of the first dielectric layer 306 in the trenches and residual impurities. In the disclosed embodiment, by first using an atomic layer deposition process with a larger film coverage to fill the trenches to form the first dielectric layer 306, and then using a spin-coating process to form the second dielectric layer 307, not only can residual impurities be reduced, but also the manufacturing cost can be reduced.

[0078] In some embodiments, the above step S230 includes: forming a second dielectric layer 307 in the second recess 3062. Figure 3B An insulating medium is spin-coated on the surface of the structure shown, and the liquid insulating medium fills the second recess 3062 . After annealing, the insulating medium in the second recess 3062 solidifies to form a second dielectric layer 307 .

[0079] It can be understood that, compared with using liquid insulating medium to fill a deeper groove, the liquid insulating medium only needs to fill the second recess 3062 with a smaller depth, which is more conducive to the filling of the liquid insulating medium and complete conversion into the second dielectric layer 307, thereby avoiding residual impurities in subsequent processes.

[0080] In some embodiments, the density of the first dielectric layer 306 is greater than that of the second dielectric layer 307. Since the first dielectric layer 306 is formed by an atomic layer deposition process with good step coverage, the density of the first dielectric layer 306 is greater than that of the second dielectric layer 307.

[0081] In some embodiments, reference Figure 3C As shown, the above manufacturing method further includes: etching the second dielectric layer 307 until the bit line isolation structure 305 is exposed, such as Figure 3D By removing the second dielectric layer 307 on the bit line isolation structure 305 by etching, the height of the structure to be processed can be reduced, and the difficulty of subsequent contact hole etching can be reduced.

[0082] In some embodiments, the above-mentioned manufacturing method also includes: forming a mask structure having a mask pattern on the bit line isolation structure; wherein the mask pattern is located above a preset formation position of the capacitor contact; etching the first dielectric layer according to the mask pattern to form a contact hole; wherein the bottom of the contact hole exposes the active area; and forming a capacitor contact in the contact hole.

[0083] A thin film deposition process can be used to form a mask structure covering the bit line isolation structure, the first dielectric layer and the second dielectric layer. The mask structure includes a single film layer or a composite film layer composed of multiple film layers. In the embodiment of the present disclosure, the mask structure is an example of a composite film layer composed of amorphous carbon-silicon oxynitride-spin-on hard mask-silicon oxynitride.

[0084] A mask pattern can be formed above the preset formation position of the capacitor contact by a self-alignment process, and the second dielectric layer and the first dielectric layer are etched downward according to the mask pattern to form a contact hole, the bottom of the contact hole exposes the active area, and a capacitor contact can be formed by filling the contact hole with a conductive material. Since there is no impurity residue in the contact hole, good contact between the capacitor contact and the active area can be achieved.

[0085] It should be noted that the number of the contact holes formed may be one or more, and the present disclosure has no special limitation on this.

[0086] The self-aligned process includes: one or more of the self-aligned double patterning (SADP) process, the self-aligned reverse patterning (SARP) process, the self-aligned quadruple patterning (SAQP) process, and the self-aligned octuple patterning (SAOP) process, so as to obtain a finer mask pattern.

[0087] Accordingly, the mask pattern includes one or more of a self-aligned double exposure mask pattern, a self-aligned reverse exposure mask pattern, a self-aligned quadruple exposure mask pattern, or a self-aligned eight-exposure mask pattern.

[0088] The following will be combined FIG. 3E to FIG. 3N Describing the process of forming contact holes in detail, it is important to emphasize that FIG. 3E to FIG. 3N It is merely exemplary and is not intended to limit the present disclosure.

[0089] Reference Figure 3E As shown, a mask structure 309 covering the bit line isolation structure 305, the first dielectric layer 306 and the second dielectric layer 307 is formed, and the mask structure 309 includes a first mask layer 3091, a second mask layer 3092, a third mask layer 3093 and a fourth mask layer 3094; the first mask layer 3091 includes but is not limited to amorphous carbon, the second mask layer 3092 includes but is not limited to silicon oxynitride, the third mask layer 3093 includes but is not limited to a spin-on hard mask, and the fourth mask layer 3094 includes but is not limited to silicon oxynitride; before forming the mask structure 309, an isolation layer 308 may be formed first. The material of the isolation layer 308 includes silicon oxide, for example, silicon oxide. The isolation layer 308 is used to isolate the mask structure from the structure formed below the isolation layer 308, and plays a role in protecting the structure formed below.

[0090] Reference Figure 3F As shown, a patterned photoresist layer 310 is formed on the mask structure 309, and the photolithography pattern in the photoresist layer 310 exposes a portion of the mask structure 309, for example, the fourth mask layer 3094 (not shown in the figure) at the position aa' is exposed. For ease of understanding, refer to the above Figure 1E Here, the patterned photoresist layer 310 can be formed by processes such as exposure and development, and the material of the photoresist layer 310 includes a photosensitive compound, such as a resin, a photosensitizer, a solvent, and other additives.

[0091] The fourth mask layer 3094 and the third mask layer 3093 exposed by etching are formed according to the photolithography pattern to form a plurality of mandrels 311 arranged at intervals, such as Figure 3G As shown, the interval between two adjacent mandrels 311 exposes the second mask layer 3092, for example, the second mask layer 3092 at the position aa' is exposed (not shown in the figure). For ease of understanding, please refer to the above Figure 1F It can be understood that the mandrel 311 includes a stacked fourth mask layer 3094 and a third mask layer 3093; after the mandrel 311 is formed, the photoresist layer 310 can be removed by ashing.

[0092] Reference Figure 3H As shown, a spacer layer 312 is formed to cover the top of the mandrel 311. The spacer layer 312 includes but is not limited to silicon oxide. The process of forming the spacer layer 312 includes an atomic layer deposition process. The spacer layer 312 covers the exposed second mask layer 3092 and the sidewall of the mandrel 311 at the same time. For ease of understanding, please refer to the above Figure 1G shown.

[0093] Reference Fig. 3I As shown, a covering layer 313 covering the spacer layer 312 is formed, and the covering layer 313 includes but is not limited to a spin-on hard mask; the covering layer 313 and the spacer layer 312 on the top of the mandrel 311 are etched until the mandrel 311 is exposed, as shown in FIG. Figure 3J Here, the cover layer 313 covers both the aa' and bb' positions, and the spacer layer on the sidewall of the mandrel 311 is exposed after etching. For ease of understanding, refer to the above Fig. 1I Then, the spacer layer 312 on the side wall of the mandrel 311 is removed to form a plurality of openings; the first dielectric layer 306 is etched according to the openings to form a plurality of first contact holes (not shown in the figure). For ease of understanding, please refer to the above Figure 1J After forming the first contact hole, the mask structure can be removed to expose the isolation layer 308, as shown in FIG. Figure 3K shown.

[0094] A filling layer 315 is formed to fill the first contact hole, and the filling layer 315 also covers the exposed isolation layer 308. Figure 3L As shown, the material of the filling layer 315 includes but is not limited to silicon nitride; the filling layer 315 is etched until the isolation layer 308 is exposed again, as shown in FIG. Figure 3M As shown, the isolation layer 308 and the second dielectric layer 307 and the first dielectric layer 306 below the isolation layer 308 are removed to form a second contact hole 316. Here, the bit line isolation structure exposed by the second contact hole 316 can be further etched downward until the active area is exposed.

[0095] Based on the above semiconductor structure, an embodiment of the present disclosure further provides a semiconductor device, comprising the semiconductor structure in any of the above embodiments.

[0096] In some embodiments, the semiconductor device further includes: a capacitor connected to the active region through a capacitor contact.

[0097] In some embodiments, the semiconductor device includes a memory; the memory includes but is not limited to dynamic random access memory (DRAM), ferroelectric random access memory (FeRAM), phase change memory (PCM), etc.

[0098] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate structure; wherein the substrate structure includes a plurality of bit line isolation structures; a trench is formed between two adjacent bit line isolation structures; performing a first thin film deposition process to form a first dielectric layer in the trench; A second thin film deposition process is performed to form a second dielectric layer covering the bit line isolation structure and the first dielectric layer; wherein the film coverage of the first thin film deposition process is greater than the film coverage of the second thin film deposition process.

2. The method according to claim 1, characterized in that: The first dielectric layer has a first depression on a surface away from the base structure; the manufacturing method further includes: A portion of the first dielectric layer exposed by the first recess is removed by etching, and a second recess is formed on a surface of the first dielectric layer away from the substrate structure; wherein a bottom opening size of the second recess is larger than a bottom opening size of the first recess.

3. The method according to claim 2, characterized in that: A top opening size of the second recess is larger than a top opening size of the first recess.

4. The method according to claim 2 or 3, characterized in that: The forming of a second dielectric layer covering the bit line isolation structure and the first dielectric layer comprises: The second dielectric layer is formed in the second recess.

5. The method according to claim 1, characterized in that: The density of the first dielectric layer is greater than the density of the second dielectric layer.

6. The method according to claim 1, characterized in that: The substrate structure further comprises a plurality of active regions and a bit line structure located above the active regions; wherein the bit line structure is connected to the active regions; and the bit line isolation structure covers the active regions, the sidewalls and the top of the bit line structure; The production method further comprises: Etching the second dielectric layer until the bit line isolation structure is exposed; Forming a mask structure having a mask pattern on the bit line isolation structure; wherein the mask pattern is located above a preset formation position of a capacitor contact; Etching the first dielectric layer according to the mask pattern to form a contact hole; wherein the bottom of the contact hole exposes the active area; The capacitor contact is formed in the contact hole.

7. The manufacturing method according to claim 6, characterized in that: The mask pattern includes a self-aligned double exposure mask pattern or a self-aligned quadruple exposure mask pattern.

8. The manufacturing method according to claim 1, characterized in that: The first thin film deposition process includes: an atomic layer deposition process; the second thin film deposition process includes: a spin coating process.

9. The manufacturing method according to claim 8, characterized in that: The atomic layer deposition process includes: catalytic atomic layer deposition or plasma atomic layer deposition.

10. The manufacturing method according to claim 8, characterized in that: The reaction temperature of the atomic layer deposition process is less than 100°C.

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