Method for manufacturing thin film resistor on dielectric layer

Abstract

The invention provides a method for manufacturing a thin film resistor on a dielectric layer. The method comprises the following steps: S1, depositing at least one dielectric layer on a substrate; s2, exposure and development are carried out, and a first processing groove is formed in the photoresist layer; s3, metal sputtering or evaporation is carried out, and a metal layer I is formed at the bottom of the first processing groove; s4, removing the metal layer II, and removing the first photoresist layer; s5, coating a second photoresist layer; s6, exposure and development are carried out, and a second processing groove is formed in the photoresist layer; s7, etching all the metal layer I; s8, metal sputtering or evaporation is carried out, and a metal layer III is formed in the metal layer groove; and S9, removing the metal layer IV and the second photoresist layer. According to the method, the edge of the metal layer III cannot be warped, the appearance of the metal layer III is good, the yield is high, and the problem of device failure caused by the fact that lead metal is connected with the salient point position subsequently cannot be solved.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a thin film resistor on a dielectric layer. Background Art

[0002] Existing sputtering process technology of thin film resistors, such as Figure 1 Specifically, photoresist is used → photoresist coating → alignment → IR inversion → full exposure → development to form a positive trapezoidal morphology → metal sputtering; the bottom corner of this morphology will be connected to the bottom sputtered metal during the sputtering operation, so when the metal is lifted off, the metal at the bottom edge will be torn up, causing the edge of the sputtered metal to warp up, affecting the appearance yield, and the subsequent lead metal connecting through the bump position is prone to cause device failure defects. Summary of the invention

[0003] In view of the above problems, the present invention proposes a method for manufacturing a thin film resistor on a dielectric layer, which has the characteristics of no warping of the metal edge, good appearance and good yield.

[0004] The technical solution of the present invention is achieved in this way:

[0005] A method for manufacturing a thin film resistor on a dielectric layer comprises the following steps:

[0006] S1: depositing at least one dielectric layer on a substrate;

[0007] S2: coating a first photoresist layer on the dielectric layer, exposing and developing the first photoresist layer in the process area, and forming a first process groove on the photoresist layer;

[0008] S3: performing metal sputtering or evaporation to form a metal layer I at the bottom of the first process tank and a metal layer II on the first photoresist layer;

[0009] S4: removing the metal layer II, and finally removing the first photoresist layer, and retaining the metal layer I;

[0010] S5: coating a second photoresist layer on the dielectric layer to cover the metal layer I;

[0011] S6: exposing and developing the second photoresist layer above the middle of the metal layer I to form a second process groove on the photoresist layer, wherein the width of the second process groove is smaller than the width of the metal layer I;

[0012] S7: etching the metal layer I through the second process tank, etching away the entire metal layer I, and forming a metal layer groove in the vacant part of the metal layer I;

[0013] S8: performing metal sputtering or evaporation to form a metal layer III in the metal layer groove and a metal layer IV on the second photoresist layer, wherein the height of the metal layer III is smaller than the height of the metal layer groove;

[0014] S9: remove the metal layer IV, and finally remove the second photoresist layer.

[0015] Preferably, the substrate is a single crystal silicon substrate, a gallium arsenide substrate, a gallium nitride substrate, an indium phosphide substrate or a silicon carbide substrate.

[0016] Preferably, the dielectric layer is one layer, two layers, three layers or four layers.

[0017] Preferably, the dielectric layer is a SiN layer, a TiW layer, an InGaP layer or a GaAs layer.

[0018] Preferably, the metal layer I is a TaN layer, a TiW layer, a Ti layer or an Au layer.

[0019] Preferably, the metal layer III is a TaN layer, a TiW layer, a Ti layer or an Au layer.

[0020] Preferably, the first process groove is a rectangular groove or a trapezoidal groove that is smaller at the top and larger at the bottom.

[0021] Preferably, the second process groove is a rectangular groove or a trapezoidal groove that is smaller at the top and larger at the bottom.

[0022] Preferably, the first photoresist layer is a positive photoresist layer or a negative photoresist layer; and the second photoresist layer is a positive photoresist layer or a negative photoresist layer.

[0023] Beneficial effects of the present invention: During the formation process of the metal layer III of the present invention, the height of the metal layer III is less than the height of the metal layer groove, so during metal sputtering or evaporation, the metal layer III and the metal layer IV are disconnected and will not be connected together, so when the metal layer IV is removed, the metal layer III will not be torn up by the metal layer IV, and the edge of the metal layer III will not be warped. The metal layer III has a good appearance and a good yield, and there will be no subsequent device failure caused by the lead metal passing through the bump position. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 The sputtering process of the existing thin film resistor;

[0026] Figure 2 is a manufacturing process diagram of Example 2;

[0027] Figure 3This is a manufacturing process diagram of Example 3. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] Example 1

[0030] A method for manufacturing a thin film resistor on a dielectric layer comprises the following steps:

[0031] S1: depositing at least one dielectric layer on a substrate;

[0032] S2: coating a first photoresist layer on the dielectric layer, exposing and developing the first photoresist layer in the process area, and forming a first process groove on the photoresist layer;

[0033] S3: performing metal sputtering or evaporation to form a metal layer I at the bottom of the first process tank and a metal layer II on the first photoresist layer;

[0034] S4: removing the metal layer II, and finally removing the first photoresist layer, and retaining the metal layer I;

[0035] S5: coating a second photoresist layer on the dielectric layer to cover the metal layer I;

[0036] S6: exposing and developing the second photoresist layer above the middle of the metal layer I to form a second process groove on the photoresist layer, wherein the width of the second process groove is smaller than the width of the metal layer I;

[0037] S7: etching the metal layer I through the second process tank, etching away the entire metal layer I, and forming a metal layer groove in the vacant part of the metal layer I;

[0038] S8: performing metal sputtering or evaporation to form a metal layer III in the metal layer groove and a metal layer IV on the second photoresist layer, wherein the height of the metal layer III is smaller than the height of the metal layer groove;

[0039] S9: remove the metal layer IV, and finally remove the second photoresist layer. The remaining metal layer III is the desired thin film resistor.

[0040] The substrate may be a single crystal silicon substrate, a gallium arsenide substrate, a gallium nitride substrate, an indium phosphide substrate or a silicon carbide substrate, which may be selected according to actual needs, but is not limited to the above materials.

[0041] The dielectric layer may be one layer, two layers, three layers, four layers or more layers.

[0042] The dielectric layer may be a SiN layer, a TiW layer, an InGaP layer or a GaAs layer, which may be selected according to actual needs, but is not limited to the above materials.

[0043] The metal layer I may be a TaN layer, a TiW layer, a Ti layer or an Au layer, which may be selected according to actual needs, but is not limited to the above materials.

[0044] Wherein, the metal layer III is a TaN layer, a TiW layer, a Ti layer or an Au layer, which is selected according to actual needs, but is not limited to the above materials.

[0045] Among them, the first process groove is a rectangular groove or a trapezoidal groove that is smaller at the top and larger at the bottom, and the second process groove is a rectangular groove or a trapezoidal groove that is smaller at the top and larger at the bottom.

[0046] Wherein, the first photoresist layer is a positive photoresist layer or a negative photoresist layer; the second photoresist layer is a positive photoresist layer or a negative photoresist layer.

[0047] During the formation process of the metal layer III of the present invention, the height of the metal layer III is less than the height of the metal layer groove, so during metal sputtering or evaporation, the metal layer III and the metal layer IV are disconnected and will not be connected together. Therefore, when the metal layer IV is removed, the metal layer III will not be torn up by the metal layer IV, and the edge of the metal layer III will not be warped. The metal layer III has a good appearance and a good yield rate, and there will be no subsequent device failure caused by the lead metal passing through the bump position.

[0048] Example 2

[0049] Reference Figure 2 The difference between this embodiment and embodiment 1 is that metal sputtering is used in step S3 and metal sputtering is used in step S8.

[0050] Example 3

[0051] Reference Figure 3 The difference between this embodiment and embodiment 1 is that metal evaporation is used in step S3 and metal evaporation is used in step S8.

[0052] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for manufacturing a thin film resistor on a dielectric layer, characterized in that: The following steps are involved: S1: depositing at least one dielectric layer on a substrate; S2: coating a first photoresist layer on the dielectric layer, exposing and developing the first photoresist layer in the process area, and forming a first process groove on the photoresist layer; S3: performing metal sputtering or evaporation to form a metal layer I at the bottom of the first process tank and a metal layer II on the first photoresist layer; S4: removing the metal layer II, and finally removing the first photoresist layer, and retaining the metal layer I; S5: coating a second photoresist layer on the dielectric layer to cover the metal layer I; S6: exposing and developing the second photoresist layer above the middle of the metal layer I to form a second process groove on the photoresist layer, wherein the width of the second process groove is smaller than the width of the metal layer I; S7: etching the metal layer I through the second process tank, etching away the entire metal layer I, and forming a metal layer groove in the empty space of the metal layer I; S8: performing metal sputtering or evaporation to form a metal layer III in the metal layer groove and a metal layer IV on the second photoresist layer, wherein the height of the metal layer III is smaller than the height of the metal layer groove; S9: remove the metal layer IV, and finally remove the second photoresist layer.

2. The method for manufacturing a thin film resistor on a dielectric layer according to claim 1, characterized in that: The substrate is a single crystal silicon substrate, a gallium arsenide substrate, a gallium nitride substrate, an indium phosphide substrate or a silicon carbide substrate.

3. The method for manufacturing a thin film resistor on a dielectric layer according to claim 1, characterized in that: The dielectric layer is one layer, two layers, three layers or four layers.

4. The method for manufacturing a thin film resistor on a dielectric layer according to claim 1, wherein: The dielectric layer is a SiN layer, a TiW layer, an InGaP layer or a GaAs layer.

5. The method for manufacturing a thin film resistor on a dielectric layer according to claim 1, wherein: The metal layer I is a TaN layer, a TiW layer, a Ti layer or an Au layer.

6. The method for manufacturing a thin film resistor on a dielectric layer according to claim 1, characterized in that: The metal layer III is a TaN layer, a TiW layer, a Ti layer or an Au layer.

7. The method for manufacturing a thin film resistor on a dielectric layer according to claim 1, wherein: The first process groove is a rectangular groove or a trapezoidal groove that is smaller at the top and larger at the bottom.

8. The method for manufacturing a thin film resistor on a dielectric layer according to claim 1, wherein: The second process groove is a rectangular groove or a trapezoidal groove that is smaller at the top and larger at the bottom.

9. The method for manufacturing a thin film resistor on a dielectric layer according to claim 1, wherein: The first photoresist layer is a positive photoresist layer or a negative photoresist layer; the second photoresist layer is a positive photoresist layer or a negative photoresist layer.

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