Forming method of low-voltage DMOS device

Abstract

The invention provides a forming method of a low-voltage DMOS device, which comprises the following steps: providing a substrate, forming an epitaxial layer on the surface of the substrate, and sequentially forming a gate oxide layer and polycrystalline silicon on the epitaxial layer; forming a double-layer hard mask layer on the surface of the polycrystalline silicon; performing ion implantation on the epitaxial layer to form a first P-type body region; photoetching to define a forming region of a gate, and etching the hard mask layer and the polycrystalline silicon; performing photoetching to define a forming region of a second P-type body region, and performing ion implantation on the epitaxial layer to form the second P-type body region; photoetching to define a forming region of an N-type drift region, and performing ion implantation on the epitaxial layer to form the N-type drift region; etching to remove the upper layer of the hard mask layer, and retaining the lower layer; performing source-drain ion implantation on the epitaxial layer to form a source region and a drain region; and carrying out a back-end process. According to the invention, the existing process is improved, the process flow is optimized, only one-step polysilicon etching is realized, the consistency of the gate feature size is ensured, and the breakdown voltage and reliability of the device are further improved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a low-voltage DMOS device. Background Art

[0002] BD180 is a new 0.18m BCD process developed by integrating standard 0.18m CMOS with 5V CMOS, high-voltage devices, BJTs and analog components. In particular, the breakdown voltage (BV) of BD1805VSNLD was found to be 2-3V lower than the design value in actual application. FA (failure analysis) analysis found that the overlay accuracy of the two gate etchings was not enough, resulting in a gate feature size (Critical Dimension, CD) on one side being 10% smaller than the design value, resulting in a lower BV. Summary of the invention

[0003] In view of this, the present invention proposes a method for forming a low-voltage DMOS device to increase the breakdown voltage of the device.

[0004] The present invention provides a method for forming a low voltage DMOS device, comprising the following steps:

[0005] Step 1: providing a substrate, wherein an epitaxial layer is formed on the surface of the substrate, and a gate oxide layer and polysilicon are sequentially formed on the epitaxial layer;

[0006] Step 2, forming a double-layer hard mask layer on the surface of the polysilicon;

[0007] Step 3, performing ion implantation on the epitaxial layer to form a first P-type body region;

[0008] Step 4: Photolithography is used to define the gate formation area, and the hard mask layer and the polysilicon are etched;

[0009] Step 5: photolithography to define a formation area of ​​the second P-type body region, and ion implantation is performed on the epitaxial layer to form the second P-type body region;

[0010] Step 6: Photolithography is used to define the formation area of ​​the N-type drift region, and ion implantation is performed on the epitaxial layer to form the N-type drift region;

[0011] Step 7: etching and removing the upper layer of the hard mask layer, and retaining the lower layer;

[0012] Step 8: performing source-drain ion implantation on the epitaxial layer to form a source region and a drain region;

[0013] Step nine: carry out the back-end process.

[0014] Preferably, in step one, the substrate is a silicon substrate, and the epitaxial layer is a silicon epitaxial layer.

[0015] Preferably, the hard mask layer in step 2 comprises an upper silicon nitride layer and a lower silicon oxide layer.

[0016] Preferably, in step three, the first P-type body region is located above the epitaxial layer.

[0017] Preferably, the same photomask is used in step five and step six.

[0018] Preferably, in step five, the second P-type body region is located on both sides of the first P-type body region.

[0019] Preferably, in step six, the N-type drift region is located in the middle, adjacent to the second P-type body region.

[0020] Preferably, the depth of the second P-type body region in step five is smaller than the depth of the N-type drift region in step six.

[0021] Preferably, the etching in step seven adopts a wet etching process.

[0022] Preferably, the lower hard mask layer retained in step seven is used to prevent subsequent implantation from penetrating the polysilicon.

[0023] The present invention improves the existing method for forming a low-voltage DMOS device, performs two P-type body region injections, the first P-type body region injection optimizes the P-type body region junction depth consistency, and before the first P-type body region injection, grows a double-layer hard mask layer to prevent the N-type drift region injection from punching through polysilicon. After the N-type drift region injection is completed, the upper layer of the hard mask layer is etched away, and the lower layer is retained, which can also prevent the subsequent injection from punching through polysilicon. The present invention only performs one-step polysilicon etching, ensures the consistency of gate feature size, and improves the device breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0025] Figure 1 A schematic diagram showing a method for forming a low voltage DMOS device currently in the industry;

[0026] Figures 2 to 5 Display as Figure 1 Schematic diagram of the device structure in each step of the method shown;

[0027] Figure 6 A flow chart showing a method for forming a low voltage DMOS device according to an embodiment of the present invention;

[0028] Figures 7 to 11Shown are schematic diagrams of device structures in various steps of a method for forming a low-voltage DMOS device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, flows, components and circuits are not described in detail.

[0030] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0031] Unless the context clearly requires otherwise, the words "include", "comprising" and similar words throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, the meaning is "including but not limited to".

[0032] In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0033] Figure 1 The figure shows the current method of forming a low voltage DMOS device in the industry. Figure 1 As shown, it includes: polysilicon growth; P-type body region polysilicon etching; P-type body region implantation; N-type drift region polysilicon etching; N-type drift region implantation; source and drain region processes; and back-end processes. Figures 2 to 5 As shown in the figure, polysilicon etching is performed before the P-type body region injection and the N-type drift region injection. However, FA (failure analysis) found that the gate CD on one side is 10% smaller than the design value due to the insufficient overlay accuracy of the two gate etchings, resulting in a lower BV. Therefore, the present invention proposes a new method for forming a low-voltage DMOS device, which only performs one-step polysilicon etching to ensure the consistency of the gate CD. The technical solution of the present invention is further explained below in conjunction with the accompanying drawings and through specific implementation methods.

[0034] Figure 6 The flowchart is a method for forming a low voltage DMOS device according to an embodiment of the present invention. Figures 7 to 11 The structure diagram of each step of the method for forming a low voltage DMOS device according to an embodiment of the present invention is shown. Figure 6 As shown, the following steps are included:

[0035] Step 1: providing a substrate, an epitaxial layer is formed on the surface of the substrate, and a gate oxide layer and polysilicon are sequentially formed on the epitaxial layer.

[0036] The substrate may be any suitable substrate material, such as silicon, silicon on insulator, germanium, silicon carbide, silicon germanium, etc., or may be a substrate material on which a semiconductor epitaxial layer such as silicon carbide is epitaxially grown on a substrate. The epitaxial layer is formed by epitaxial growth. In the embodiment of the present invention, the substrate is a silicon substrate, and the epitaxial layer is a silicon epitaxial layer.

[0037] A gate oxide layer and polysilicon are sequentially formed on the epitaxial layer, and the structure formed is as follows Figure 2 As shown. In the embodiment of the present invention, the gate oxide layer can be formed by a thermal oxidation process or other suitable methods. Here, the thickness of the gate dielectric layer is not specifically described, and a gate dielectric layer of suitable thickness is formed according to specific actual needs. Polysilicon deposition is performed by chemical vapor deposition or other suitable methods.

[0038] Step 2: forming a double-layer hard mask layer on the surface of polysilicon.

[0039] In an embodiment of the present invention, the hard mask layer includes an upper silicon nitride layer (SiN) and a lower silicon oxide layer. The formation method thereof may be chemical vapor deposition (CVD) or physical vapor deposition (PVD). Of course, the hard mask layer may also be a three-layer stacked structure, including a silicon oxide layer, a silicon nitride layer and a silicon oxide layer. In an embodiment of the present invention, the hard mask layer is not only used to define the polysilicon pattern, but also to prevent subsequent injection from penetrating the polysilicon.

[0040] Step 3: Figure 7 As shown, ion implantation is performed on the epitaxial layer to form a first P-type body region.

[0041] In the embodiment of the present invention, the first P-type body region is located above the epitaxial layer.

[0042] Step 4: Figure 8 As shown, photolithography is used to define a gate formation area, and the hard mask layer and polysilicon are etched.

[0043] In the embodiment of the present invention, the gate is defined by using a hard mask layer and a dry etching process.

[0044] Step 5: Fig. 9 As shown, photolithography is used to define a formation area of ​​the second P-type body region, and ion implantation is performed on the epitaxial layer to form the second P-type body region.

[0045] Step 6: Fig.10 As shown, photolithography is used to define a formation area of ​​an N-type drift region, and ion implantation is performed on the epitaxial layer to form the N-type drift region.

[0046] In an embodiment of the present invention, the same photomask is used for step five and step six. The second P-type body region is located on both sides of the first P-type body region. The N-type drift region is located in the middle, adjacent to the second P-type body region. The depth of the second P-type body region is less than the depth of the N-type drift region. Specifically, a photoresist (PR) layer is coated, and the photoresist layer is photolithographically processed (including exposure and development) to expose the surface of a partial area of ​​the epitaxial layer (i.e., the area to be formed), and then the photoresist layer after photolithography is used as a mask to perform ion implantation on the exposed area of ​​the epitaxial layer to form a second P-type body region, and then the epitaxial layer is continuously photolithographically processed and ion implanted to form an N-type drift region between the second P-type body regions. Among them, N-type corresponds to N-type ions, such as phosphorus (P), and P-type corresponds to P-type ions, such as boron.

[0047] Step 7: Fig.11 As shown, the upper layer of the hard mask layer is removed by etching, and the lower layer remains.

[0048] In the embodiment of the present invention, a wet etching process is used to remove the upper silicon nitride layer of the hard mask layer, and the lower silicon oxide layer is retained. The retained lower hard mask layer is used to prevent subsequent implantation from penetrating polysilicon.

[0049] Step 8: Perform source-drain ion implantation on the epitaxial layer to form a source region and a drain region.

[0050] In the embodiment of the present invention, source and drain implantation regions are defined by a photomask, and ion implantation is performed to form the source and drain regions.

[0051] Step nine: carry out the back-end process.

[0052] The embodiment of the present invention improves the existing method for forming a low-voltage DMOS device, performs two P-type body region injections, and the first P-type body region injection optimizes the consistency of the P-type body region junction depth. Before the first P-type body region injection, a double-layer hard mask layer is grown to prevent the N-type drift region injection from punching through the polysilicon. After the N-type drift region injection is completed, the upper layer of the hard mask layer is etched away, and the lower layer is retained, which can also prevent the subsequent injection from punching through the polysilicon. The present invention only performs one-step polysilicon etching, ensures the consistency of the gate feature size, and improves the device breakdown voltage.

[0053] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for forming a low voltage DMOS device, characterized in that: The following steps are involved: Step 1: providing a substrate, wherein an epitaxial layer is formed on the surface of the substrate, and a gate oxide layer and polysilicon are sequentially formed on the epitaxial layer; Step 2, forming a double-layer hard mask layer on the surface of the polysilicon; Step 3, performing ion implantation on the epitaxial layer to form a first P-type body region; Step 4: Photolithography is used to define the gate formation area, and the hard mask layer and the polysilicon are etched; Step 5: photolithography to define a formation area of ​​the second P-type body region, and ion implantation is performed on the epitaxial layer to form the second P-type body region; Step 6: Photolithography is used to define the formation area of ​​the N-type drift region, and ion implantation is performed on the epitaxial layer to form the N-type drift region; Step 7: etching and removing the upper layer of the hard mask layer, and retaining the lower layer; Step 8: performing source-drain ion implantation on the epitaxial layer to form a source region and a drain region; Step nine: carry out the back-end process.

2. The method for forming a low voltage DMOS device according to claim 1, characterized in that: In step 1, the substrate is a silicon substrate, and the epitaxial layer is a silicon epitaxial layer.

3. The method for forming a low voltage DMOS device according to claim 1, characterized in that: The hard mask layer in step 2 includes an upper silicon nitride layer and a lower silicon oxide layer.

4. The method for forming a low voltage DMOS device according to claim 1, characterized in that: In step three, the first P-type body region is located above the epitaxial layer.

5. The method for forming a low voltage DMOS device according to claim 1, characterized in that: The same photomask is used in steps 5 and 6.

6. The method for forming a low voltage DMOS device according to claim 1, characterized in that: In step five, the second P-type body region is located on both sides of the first P-type body region.

7. The method for forming a low voltage DMOS device according to claim 1, characterized in that: In step six, the N-type drift region is located in the middle, adjacent to the second P-type body region.

8. The method for forming a low voltage DMOS device according to claim 1, characterized in that: The depth of the second P-type body region in step five is less than that of the N-type drift region in step six.

9. The method for forming a low voltage DMOS device according to claim 1, characterized in that: The etching in step seven adopts a wet etching process.

10. The method for forming a low voltage DMOS device according to claim 1, characterized in that: The lower hard mask layer retained in step seven is used to prevent subsequent implantation from penetrating the polysilicon.

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