Semiconductor structure and manufacturing method thereof
By forming a junction field effect region on the base region of the semiconductor device and simplifying the process flow with the same mask layer, the problems of cumbersome and high cost in the prior art are solved, and the on-resistance of the semiconductor device are optimized.
Patent Information
- Application Number
- CN202411551064.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-01
- Publication Date
- 2025-02-18
AI Technical Summary
In the prior art, when manufacturing semiconductor devices, it is necessary to form a junction field effect region in the active region to alleviate the parasitic JFET effect, resulting in cumbersome process flow and increasing production costs.
After the base area is formed, the same mask layer is used to form the junction field effect area, and the self-alignment process is used to form the junction field effect area, simplifying the process steps and saving production costs.
The optimization of the on-resistance of semiconductor devices is achieved, the natural depletion layer of the PN junction between the base region and the epitaxial layer is thinned, and the carrier transportation channel is increased.
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Figure CN119486176A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art
[0002] In the current field of semiconductor technology, there is a parasitic junction field effect transistor (JFET) between the base region (base) and the epitaxial layer (Epitaxy, epi for short) in silicon carbide (SiC) planar power devices (such as VDMOSFET devices), that is, there is a parasitic JFET effect. The parasitic JFET effect causes a natural depletion layer to exist in the PN junction of the semiconductor device, resulting in a shortening of the carrier transport channel when the semiconductor device is turned on, thereby adversely affecting the overall on-resistance of the semiconductor device. In the related art, a junction field effect region (i.e., JFET region) is usually formed within the entire active area (AA) of the semiconductor device to reduce the width of the natural depletion layer of the PN junction between the base region and the epitaxial layer, alleviate the parasitic JFET effect, and thus achieve the purpose of optimizing the on-resistance of the semiconductor device.
[0003] However, this method performs the doping process of the junction field effect region after the doping regions in the active area (AA) are formed, which requires a separate definition of the mask corresponding to the junction field effect region (i.e., JFET region), adds additional mask deposition, etching and removal steps, makes the process flow cumbersome, increases production costs and reduces process efficiency. Summary of the invention
[0004] Based on this, the embodiment of the present application provides a semiconductor structure and a manufacturing method thereof, which can use the mask pattern of the base region to form a junction field effect region (i.e., JFET region), thereby optimizing the on-resistance of the semiconductor device while simplifying the process flow.
[0005] In order to achieve the above-mentioned purpose, on the one hand, some embodiments of the present application provide a method for manufacturing a semiconductor structure. The manufacturing method includes: providing an epitaxial layer; forming a first mask layer on one side of the epitaxial layer; the first mask layer has a first mask pattern for defining a base region; based on the first mask layer, forming at least two base regions spaced and distributed on both sides of the first mask layer along a first direction in the epitaxial layer; based on the first mask layer, forming at least two junction field effect regions covering each base region; wherein the junction field effect region is formed by a self-alignment process.
[0006] In some embodiments, the junction field effect region includes a first junction field effect region and a second junction field effect region; the formation of at least two junction field effect regions covering each base region based on the first mask layer includes: based on the first mask layer, forming a first junction field effect region directly below each base region; based on the first mask layer, forming a second junction field effect region on the side wall of each base region; wherein a side of each first junction field effect region close to the second junction field effect region is connected to the bottom of each second junction field effect region to form at least two junction field effect regions covering each base region.
[0007] In some embodiments, the first junction field effect region is formed by a self-aligned vertical implantation process, and the second junction field effect region is formed by a self-aligned oblique implantation process.
[0008] In some embodiments, the ion implantation angle of the second junction field effect region ranges from 0° to 60°.
[0009] In some embodiments, the conductivity type of the junction field effect region is the same as the conductivity type of the epitaxial layer; and the doping concentration of the junction field effect region is greater than the doping concentration of the epitaxial layer.
[0010] In some embodiments, each of the junction field effect regions has a gap in the first direction.
[0011] In some embodiments, before forming the first mask layer on one side of the epitaxial layer, the method for manufacturing a semiconductor structure further includes: forming an oxide layer covering a surface of one side of the epitaxial layer; wherein the first mask layer is formed on a side of the oxide layer away from the epitaxial layer.
[0012] In some embodiments, after forming a junction field effect region covering each base region based on the first mask layer, the method for manufacturing a semiconductor structure further includes: forming a second mask layer on one side of the base region; the second mask layer has a second mask pattern for defining a first type doping region; based on the second mask layer, forming a first type doping region in the base region; removing the first mask layer and the second mask layer; forming a third mask layer on one side of the epitaxial layer; the third mask layer has a third mask pattern for defining a second type doping region; based on the third mask layer, forming a second type doping region on a side of the first type doping region away from the junction field effect region in the first direction; removing the third mask layer to obtain a semiconductor structure.
[0013] On the other hand, according to some embodiments, the present application also provides a semiconductor structure; the semiconductor structure includes an epitaxial layer, at least two base regions and at least two junction field effect regions; at least two base regions are spaced apart in the epitaxial layer along a first direction; at least two junction field effect regions cover each base region; wherein each junction field effect region has a gap in the first direction.
[0014] In some embodiments, the semiconductor structure further includes a first type doping region and a second type doping region; the first type doping region is located in the base region; and the second type doping region is located on a side of the first type doping region away from the junction field effect region in the first direction.
[0015] The embodiments of the present application may or at least have the following advantages:
[0016] In an embodiment of the present application, the junction field effect region is manufactured after the base region is formed, and based on the first mask pattern in the first mask layer for defining the base region, a self-alignment process is used to form the junction field effect region; in this way, the base region and the junction field effect region can be formed based on the same mask layer (i.e., the first mask layer), and there is no need to perform additional mask deposition, etching and removal processes for the junction field effect region, which effectively simplifies the process steps and saves production costs; in addition, by forming a junction field effect region that covers the base region, the natural depletion layer of the PN junction between the base region and the epitaxial layer is thinned, so that the carrier transport channel increases when the PN junction is turned on, thereby achieving the optimization of the on-resistance in the semiconductor structure.
[0017] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0019] Figure 1 A schematic flow chart of a method for manufacturing a semiconductor structure provided in some embodiments;
[0020] Figure 2 A schematic flow chart of another method for manufacturing a semiconductor structure provided in some embodiments;
[0021] Figure 3 A schematic flow chart of another method for manufacturing a semiconductor structure provided in some embodiments;
[0022] Figure 4 A schematic flow chart of another method for manufacturing a semiconductor structure provided in some embodiments;
[0023] Figure 5 A schematic flow chart of another method for manufacturing a semiconductor structure provided in some embodiments;
[0024] Figure 6 A schematic structural diagram of a structure obtained after forming a first mask layer provided in some embodiments;
[0025] Figure 7 A schematic diagram of a structure obtained after forming a base region provided in some embodiments;
[0026] Figure 8 A schematic diagram of a structure obtained after forming a junction field effect region provided in some embodiments;
[0027] Fig. 9 A schematic diagram of a structure obtained after forming a first junction field effect region provided in some embodiments;
[0028] Fig.10 A schematic diagram of a structure obtained after forming a second junction field effect region provided in some embodiments;
[0029] Fig.11 A schematic diagram of a semiconductor structure provided in some embodiments;
[0030] Fig.12 A schematic diagram of the structure of another semiconductor structure provided in some embodiments.
[0031] Description of reference numerals:
[0032] 1. epitaxial layer, 2. first mask layer, 3. oxide layer, 4. base region, 5. junction field effect region, 51. first junction field effect region, 52. second junction field effect region, 6. first type doping region, 7. second type doping region. DETAILED DESCRIPTION
[0033] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0035] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.
[0036] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0037] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments (and intermediate structures) of the present application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.
[0038] The embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, which can form a junction field effect region (ie, JFET region) by using a mask pattern of a base region, thereby optimizing the on-resistance of the semiconductor device while simplifying the process flow.
[0039] In some embodiments, see Figure 1 , the manufacturing method of the semiconductor structure includes the following steps S100~S400.
[0040] S100 , providing an epitaxial layer.
[0041] S200 , forming a first mask layer on one side of the epitaxial layer; the first mask layer has a first mask pattern for defining a base region.
[0042] S300 , based on the first mask layer, forming at least two base regions in the epitaxial layer and spaced apart along a first direction and on both sides of the first mask layer.
[0043] S400, based on the first mask layer, forming at least two junction field effect regions covering each base region; wherein the junction field effect regions are formed by a self-alignment process.
[0044] In an embodiment of the present application, the junction field effect region is manufactured after the base region is formed, and based on the first mask pattern in the first mask layer for defining the base region, a self-alignment process is used to form the junction field effect region; in this way, the base region and the junction field effect region can be formed based on the same mask layer (i.e., the first mask layer), and there is no need to perform additional mask deposition, etching and removal processes for the junction field effect region, which effectively simplifies the process steps and saves production costs; in addition, by forming a junction field effect region that covers the base region, the natural depletion layer of the PN junction between the base region and the epitaxial layer is thinned, so that the carrier transport channel increases when the PN junction is turned on, thereby achieving the optimization of the on-resistance in the semiconductor structure.
[0045] In some embodiments, see Figure 2 Before step S200, the method for manufacturing the semiconductor structure further includes the following step S201.
[0046] S201, forming an oxide layer covering a surface of one side of the epitaxial layer.
[0047] Accordingly, please continue to refer to Figure 2 , step S200 includes the following step S210.
[0048] S210, forming a first mask layer on a side of the oxide layer away from the epitaxial layer; the first mask layer has a first mask pattern for defining a base region.
[0049] In some embodiments, see Figure 3 , step S210 includes the following steps S211~S214.
[0050] S211, forming a first mask material layer on a side of the oxide layer away from the epitaxial layer.
[0051] S212, forming a photoresist pattern layer on a side of the first mask material layer away from the oxide layer.
[0052] S213, etching the first mask material layer based on the photoresist pattern layer to form a first mask layer; the first mask layer has a first mask pattern for defining a base region.
[0053] S214, removing the photoresist pattern layer.
[0054] In some embodiments, see Figure 4, step S400 includes the following steps S410~S420.
[0055] S410 , forming a first junction field effect region directly below each base region based on a first mask layer.
[0056] S420, based on the first mask layer, forming a second junction field effect region on the sidewall of each base region; wherein a side of each first junction field effect region close to the second junction field effect region is connected to a bottom of each second junction field effect region to form at least two junction field effect regions covering each base region.
[0057] In some embodiments, the first junction field effect region is formed by a self-aligned vertical implantation process, and the second junction field effect region is formed by a self-aligned oblique implantation process.
[0058] In an embodiment of the present application, a first junction field effect region is formed directly below the base region by a self-aligned vertical injection process based on the first mask layer, and a second junction field effect region is formed on the side wall of the base region by a self-aligned quasi-oblique injection process based on the first mask layer, so that the first junction field effect region is connected to the second junction field effect region to cover the base region; in this way, based on the same mask layer, the manufacture of junction field effect regions at different positions is achieved by flexibly using the self-alignment process, and the carrier transport channel between the base region and the epitaxial layer when the PN junction is turned on is effectively increased.
[0059] In some embodiments, see Figure 5 After step S400, the method for manufacturing the semiconductor structure further includes the following steps S510 to S560.
[0060] S510, forming a second mask layer on one side of the base region; the second mask layer has a second mask pattern for defining the first type doping region.
[0061] S520, forming a first type doping region in the base region based on the second mask layer.
[0062] S530, removing the first mask layer and the second mask layer.
[0063] S540, forming a third mask layer on one side of the epitaxial layer; the third mask layer has a third mask pattern for defining the second type doping region.
[0064] S550 , based on the third mask layer, forming a second type doping region on a side of the first type doping region away from the junction field effect region in the first direction.
[0065] S560, removing the third mask layer to obtain a semiconductor structure.
[0066] It should be understood that although Figure 1~Figure 5The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1~Figure 5 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.
[0067] In order to more clearly illustrate the manufacturing method of the semiconductor structure in some of the above embodiments, the following embodiments are combined with Figure 6~Figure 11 Understand.
[0068] In some embodiments, the method for manufacturing a semiconductor structure includes steps S100 to S400.
[0069] In step S100 , an epitaxial layer 1 (Epitaxy, epi for short) is provided.
[0070] Illustratively, the epitaxial layer 1 includes a silicon carbide (SiC) epitaxial layer.
[0071] In some examples, epitaxial layer 1 includes a substrate.
[0072] For example, the substrate can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for example, the substrate can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate should not limit the scope of protection of this application.
[0073] Illustratively, the conductivity type of the epitaxial layer 1 is the first conductivity type.
[0074] In step S200, refer to Figure 6 , a first mask layer 2 is formed on one side of the epitaxial layer 1 ; the first mask layer 2 has a first mask pattern for defining the base region 4 .
[0075] In some embodiments, before step S200 , the method for manufacturing a semiconductor structure further includes step S201 .
[0076] In step S201, please continue to refer to Figure 6 , forming an oxide layer 3 covering one side surface of the epitaxial layer 1.
[0077] By way of example, the material of the oxide layer 3 includes, but is not limited to, silicon oxide (SiO).
[0078] For some examples, see Figure 6 , the size of the oxide layer 3 in the first direction (eg, X direction) is the same as the size of the epitaxial layer 1 in the first direction (eg, X direction).
[0079] Accordingly, step S200 includes step S210.
[0080] In step S210, please continue to refer to Figure 6 , a first mask layer 2 is formed on a side of the oxide layer 3 facing away from the epitaxial layer 1 ; the first mask layer 2 has a first mask pattern for defining the base region 4 .
[0081] For example, the first mask layer 2 may be a hard mask layer; the material of the first mask layer 2 includes but is not limited to polysilicon (Poly).
[0082] For example, the formation process of the first mask layer 2 includes but is not limited to a deposition process; the formation process of the first mask layer 2 may be, for example, physical vapor deposition (Physical Vapor Deposition, PVD for short) or chemical vapor deposition (Chemical Vapor Deposition, CVD for short).
[0083] In some embodiments, step S210 includes steps S211 to S214.
[0084] In step S211 , a first mask material layer is formed on a side of the oxide layer 3 facing away from the epitaxial layer 1 .
[0085] By way of example, the material of the first mask material layer includes but is not limited to polysilicon (Poly).
[0086] In step S212 , a photoresist pattern layer is formed on a side of the first mask material layer away from the oxide layer 3 .
[0087] By way of example, the process for forming the photoresist pattern layer includes, but is not limited to, a coating process.
[0088] In step S213 , the first mask material layer is etched based on the photoresist pattern layer to form a first mask layer 2 ; the first mask layer 2 has a first mask pattern for defining the base region 4 .
[0089] For example, the etching process of the first mask material layer includes but is not limited to a dry etching process; the etching process of the first mask material layer may be, for example, a photolithography process.
[0090] It should be noted that the oxide layer 3 can be used as an etching stop layer during the etching process of the first mask material layer to protect the underlying epitaxial layer 1 .
[0091] For some examples, see Figure 6 The size of the first mask layer 2 in the first direction (eg, X direction) is smaller than the size of the epitaxial layer 1 in the first direction (eg, X direction), and the first mask layer 2 is located in the central region of the epitaxial layer 1 .
[0092] In step S214 , the photoresist pattern layer is removed.
[0093] Illustratively, the process of removing the photoresist pattern layer includes, but is not limited to, a dry stripping process and / or a wet stripping process.
[0094] In step S300, refer to Figure 7 Based on the first mask layer 2 , at least two base regions 4 are formed in the epitaxial layer 1 and are distributed along a first direction (eg, X direction) at intervals on both sides of the first mask layer 2 .
[0095] For example, the process for forming the base region 4 includes, but is not limited to, an ion implantation (IMP) process; the process for forming the base region 4 may be, for example, a self-aligned vertical ion implantation process.
[0096] By way of example, the ion implantation angle of the base region 4 may be 0°.
[0097] In some examples, the conductivity type of base region 4 is the second conductivity type.
[0098] It should be noted that the conductivity type of the base region 4 is opposite to the conductivity type of the epitaxial layer 1 .
[0099] By way of example, the first conductivity type is, for example, an N type, and the second conductivity type is, for example, a P type.
[0100] In step S400, refer to Figure 8 Based on the first mask layer 2, at least two junction field effect regions 5 covering each base region 4 are formed; wherein the junction field effect region 5 is formed by a self-alignment process.
[0101] In some embodiments, the conductivity type of the junction field effect region 5 is the same as the conductivity type of the epitaxial layer 1 ; and the doping concentration of the junction field effect region 5 is greater than the doping concentration of the epitaxial layer 1 .
[0102] By way of example, the conductivity type of the junction field effect region 5 is the first conductivity type.
[0103] It should be explained that by forming at least two junction field effect regions 5 covering each base region 4, and the doping concentration of the junction field effect region 5 is greater than the doping concentration of the epitaxial layer 1; in this way, the doping concentration of the first conductive type ions (for example, N+) around the base region 4 is increased, thereby alleviating the parasitic junction field effect transistor (Junction Field Effect Transistor, referred to as JFET) effect.
[0104] In some embodiments, please refer to Figure 8 , each junction field effect region 5 has a gap in the first direction.
[0105] It should be noted that each junction field effect region 5 corresponds to and covers each base region 4, that is, each base region 4 corresponds to each junction field effect region 5 one by one; and each base region 4 is spaced apart in the first direction (for example, the X direction), and each junction field effect region 5 has a gap in the first direction (for example, the X direction).
[0106] In some embodiments, the junction field effect region 5 includes a first junction field effect region 51 and a second junction field effect region 52 ; step S400 includes steps S410 - S420 .
[0107] In step S410, refer to Fig. 9 Based on the first mask layer 2 , a first junction field effect region 51 is formed directly below each base region 4 .
[0108] In some embodiments, the formation process of the first junction field effect region 51 includes but is not limited to an ion implantation (IMP) process; the formation process of the first junction field effect region 51 may be, for example, a self-aligned vertical ion implantation process.
[0109] For example, the ion implantation angle of the first junction field effect region 51 may be 0°.
[0110] For example, please refer to Fig. 9 , the orthographic projection of the first junction field effect region 51 in the second direction (eg, the Y direction) coincides with the orthographic projection of the base region 4 in the second direction (eg, the Y direction).
[0111] In step S420, refer to Fig.10 Based on the first mask layer 2, a second junction field effect region 52 is formed on the side wall of each base region 4; wherein, a side of each first junction field effect region 51 close to the second junction field effect region 52 is connected to the bottom of each second junction field effect region 52 to form at least two junction field effect regions 5 covering each base region 4.
[0112] In some embodiments, the formation process of the second junction field effect region 52 includes but is not limited to an ion implantation (IMP) process; the formation process of the second junction field effect region 52 may be a self-aligned oblique implantation process.
[0113] In some examples, the ion implantation angle of the second junction field effect region 52 ranges from 0° to 60°.
[0114] For example, the ion implantation angle of the second junction field effect region 52 may be 0°, 10°, 20°, 30°, 40°, 50° or 60°.
[0115] For example, please refer to Fig.10 There is a gap between the second junction field effect regions 52 corresponding to two adjacent base regions 4 in the first direction (eg, X direction).
[0116] It should be noted that in order to make the side of each first junction field effect region 51 close to the second junction field effect region 52 connected to the bottom of each second junction field effect region 52 and form a junction field effect region 5 covering the base region 4, the semiconductor structure needs to be rotated at least 4 times in the self-aligned bevel injection process of the second junction field effect region 52 to ensure the thickness uniformity of the formed second junction field effect region 52, thereby improving the improvement effect of the junction field effect region 5 on the parasitic JFET effect.
[0117] In some embodiments, after step S400 , the method for manufacturing a semiconductor structure further includes steps S510 - S560 .
[0118] In step S510 , a second mask layer is formed on one side of the base region 4 ; the second mask layer has a second mask pattern for defining the first type doping region 6 .
[0119] By way of example, the second mask layer may be a hard mask layer.
[0120] For example, the formation process of the second mask layer includes but is not limited to a deposition process; the formation process of the first mask layer 2 may be, for example, physical vapor deposition (PVD) or chemical vapor deposition (CVD).
[0121] In step S520 , a first type doping region 6 is formed in the base region 4 based on the second mask layer.
[0122] For example, the process for forming the first type doping region 6 includes but is not limited to an ion implantation (IMP) process.
[0123] Illustratively, the conductivity type of the first-type doping region 6 is the first conductivity type (eg, N-type).
[0124] In step S530 , the first mask layer 2 and the second mask layer are removed.
[0125] For example, the removal processes of the first mask layer 2 and the second mask layer include but are not limited to dry etching (DryEtch) process or grinding process.
[0126] In step S540 , a third mask layer is formed on one side of the epitaxial layer 1 ; the third mask layer has a third mask pattern for defining the second type doping region 7 .
[0127] By way of example, the third mask layer may be a hard mask layer.
[0128] For example, the formation process of the third mask layer includes but is not limited to a deposition process; the formation process of the first mask layer 2 may be, for example, physical vapor deposition (PVD) or chemical vapor deposition (CVD).
[0129] In step S550 , based on the third mask layer, a second type doping region 7 is formed on a side of the first type doping region 6 away from the junction field effect region 5 in the first direction.
[0130] Illustratively, the conductivity type of the second-type doping region 7 is the second conductivity type (eg, P-type).
[0131] In step S560, refer to Fig.11 , remove the third mask layer to obtain a semiconductor structure.
[0132] For example, the removal process of the third mask layer includes but is not limited to a dry etching process or a grinding process.
[0133] The present application also provides a semiconductor structure according to some embodiments, which can be prepared by the manufacturing method of the semiconductor structure in some of the above embodiments. The semiconductor structure also has the technical advantages of the manufacturing method of the above semiconductor structure. It should be noted that the parts that are the same or corresponding to the above embodiments can refer to the corresponding description of the above embodiments, and will not be described in detail below.
[0134] In some embodiments, see Fig.11The semiconductor structure includes an epitaxial layer 1, at least two base regions 4 and at least two junction field effect regions 5; at least two base regions 4 are spaced apart in the epitaxial layer 1 along a first direction; at least two junction field effect regions 5 cover each base region 4; wherein each junction field effect region 5 has a gap in the first direction.
[0135] Illustratively, the epitaxial layer 1 includes a silicon carbide (SiC) epitaxial layer.
[0136] By way of example, the conductivity type of the epitaxial layer 1 is the first conductivity type; the conductivity type of the base region 4 is the second conductivity type; and the conductivity type of the junction field effect region 5 is the first conductivity type.
[0137] For example, the doping concentration of the junction field effect region 5 is greater than the doping concentration of the epitaxial layer 1 .
[0138] By way of example, the junction field effect region 5 is formed by a self-aligned ion implantation process.
[0139] In some embodiments, see Fig.12 The junction field effect region 5 includes a first junction field effect region 51 and a second junction field effect region 52; the first junction field effect region 51 is located directly below each base region 4; the second junction field effect region 52 is located on the side wall of each base region 4; wherein, one side of each first junction field effect region 51 close to the second junction field effect region 52 is connected to the bottom of each second junction field effect region 52 to form at least two junction field effect regions 5 covering each base region 4.
[0140] It should be noted that each junction field effect region 5 corresponds to and covers each base region 4, that is, each base region 4 corresponds to each junction field effect region 5 one by one; and each base region 4 is spaced apart in the first direction (for example, the X direction), and each junction field effect region 5 has a gap in the first direction (for example, the X direction).
[0141] For example, please refer to Fig.12 , the orthographic projection of the first junction field effect region 51 in the second direction (eg, the Y direction) coincides with the orthographic projection of the base region 4 in the second direction (eg, the Y direction).
[0142] For example, please refer to Fig.12 There is a gap between the second junction field effect regions 52 corresponding to two adjacent base regions 4 in the first direction (eg, X direction).
[0143] For example, the first junction field effect region 51 is formed by a self-aligned vertical ion implantation process, and the second junction field effect region 52 is formed by a self-aligned oblique angle ion implantation process.
[0144] In some embodiments, see Fig.11 or Fig.12The semiconductor structure further includes a first-type doping region 6 and a second-type doping region 7; the first-type doping region 6 is located in the base region 4; the second-type doping region 7 is located on a side of the first-type doping region 6 away from the junction field effect region 5 in the first direction.
[0145] For example, the conductivity type of the first-type doping region 6 is a first conductivity type (eg, N-type); the conductivity type of the second-type doping region 7 is a second conductivity type (eg, P-type).
[0146] The present application also provides a semiconductor device according to some embodiments, and the semiconductor device may include the semiconductor structure in some of the above embodiments. The semiconductor device also has the technical advantages of the above semiconductor structure and its manufacturing method. It should be noted that the parts that are the same or corresponding to the above embodiments can refer to the corresponding description of the above embodiments, and will not be described in detail below.
[0147] In some embodiments, the semiconductor device includes a silicon carbide (SiC) planar power device.
[0148] By way of example, the semiconductor device may be a vertical double diffused metal oxide semiconductor field effect transistor (Vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor, VDMOSFET for short) device.
[0149] In the description of this specification, the description with reference to the terms "some embodiments", "some examples", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
[0150] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0151] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: include: providing an epitaxial layer; forming a first mask layer on one side of the epitaxial layer; The first mask layer has a first mask pattern for defining a base region; Based on the first mask layer, at least two base regions are formed in the epitaxial layer and are spaced apart and distributed on both sides of the first mask layer along a first direction; Based on the first mask layer, forming at least two junction field effect regions covering each of the base regions; Wherein, the junction field effect region is formed by a self-alignment process.
2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The junction field effect region includes a first junction field effect region and a second junction field effect region; and based on the first mask layer, forming at least two junction field effect regions covering each of the base regions includes: Based on the first mask layer, forming the first junction field effect region directly below each of the base regions; Based on the first mask layer, forming the second junction field effect region on the sidewall of each of the base regions; Wherein, a side of each of the first junction field effect regions close to the second junction field effect region is connected to a bottom of each of the second junction field effect regions to form at least two junction field effect regions covering each of the base regions.
3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The first junction field effect region is formed by a self-aligned vertical implantation process, and the second junction field effect region is formed by a self-aligned oblique implantation process.
4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that: The value range of the ion implantation angle of the second junction field effect region includes 0° to 60°.
5. The method for manufacturing a semiconductor structure according to any one of claims 1 to 4, characterized in that: The conductivity type of the junction field effect region is the same as the conductivity type of the epitaxial layer; and the doping concentration of the junction field effect region is greater than the doping concentration of the epitaxial layer.
6. The method for manufacturing a semiconductor structure according to any one of claims 1 to 4, characterized in that: Each of the junction field effect regions has a gap in the first direction.
7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Before forming the first mask layer on one side of the epitaxial layer, the method for manufacturing the semiconductor structure further includes: forming an oxide layer covering a surface of one side of the epitaxial layer; Wherein, the first mask layer is formed on a side of the oxide layer away from the epitaxial layer.
8. The method for manufacturing a semiconductor structure according to claim 1, wherein: After forming the junction field effect region covering each of the base regions based on the first mask layer, the method for manufacturing the semiconductor structure further includes: forming a second mask layer on one side of the base region; the second mask layer having a second mask pattern for defining a first type doping region; Based on the second mask layer, forming the first type doping region in the base region; removing the first mask layer and the second mask layer; forming a third mask layer on one side of the epitaxial layer; the third mask layer having a third mask pattern for defining a second type doping region; Based on the third mask layer, forming a second type doping region on a side of the first type doping region away from the junction field effect region in the first direction; The third mask layer is removed to obtain a semiconductor structure.
9. A semiconductor structure, characterized in that: include: Epitaxial layer; At least two base regions are spaced apart and distributed in the epitaxial layer along a first direction; At least two junction field effect regions, covering each of the base regions; Wherein, each of the junction field effect regions has a gap in the first direction.
10. The semiconductor structure according to claim 9, characterized in that: Also includes: A first type doping region, located in the base region; The second type doping region is located at a side of the first type doping region away from the junction field effect region in the first direction.