Power device with asymmetric structure

Abstract

The invention discloses a power device with an asymmetric structure, and relates to the field of semiconductor devices, the power device comprises a semiconductor substrate of a first conduction type and an active region prepared in a central region of the semiconductor substrate, the active region internally comprises a plurality of cells distributed in parallel, each cell comprises an asymmetric structure and a gate structure, and the gate structure is arranged in the asymmetric structure. The asymmetric structure comprises a second conductive type shielding region, the composite gate structure at least comprises a trench gate unit, and the trench gate unit comprises a cellular trench; the second conductive type shielding region covers the first groove angle of the cellular groove and extends from the first groove angle to the first outer side wall and the groove bottom of the cellular groove. According to the power device, the internal electric field distribution is optimized through an asymmetric structure, and the conduction capability and the voltage resistance of the device are improved.

Description

Technical Field

[0001] The invention relates to the field of semiconductor devices, in particular to a power device with an asymmetric structure. Background Art

[0002] Power semiconductor devices have the advantages of fast switching speed, low power consumption, and high power density, and are widely used in consumer electronics, industrial equipment, and aerospace. The cell structure of power semiconductor devices usually adopts a symmetrical structure, which cannot improve the local effect of the electric field in the device in a targeted manner and brings greater switching losses, which is not conducive to improving the comprehensive capabilities of the device such as voltage resistance, low loss, and reliability. Summary of the invention

[0003] In view of the above problems and technical requirements, the inventors have proposed a power device with an asymmetric structure. The technical solution of the present invention is as follows:

[0004] A power device with an asymmetric structure comprises a semiconductor substrate of a first conductivity type and an active region prepared in the central region of the semiconductor substrate, wherein the active region comprises a plurality of cells distributed in parallel, the cells comprise an asymmetric structure, the asymmetric structure comprises a gate structure and a shielding region of a second conductivity type, wherein:

[0005] The gate structure at least includes a trench gate unit, and the trench gate unit includes a cell trench;

[0006] The second conductive type shielding region covers a first groove corner of the cell groove and extends from the first groove corner to a first outer side wall and a groove bottom of the cell groove.

[0007] A further technical solution is that a first base region of the second conductivity type is disposed on the first side of the cell trench, a second base region of the second conductivity type is disposed on the second side of the cell trench, a first source region of the first conductivity type is disposed in the first base region of the second conductivity type, and a second source region of the first conductivity type is disposed in the second base region of the second conductivity type;

[0008] The second conductivity type first base region is located above the second conductivity type shielding region and in contact with the second conductivity type shielding region, and a second conductivity type heavily doped region is disposed in the second conductivity type first base region;

[0009] The second conductive type heavily doped region is disposed between the first conductive type first source region and the second conductive type shielding region, and the second conductive type heavily doped region is in contact with the first conductive type first source region, the second conductive type shielding region and the first outer sidewall of the cell trench;

[0010] The second conductive type heavily doped region is uniformly doped or gradually doped, wherein:

[0011] When the second conductivity type heavily doped region is uniformly doped, the doping concentration of the second conductivity type heavily doped region is greater than the doping concentration of the second conductivity type first base region;

[0012] When the second conductivity type heavily doped region is gradually doped, the doping concentration of the second conductivity type heavily doped region gradually decreases in the direction from the first sidewall of the cell trench to the second conductivity type first base region and / or in the direction from the second conductivity type shielding region to the first conductivity type first source region.

[0013] A further technical solution is that a second conductive type first source region is disposed on a side of the second conductive type first base region away from the cell trench, and a second conductive type second source region is disposed on a side of the second conductive type second base region away from the cell trench;

[0014] The junction depth of the second conductivity type first source region is greater than the junction depth of the second conductivity type first base region, and the junction depth of the second conductivity type second source region is greater than the junction depth of the second conductivity type second base region;

[0015] The junction depth between the second conductivity type first source region and the second conductivity type second source region is not greater than the junction depth of the second conductivity type shielding region;

[0016] The junction depth between the second conductivity type first source region and the second conductivity type second source region is not less than the trench depth of the cell trench.

[0017] A further technical solution is that the asymmetric structure further includes a first conductive type JFET region;

[0018] The first conductive type JFET region is located between the second conductive type first source region and the second conductive type first base region, and is in contact with both the second conductive type first source region and the second conductive type first base region;

[0019] The junction depth of the second conductivity type first source region is not less than the junction depth of the first conductivity type JFET region, and the junction depth of the first conductivity type JFET region is not less than the junction depth of the second conductivity type first base region.

[0020] A further technical solution is that the first conductive type JFET region is in Schottky contact with a contact metal on the semiconductor substrate to form a Schottky diode;

[0021] The contact metal is electrically connected to a first electrode metal for forming a first electrode.

[0022] A further technical solution is that the gate structure is a composite gate structure, and when the gate structure is a composite gate structure, it also includes a planar gate unit;

[0023] The planar gate unit is electrically connected to the trench gate unit, and both the planar gate unit and the trench gate unit are electrically connected to a second electrode metal for forming a second electrode above the semiconductor substrate;

[0024] The planar gate unit overlaps with the second conductivity type shielding region, the second conductivity type first base region, the first conductivity type first source region and the first conductivity type JFET region.

[0025] A further technical solution is that the planar gate unit includes a planar gate oxide layer prepared on a semiconductor substrate, and a planar gate electrode body prepared on the planar gate oxide layer;

[0026] The trench gate unit includes a trench gate oxide layer and a trench gate electrode body prepared in a cell trench. The trench gate electrode body is electrically connected to a planar gate electrode body, and the trench gate electrode body is insulated and isolated from the cell trench by the trench gate oxide layer.

[0027] A further technical solution is that a second conductive type first buried region is arranged below the second conductive type shielding region, and the second conductive type first buried region is in contact with the second conductive type shielding region.

[0028] A further technical solution is that a second conductive type second buried region is provided below the second conductive type first source region and / or the second conductive type second source region;

[0029] The second conductivity type first source region and the second conductivity type second source region are in contact with the corresponding second conductivity type second buried region, and the second conductivity type first buried region and the second conductivity type second buried region are separated by a semiconductor substrate.

[0030] A further technical solution is that the second conductive type shielding region is prepared by a multi-angle ion implantation process, and the multi-angle ion implantation process includes:

[0031] Injecting second conductive type doping ions into the semiconductor substrate at a first injection angle through the bottom of the cell trench to prepare a first preliminary shielding area covering part or all of the bottom of the cell trench;

[0032] Injecting second conductive type doping ions into the semiconductor substrate at a second injection angle through the first inner sidewall of the cell trench to prepare a second preliminary shielding region covering a portion of the first outer sidewall of the cell trench;

[0033] The first preliminary shielding area and the second preliminary shielding area are connected as one to form a second conductive type shielding area;

[0034] The first implantation angle and the second implantation angle are angles between the implanted ion beam and the first sidewall of the cell trench, and the first implantation angle is smaller than the second implantation angle.

[0035] Among the “first conductivity type” and “second conductivity type”, for N-type power devices, the first conductivity type refers to N-type, and the second conductivity type is P-type; for P-type power devices, the types referred to by the first conductivity type and the second conductivity type are opposite to those of N-type devices.

[0036] The beneficial technical effects of the present invention are:

[0037] The present invention optimizes the electric field distribution and suppresses the parasitic effects of power devices by setting an asymmetric structure, thereby preventing the triggering of parasitic bipolar transistors, reducing conduction losses, reducing the risk of latch-up effects, and improving the voltage resistance of the device. The asymmetric structure includes a P-type shielding area, which can improve the local effect of the electric field in the device in a targeted manner. In addition, the design of the asymmetric structure can better manage heat distribution, optimize on-resistance, and thus improve the comprehensive performance of the device, such as thermal stability and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a cross-sectional view of a power device with an asymmetric structure provided in Embodiment 1 of the present invention.

[0039] Figure 2 It is a cross-sectional view of a power device with an asymmetric structure provided in the second embodiment of the present invention.

[0040] Figure 3 It is a schematic diagram of a power device with an asymmetric structure provided in Embodiment 3 of the present invention.

[0041] Figure 4 The power device provided in the third embodiment of the present invention is Figure 3 Cross-sectional view along the xz plane at AA'.

[0042] Figure 5 It is a top view schematic diagram of a power device provided in the third embodiment of the present invention.

[0043] Figure 6 It is a cross-sectional view of a power device with an asymmetric structure provided in Embodiment 4 of the present invention.

[0044] Figure 7 It is a cross-sectional view of a power device with an asymmetric structure provided in Embodiment 5 of the present invention.

[0045] Figure 8 It is a cross-sectional view of a power device with an asymmetric structure provided in Embodiment 6 of the present invention.

[0046] Fig. 9 It is a process schematic diagram of the multi-angle ion implantation process provided by the present invention.

[0047] Figure numerals: 1-substrate, 2-N-type buffer layer, 3-N-type drift region, 4-N-type current spreading layer, 5-P-type shielding region, 6-cell trench, 7-trench gate oxide layer, 8-trench gate polysilicon, 9-P-type heavily doped region, 10-first electrode metal, 111-P-type first base region, 112-P-type second base region, 121-N-type first source region, 122-N-type second source region, 131-P-type first source region, 132-P-type second source region, 14-third electrode metal, 15-N-type JFET region, 16-contact metal, 17-planar gate oxide layer, 18-planar gate electrode body, 19-P-type first buried region, 20-P-type second buried region, 101-first source metal, 102-second source metal, 103-third source metal. DETAILED DESCRIPTION

[0048] The specific implementation of the present invention is further described below in conjunction with the drawings and examples.

[0049] The present invention provides a power device with an asymmetric structure. Taking the first conductivity type as N-type as an example, in one embodiment of the present invention, the power device includes an N-type semiconductor substrate and an active area prepared in the central area of ​​the semiconductor substrate, wherein the active area includes a plurality of cells distributed in parallel, and the cells include an asymmetric structure, and the asymmetric structure includes a gate structure and a P-type shielding area 5, wherein:

[0050] The gate structure at least includes a trench gate unit, and the trench gate unit includes a cell trench 6;

[0051] The P-type shielding region 5 covers a first groove corner of the cell groove 6 and extends from the first groove corner to a first outer side wall and a groove bottom of the cell groove 6 .

[0052] Specifically, the semiconductor substrate can be made of existing common materials, such as silicon substrate, silicon carbide substrate, etc., to meet application requirements. The semiconductor substrate generally has a front side and a back side corresponding to the front side. For a power device, it generally includes an active area located on the semiconductor substrate and a terminal protection area surrounding the active area. The specific functions and distribution states of the active area and the terminal protection area can be consistent with the prior art. Generally, the active area includes a number of parallel distributed cells, and the cells generally adopt the same structural form.

[0053] The asymmetric structure described in the present invention specifically refers to that the asymmetric structure is asymmetrically arranged about the longitudinal center axis of the cell, and the longitudinal direction is the thickness direction of the semiconductor substrate. The P-type shielding region 5 only covers the first outer side wall, the first groove corner and part or all of the bottom of the cell groove 6, forming an "L"-shaped semi-enclosed structure around the cell groove 6, that is, the P-type shielding region 5 is asymmetrically arranged about the longitudinal center axis of the cell on the cross section of the cell.

[0054] Compared with the symmetrically arranged P-type shielding area 5, the asymmetrically arranged P-type shielding area 5 has the advantages of optimizing the electric field distribution, reducing the electric field concentration area, increasing the breakdown voltage, and reducing the on-resistance. Specifically, the symmetrically arranged shielding area refers to the symmetry of the shielding area about the central axis of the cell groove 6, covering the bottom of the groove and part of the side walls on both sides of the cell groove 6. Although this design will produce a uniform electric field distribution on both sides and the bottom of the groove, which helps to balance the overall electric field, in some areas (such as the groove corners and the groove bottom), the electric field may be over-concentrated. This electric field concentration can cause local breakdown of the device, especially under high-voltage application conditions. Therefore, although the symmetrical setting can provide better electric field shielding, it is often difficult to divert the electric field away from the groove corners, resulting in an excessively strong electric field at the groove corners, thereby increasing the breakdown risk and limiting the breakdown voltage of the device, and is only suitable for low-voltage applications.

[0055] The asymmetrically arranged P-type shielding region 5 provided in the present invention only covers one side corner of the cell groove 6 and extends toward one side cell side wall, i.e., the side where the P-type shielding region 5 is located, and the bottom of the groove. The core advantage of the asymmetrically arranged P-type shielding region 5 is that it can effectively guide the electric field distribution, move the electric field away from the easily breakdown parts of the groove (such as the groove corner and the groove bottom), avoid electric field concentration, thereby solving the problem of excessive local electric field, significantly reducing the risk of local breakdown, and improving the voltage resistance and reliability of the device.

[0056] At the same time, since the P-type shielding region 5 is only distributed in a part of the periphery of the groove, the asymmetrically arranged P-type shielding region 5 usually has a lower on-resistance (R_on) than the symmetrically arranged P-type shielding region 5, thereby improving the efficiency and conduction performance of the device. Although the asymmetrically arranged P-type shielding region 5 has a higher complexity in the manufacturing process and a higher requirement for the process than the symmetrically arranged P-type shielding region 5, the asymmetrically arranged P-type shielding region 5 can effectively optimize the electric field distribution, reduce the breakdown risk, and has greater advantages in improving the breakdown voltage and reducing the on-resistance, thereby improving the overall performance of the device and making the device more suitable for high-voltage and high-power applications.

[0057] The asymmetrically arranged P-type shielding region 5 can also optimize the current path and improve the overall performance of the device. Since the doping concentration of the P-type shielding region 5 is generally high and has a high threshold voltage, the sidewall of the cell trench 6 on the side where it is located will not form a conductive channel, which limits the unnecessary leakage path on the side and ensures that the carriers on the other side flow effectively, so that the main current channel remains clear, reducing the overall on-resistance of the device and reducing the conduction loss, which is conducive to the efficient operation of the device in high-power applications. In addition, the P-type shielding region 5 does not affect the switching characteristics of the other side while improving the withstand voltage performance on the side, so that the device can withstand high withstand voltage while also having good switching characteristics and better overall performance.

[0058] At the same time, the P-type shielding region 5 can also limit the charge accumulation in the peripheral area of ​​the cell trench 6, prevent the electric field concentration under high voltage from inducing the conduction of the parasitic bipolar transistor (BJT), and effectively suppress the occurrence of latch-up phenomenon. The formation form of the parasitic bipolar transistor is consistent with the prior art. In summary, wrapping the P-type shielding region 5 only at the groove corner on one side of the cell trench 6 has multiple advantages compared to the symmetrical setting, including optimizing the electric field distribution, improving the overall performance of the device, reducing parasitic effects and optimizing the current flow path. This design can provide effective protection for the high efficiency and reliability of high-voltage power devices, so that they can show better performance in applications.

[0059] Further, a P-type first base region 111 is disposed on the first side of the cell trench 6, a P-type second base region 112 is disposed on the second side of the cell trench 6, and an N-type first source region 121 is disposed in the P-type first base region 111, and an N-type second source region 122 is disposed in the P-type second base region 112;

[0060] The P-type first base region 111 is located above the P-type shielding region 5 and contacts the P-type shielding region 5 , and a P-type heavily doped region 9 is disposed in the P-type first base region 111 ;

[0061] The P-type heavily doped region 9 is disposed between the N-type first source region 121 and the P-type shielding region 5 , and the P-type heavily doped region 9 is in contact with the N-type first source region 121 , the P-type shielding region 5 and the first outer sidewall of the cell trench 6 ;

[0062] The P-type heavily doped region 9 is uniformly doped or gradually doped, wherein:

[0063] When the P-type heavily doped region 9 is uniformly doped, the doping concentration of the P-type heavily doped region 9 is greater than the doping concentration of the P-type first base region 111 ;

[0064] When the P-type heavily doped region 9 is gradually doped, the doping concentration of the P-type heavily doped region 9 gradually decreases from the first side wall of the cell trench 6 to the P-type first base region 111 and / or from the P-type shielding region 5 to the N-type first source region 121 .

[0065] Figure 1 1 shows a cross-sectional view of a first embodiment of a power device of the present invention, Figure 1 In the figure, the left side of the cell trench 6 is taken as the first side of the cell trench 6, and the right side of the cell trench 6 is taken as the second side of the cell trench 6. The P-type first base region 111 and the N-type first source region 121 both extend vertically from the front side to the back side of the semiconductor substrate, and the N-type first source region 121 contacts the first outer side wall of the cell trench 6. The P-type second base region 112 and the N-type second source region 122 both extend vertically from the front side to the back side of the semiconductor substrate, and the P-type second base region 112 and the N-type second source region 122 contact the second outer side wall of the cell trench 6. Generally, the junction depth of the N-type first source region 121 is less than the junction depth of the P-type first base region 111, and the junction depth of the N-type second source region 122 is less than the junction depth of the P-type second base region 112. The doping concentration of the P-type shielding region 5 is greater than the doping concentration of the P-type first base region 111 and the P-type second base region 112, so as to ensure a stronger electric field control capability and higher device reliability. The typical doping concentration range of the P-type first base region 111 and the P-type second base region 112 is 1×10 16 cm -3 to 1×10 17 cm -3 The typical doping concentration range of the P-type shielding region 5 is 1×10 17 cm -3 to 1×10 19 cm -3 .

[0066] The P-type heavily doped region 9 is disposed between the N-type first source region 121 and the P-type shielding region 5, and is in contact with both the N-type first source region 121 and the P-type shielding region 5. Figure 1 As shown, the P-type heavily doped region 9 extends from the bottom of the N-type first source region 121 along the first outer side wall of the cell trench 6 to the P-type shielding region 5, so that the P-type first base region 111 is isolated from the first outer side wall of the cell trench 6 by the P-type heavily doped region 9. When the doping concentration of the P-type heavily doped region 9 is greater than the doping concentration of the P-type first base region 111, the region of the P-type first base region 111 close to the first outer side wall of the cell trench 6 has a higher doping concentration. Since the P-type first base region 111 is a key part of the formation of the parasitic BJT, increasing the P-type ion doping concentration of the P-type first base region 111 close to the cell trench 6 helps to control the trench electric field and reduce the risk of the parasitic BJT being turned on. In addition, since the latch-up effect is usually triggered by parasitic devices such as parasitic BJTs, after the P-type heavily doped region 9 is provided in the P-type first base region 111, the latch-up effect can be suppressed by reducing the triggering opportunity of the parasitic devices.

[0067] At the same time, the P-type heavily doped region 9 also contributes to the uniform distribution of the electric field, reduces the electric field concentration near the first side wall of the cell trench 6, and thus improves the voltage resistance and reliability of the device. In addition, since a higher P-type ion doping concentration can better limit the movement of carriers and reduce unnecessary leakage current channels, the P-type heavily doped region 9 can also reduce the leakage current near the first side wall of the cell trench 6.

[0068] Preferably, the P-type heavily doped region 9 is gradually doped and the doping concentration of the P-type heavily doped region 9 gradually decreases in the direction from the first side wall of the cell trench 6 to the P-type first base region 111, and in the direction from the P-type shielding region 5 to the N-type first source region 121, that is, the doping concentration of the P-type heavily doped region 9 is gradually distributed in both the horizontal and vertical directions, and, when the doping concentration of the P-type heavily doped region 9 is gradually distributed, the maximum doping concentration of the P-type heavily doped region 9 is less than the doping concentration of the P-type shielding region 5, and the minimum doping concentration of the P-type heavily doped region 9 is greater than the doping concentration of the P-type first base region 111, so as to optimize the smooth transition of the electric field and further enhance the electrical performance of the device. The vertical direction is the thickness direction of the semiconductor substrate, and the horizontal direction is perpendicular to the vertical direction.

[0069] In the lateral gradient of the P-type heavily doped region 9, the doping concentration of the region closer to the first side wall of the cell groove 6 is higher to enhance the shielding effect on the electric field; the doping concentration of the region farther away from the first side wall of the cell groove 6 is lower to reduce the impact on the leakage current and maintain good conduction characteristics at the same time. In the longitudinal gradient of the P-type heavily doped region 9, the doping concentration of the region closer to the bottom of the cell groove 6 is higher to improve the shielding effect of the bottom of the groove and enhance the withstand voltage performance of the device; the doping concentration of the region farther away from the bottom of the cell groove 6 is lower to prevent the increase of the on-resistance and optimize the switching performance of the device. In short, when the doping concentration of the P-type heavily doped region 9 is set in a gradient, it can further optimize the electric field distribution, reduce leakage current, and improve the withstand voltage performance and reliability of the device.

[0070] Furthermore, a P-type first source region 131 is disposed on a side of the P-type first base region 111 away from the cell trench 6 , and a P-type second source region 132 is disposed on a side of the P-type second base region 112 away from the cell trench 6 ;

[0071] The junction depth of the P-type first source region 131 is greater than the junction depth of the P-type first base region 111, the junction depth of the P-type second source region 132 is greater than the junction depth of the P-type second base region 112, the junction depths of the P-type first source region 131 and the P-type second source region 132 are not greater than the junction depth of the P-type shielding region 5; the junction depths of the P-type first source region 131 and the P-type second source region 132 are not less than the groove depth of the cell trench 6.

[0072] Specifically, the P-type first source region 131 and the P-type second source region 132 both extend vertically from the front side of the semiconductor substrate to the back side of the semiconductor substrate, and the junction depths of the P-type first source region 131 and the P-type second source region 132 are similar to the junction depth of the P-type shielding region 5, that is, the junction depths of the P-type first source region 131 and the P-type second source region 132 are equal to or slightly smaller than the junction depth of the P-type shielding region 5, so as to enhance the uniform distribution of the electric field in the semiconductor substrate. Since the main function of the P-type shielding region 5 is to suppress electric field concentration, making the junction depths of the P-type first source region 131 and the P-type second source region 132 similar to the junction depth of the P-type shielding region 5 helps the P-type shielding region 5 to more effectively suppress electric field concentration, further reduce parasitic effects, especially suppress the conduction of parasitic BJTs, prevent the occurrence of latch-up effects, etc., and improve the reliability of the device.

[0073] The junction depth between the P-type first source region 131 and the P-type second source region 132 is greater than or equal to the groove depth of the cell groove 6. Preferably, the junction depth between the P-type first source region 131 and the P-type second source region 132 is greater than the groove depth of the cell groove 6, thereby moving the high electric field area downward from the bottom of the cell groove 6, extending the electric field to the area outside the bottom of the groove, and reducing the local electric field intensity at the bottom of the cell groove 6. By extending the electric field and reducing the electric field concentration, the peak electric field distribution at the bottom of the cell groove 6 is significantly improved. Thereby reducing the risk of electric field concentration and breakdown, and improving the voltage resistance of the device.

[0074] The semiconductor substrate described in the first embodiment includes, from bottom to top, an N-type substrate 1, an N-type buffer layer 2, an N-type drift region 3, and an N-type current expansion layer 4, wherein the N-type current expansion layer 4 is a CSL (Current Spreading Layer) layer, wherein the doping concentrations of the N-type substrate 1, the N-type buffer layer 2, and the N-type current expansion layer 4 are all greater than the doping concentration of the N-type drift region 3, and the N-type current expansion layer 4 can help the current to be more evenly distributed in the device, reduce the local high current density, and improve the device's impact resistance. The first embodiment of the P-type shielding region 5, the cell trench 6, the P-type heavily doped region 9, the P-type first base region 111, the P-type second base region 112, the P-type first source region 131, and the P-type second source region 132 are all located in the N-type current expansion layer 4. In specific implementation, the P-type shielding region 5, the P-type first source region 131, and the P-type second source region 132 may also partially extend into the N-type drift region 3.

[0075] The N-type second source region 122, the P-type first source region 131, the P-type first base region 111, the P-type second base region 112, and the P-type second source region 132 are all in ohmic contact with the first electrode metal for forming the first electrode 10 above the semiconductor substrate. When the gate structure only includes a trench gate unit, since the side wall of the cell trench 6 on the side where the P-type shielding region 5 is located does not form a conductive channel, the N-type first source region 121 can be set in a floating state or in ohmic contact with the first electrode metal 10. The trench gate unit also includes a trench gate oxide layer 7 prepared in the cell trench 6 and a trench gate electrode body 8, and the trench gate electrode body 8 is in ohmic contact with the second electrode metal for forming the second electrode above the semiconductor substrate. The N-type substrate 1 is in ohmic contact with the third electrode metal 14 for forming the third electrode on the back of the semiconductor substrate. The power device described in the present invention can form a MOSFET type device or an IGBT type device. For a MOSFET type device, the first electrode is a source electrode, the second electrode is a gate electrode, and the third electrode is a drain electrode. For an IGBT type device, the first electrode is an emitter, the second electrode is a gate, and the third electrode is a collector. The power device in the first embodiment is a MOSFET type device.

[0076] Furthermore, the asymmetric structure further includes an N-type JFET region 15;

[0077] The N-type JFET region 15 is located between the P-type first source region 131 and the P-type first base region 111 , and is in contact with both the P-type first source region 131 and the P-type first base region 111 ;

[0078] The junction depth of the P-type first source region 131 is not less than the junction depth of the N-type JFET region 15 , and the junction depth of the N-type JFET region 15 is not less than the junction depth of the P-type first base region 131 .

[0079] Specifically, the junction depth of the N-type JFET region 15 is greater than or equal to the junction depth of the P-type first base region 131, because the N-type JFET region 15 needs a sufficient depth to form a current path, especially when the device is turned on, the N-JFET region 15 with a deeper junction depth helps to reduce the on-resistance (R_on), reduce the conduction loss, enhance the current conduction capability and reduce the current density concentration phenomenon, thereby improving the conduction efficiency and overall performance of the device. In addition, the doping concentration of the N-type JFET region 15 is usually greater than the doping concentration of the N-type current expansion layer 4, because the N-type JFET region 15 requires a higher doping concentration to ensure that its current path has a smaller on-resistance, while the N-type current expansion layer 4 requires a lower doping concentration to maintain the high voltage resistance of the power device.

[0080] The N-type JFET region 15 is only arranged on the first side of the cell trench 6 corresponding to the P-type shielding region 5, that is, an asymmetric arrangement is formed. The N-type JFET region 15 can cooperate with the P-type shielding region 5 to further optimize the electric field distribution, reduce the influence of parasitic effects, suppress the generation of latch effects and further reduce the loss during the switching process, thereby improving the efficiency of the power device and making it suitable for high-frequency application scenarios. In addition, the asymmetric arrangement of the N-type JEFT region and the P-type shielding region 5 allows the overall size of the device to be reduced without sacrificing the performance of the device while achieving electric field optimization and parasitic effect suppression, and can obtain the same or even better electrical performance at a smaller device size, reduce the manufacturing cost of the power device, and make the power device suitable for applications with smaller packages or higher power densities.

[0081] Further, the N-type JFET region 15 is in Schottky contact with a contact metal 16 on the semiconductor substrate to form a Schottky diode;

[0082] The contact metal 16 is electrically connected to the first electrode metal 10 for forming a first electrode.

[0083] Specifically, Figure 2 The cross-sectional view of the second embodiment of the power device of the present invention is shown. The power device shown in the second embodiment is a MOSFET type device. The difference between the second embodiment and the first embodiment is that an N-type JFET region 15 is provided in the second embodiment, and the N-type JEFT region 15 is in Schottky contact with the contact metal 16 to integrate the Schottky diode into the device, wherein the contact metal 16 is electrically connected to the first electrode metal as the anode of the Schottky diode, and the third electrode metal is used as the cathode of the Schottky diode. The Schottky diode has a lower forward voltage drop, can optimize the reverse recovery characteristics of the power device, and reduce the switching loss. At the same time, since the Schottky diode is formed based on the N-type JFET region 15, the doping concentration of the N-type JFET region 15 is relatively high and has a low resistance characteristic. The low resistance characteristic of the N-type JFET region 15 can reduce the forward voltage drop of the Schottky diode when it is forward-conducted, thereby reducing power loss.

[0084] In addition, the Schottky diode formed by the N-type JFET region 15, in combination with the P-type shielding region 5, the P-type first source region 131, the P-type heavily doped region 9 and the P-type first base region 111, can also bring about unique electric field management and current optimization effects, thereby improving the key performance of the device. Specifically, the P-type shielding region 5, the P-type first base region 111 and the P-type heavily doped region 9 in the P-type first base region 111 can reduce the electric field strength during the reverse recovery of the Schottky diode, thereby improving the reverse recovery characteristics of the Schottky diode, reducing the reverse recovery loss, and further improving the efficiency and reliability of the device in high-frequency applications. The P-type first source region 131 and the P-type first base region 111, which are respectively located on both sides of the N-type JFET region 15, have a high doping concentration and can be used as a parasitic current blocking layer to prevent carriers from leaking to the N-type JFET region when the Schottky diode is turned off, thereby reducing leakage current. The P-type shielding region 5, the P-type first source region 131, the P-type heavily doped region 9 and the P-type first base region 111 can also optimize the electric field distribution near the Schottky diode to prevent the electric field from being too concentrated near the Schottky diode, causing breakdown or performance degradation, thereby improving the voltage resistance of the device and reducing the risk of failure in high-voltage applications.

[0085] Furthermore, the gate structure is a composite gate structure, and when the gate structure is a composite gate structure, it also includes a planar gate unit;

[0086] The planar gate unit is electrically connected to the trench gate unit, and both the planar gate unit and the trench gate unit are electrically connected to a second electrode metal for forming a second electrode above the semiconductor substrate;

[0087] The planar gate unit overlaps with the P-type shielding region 5 , the P-type first base region 111 , the N-type first source region 121 and the N-type JFET region 15 .

[0088] Figure 3 A schematic diagram of a third embodiment of a power device is shown. The power device in the third embodiment is also a MOSFET device. The difference between the third embodiment and the first embodiment is that the gate structure is a composite gate structure, including a planar gate unit and a trench gate unit, and an N-type JFET region 15 is provided. Figure 4 for Figure 3The cross-sectional view along the xz plane at AA'. The planar gate unit overlaps with the P-type shielding region 5, the P-type first base region 111, the N-type first source region 121 and the N-type JFET region 15, which specifically means that when the planar gate unit is projected onto the P-type shielding region 5, the P-type first base region 111, the N-type first source region 121 and the N-type JFET region 15 respectively, the projection of the planar gate unit overlaps with the P-type shielding region 5, the P-type first base region 111, the N-type first source region 121 and the N-type JFET region 15. When the gate structure is a composite gate, the N-type first source region 121, the N-type second source region 122, the P-type first base region 111, the P-type second base region 112, the P-type first source region 131 and the P-type second source region 132 are in ohmic contact, and the planar gate unit is only arranged on one side of the trench gate unit corresponding to the P-type shielding region 5 and the N-type JFET region 15, that is, an asymmetric composite gate structure is formed. When the device is forward-conducted, two conductive channels along the z-axis direction and along the x-axis direction can be generated based on the composite gate structure, optimizing the current path, effectively preventing current crowding, increasing current density, and reducing on-resistance. The conductive channel is Figure 3 to Figure 4 In the channel region shown in the figure, since the P-type heavily doped region 9 and the P-type shielding region 5 have a higher threshold voltage, the current path flowing through the conductive channel in the lateral direction, i.e., along the x-axis direction, does not pass through the P-type heavily doped region 9 and the P-type shielding region 5, but flows along the interface between the P-type heavily doped region 9 and the P-type first base region 111, and the interface between the P-type shielding region 5 and the current spreading layer 4.

[0089] Figure 5 The top view of the third embodiment is shown. Figure 3 The schematic diagram of the xy plane is shown in FIG. Figure 5 The black rectangles in the figure all represent the first electrode metal 10, i.e., the source metal in the MOSFET device. For ease of description, all source metals are sequentially referred to as the first source metal 101, the second source metal 102, and the third source metal 103 from left to right, wherein the second source metal 102 is divided into two parts, upper and lower, respectively located on the upper and lower sides of the planar gate unit. The first source metal 101 is in ohmic contact with the P-type first source region 131, the second source metal 102 is in ohmic contact with the N-type first source region 121 and the P-type first base region 111, and the third source metal 103 is in ohmic contact with the N-type second source region 122, the P-type second base region 112, and the P-type second source region 132.

[0090] Furthermore, the planar gate unit includes a planar gate oxide layer 17 prepared on a semiconductor substrate, and a planar gate electrode body 18 prepared on the planar gate oxide layer 17 , and the trench gate electrode body 8 is electrically connected to the planar gate electrode body 18 .

[0091] In the third embodiment, the planar gate electrode body 18 and the trench gate electrode body 8 are connected as one body to complete the electrical connection. In a specific implementation, the planar gate electrode body 18 and the trench gate electrode body 8 can also be electrically connected through a lead. Figure 6 A cross-sectional view of a power device in Embodiment 4 is shown. Figure 6 As shown, the difference between the fourth embodiment and the third embodiment is that in the fourth embodiment, the planar gate electrode body 18 is separated from the trench gate electrode body 8 and is electrically connected through a lead. The material of the planar gate electrode body 18 and the trench gate electrode body 8 can be polysilicon or metal, and the material of the planar gate oxide layer 17 and the trench gate oxide layer 7 can be silicon dioxide. In specific implementation, the materials of the planar gate electrode body 18, the trench gate electrode body 8, the planar gate oxide layer 17 and the trench gate oxide layer 7 can be selected according to actual needs.

[0092] The structure of the planar gate electrode body 18 and the trench gate electrode body 8 connected as one body as shown in the third embodiment can achieve a narrow cell pitch and a smaller cell size, which can be flexibly selected for actual use, thereby optimizing the manufacturing process and device layout. The structure of the planar gate electrode body 18 and the trench gate electrode body 8 separated as shown in the fourth embodiment can achieve a wide cell pitch and a larger cell size, which is convenient for heat distribution management.

[0093] Furthermore, a P-type first buried region 19 is disposed below the P-type shielding region 5 , and the P-type first buried region 19 is in contact with the P-type shielding region 5 .

[0094] Figure 7 FIG. 4 shows a cross-sectional view of a power device in Embodiment 5, as shown in FIG. Figure 7 As shown, the difference between the fifth embodiment and the fourth embodiment is that the fifth embodiment is provided with a P-type first buried region 19 below the P-type shielding region 5, and the P-type first buried region 19 can further optimize the electric field distribution, improve the breakdown voltage, and reduce the electric field peak inside the device. In addition, the P-shielding region 5 and the P-type first buried region 19 are in contact to form a more continuous potential gradient, further improve the withstand voltage performance of the device, and improve the control of leakage current.

[0095] Furthermore, a P-type second buried region 20 is disposed below the P-type first source region 131 and / or the P-type second source region 132;

[0096] The P-type first source region 131 and the P-type second source region 132 are in contact with the corresponding P-type second buried region 20 , and the P-type first buried region 19 and the P-type second buried region 20 are separated by a semiconductor substrate.

[0097] Preferably, a P-type second buried region 20 is disposed below the P-type first source region 131 and the P-type second source region 132. Figure 8 A cross-sectional view of a power device in Embodiment 6 is shown. Figure 8As shown, the difference between the sixth embodiment and the fifth embodiment is that the sixth embodiment is provided with a P-type second buried region 20 below the P-type first source region 131 and the P-type second source region 132. Similarly, the P-type second buried region 20 can also further optimize the electric field distribution and improve the breakdown voltage. The P-type first buried region 19 and the P-type second buried region 20 are separated by the N-type drift region 3 and the N-type current extension layer 4 to retain the current path. It should be noted that the above-mentioned first to sixth embodiments all take MOSFET type devices as an example to illustrate the structure of the power device.

[0098] Furthermore, the P-type shielding region 5 is prepared by a multi-angle ion implantation process, and the multi-angle ion implantation process includes:

[0099] Injecting P-type doping ions into the semiconductor substrate through the bottom of the cell trench 6 at a first injection angle to prepare a first preliminary shielding area covering part or all of the bottom of the cell trench 6;

[0100] Injecting P-type doping ions into the semiconductor substrate through the first inner sidewall of the cell trench 6 at a second injection angle to prepare a second preliminary shielding region covering a portion of the first outer sidewall of the cell trench 6;

[0101] The first preliminary shielding region and the second preliminary shielding region are connected as one to form a P-type shielding region 5;

[0102] The first implantation angle and the second implantation angle are angles between the implanted ion beam and the first sidewall of the cell trench 6 , and the first implantation angle is smaller than the second implantation angle.

[0103] The P-type shielding region 5 can be accurately prepared in a designated area through a multi-angle ion implantation process, so as to adjust the electric field and optimize the breakdown voltage of the device. Fig. 9 A schematic diagram of a multi-angle ion implantation process is shown. In this embodiment, a first preliminary shielding region is prepared first and then a second preliminary shielding region is prepared. In specific implementation, the preparation order of the first preliminary shielding region and the second preliminary shielding region can be selected according to actual conditions. After the cell trench 6, the P-type first base region 111, the P-type second base region 112, the N-type first source region 121 and the N-type first source region 122 are prepared on the semiconductor substrate by the existing common process, P-type doping ions are injected into the N-type current spreading layer 4 in the semiconductor substrate through the bottom of the cell trench 6 at a first injection angle α to prepare the first preliminary shielding region located at the bottom of the cell trench 6.

[0104] For high voltage devices, in order to enhance electric field control and withstand voltage performance at high voltage, the implantation dose of P-type doping ions is usually high, close to 1×10 15 cm -2For low voltage devices, in order to maintain a low on-resistance, the implantation dose of P-type doping ions is usually low, around 1×10 13 cm -2 to 5×10 13 cm -2 Generally speaking, the implantation dose of the P-type doping ions is usually between 1×10 13 cm -2 to 1×10 15 cm -2 The specific dosage depends on the device's operating voltage, withstand voltage requirements, required electric field shielding level and the need to suppress parasitic effects. During specific implementation, the ion implantation dosage is determined to ensure that while providing sufficient electric field shielding effect, it does not cause excessive resistance or degradation of other device parameters.

[0105] P-type doping ions are injected into the N-type current spreading layer 4 in the semiconductor substrate through the first inner sidewall of the cell trench 6 at a second injection angle β to prepare a second preliminary shielding region covering a portion of the first outer sidewall of the cell trench 6, and the first preliminary shielding region and the second preliminary shielding region are connected as a whole to form a P-type shielding region 5. The first injection angle α may range from 7° to 15°, and the second injection angle β may range from 15° to 30°.

[0106] When the P-type heavily doped region 9 has a uniform doping concentration greater than that of the P-type first base region 111, the P-type heavily doped region 9 can be prepared in the P-type first base region 111 simultaneously with the preparation of the second preliminary shielding region, that is, when the P-type doping ions are injected into the N-type current spreading layer 4, part of the P-type doping ions are also injected into the P-type first base region 111 at the same time, so that the doping concentration of the P-type first base region 111 close to the first side wall region of the cell trench 6 is increased to form the P-type heavily doped region 9.

[0107] When preparing the power device, the planar gate electrode 18 and the trench gate electrode 8 can be formed by depositing multiple layers of polysilicon or metal materials. The metal material can be tungsten or titanium silicon compounds, and can be achieved through a selective deposition process (SACVD) or atomic layer deposition (ALD) technology to ensure good gate control and conduction characteristics.

[0108] It should be noted that the words "front", "rear", "left", "right", "upper" and "lower" used in the above description refer to directions in the drawings of the present application specification, and the words "front" and "back", "inner" and "outer" refer to directions toward or away from a specific component, respectively. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0109] The above is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the protection scope of the present invention.

Claims

1. A power device with an asymmetric structure, characterized in that: It comprises a semiconductor substrate of a first conductivity type and an active area prepared in the central area of ​​the semiconductor substrate, wherein the active area comprises a plurality of cells distributed in parallel, the cells comprise a gate structure and an asymmetric structure, the asymmetric structure comprises a shielding area of ​​a second conductivity type, wherein: The gate structure at least includes a trench gate unit, and the trench gate unit includes a cell trench; The second conductive type shielding region covers a first groove corner of the cell groove and extends from the first groove corner to a first outer side wall and a groove bottom of the cell groove.

2. The power device with an asymmetric structure according to claim 1, characterized in that: A first base region of the second conductivity type is disposed on the first side of the cell trench, a second base region of the second conductivity type is disposed on the second side of the cell trench, a first source region of the first conductivity type is disposed in the first base region of the second conductivity type, and a second source region of the first conductivity type is disposed in the second base region of the second conductivity type; The second conductivity type first base region is located above the second conductivity type shielding region and in contact with the second conductivity type shielding region, and a second conductivity type heavily doped region is disposed in the second conductivity type first base region; The second conductive type heavily doped region is disposed between the first conductive type first source region and the second conductive type shielding region, and the second conductive type heavily doped region is in contact with the first conductive type first source region, the second conductive type shielding region and the first outer sidewall of the cell trench; The second conductive type heavily doped region is uniformly doped or gradually doped, wherein: When the second conductivity type heavily doped region is uniformly doped, the doping concentration of the second conductivity type heavily doped region is greater than the doping concentration of the second conductivity type first base region; When the second conductivity type heavily doped region is gradually doped, the doping concentration of the second conductivity type heavily doped region gradually decreases in the direction from the first sidewall of the cell trench to the second conductivity type first base region and / or in the direction from the second conductivity type shielding region to the first conductivity type first source region.

3. The power device with an asymmetric structure according to claim 2, characterized in that: A second conductive type first source region is disposed on a side of the second conductive type first base region away from the cell trench, and a second conductive type second source region is disposed on a side of the second conductive type second base region away from the cell trench; The junction depth of the second conductivity type first source region is greater than the junction depth of the second conductivity type first base region, and the junction depth of the second conductivity type second source region is greater than the junction depth of the second conductivity type second base region; The junction depth between the second conductivity type first source region and the second conductivity type second source region is not greater than the junction depth of the second conductivity type shielding region; The junction depth between the second conductivity type first source region and the second conductivity type second source region is not less than the trench depth of the cell trench.

4. The power device with an asymmetric structure according to claim 3, characterized in that: The asymmetric structure also includes a first conductivity type JFET region; The first conductive type JFET region is located between the second conductive type first source region and the second conductive type first base region, and is in contact with both the second conductive type first source region and the second conductive type first base region; The junction depth of the second conductivity type first source region is not less than the junction depth of the first conductivity type JFET region, and the junction depth of the first conductivity type JFET region is not less than the junction depth of the second conductivity type first base region.

5. The power device with an asymmetric structure according to claim 4, characterized in that: The first conductive type JFET region is in Schottky contact with a contact metal above the semiconductor substrate to form a Schottky diode; The contact metal is electrically connected to a first electrode metal for forming a first electrode.

6. The power device with an asymmetric structure according to claim 4, characterized in that: The gate structure is a composite gate structure, and when the gate structure is a composite gate structure, it also includes a planar gate unit; The planar gate unit is electrically connected to the trench gate unit, and both the planar gate unit and the trench gate unit are electrically connected to a second electrode metal for forming a second electrode above the semiconductor substrate; The planar gate unit overlaps with the second conductivity type shielding region, the second conductivity type first base region, the first conductivity type first source region and the first conductivity type JFET region.

7. The power device with an asymmetric structure according to claim 6, characterized in that: The planar gate unit includes a planar gate oxide layer prepared on a semiconductor substrate, and a planar gate electrode body prepared on the planar gate oxide layer; The trench gate unit includes a trench gate oxide layer and a trench gate electrode body prepared in a cell trench. The trench gate electrode body is electrically connected to a planar gate electrode body, and the trench gate electrode body is insulated and isolated from the cell trench by the trench gate oxide layer.

8. The power device with an asymmetric structure according to claim 2, characterized in that: A second conductive type first buried region is disposed below the second conductive type shielding region, and the second conductive type first buried region is in contact with the second conductive type shielding region.

9. The power device with an asymmetric structure according to claim 8, characterized in that: A second conductive type second buried region is disposed below the second conductive type first source region and / or the second conductive type second source region; The second conductivity type first source region and the second conductivity type second source region are in contact with the corresponding second conductivity type second buried region, and the second conductivity type first buried region and the second conductivity type second buried region are separated by a semiconductor substrate.

10. The power device with an asymmetric structure according to claim 8, characterized in that: The second conductive type shielding region is prepared by a multi-angle ion implantation process, and the multi-angle ion implantation process includes: Injecting second conductive type doping ions into the semiconductor substrate at a first injection angle through the bottom of the cell trench to prepare a first preliminary shielding area covering part or all of the bottom of the cell trench; Injecting second conductive type doping ions into the semiconductor substrate at a second injection angle through the first inner sidewall of the cell trench to prepare a second preliminary shielding region covering a portion of the first outer sidewall of the cell trench; The first preliminary shielding area and the second preliminary shielding area are connected as one to form a second conductive type shielding area; The first implantation angle and the second implantation angle are angles between the implanted ion beam and the first sidewall of the cell trench, and the first implantation angle is smaller than the second implantation angle.

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