LED epitaxial wafer for ultra-large current and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, and discloses an LED epitaxial wafer for ultra-large current and a preparation method thereof, the LED epitaxial wafer comprises a substrate, and an AlN layer, a buffer layer, a first GaN layer, a second GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, an electron barrier layer and a P-type GaN layer are sequentially arranged on the substrate; the stress release layer is of a periodic structure, each periodic structure comprises a third GaN layer, an In < x > Ga < 1-x > N layer and an Al < y > Ga < 1-y > N layer which are stacked in sequence, the third GaN layer, the In < x > Ga < 1-x > N layer and the Al < y > Ga < 1-y > N layer are subjected to recrystallization treatment after growth, and the recrystallization treatment is carried out in the atmosphere of N2 and NH3 at the temperature higher than or equal to 800 DEG C. By implementing the LED epitaxial wafer, stress can be released, the growth quality of the multi-quantum well layer is improved, and the luminous efficiency is ensured. Meanwhile, the working voltage of the LED chip under the ultra-large current can be reduced, and the luminance and the reliability are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductors, and in particular to an ultra-high current LED epitaxial wafer and a preparation method thereof. Background Art

[0002] LED chips are semiconductor electronic components that emit light. They are compact, bright, and consume little energy. Consequently, they are widely used in lighting and other fields. LED chips are obtained by splitting LED epitaxial wafers, which consist of a substrate and a GaN epitaxial layer grown on top of it.

[0003] Currently, sapphire, silicon, or silicon carbide are commonly used as substrates. Different LED chip applications require different chip structures. For example, large-scale flip-chip or vertical chip structures require higher terminal application currents, typically exceeding 800mA or even 1.5A, while conventional lighting applications typically do not exceed 150mA. When LED epitaxial wafers designed for conventional, lower currents are operated at ultra-high currents, the resulting LED chips' luminous efficiency rapidly degrades, and reliability also decreases. Therefore, improving the performance of LED chips under ultra-high currents has become a technical challenge that urgently needs to be overcome. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide an LED epitaxial wafer for ultra-high current and a preparation method thereof, which is used to reduce the operating voltage of the LED chip under ultra-high current and improve the luminous efficiency and reliability of the LED chip under ultra-high current.

[0005] In order to solve the above technical problems, the first aspect of the present invention provides an ultra-high current LED epitaxial wafer, comprising a substrate, on which an AlN layer, a buffer layer, a first GaN layer, a second GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer are sequentially arranged; The stress release layer is a periodic structure, and each periodic structure includes a third GaN layer, an In layer, and a plurality of GaN layers stacked in sequence. x Ga 1-x N layer and Al y Ga 1-y N layer, the third GaN layer, In x Ga 1-x N layer and Al y Ga 1-y The N layer is further subjected to a recrystallization treatment after growth, wherein the recrystallization treatment is performed at a temperature ≥ 800° C. in an atmosphere of N 2 and NH 3 .

[0006] As an improvement of the above scheme, when the recrystallization treatment is carried out, the temperature is 800℃~1000℃, the N2 flow rate is 20slm~200slm, the NH3 flow rate is 50slm~300slm, the N2 introduction time is 0.5min~2min, and the NH3 introduction time is 0.5min~2min.

[0007] As an improvement to the above solution, the number of cycles of the stress release layer is 1 to 6.

[0008] As an improvement of the above solution, the In x Ga 1-x In the N layer, 0<x<1; The Al y Ga 1-y In the N layer, 0<y<1.

[0009] As an improvement of the above solution, the In x Ga 1-x N layer and Al y Ga 1-y The thickness ratio of the N layer is 1:0.25~1:4.

[0010] As an improvement of the above solution, the In x Ga 1-x The thickness of the N layer is 0.5nm~2nm; The Al y Ga 1-y The thickness of the N layer is 0.5nm~2nm.

[0011] As an improvement of the above solution, the thickness of the third GaN layer is 5 nm to 30 nm.

[0012] As an improvement to the above scheme, the growth temperature of the third GaN layer is 800°C to 1000°C, the growth pressure is 100 torr to 300 torr, the growth atmosphere is NH3, N2 and H2, the flow rate of NH3 and NH3 is 70 mL / min to 150 mL / min, the flow rate of N2 is 7 mL / min to 150 mL / min, and the flow rate of H2 is 7 mL / min to 75 mL / min; In x Ga 1-x The growth temperature of the N layer is 800℃~1000℃, the growth pressure is 100torr~300torr, the growth atmosphere is NH3, N2 and H2, the flow rate of NH3 is 70mL / min~150mL / min, the flow rate of N2 is 7mL / min~150mL / min, and the flow rate of H2 is 7mL / min~75mL / min; The Aly Ga 1-y The growth temperature of the N layer is 800℃~1000℃, the growth pressure is 100torr~300torr, the growth atmosphere is NH3, N2 and H2, the NH3 flow rate is 70mL / min~150mL / min, the N2 flow rate is 7mL / min~150mL / min, and the H2 flow rate is 7mL / min~75mL / min.

[0013] The second aspect of the present invention further provides a method for preparing the ultra-high current LED epitaxial wafer, comprising: providing a substrate; growing an AlN layer on a substrate; growing a buffer layer on the AlN layer; growing a first GaN layer on the buffer layer; growing a second GaN layer on the first GaN layer; growing an N-type GaN layer on the second GaN layer; growing a stress relief layer on the N-type GaN layer; growing a multi-quantum well layer on the stress release layer; growing an electron blocking layer on the multi-quantum well layer; Growing a P-type GaN layer on the electron blocking layer; The stress release layer is a periodic structure, and each periodic structure includes a third GaN layer, an In layer, and a plurality of GaN layers stacked in sequence. x Ga 1-x N layer and Al y Ga 1-y N layer, the third GaN layer, In x Ga 1-x N layer and Al y Ga 1-y The N layer is further subjected to a recrystallization treatment after growth, wherein the recrystallization treatment is performed at a temperature ≥ 800° C. in an atmosphere of N 2 and NH 3 .

[0014] As an improvement of the above solution, the method for preparing the stress release layer includes: The temperature of the reaction chamber is controlled to be 800°C to 1000°C and the pressure is controlled to be 100 torr to 300 torr. NH3, N2, H2 and Ga sources are introduced to grow the third GaN layer. The temperature of the reaction chamber is controlled at 800℃~1000℃, the pressure is 100torr~300torr, and NH3, N2, H2, In source and Ga source are introduced to grow In x Ga 1-x N-layer; The temperature of the reaction chamber is controlled to be 800℃~1000℃, the pressure is 100torr~300torr, and NH3, N2, H2, Al source and Ga source are introduced to grow Al y Ga 1-y N-layer; The temperature of the reaction chamber is controlled at 800°C to 1000°C and the pressure is controlled at 100 torr to 300 torr. NH3 and N2 are introduced and maintained for 0.5 to 2 minutes for recrystallization to complete one cycle of growth. The layered growth is repeated according to a preset number of cycles to complete the periodic growth of the stress release layer.

[0015] The implementation of the present invention has the following beneficial effects: In the present invention, a stress release layer is provided between the N-type GaN layer and the multi-quantum well layer to release stress, wherein the stress release layer is a periodic structure, and each periodic structure includes a third GaN layer, an In layer, and a plurality of GaN layers stacked in sequence. x Ga 1-x N layer and Al y Ga 1-y N layer, the third GaN layer, In x Ga 1-x N layer and Al y Ga 1-y The N layer is also recrystallized after growth. The recrystallization process is carried out at a temperature of ≥800°C in an atmosphere of N2 and NH3. This can release the stress caused by lattice mismatch and thermal expansion coefficient difference, improve the growth quality of the multi-quantum well layer, and ensure the luminous efficiency of the LED chip. y Ga 1-y The setting of N layer and recrystallization layer effectively reduces In x Ga 1-x The size of the V-pits introduced during the growth of the N layer also promotes the uniform distribution of the V-pits, which reduces the operating voltage of the LED chip under ultra-high current, and further improves the luminous brightness, luminous efficiency and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 : A schematic structural diagram of an LED epitaxial wafer for ultra-high current in the present invention; Figure 2 : A schematic structural diagram of the stress release layer of the present invention; Figure 3 : AFM image of the epitaxial wafer provided in Example 1; Figure 4 : AFM image of the epitaxial wafer provided in Comparative Example 1.

[0017] Reference numerals: 1-substrate; 2-AlN layer; 3-buffer layer; 4-first GaN layer; 5-second GaN layer; 6-N-type GaN layer; 7-stress release layer; 71-third GaN layer; 72-In x Ga 1-x N layer; 73-Al y Ga 1-y N layer; 8-multi-quantum well layer; 9-electron blocking layer; 10-P-type GaN layer. DETAILED DESCRIPTION

[0018] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail with reference to specific embodiments below.

[0019] Currently, conventional LED epitaxial wafers consist of a substrate on which are sequentially arranged an AlN layer, a buffer layer, a first GaN layer, a second GaN layer, an N-type GaN layer, a stress relief layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer. The stress relief layer is a periodic structure of alternating InGaN and GaN layers. However, LED chips formed from these epitaxial wafers experience rapid degradation in luminous efficiency and reliability when exposed to extremely high currents.

[0020] To solve the above problems, the present invention provides an LED epitaxial wafer for ultra-high current, see Figure 1 , comprising a substrate 1, on which an AlN layer 2, a buffer layer 3, a first GaN layer 4, a second GaN layer 5, an N-type GaN layer 6, a stress release layer 7, a multi-quantum well layer 8, an electron blocking layer 9 and a P-type GaN layer 10 are sequentially arranged; It should be noted that the ultra-large current in the embodiment of the present invention refers to a current applied by the terminal that is greater than 800 mA.

[0021] Among them, see Figure 2 The stress release layer 7 is a periodic structure, each periodic structure includes a third GaN layer 71, an In x Ga 1-x N layer 72 and Al y Ga 1-y N layer 73, the third GaN layer 71, In x Ga 1-x N layer 72 and Al y Ga 1- y The N layer 73 is further recrystallized after growth. The recrystallization treatment is performed at a temperature ≥ 800° C. in an atmosphere of N 2 and NH 3 . The number of periods of the stress release layer 7 is 1 to 6, exemplarily 1, 2, 3, 4, 5, 6, and preferably 2 to 5.

[0022] Due to lattice mismatch and differences in thermal expansion coefficients, a large amount of stress will be generated during the growth of GaN on the substrate 1. Therefore, providing a stress release layer 7 between the N-type GaN layer 6 and the multi-quantum well layer 8 can release the stress and improve the subsequent growth quality of the multi-quantum well layer 8. At the same time, it can also reduce the aggregation of electrons and holes to a certain extent, reduce the probability of non-radiative recombination, improve the luminous efficiency of the chip in many aspects, and improve the reliability of the chip and extend its service life.

[0023] Specifically, the third GaN layer 71, In x Ga 1-x The N layer 72 can release stress and reduce lattice mismatch, thereby reducing dislocation and stress concentration caused by lattice mismatch. x Ga 1-x During the growth of the N layer 72, defects are introduced, and these defects will form V-pits (V-shaped holes) as they grow. Under ultra-high current conditions, V-pits will cause electrons and holes to aggregate to a certain extent, thereby concentrating at concentrated locations and generating a large amount of non-radiative recombination, which will reduce the luminous efficiency on the one hand and generate heat on the other hand to damage the epitaxial layer, eventually causing the chip to fail. In the third GaN layer 71, In x Ga 1-x Al continues to grow on the N layer 72 y Ga 1-y N layer 73, and the grown third GaN layer 71, In x Ga 1-x N layer 72 and Al y Ga 1-y The N layer 73 is subjected to recrystallization treatment, which can reduce the size of V-pits and improve the distribution of V-pits, thereby improving the luminous efficiency and reliability of the epitaxial wafer under ultra-high current conditions.

[0024] Preferably, the third GaN layer 71 is a non-doped GaN layer, which can promote the release of lattice mismatch stress between the substrate 1 and the GaN epitaxial material. Such release helps to reduce the formation of dislocations, thereby improving the crystal quality of the epitaxial wafer.

[0025] Furthermore, the thickness of the third GaN layer 71 is 5 nm to 30 nm, and exemplary thicknesses are 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, and 30 nm, but not limited thereto.

[0026] Preferably, the In x Ga 1-x In the N layer 72, 0<x<1, In x Ga 1-xThe proportion of In components in the N layer 72 can adjust the stress state, thereby reducing dislocation and stress concentration caused by lattice mismatch and further improving the crystal quality. x Ga 1-x The proportion x of the In component in the N layer 72 is exemplarily 0.01, 0.05, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 0.95, but is not limited thereto; more preferably, In x Ga 1-x In the N layer 72, 0.01<x<0.5. x Ga 1-x During the growth process of the N layer 72, defects are introduced, and these defects will form V-pits as they grow and extend. The formation of V-pits can improve the luminous efficiency to a certain extent, and the morphology and density of V-pits are also different under different current applications. Under ultra-high current applications, both electrons and holes can obtain enough electrical energy to migrate, so it is necessary to improve the lateral current expansion and reduce the aggregation of electrons and holes. V-pits will promote the aggregation of electrons and holes to a certain extent, causing a large number of electrons and holes to gather in a concentrated position and produce a large amount of non-radiative recombination. On the one hand, it will reduce the luminous efficiency, and on the other hand, it will also generate heat to damage the epitaxial layer, and ultimately cause the chip to fail. Therefore, reducing the size of V-pits and improving the distribution of V-pits have become the technical direction for improving the performance of epitaxial wafers under ultra-high current conditions.

[0027] Furthermore, the Al y Ga 1-y The Al atoms in the N layer 73 are relatively small and can fill the gaps of the V-pits, which can reduce the opening of the V-pits to a certain extent, that is, reduce the size of the V-pits. y Ga 1-y In the N layer 73, 0<y<1, and the content of the Al component is reasonably regulated, which can further regulate the distribution of V-pits, reduce non-radiative recombination, and thus improve the luminous efficiency and the reliability of the epitaxial layer. y Ga 1-y The proportion y of the Al component in the N layer 73 is exemplarily 0.01, 0.05, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 0.95, 0.99, but is not limited thereto; more preferably, the Al y Ga 1-y In the N layer 73, 0.1<y<0.5.

[0028] Furthermore, the In x Ga 1-x N layer 72 and Al y Ga 1-yThe thickness ratio of the N layer 73 is 1:0.25 to 1:4. x Ga 1-x N layer 72 and Al y Ga 1-y The N layer 73 cooperates with each other, which can not only effectively release the stress caused by lattice mismatch, but also control the size and distribution of V-pits, further improving the reliability of the epitaxial wafer. x Ga 1-x N layer 72 and Al y Ga 1-y The thickness ratio of the N layer 73 is exemplarily 1:0.25, 1:0.5, 1:0.75, 1:1, 1:1.25, 1:1.5, 1:1.75, 1:2, 1:2.25, 1:2.5, 1:2.75, 1:3, 1:3.25, 1:3.5, 1:3.75, and 1:4, but is not limited thereto.

[0029] In some embodiments, the In x Ga 1-x The thickness of the N layer 72 is 0.5 nm to 2 nm, and examples thereof are 0.5 nm, 0.75 nm, 1 nm, 1.25 nm, 1.5 nm, 1.75 nm, and 2 nm, but are not limited thereto. In some embodiments, the Al y Ga 1-y The thickness of the N layer 73 is 0.5 nm to 2 nm, and exemplary thicknesses are 0.5 nm, 0.75 nm, 1 nm, 1.25 nm, 1.5 nm, 1.75 nm, and 2 nm, but not limited thereto.

[0030] Preferably, in each cycle, the third GaN layer 71 and the In x Ga 1-x N layer 72 and Al y Ga 1- y The N layer 73 undergoes a recrystallization process at temperatures ≥800°C in an atmosphere of N2 and NH3, eliminating thickness buildup and enabling more precise control of the distribution and size of the V-pits. Specifically, N2 and NH3 are introduced into the reaction chamber at a high temperature of 800°C or higher, causing some of the NH3 to decompose into N2 and H2. The reducing properties of H2 can reduce and separate some of the lower-quality Al, In, and Ga atoms, or allow the Al, In, and Ga atoms to react with NH3 and recrystallize, further improving the distribution of the V-pits.

[0031] Furthermore, when the recrystallization layer treatment is carried out, the temperature is 800℃~1000℃, the N2 flow rate is 20slm~200slm, the NH3 flow rate is 50slm~300slm, the N2 introduction time is 0.5min~2min, and the NH3 introduction time is 0.5min~2min. This can enable the poor quality In, Al, and Ga atoms in the system to be fully reduced and separated or re-react and recrystallize, further improving the crystal quality of the stress release layer 7 and promoting the high-quality growth of the multi-quantum well layer 8 on the stress release layer 7.

[0032] Accordingly, the present invention also provides a method for preparing an ultra-high current LED epitaxial wafer, comprising: (1) Providing a substrate 1; Preferably, the substrate 1 can be one of a sapphire substrate, a SiO2 sapphire composite substrate, a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, and a zinc oxide substrate; more preferably, it is a sapphire substrate. Sapphire is currently the most commonly used GaN-based LED substrate material. Sapphire substrates have mature preparation technology, low price, are easy to clean and handle, and have good stability at high temperatures.

[0033] (2) growing an AlN layer 2 on a substrate 1; Preferably, the AlN layer 2 provides a nucleation center with the same orientation as the substrate 1, releasing the stress generated by the lattice mismatch between GaN and the substrate 1 and the thermal stress generated by the thermal expansion coefficient mismatch, providing a flat nucleation surface for further growth and reducing the contact angle of its nucleation growth.

[0034] Furthermore, the AlN layer 2 is grown by PVD, and the thickness of the AlN layer 2 is 10 nm to 30 nm.

[0035] (3) growing a buffer layer 3 on the AlN layer 2; Preferably, the buffer layer 3 is a GaN layer to further release the thermal stress between the GaN layer and the substrate 1. The buffer layer 3 has a thickness of 15 nm to 35 nm and is grown in an MOCVD device. The subsequent deposition processes are all performed in MOCVD.

[0036] Furthermore, the growth temperature of the buffer layer 3 may be 500° C. to 800° C., and the growth pressure may be 100 torr to 600 torr.

[0037] (4) growing a first GaN layer 4 on the buffer layer 3; Preferably, the first GaN layer 4 is a three-dimensionally grown GaN layer. The growth of the three-dimensional GaN layer can change the dislocation transmission direction, cut off some dislocations, and block the transmission of dislocations, thereby improving the crystal quality of the subsequently grown material.

[0038] Furthermore, the thickness of the first GaN layer 4 is 500 nm to 2000 nm, the growth temperature of the first GaN layer 4 may be 1050° C. to 1100° C., and the growth pressure may be 100 torr to 500 torr.

[0039] (5) growing a second GaN layer 5 on the first GaN layer 4; Preferably, the second GaN layer 5 is an undoped GaN layer. Growing a two-dimensional GaN layer on a three-dimensional GaN layer can timely repair the defects and surface undulations of the three-dimensional GaN layer growth, improve the surface morphology of the material, and obtain an undoped GaN layer with better crystal quality. At the same time, as the GaN thickness increases, the compressive stress will be released through stacking faults, the line defects will be reduced, the crystal quality will be improved, and the reverse leakage will be reduced.

[0040] Furthermore, the thickness of the second GaN layer 5 is 800 nm to 1200 nm, the growth temperature of the second GaN layer 5 may be 1000° C. to 1200° C., and the growth pressure may be 50 torr to 300 torr.

[0041] (6) growing an N-type GaN layer 6 on the second GaN layer 5; Preferably, the N-type GaN layer 6 provides sufficient electrons for LED light emission, and the doping concentration in the N-type GaN layer 6 is 1×10 19 cm -3 ~1×10 20 cm -3 , doping elements include but are not limited to Si.

[0042] Furthermore, the thickness of the N-type GaN layer 6 is 1000 nm to 3000 nm, the growth temperature of the N-type GaN layer 6 may be 1000° C. to 1200° C., and the growth pressure may be 50 torr to 300 torr.

[0043] (7) growing a stress release layer 7 on the N-type GaN layer 6; Preferably, the stress release layer 7 is a periodic structure, and each periodic structure includes a third GaN layer 71, an In layer 72, and a plurality of GaN layers 73 stacked in sequence. x Ga 1-x N layer 72 and Al y Ga 1-y N layer 73, the third GaN layer 71, In x Ga 1-x N layer 72 and Al y Ga 1-y The N layer 73 is further subjected to a recrystallization treatment after growth. The recrystallization treatment is performed at a temperature of ≥800° C. in an atmosphere of N 2 and NH 3 .

[0044] Specifically include: (71) Controlling the temperature of the reaction chamber to 800°C to 1000°C and the pressure to 100 torr to 300 torr, introducing NH3, N2, H2 and Ga sources to grow the third GaN layer 71, wherein NH3 is used as a reaction gas and N2 and H2 are used as carrier gases; Preferably, the ratio of the flow rates of NH3, N2, and H2 is 1:(0.1-1):(0.1-0.5). In some embodiments, the flow rate of NH3 is 70 mL / min-150 mL / min, the flow rate of N2 is 7 mL / min-150 mL / min, and the flow rate of H2 is 7 mL / min-75 mL / min.

[0045] (72) The temperature of the reaction chamber is controlled to 800℃~1000℃, the pressure is 100torr~300torr, and NH3, N2, H2, In source and Ga source are introduced to grow In x Ga 1-x N layer 72, wherein NH3 is used as a reaction gas, and N2 and H2 are used as carrier gases; Preferably, the ratio of the flow rates of NH3, N2, and H2 is 1:(0.1-1):(0.1-0.5). In some embodiments, the flow rate of NH3 is 70 mL / min-150 mL / min, the flow rate of N2 is 7 mL / min-150 mL / min, and the flow rate of H2 is 7 mL / min-75 mL / min.

[0046] (73) The temperature of the reaction chamber is controlled to 800℃~1000℃, the pressure is 100torr~300torr, and NH3, N2, H2, Al source and Ga source are introduced to grow Al y Ga 1-y N layer 73, where NH3 is used as a reaction gas and N2 and H2 are used as carrier gases; Preferably, the ratio of the flow rates of NH3, N2, and H2 is 1:(0.1-1):(0.1-0.5). In some embodiments, the flow rate of NH3 is 70 mL / min-150 mL / min, the flow rate of N2 is 7 mL / min-150 mL / min, and the flow rate of H2 is 7 mL / min-75 mL / min.

[0047] (74) The temperature of the reaction chamber is controlled to 800°C~1000°C, the pressure is 100torr~300torr, NH3 and N2 are introduced and maintained for 0.5min~2min, and recrystallization treatment is performed to complete one cycle of growth; Preferably, the N2 flow rate is 20slm~200slm, and the NH3 flow rate is 50slm~300slm. The N2 flow rate is exemplarily 20slm, 50slm, 75slm, 100slm, 120slm, 150slm, 175slm, and 200slm, but is not limited thereto; the NH3 flow rate is exemplarily 50slm, 75slm, 100slm, 125slm, 150slm, 175slm, 200slm, 225slm, 250slm, 275slm, and 300slm, but is not limited thereto.

[0048] (75) Repeat the stacking growth according to a preset number of cycles to complete the periodic growth of the stress release layer 7.

[0049] (8) growing a multi-quantum well layer 8 on the stress release layer 7; Preferably, the multi-quantum well layer 8 is a periodic structure of alternating InGaN quantum well layers and GaN quantum barrier layers, with the number of stacking periods being 6 to 14. Within a single period, the In composition of the InGaN quantum well layer is 0.1 to 0.5, the thickness of the InGaN quantum well layer is 2 nm to 4 nm, and the thickness of the GaN quantum barrier layer is 8 nm to 12 nm.

[0050] Furthermore, the growth temperature of the InGaN quantum well layer may be 700° C. to 900° C., and the growth pressure may be 50 torr to 300 torr; the growth temperature of the GaN quantum barrier layer may be 800° C. to 900° C., and the growth pressure may be 100 torr to 300 torr.

[0051] (9) growing an electron blocking layer 9 on the multi-quantum well layer 8; Preferably, the electron blocking layer 9 has a periodic structure of alternating AlGaN and GaN layers, with a stacking period of 5 to 15, and a total thickness of 10 nm to 60 nm. Within a single period, the AlGaN layer has an Al content of 0.1 to 0.5, and a thickness of 1 nm to 5 nm; the GaN layer has a thickness of 1 nm to 5 nm. This effectively limits electron overflow and reduces hole blocking, thereby improving the efficiency of hole injection into the multi-quantum well layer 8, reducing carrier Auger recombination, and improving the luminous efficiency of the light-emitting diode.

[0052] Furthermore, the growth temperature of the AlGaN layer may be 800° C. to 1000° C., and the growth pressure may be 50 torr to 200 torr; the growth temperature of the GaN layer may be 800° C. to 1000° C., and the growth pressure may be 50 torr to 200 torr.

[0053] (10) growing a P-type GaN layer 10 on the electron blocking layer 9; Preferably, the doping concentration of the P-type GaN layer 10 is 1×10 20 cm -3 ~1×10 21 cm -3 , doping elements include but are not limited to Mg. Too high a doping concentration will destroy the crystal quality, while a low doping concentration will affect the hole concentration.

[0054] Furthermore, the thickness of the P-type GaN layer 10 is 5 nm to 100 nm, the growth temperature of the P-type GaN layer 10 may be 900° C. to 1050° C., and the growth pressure may be 100 torr to 600 torr.

[0055] It should be noted that the MOCVD used in this invention is a Micro A7 MOCVD (Metal-organic Chemical Vapor Deposition) device to achieve epitaxial wafer growth. A mixture of high-purity H2 (hydrogen) and high-purity N2 (nitrogen) is used as the carrier gas. The nitrogen source is high-purity NH3, the aluminum source is TMAl (trimethylaluminum), the gallium source is TMGa (trimethylgallium), the in source is TMIn (trimethylindium), the silicon source is SiH4 (silane), and the magnesium source is CP2Mg.

[0056] The present invention will be further described below with specific embodiments: Example 1 This embodiment provides an epitaxial wafer for ultra-high current LEDs, comprising a substrate, on which an AlN layer, a buffer layer, a first GaN layer, a second GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer are sequentially arranged; The stress release layer is a periodic structure, and each periodic structure includes a third GaN layer, an In layer, and a plurality of GaN layers stacked in sequence. x Ga 1-x N layer and Al y Ga 1-y N layer, the third GaN layer, In x Ga 1-x N layer and Al y Ga 1-y The N layer is further subjected to a recrystallization treatment after growth. The recrystallization treatment is performed at 900° C. in an atmosphere of N 2 and NH 3 for three cycles.

[0057] The thickness of the third GaN layer is 10 nm; x Ga 1-xThe thickness of the N layer is 1 nm, x=0.3; the Al y Ga 1-y The thickness of the N layer is 1 nm, y=0.2; the recrystallization layer treatment is as follows: the third GaN layer and the In layer are stacked sequentially after growth. x Ga 1-x N layer and Al y Ga 1-y The N layer was recrystallized at 900°C in an atmosphere of N2 and NH3, with an N2 flow rate of 100 slm and an NH3 flow rate of 175 slm. The N2 and NH3 introduction times were both 1 min.

[0058] This embodiment also provides a method for preparing an ultra-high current LED epitaxial wafer, comprising: (1) Providing a substrate; The substrate is a sapphire substrate.

[0059] (2) growing an AlN layer on a substrate; Specifically, an AlN layer is grown in a PVD device, and the thickness of the AlN layer is 20 nm.

[0060] (3) growing a buffer layer on the AlN layer; Specifically, a buffer layer is grown in an MOCVD device. The buffer layer is a GaN layer. The thickness of the buffer layer is 25 nm. The growth temperature is 600° C., and the growth pressure is 200 Torr.

[0061] (4) growing a first GaN layer on the buffer layer; Specifically, a first GaN layer is grown in an MOCVD device. The first GaN layer is a three-dimensionally grown GaN layer. The thickness of the first GaN layer is 1250 nm. The growth temperature is 1075° C. and the growth pressure is 150 Torr.

[0062] (5) growing a second GaN layer on the first GaN layer; Specifically, a second GaN layer is grown in an MOCVD device. The second GaN layer is an undoped GaN layer. The thickness of the second GaN layer is 1000 nm. The growth temperature is 1100° C. and the growth pressure is 150 Torr.

[0063] (6) growing an N-type GaN layer on the second GaN layer; Specifically, an N-type GaN layer is grown in an MOCVD device. The doping element of the N-type GaN layer is Si, and the doping concentration is 5×10 19 cm -3 The thickness of the N-type GaN layer is 2000 nm, the growth temperature is 1100° C., and the growth pressure is 150 Torr.

[0064] (7) growing a stress release layer on the N-type GaN layer; Specifically, in MOCVD equipment, (71) The temperature of the reaction chamber was controlled to be 900°C and the pressure was controlled to be 200 torr. NH3, N2, H2 and Ga sources were introduced to grow the third GaN layer, wherein NH3 was used as the reaction gas and N2 and H2 were used as carrier gases; the flow rate of NH3 was 80 mL / min, the flow rate of N2 was 40 mL / min, and the flow rate of H2 was 24 mL / min; (72) The temperature of the reaction chamber was controlled at 900℃ and the pressure was 200torr. NH3, N2, H2, In source and Ga source were introduced to grow In x Ga 1-x N layer, wherein NH3 is used as the reaction gas, and N2 and H2 are used as carrier gases; the flow rate of NH3 is 80 mL / min, the flow rate of N2 is 40 mL / min, and the flow rate of H2 is 24 mL / min; (73) The temperature of the reaction chamber was controlled at 900℃ and the pressure was 200torr. NH3, N2, H2, Al source and Ga source were introduced to grow Al y Ga 1-y N layer, wherein NH3 is used as the reaction gas, and N2 and H2 are used as carrier gases; the flow rate of NH3 is 80 mL / min, the flow rate of N2 is 40 mL / min, and the flow rate of H2 is 24 mL / min; (74) The temperature of the reaction chamber was controlled to 900 °C and the pressure was 200 torr. NH3 and N2 were introduced and maintained for 1 min to perform recrystallization treatment to complete one cycle of growth. The flow rate of N2 was 100 slm and the flow rate of NH3 was 175 slm. (75) Repeat steps (71) to (74) twice according to a preset number of cycles to complete the periodic growth of the stress release layer.

[0065] (8) growing a multi-quantum well layer on the stress release layer; Specifically, a multi-quantum well layer is grown in an MOCVD device. The multi-quantum well layer is a periodic structure in which InGaN quantum well layers and GaN quantum barrier layers are alternately stacked. The number of stacking periods is 10. In a single period, the In component in the InGaN quantum well layer is 0.2, and the thickness of the InGaN quantum well layer is 3 nm; the thickness of the GaN quantum barrier layer is 10 nm, and the total thickness is 130 nm.

[0066] The growth temperature of the InGaN quantum well layer is 800° C., and the growth pressure is 150 Torr; the growth temperature of the GaN quantum barrier layer is 880° C., and the growth pressure is 150 Torr.

[0067] (9) Growing an electron blocking layer on the multi-quantum well layer; Specifically, an electron blocking layer is grown in an MOCVD device. The electron blocking layer has a periodic structure in which AlGaN layers and GaN layers are alternately stacked. The number of stacking periods is 8. In a single period, the Al component in the AlGaN layer is 0.25, and the thickness of the AlGaN layer is 3 nm. The thickness of the GaN layer is 3 nm, and the total thickness is 48 nm.

[0068] The AlGaN layer is grown at a temperature of 950° C. and a pressure of 100 Torr; the GaN layer is grown at a temperature of 950° C. and a pressure of 100 Torr.

[0069] (10) Growing a P-type GaN layer on the electron blocking layer; Specifically, a P-type GaN layer was grown in an MOCVD device. The doping element of the P-type GaN layer was Mg, and the doping concentration of Mg was 5×10 20 cm -3 The thickness of the P-type GaN layer is 50 nm, the growth temperature is 985° C., and the growth pressure is 200 torr.

[0070] Examples 2 to 12 and Comparative Example 1 are substantially the same as Example 1, except for the setting of parameters related to the stress release layer. Specifically, Examples 2 to 12 and Comparative Example 1 were prepared according to the parameters in Table 1 below.

[0071] Table 1 Parameters of stress release layer in Examples 1 to 12 and Comparative Example 1

[0072] Performance Testing (1) The epitaxial wafers obtained in Example 1 and Comparative Example 1 were subjected to AFM testing. The test results are as follows: Figure 3 and Figure 4 shown.

[0073] Figure 3 This is the AFM image of the epitaxial wafer obtained in Example 1. Figure 4 This is the AFM image of the epitaxial wafer obtained in Comparative Example 1. Figure 3 and Figure 4 Comparative analysis shows that the V-pits in the epitaxial wafer of Example 1 are smaller in size and more evenly distributed, which helps to improve the luminous efficiency of the LED chip.

[0074] (2) The epitaxial wafers obtained in Example 1 and Comparative Example 1 were made into 43 mil*43 mil chips and their reliability was tested at a test current of 1 A, a temperature of 85°C, and a humidity of 85% RH. The test results are shown in Table 2.

[0075] Table 2 Reliability test results of Example 1 and Comparative Example 1

[0076] As can be seen from Table 2, in the present invention, the stress release layer is a periodic structure, and each periodic structure includes a third GaN layer, an In layer, and a plurality of GaN layers stacked in sequence. x Ga 1-x N layer and Al y Ga 1-y N layer, the third GaN layer, In x Ga 1-x N layer and Al y Ga 1-y The N layer undergoes recrystallization treatment after growth, which can effectively improve the reliability of the LED chip under ultra-high current conditions, allowing it to maintain a failure rate of 0% for 1000 hours under high humidity conditions of 85°C and 85%.

[0077] (3) The epitaxial wafers obtained in Examples 1 to 12 and Comparative Example 1 were made into 43mil*43mil chips with a flip-chip structure. 300 LED chips were extracted and tested at a current of 800mA. The operating voltage, luminous brightness and luminous efficiency of the obtained chips were tested. The improvement in luminous efficiency was calculated based on Comparative Example 1.

[0078] The performance test results are shown in Table 3.

[0079] Table 3 Performance test results of examples and comparative examples

[0080] As shown in Table 3, in the present invention, the stress release layer is a periodic structure, and each periodic structure includes a third GaN layer, an In layer, and a plurality of GaN layers stacked in sequence. x Ga 1-x N layer and Al y Ga 1-y N layer, the third GaN layer, In x Ga 1-x N layer and Al y Ga 1-y The N layer undergoes recrystallization after growth, which can reduce the operating voltage of the LED under ultra-high current conditions and improve the luminous brightness and luminous efficiency.

[0081] The above disclosure is only a preferred embodiment of the present invention and certainly cannot be used to limit the scope of the present invention. Therefore, equivalent changes made according to the claims of the present invention are still within the scope of the present invention.

Claims

1. An LED epitaxial wafer for ultra-high current, characterized in that: It comprises a substrate, on which an AlN layer, a buffer layer, a first GaN layer, a second GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, an electron blocking layer and a P-type GaN layer are sequentially arranged; The stress release layer is a periodic structure, each of which includes a third GaN layer, an In x Ga 1-x N layer and Al y Ga 1-y N layer, the third GaN layer, In x Ga 1-x N layer and Al y Ga 1-y The N layer is further subjected to a recrystallization treatment after growth, wherein the recrystallization treatment is performed at a temperature ≥ 800° C. in an atmosphere of N 2 and NH 3 .

2. The LED epitaxial wafer for ultra-high current according to claim 1, characterized in that: When the recrystallization treatment is carried out, the temperature is 800°C~1000°C, the flow rate of N2 is 20slm~200slm, the flow rate of NH3 is 50slm~300slm, the introduction time of N2 is 0.5min~2min, and the introduction time of NH3 is 0.5min~2min.

3. The LED epitaxial wafer for ultra-high current according to claim 1, characterized in that: The number of cycles of the stress release layer is 1 to 6.

4. The LED epitaxial wafer for ultra-high current according to claim 1, characterized in that: In x Ga 1-x In the N layer, 0<x<1; The Al y Ga 1-y In the N layer, 0<y<1.

5. The LED epitaxial wafer for ultra-high current according to claim 1, characterized in that: In x Ga 1-x N layer and Al y Ga 1-y The thickness ratio of the N layer is 1:0.25~1:

4.

6. The LED epitaxial wafer for ultra-high current according to claim 1 or 5, characterized in that: In x Ga 1-x The thickness of the N layer is 0.5nm~2nm; The Al y Ga 1-y The thickness of the N layer is 0.5nm~2nm.

7. The LED epitaxial wafer for ultra-high current according to claim 1, characterized in that: The thickness of the third GaN layer is 5nm-30nm.

8. The LED epitaxial wafer for ultra-high current according to claim 1, characterized in that: The growth temperature of the third GaN layer is 800° C. to 1000° C., the growth pressure is 100 torr to 300 torr, the growth atmosphere is NH3, N2 and H2, the flow rate of NH3 is 70 mL / min to 150 mL / min, the flow rate of N2 is 7 mL / min to 150 mL / min, and the flow rate of H2 is 7 mL / min to 75 mL / min; In x Ga 1-x The growth temperature of the N layer is 800℃~1000℃, the growth pressure is 100torr~300torr, the growth atmosphere is NH3, N2 and H2, the flow rate of NH3 is 70mL / min~150mL / min, the flow rate of N2 is 7mL / min~150mL / min, and the flow rate of H2 is 7mL / min~75mL / min; The Al y Ga 1-y The growth temperature of the N layer is 800℃~1000℃, the growth pressure is 100torr~300torr, the growth atmosphere is NH3, N2 and H2, the flow rate of NH3 is 70mL / min~150mL / min, the flow rate of N2 is 7mL / min~150mL / min, and the flow rate of H2 is 7mL / min~75mL / min.

9. A method for preparing an ultra-high current LED epitaxial wafer according to any one of claims 1 to 8, characterized in that: include: providing a substrate; growing an AlN layer on a substrate; growing a buffer layer on the AlN layer; growing a first GaN layer on the buffer layer; growing a second GaN layer on the first GaN layer; growing an N-type GaN layer on the second GaN layer; growing a stress relief layer on the N-type GaN layer; growing a multi-quantum well layer on the stress release layer; growing an electron blocking layer on the multi-quantum well layer; Growing a P-type GaN layer on the electron blocking layer; The stress release layer is a periodic structure, each of which includes a third GaN layer, an In x Ga 1-x N layer and Al y Ga 1-y N layer, the third GaN layer, In x Ga 1-x N layer and Al y Ga 1-y The N layer is further subjected to a recrystallization treatment after growth, wherein the recrystallization treatment is performed at a temperature ≥ 800° C. in an atmosphere of N 2 and NH 3 .

10. The method for preparing an ultra-high current LED epitaxial wafer according to claim 9, characterized in that: The preparation method of the stress release layer comprises: The temperature of the reaction chamber is controlled to be 800°C to 1000°C, the pressure is 100 torr to 300 torr, NH3, N2, H2 and Ga sources are introduced, and the third GaN layer is grown; The temperature of the reaction chamber is controlled to be 800℃~1000℃, the pressure is 100torr~300torr, and NH3, N2, H2, In source and Ga source are introduced to grow In x Ga 1-x N layers; The temperature of the reaction chamber is controlled to be 800℃~1000℃, the pressure is 100torr~300torr, and NH3, N2, H2, Al source and Ga source are introduced to grow Al y Ga 1-y N layers; The temperature of the reaction chamber is controlled to be 800°C~1000°C, the pressure is 100torr~300torr, NH3 and N2 are introduced and maintained for 0.5min~2min, and a recrystallization treatment is performed to complete a cycle of growth; The layered growth is repeated according to a preset number of cycles to complete the periodic growth of the stress release layer.

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