Isolated integrated circuit, carrier frequency control circuit and modulation signal generation method
By detecting the enablement and disable periods of input signals in the carrier frequency control circuit, the control carrier frequency generation circuit stops outputting the carrier frequency signal during the disable period, solving the increase in power consumption caused by continuous output of carrier frequency signals in the prior art. The problem is that lower circuit power consumption is achieved.
Patent Information
- Application Number
- CN202311047067.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-18
- Publication Date
- 2025-02-21
AI Technical Summary
The prior art still allows the oscillator to output the carrier frequency signal when the carrier frequency signal is not required, resulting in an increase in circuit power consumption.
A carrier frequency control circuit is designed to control the carrier frequency generation circuit to stop outputting the carrier frequency signal during the power-disabled period by detecting the power-disabled period of the input signal. This circuit includes an edge detection circuit, a timing pulse generation circuit and a switch control circuit to ensure that the carrier frequency signal output is effectively stopped during the power disable.
By stopping the carrier frequency signal output during the power disconnection, the power consumption of the circuit is significantly reduced and energy efficiency is improved.
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Figure CN119496488A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a carrier frequency control circuit and a modulation signal generation method, and more particularly to a carrier frequency control circuit and a modulation signal generation method applied to an isolated integrated circuit. Background Art
[0002] In some related technologies for generating a modulation signal, a modulator usually generates a modulation signal by modulating an input signal with a carrier signal output by an oscillator. However, even when the carrier signal is not needed, the oscillator will continue to output the carrier signal, which increases the power consumption of the circuit. Summary of the invention
[0003] One aspect of the present disclosure is an isolated integrated circuit. The isolated integrated circuit includes a primary circuit, an isolation circuit, and a secondary circuit. The primary circuit includes a carrier frequency generating circuit, a carrier frequency control circuit, and a modulation circuit. The carrier frequency generating circuit is used to generate a carrier frequency signal. The carrier frequency control circuit is electrically coupled to the carrier frequency generating circuit, and is used to detect at least one enable period and at least one disable period of an input signal, and is used to control the carrier frequency generating circuit to output the carrier frequency signal during the at least one enable period, and is used to control the carrier frequency generating circuit to stop outputting the carrier frequency signal during the output period of at least one timing pulse during the at least one disable period, wherein the at least one timing pulse is generated in response to detecting the entry into the at least one disable period, and when the output period of one of the at least one timing pulses does not overlap with one of the at least one enable periods adjacent to and located after the at least one timing pulse, the output period of the next of the at least one timing pulses will be adjusted. The modulation circuit is electrically coupled to the carrier frequency generating circuit, and is used to receive the input signal and the carrier frequency signal, and is used to output the modulation signal according to the input signal and the carrier frequency signal. The isolation circuit is coupled to the primary side circuit, and is used to transmit the modulation signal. The secondary side circuit is coupled to the isolation circuit, and is used to receive the modulation signal through the isolation circuit, and is used to generate an output signal according to the modulation signal.
[0004] In some embodiments, the carrier frequency control circuit includes: an edge detection circuit, which is used to output at least one rising signal during the at least one enabling period, and to output at least one falling signal during the at least one disabling period; a timing pulse generating circuit, which is electrically coupled to the edge detection circuit, which is used to output a frequency filtering signal, and is used to adjust the voltage level of the frequency filtering signal according to the at least one falling signal to generate the at least one timing pulse; a switch control circuit, which is electrically coupled to the carrier frequency generating circuit, the edge detection circuit and the timing pulse generating circuit, which is used to control the carrier frequency generating circuit to output the carrier frequency signal according to the at least one rising signal, and is used to control the carrier frequency generating circuit to stop outputting the carrier frequency signal according to the at least one timing pulse; and a delay judgment circuit, which is electrically coupled to the edge detection circuit and the timing pulse generating circuit, and is used to output a judgment signal to control the timing pulse generating circuit according to the frequency filtering signal, the at least one rising signal and the at least one falling signal.
[0005] In some embodiments, the at least one timing pulse includes a current timing pulse corresponding to a current cycle of the input signal, and the at least one rising signal includes a next rising signal corresponding to a next cycle after the current cycle. When the falling edge of the current timing pulse is detected and the next rising signal has not been received, the delay judgment circuit adjusts the voltage level of the judgment signal to generate a delay pulse, so as to control the timing pulse generating circuit to increase the output period of the next timing pulse corresponding to the next cycle in the at least one timing pulse.
[0006] In some embodiments, the timing pulse generating circuit is used to adjust the voltage level of the frequency filtering signal according to the at least one falling signal to sequentially generate at least one first buffer pulse, the at least one timing pulse and the at least one second buffer pulse. The switch control circuit is used to control the carrier frequency generating circuit to output the carrier frequency signal according to the at least one first buffer pulse, and to control the carrier frequency generating circuit to output the carrier frequency signal according to the at least one second buffer pulse.
[0007] One aspect of the present disclosure is a carrier frequency control circuit. The carrier frequency control circuit is electrically coupled to a carrier frequency generating circuit, and is used to receive an input signal, and includes an edge detection circuit, a timing pulse generating circuit, and a switch control circuit. The edge detection circuit is used to output at least one rising signal during at least one enabling period of the input signal, and is used to output at least one falling signal during at least one disabling period of the input signal. The timing pulse generating circuit is electrically coupled to the edge detection circuit, and is used to output a frequency filtering signal, and is used to adjust the voltage level of the frequency filtering signal according to the at least one falling signal to generate the at least one timing pulse, wherein when the output period of one of the at least one timing pulses does not overlap with one of the at least one enabling periods adjacent to and located after the at least one timing pulse, the output period of the next of the at least one timing pulses will be adjusted. The switch control circuit is electrically coupled to the carrier generating circuit, the edge detection circuit and the timing pulse generating circuit, and is used to control the carrier generating circuit to output the carrier signal according to the at least one rising signal, and to control the carrier generating circuit to stop outputting the carrier signal according to the at least one timing pulse.
[0008] In some embodiments, the at least one timing pulse includes a current timing pulse corresponding to a current cycle of the input signal, and the input signal includes a next rising edge corresponding to a next cycle after the current cycle. In the case where the timing of the falling edge of the current timing pulse is before the timing of the next rising edge, the timing pulse generating circuit increases the output period of the next timing pulse corresponding to the next cycle among the at least one timing pulse, so that the output period of the next timing pulse is longer than the output period of the current timing pulse.
[0009] In some embodiments, the timing pulse generating circuit is used to adjust the voltage level of the frequency filtering signal according to the at least one falling signal to sequentially generate at least one first buffer pulse, the at least one timing pulse and the at least one second buffer pulse. The switch control circuit is used to control the carrier frequency generating circuit to output the carrier frequency signal according to the at least one first buffer pulse, and to control the carrier frequency generating circuit to output the carrier frequency signal according to the at least one second buffer pulse.
[0010] In some embodiments, the carrier frequency control circuit further includes: a delay judgment circuit, electrically coupled to the edge detection circuit and the timing pulse generating circuit, and configured to output a judgment signal to control the timing pulse generating circuit according to the frequency filtering signal, the at least one rising signal, and the at least one falling signal. The delay judgment circuit is also configured to adjust the voltage level of the judgment signal to generate at least one delay pulse to control the timing pulse generating circuit to adjust the output period of the at least one timing pulse.
[0011] One aspect of the present disclosure is a method for generating a modulation signal. The method is implemented by an isolated integrated circuit, wherein the isolated integrated circuit includes a carrier frequency generating circuit, a carrier frequency control circuit, and a modulation circuit, and the method includes: the carrier frequency control circuit detects at least one enable period and at least one disable period of an input signal; during the at least one enable period, the carrier frequency control circuit controls the carrier frequency generating circuit to output a carrier frequency signal; during the at least one disable period, the carrier frequency control circuit controls the carrier frequency generating circuit to stop outputting the carrier frequency signal during the output period of at least one timing pulse, wherein the at least one timing pulse is generated in response to detecting the entry into the at least one disable period, and when the output period of one of the at least one timing pulses does not overlap with one of the at least one enable periods adjacent to and following the at least one timing pulse, the output period of the next of the at least one timing pulses is adjusted; and the modulation circuit generates a modulation signal according to the input signal and the carrier frequency signal.
[0012] In some embodiments, the at least one timing pulse includes a current timing pulse corresponding to a current cycle of the input signal, the input signal includes a next rising edge corresponding to a next cycle after the current cycle, and the modulation signal generating method further includes: when the timing of the falling edge of the current timing pulse is before the timing of the next rising edge, the carrier frequency control circuit increases the output period of the next timing pulse corresponding to the next cycle in the at least one timing pulse, so that the output period of the next timing pulse is longer than the output period of the current timing pulse.
[0013] In summary, the carrier frequency control circuit of the present disclosure detects the enable period and disable period of the input signal, and controls the carrier frequency generation circuit to stop outputting the carrier frequency signal during the output period of the timing pulse during the disable period of the input signal. Therefore, compared with the related art that does not stop outputting the carrier frequency signal during the disable period of the input signal, the isolated integrated circuit of the present disclosure has lower power consumption. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 The invention is a block diagram of an isolated integrated circuit according to some embodiments of the present disclosure.
[0015] Figure 2 The following is a timing diagram of some signals related to the operation of the primary-side circuit according to some embodiments of the present disclosure.
[0016] Figure 3A The diagram is a schematic diagram of the operation of a carrier frequency control circuit during an enable period of an input signal according to some embodiments of the present disclosure.
[0017] Figure 3BThe diagram is a schematic diagram of the operation of a carrier frequency control circuit during a disable period of an input signal according to some embodiments of the present disclosure.
[0018] Figure 4 It is a schematic diagram of a modulation signal and an output signal according to some embodiments of the present disclosure.
[0019] Figure 5 The flowchart of a modulation signal generating method is shown according to some embodiments of the present disclosure. DETAILED DESCRIPTION
[0020] The following is a detailed description of the embodiments with the accompanying drawings, but the specific embodiments described are only used to explain the present case and are not used to limit the present case. The description of the structural operation is not used to limit the order of its execution. Any structure recombined by the elements to produce a device with equal functions is within the scope of the present disclosure.
[0021] The terms used throughout the specification and claims generally have the ordinary meanings of each term used in the art, in the context of this disclosure, and in the specific context, unless otherwise noted.
[0022] As used herein, “coupled” or “connected” may refer to two or more elements being in direct physical or electrical contact with each other, or being in indirect physical or electrical contact with each other, or may refer to two or more elements operating or moving with each other.
[0023] See also Figure 1 , Figure 1 FIG. 1 is a block diagram of an isolated integrated circuit 100 according to some embodiments of the present disclosure. In some embodiments, the isolated integrated circuit 100 includes a primary circuit 10, an isolation circuit 20, and a secondary circuit 30. Specifically, the isolated integrated circuit 100 may be a gate driver.
[0024] In some embodiments, such as Figure 1 As shown, one end of the isolation circuit 20 is coupled to the output end of the primary circuit 10, and the other end of the isolation circuit 20 is coupled to the input end of the secondary circuit 30, so as to provide electrical insulation between the primary circuit 10 and the secondary circuit 30 in the isolated integrated circuit 100 in response to system requirements. Accordingly, the primary circuit 10 can use the first power supply voltage VCC1 and the first ground voltage GND1 as operating voltages, and the secondary circuit 30 can use the second power supply voltage VCC2 different from the first power supply voltage VCC1 and the second ground voltage GND2 different from the first ground voltage GND1 as operating voltages. Specifically, the isolation circuit 20 can be implemented by insulating elements such as transformers and capacitors.
[0025] In some embodiments, while ensuring voltage isolation between the primary circuit 10 and the secondary circuit 30 (i.e., the aforementioned electrical insulation), the isolation circuit 20 can also serve as a communication interface between the primary circuit 10 and the secondary circuit 30 to allow data, signals and / or information to be transmitted from the primary circuit 10 to the secondary circuit 30, thereby allowing the isolated integrated circuit 100 to operate normally.
[0026] In some embodiments, such as Figure 1 As shown, the primary side circuit 10 includes a carrier frequency generating circuit 11, a carrier frequency control circuit 13, a modulation circuit 15, a buffer circuit 17 and a transmitting circuit 19. Specifically, the modulation circuit 15 is electrically coupled to the carrier frequency generating circuit 11, the buffer circuit 17 and the transmitting circuit 19, and the carrier frequency control circuit 13 is electrically coupled to the carrier frequency generating circuit 11. One end of the isolation circuit 20 is coupled to the transmitting circuit 19 of the primary side circuit 10 through the output end of the primary side circuit 10. In addition, the secondary side circuit 30 includes a receiving circuit 31 and a demodulation circuit 33. The receiving circuit 31 is coupled to the other end of the isolation circuit 20 through the input end of the secondary side circuit 30, and the demodulation circuit 33 is electrically coupled to the receiving circuit 31.
[0027] Then, pair with Figure 1 and Figure 2 The operation of the primary circuit 10 is further described. Figure 2 The following is a timing diagram of some signals related to the operation of the primary-side circuit 10 according to some embodiments of the present disclosure.
[0028] In some embodiments, such as Figure 1 As shown, the primary side circuit 10 is used to receive the input signal Vin. Figure 2 As shown, the input signal Vin is a periodic signal, such as a pulse width modulation (PWM) signal, and has a period TC. Specifically, the frequency of the input signal Vin can be 100-1 MHz, and the reciprocal of the frequency of the input signal Vin is the period TC.
[0029] In some embodiments, in each cycle TC, the input signal Vin is at the enable level for a period of time and at the disable level for another period of time. Figure 2 As shown, each cycle TC of the input signal Vin has an enable period EA (corresponding to the input signal Vin at an enable level) and a disable period DA (corresponding to the input signal Vin at a disable level).
[0030] For the sake of clarity and convenience, Figure 2In the present disclosure, the numerical indices [1] to [4] are used to refer to individual components or signals, but this does not intend to limit the number of components or signals to a specific number. If only a component or signal symbol is used without specifying the index of the component or signal symbol, it means that the component or signal symbol refers to an unspecified one of the components or signals in the group to which it belongs. For example, the period TC refers to an unspecified one of the periods TC[1] to TC[4].
[0031] In some embodiments, such as Figure 1 As shown, the carrier frequency generating circuit 11 is used to generate a carrier frequency signal Vosi. The carrier frequency signal Vosi is also a periodic signal, and in one embodiment, the frequency of the carrier frequency signal Vosi is about 500 MHz. It can be seen that the frequency of the carrier frequency signal Vosi is higher than the frequency of the input signal Vin. Specifically, the carrier frequency generating circuit 11 can be implemented by an oscillator.
[0032] In some embodiments, such as Figure 1 As shown, the modulation circuit 15 is used to receive the input signal Vin and the carrier signal Vosi buffered by the buffer circuit 17, and to output the modulation signal Vmod according to the input signal Vin and the carrier signal Vosi, so that the transmitting circuit 19 couples the modulation signal Vmod to the isolation circuit 20. Specifically, the modulation circuit 15 can use the carrier signal Vosi to modulate the input signal Vin to generate the modulation signal Vmod. Figure 2 As shown, during the enable period EA of the input signal Vin, the modulation circuit 15 controls the modulation signal Vmod to oscillate at the frequency of the carrier signal Vosi according to the enable level input signal Vin. During the disable period DA of the input signal Vin, the modulation circuit 15 controls the modulation signal Vmod to stop oscillating according to the disable level input signal Vin.
[0033] From the above description of generating the modulation signal Vmod, it can be seen that when the input signal Vin is at the disable level, the carrier signal Vosi basically does not play any role in generating the modulation signal Vmod. However, in some related technologies, the carrier signal is continuously output by the oscillator. In other words, no matter whether the input signal is at the enable level or the disable level, the oscillator will not stop outputting the carrier signal, which results in an increase in the power consumption of the entire circuit in the related technology.
[0034] In view of this, the present disclosure utilizes the carrier frequency control circuit 13 to control the input signal Vin to a disabled level (ie, Figure 2 During the disable period DA), the carrier frequency generating circuit 11 is controlled to stop outputting the carrier frequency signal Vosi within an adjustable time length.
[0035] In some embodiments, such as Figure 1As shown, the carrier frequency control circuit 13 includes an edge detection circuit 131, a timing pulse generating circuit 133, a switch control circuit 135 and a delay determination circuit 137. The carrier frequency control circuit 13 is used to receive an input signal Vin through the edge detection circuit 131. The timing pulse generating circuit 133 is electrically coupled to the edge detection circuit 131. The switch control circuit 135 is electrically coupled to the carrier frequency generating circuit 11, the edge detection circuit 131, the timing pulse generating circuit 133 and the delay determination circuit 137. Moreover, the delay determination circuit 137 is electrically coupled to the edge detection circuit 131 and the timing pulse generating circuit 133.
[0036] Then, pair with Figure 2 and Figure 3A to Figure 3B The operation of the carrier frequency control circuit 13 is further described, wherein Figure 3A FIG. 1 is a schematic diagram of the operation of the carrier frequency control circuit 13 during the enabling period EA of the input signal Vin according to some embodiments of the present disclosure. Figure 3B FIG. 1 is a schematic diagram illustrating the operation of the carrier frequency control circuit 13 during the disable period DA of the input signal Vin according to some embodiments of the present disclosure.
[0037] In some embodiments, the input signal Vin is an enable level. Figure 3A As shown, the edge detection circuit 131 outputs a rising signal Vris according to the input signal Vin of the enable level. In other words, the edge detection circuit 131 outputs the rising signal Vris during the enable period EA of the input signal Vin. The switch control circuit 135 controls the carrier generation circuit 11 to output the carrier signal Vosi according to the rising signal Vris. Specifically, after receiving the rising signal Vris, the switch control circuit 135 can generate an enable signal (not shown in the figure) to the carrier generation circuit 11. Then, the carrier generation circuit 11 outputs the carrier signal Vosi after receiving the enable signal. Therefore, as Figure 2 As shown, during the enable period EA of the input signal Vin, the carrier frequency generating circuit 11 outputs the carrier frequency signal Vosi, so that the modulation circuit 15 controls the modulation signal Vmod to oscillate at the frequency of the carrier frequency signal Vosi.
[0038] In some embodiments, the input signal Vin is at a disable level. Figure 3B As shown, the edge detection circuit 131 outputs the falling signal Vfal according to the input signal Vin of the disable level. In other words, the edge detection circuit 131 outputs the falling signal Vfal during the disable period of the input signal Vin. In some embodiments, as Figure 3A and Figure 3B As shown, the timing pulse generating circuit 133 is used to output the frequency filtering signal Vtpl to the switch control circuit 135. Figure 2 and Figure 3BAs shown, after receiving the falling signal Vfal, the timing pulse generating circuit 133 adjusts the voltage level of the frequency filtering signal Vtpl to sequentially generate a first buffer pulse Ton1, a timing pulse Toff and a second buffer pulse Ton2.
[0039] In some further embodiments, Figure 2 As shown, the frequency filter signal Vtpl is at a reference voltage level during the enable period EA[1] of the input signal Vin. When entering the disable period DA[1] (i.e., when the timing pulse generating circuit 133 receives the falling signal Vfal), the timing pulse generating circuit 133 increases the voltage level of the frequency filter signal Vtpl from the reference voltage level to the preset voltage level at a first slope, and then decreases the voltage level of the frequency filter signal Vtpl from the preset voltage level back to the reference voltage level to generate the first buffer pulse Ton1[1].
[0040] After generating the first buffer pulse Ton1[1], the timing pulse generating circuit 133 increases the voltage level of the frequency filtering signal Vtpl from the reference voltage level to the preset voltage level with a second slope, and then decreases the voltage level of the frequency filtering signal Vtpl from the preset voltage level back to the reference voltage level to generate the timing pulse Toff[1].
[0041] After generating the timing pulse Toff[1], the timing pulse generating circuit 133 increases the voltage level of the frequency filtering signal Vtpl from the reference voltage level to the preset voltage level with a third slope, and then reduces the voltage level of the frequency filtering signal Vtpl from the preset voltage level back to the reference voltage level to generate a second buffer pulse Ton2[1].
[0042] Furthermore, after generating the second buffer pulse Ton2[1], the timing pulse generating circuit 133 maintains the voltage level of the frequency filter signal Vtpl at the reference voltage level until entering the disable period DA[2] (i.e., the timing pulse generating circuit 133 receives the next falling signal Vfal), and then adjusts the voltage level of the frequency filter signal Vtpl again to sequentially generate the first buffer pulse Ton1[2], the timing pulse Toff[2] and the second buffer pulse Ton2[2].
[0043] In some embodiments, the switch control circuit 135 controls the carrier frequency generating circuit 11 to output the carrier frequency signal Vosi according to the first buffer pulse Ton1, controls the carrier frequency generating circuit 11 to stop outputting the carrier frequency signal Vosi according to the timing pulse Toff, and controls the carrier frequency generating circuit 11 to output the carrier frequency signal Vosi according to the second buffer pulse Ton2. Figure 2As shown, during the disable period DA of the input signal Vin, the carrier signal Vosi maintains output during the output period of the first buffer pulse Ton1, stops output during the output period Pb of the timing pulse Toff, and resumes output during the output period of the second buffer pulse Ton2. In addition, the carrier signal Vosi still maintains output after the falling edge of the second buffer pulse Ton2.
[0044] From the above description of the first buffer pulse Ton1, the timing pulse Toff and the second buffer pulse Ton2, it can be known that the first buffer pulse Ton1, the timing pulse Toff and the second buffer pulse Ton2 can each be a ramp pulse. Accordingly, in some further embodiments, during the disable period DA of the input signal Vin, the switch control circuit 135 is used to count the number of ramp pulses received by itself, and is used to control the carrier frequency generating circuit 11 to stop outputting the carrier frequency signal Vosi when receiving the second ramp pulse (i.e., when receiving the timing pulse Toff).
[0045] In the above embodiment, if Figure 2 As shown, the timing pulse generating circuit 133 generates a first buffer pulse Ton1, a timing pulse Toff and a second buffer pulse Ton2 to the switch control circuit 135 through a single signal (i.e., the frequency filtering signal Vtpl). However, the present disclosure is not limited thereto. In some embodiments, the timing pulse generating circuit 133 generates the first buffer pulse Ton1, the timing pulse Toff and the second buffer pulse Ton2 to the switch control circuit 135 through three independent signals. For example, when receiving the falling signal Vfal, the timing pulse generating circuit 133 adjusts the voltage level of the first signal to generate the first buffer pulse Ton1. After the first buffer pulse Ton1 is generated, the timing pulse generating circuit 133 adjusts the voltage level of the second signal to generate the timing pulse Toff. After the timing pulse Toff is generated, the timing pulse generating circuit 133 adjusts the voltage level of the third signal to generate the second buffer pulse Ton2.
[0046] In some embodiments, such as Figure 3A and Figure 3B As shown, the delay determination circuit 137 is used to receive the frequency filtering signal Vtpl from the timing pulse generating circuit 133, to receive the rising signal Vris and the falling signal Vfal from the edge detecting circuit 131, and to output the determination signal Vjud to control the timing pulse generating circuit 133.
[0047] In some embodiments, such as Figure 2As shown, the timing of the falling edge of the second buffer pulse Ton2[1] corresponding to the period TC[1] is before the timing of the rising edge of the input signal Vin corresponding to the period TC[2] (i.e., the start time of the enable period EA[2]). Accordingly, the delay judgment circuit 137 detects the falling edge of the second buffer pulse Ton2[1] before receiving the rising signal Vris corresponding to the period TC[2]. When the falling edge of the second buffer pulse Ton2[1] is detected and the rising signal Vris corresponding to the period TC[2] has not been received, the delay judgment circuit 137 adjusts the voltage level of the judgment signal Vjud to generate a delay pulse Td[1] to the timing pulse generating circuit 133. After receiving the delay pulse Td[1], the timing pulse generating circuit 133 adjusts the timing pulse Toff[2] corresponding to the period TC[2]. For example, Figure 2 As shown, the output period Pb[2] of the timing pulse Toff[2] is increased by the timing pulse generating circuit 133 and is longer than the output period Pb[1] of the timing pulse Toff[1].
[0048] According to the above description, Figure 2 In the embodiment of the present invention, the delay judgment circuit 137 adjusts the voltage level of the judgment signal Vjud to generate a delay pulse Td[2] to control the timing pulse generating circuit 133 to increase the output period Pb[3] of the timing pulse Toff[3] corresponding to the cycle TC[3]. The delay judgment circuit 137 also adjusts the voltage level of the judgment signal Vjud to generate a delay pulse Td[3] to control the timing pulse generating circuit 133 to increase the output period Pb[4] of the timing pulse Toff[4] corresponding to the cycle TC[4].
[0049] In some further embodiments, the output period Pb[2] of the timing pulse Toff[2] is the output period Pb[1] of the timing pulse Toff[1] plus the output period Pb[1] of the timing pulse Toff[1]; the output period Pb[3] of the timing pulse Toff[3] is the output period Pb[2] of the timing pulse Toff[2] plus the output period Pb[1] of the timing pulse Toff[1]; and the output period Pb[4] of the timing pulse Toff[4] is the output period Pb[3] of the timing pulse Toff[3] plus the output period Pb[1] of the timing pulse Toff[1]. That is, the output period Pb of the timing pulse Toff corresponding to the next cycle TC is the output period Pb of the timing pulse Toff corresponding to the current cycle TC plus the output period Pb[1] of the timing pulse Toff[1] corresponding to the first cycle TC[1].
[0050] Furthermore, in some embodiments, the output period Pb[1] of the timing pulse Toff[1] is 1 times the output period of the first buffer pulse Ton1[1], and is 1 times the output period of the second buffer pulse Ton2[1]. The output period Pb[2] of the timing pulse Toff[2] is 2 times the output period of the first buffer pulse Ton1[2], and is 2 times the output period of the second buffer pulse Ton2[2]. The output period Pb[3] of the timing pulse Toff[3] is 3 times the output period of the first buffer pulse Ton1[3], and is 3 times the output period of the second buffer pulse Ton2[3]. The output period Pb[4] of the timing pulse Toff[4] is 4 times the output period of the first buffer pulse Ton1[4], and is 4 times the output period of the second buffer pulse Ton2[4]. It can be seen from this that, for the timing pulse Toff, the first buffer pulse Ton1 and the second buffer pulse Ton2 corresponding to the same period TC, the output period Pb of the timing pulse Toff is M times the output period of the first buffer pulse Ton1, and is M times the output period of the second buffer pulse Ton2, where M is a positive integer.
[0051] Specifically, in some embodiments, the output period of the first buffer pulse Ton1 is 20-50 nanoseconds (ns), and the output period of the second buffer pulse Ton2 is 20-50 nanoseconds.
[0052] It should be understood that, at the time after the cycle TC[4], the output period Pb of the timing pulse Toff may be excessively increased, resulting in a situation where the timing of the falling edge of the second buffer pulse Ton2 corresponding to the current cycle TC is after the timing of the rising edge (or rising signal Vris) of the input signal Vin corresponding to the next cycle TC. In the above situation, the delay judgment circuit 137 does not generate a delay pulse Td to the timing pulse generating circuit 133, so that the output period Pb of the timing pulse Toff corresponding to the next cycle TC remains the same as the output period Pb of the timing pulse Toff of the current cycle TC.
[0053] In addition, due to some non-ideal factors, the carrier control circuit 13 may cause the timing of the falling edge of the timing pulse Toff corresponding to the current cycle TC to be later than the timing of the rising edge (or rising signal Vris) of the input signal Vin corresponding to the next cycle TC. In this case, the switch control circuit 135 receives the timing pulse Toff during the enable period EA. Even so, since the edge detection circuit 131 also outputs the rising signal Vris to the switch control circuit 135 in response to the enable period EA, the switch control circuit 135 will still control the carrier generation circuit 11 to output the carrier signal Vosi according to the rising signal Vris.
[0054] By the above Figure 2 and Figure 3A to Figure 3B It can also be seen from the description of the embodiment that the carrier control circuit 13 is used to detect the enable period EA and the disable period DA of the input signal Vin, to control the carrier generating circuit 11 to output the carrier signal Vosi during the enable period EA, and to control the carrier generating circuit 11 to stop outputting the carrier signal Vosi during the output period Pb of the timing pulse Toff during the disable period DA.
[0055] It should be understood that the timing pulse Toff of the present disclosure is not Figure 2 In some embodiments, the timing pulse Toff has the same output period Pb in each cycle TC. Correspondingly, in some embodiments, Figure 1 The delay judgment circuit 137 in will be omitted.
[0056] Furthermore, the frequency filtering signal Vtpl of the present disclosure is not Figure 2 and Figure 3B The figures are shown as follows. In some embodiments, after receiving the falling signal Vfal, the timing pulse generating circuit 133 adjusts the voltage level of the frequency filtering signal Vtpl to generate the timing pulse Toff. In other words, the first buffer pulse Ton1 and the second buffer pulse Ton2 will be omitted. Correspondingly, the delay determination circuit 137 will generate or not generate the delay pulse Td to the timing pulse generating circuit 133 according to the falling edge of the timing pulse Toff.
[0057] In some embodiments, when the falling edge of the timing pulse Toff corresponding to the current cycle TC is detected and the rising signal Vris corresponding to the next cycle TC has not been received (that is, when the timing of the falling edge of the timing pulse Toff corresponding to the current cycle TC is before the timing of the rising edge of the input signal Vin corresponding to the next cycle TC), the delay judgment circuit 137 adjusts the voltage level of the judgment signal Vjud to generate a delay pulse Td, so as to control the timing pulse generating circuit 133 to increase the output period Pb of the timing pulse Toff corresponding to the next cycle TC.
[0058] In some embodiments, when the rising signal Vris corresponding to the next cycle TC is received but the falling edge of the timing pulse Toff corresponding to the current cycle TC has not been detected (that is, when the timing of the falling edge of the timing pulse Toff corresponding to the current cycle TC is later than the timing of the rising edge of the input signal Vin corresponding to the next cycle TC), the delay determination circuit 137 will not generate a delay pulse Td to the timing pulse generating circuit 133, so that the output period Pb of the timing pulse Toff corresponding to the next cycle TC remains the same as the output period Pb of the timing pulse Toff of the current cycle TC. In addition, as described above, although the switch control circuit 135 receives the timing pulse Toff during the enabling period EA in this case, the switch control circuit 135 still controls the carrier generating circuit 11 to output the carrier signal Vosi according to the rising signal Vris.
[0059] In summary, in the above embodiment, when the output period Pb of the timing pulse Toff (for example, the output period Pb[1] of the timing pulse Toff[1]) does not overlap with the enable period EA (for example, the enable period EA[2]) adjacent to and located after the timing pulse Toff, the output period Pb of the next timing pulse Toff (for example, the output period Pb[2] of the timing pulse Toff[2]) will be adjusted.
[0060] As described above, in the case where the output period Pb of the timing pulse Toff partially overlaps with the enable period EA adjacent to and after the timing pulse Toff, the output period Pb of the next timing pulse Toff will not be adjusted. In addition, in the case where the time interval between the timing pulse Toff and the enable period EA adjacent to and after the timing pulse Toff is shorter than the output period of the second buffer pulse Ton2 (i.e., the timing of the falling edge of the second buffer pulse Ton2 corresponding to the current cycle TC is later than the timing of the rising edge of the input signal Vin corresponding to the next cycle TC), the output period Pb of the next timing pulse Toff will also not be adjusted.
[0061] Please also read Figure 1 and Figure 4 , Figure 4 FIG. 1 is a schematic diagram of a modulation signal Vmod and an output signal Vout according to some embodiments of the present disclosure. Figure 1As shown, the isolation circuit 20 is used to couple the modulation signal Vmod from the primary circuit 10 to the secondary circuit 30, so that the secondary circuit 30 generates the output signal Vout. Specifically, the receiving circuit 31 receives and transmits a signal substantially identical to the modulation signal Vmod to the demodulation circuit 33, and the demodulation circuit 33 demodulates the signal substantially identical to the modulation signal Vmod to generate the output signal Vout. It can be seen that the secondary circuit 30 generates the output signal Vout according to the modulation signal Vmod. In some embodiments, Figure 2 and Figure 4 As shown, the waveform of the output signal Vout is substantially the same as the waveform of the input signal Vin.
[0062] See also Figure 5 , Figure 5 FIG. 5 is a flow chart of a modulation signal generation method 500 according to some embodiments of the present disclosure. In some embodiments, the modulation signal generation method 500 may be Figure 1 The isolated integrated circuit 100 is implemented as follows. Figure 5 As shown, the modulation signal generating method 500 includes steps S501 - S504 .
[0063] In step S501, the carrier control circuit 13 detects at least one enable period EA and at least one disable period DA of the input signal Vin. In some embodiments, the carrier control circuit 13 detects the enable period EA and the disable period DA of the input signal Vin through the edge detection circuit 131. Specifically, Figure 3A and Figure 3B As shown, the edge detection circuit 131 is used for outputting a rising signal Vris in response to an enable period EA of the input signal Vin, and is used for outputting a falling signal Vfal in response to a disable period DA of the input signal Vin.
[0064] In step S502, during at least one enable period EA, the carrier control circuit 13 controls the carrier generation circuit 11 to output the carrier signal Vosi. Figure 2 and Figure 3A As shown, the switch control circuit 135 in the carrier frequency control circuit 13 controls the carrier frequency generating circuit 11 to output the carrier frequency signal Vosi according to the rising signal Vris.
[0065] In step S503, during at least one disable period DA, the carrier control circuit 13 controls the carrier generation circuit 11 to stop outputting the carrier signal Vosi during at least one output period Pb of the timing pulse Toff. Figure 2 and Figure 3BAs shown, the timing pulse generating circuit 133 in the carrier frequency control circuit 13 adjusts the voltage level of the frequency filtering signal Vtpl according to the falling signal Vfal to sequentially generate the first buffer pulse Ton1, the timing pulse Toff and the second buffer pulse Ton2 to the switch control circuit 135, so that the switch control circuit 135 controls the carrier frequency generating circuit 11 to stop outputting the carrier frequency signal Vosi during the output period Pb of the timing pulse Toff.
[0066] In step S504, the modulation circuit 15 generates a modulation signal Vmod according to the input signal Vin and the carrier signal Vosi. Figure 1 and Figure 2 As shown, the modulation circuit 15 controls the modulation signal Vmod to oscillate at the frequency of the carrier signal Vosi according to the input signal Vin of the enable level (i.e., during the enable period EA of the input signal Vin), and controls the modulation signal Vmod to stop oscillating according to the input signal Vin of the disable level (i.e., during the disable period DA of the input signal Vin).
[0067] The remaining descriptions of step S501 to step S504 can refer to the description of the above-mentioned isolated integrated circuit 100 , and thus will not be repeated here.
[0068] From the above embodiments of the present disclosure, it can be seen that the carrier control circuit 13 of the present disclosure detects the enable period EA and the disable period DA of the input signal Vin, and controls the carrier generation circuit 11 to stop outputting the carrier signal Vosi during the output period Pb of the timing pulse Toff during the disable period DA of the input signal Vin. Therefore, compared with the related art that does not stop outputting the carrier signal during the disable period of the input signal, the isolated integrated circuit 100 of the present disclosure has lower power consumption.
[0069] Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the present disclosure. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.
[0070]
Explanation of symbols
[0071] 10: Primary side circuit
[0072] 11: Carrier frequency generation circuit
[0073] 13: Carrier frequency control circuit
[0074] 15: Modulation circuit
[0075] 17: Buffer circuit
[0076] 19: Transmitter circuit
[0077] 20: Isolation circuit
[0078] 30: Secondary circuit
[0079] 31: Receiving circuit
[0080] 33: Demodulation circuit
[0081] 100:Isolated integrated circuit
[0082] 131: Edge detection circuit
[0083] 133: Timing pulse generating circuit
[0084] 135: switch control circuit
[0085] 137: Delay judgment circuit
[0086] 500: Modulation signal generation method
[0087] DA: Disabled period
[0088] EA: Enablement Period
[0089] GND1: First ground voltage
[0090] GND2: Second ground voltage
[0091] Pb: Output period
[0092] S501~S504: Steps
[0093] TC: Cycle
[0094] Td: Delay pulse
[0095] Toff: Timing pulse
[0096] Ton1: First buffer pulse
[0097] Ton2: Second buffer pulse
[0098] VCC1: First power supply voltage
[0099] VCC2: Second power supply voltage
[0100] Vfal: falling signal
[0101] Vin: Input signal
[0102] Vjud: judgment signal
[0103] Vmod: modulation signal
[0104] Vosi: carrier frequency signal
[0105] Vout: output signal
[0106] Vris: rising signal
[0107] Vtpl: frequency filtered signal.
Claims
1. An isolated integrated circuit, characterized in that: include: The primary circuit includes: A carrier frequency generating circuit, used for generating a carrier frequency signal; a carrier frequency control circuit electrically coupled to the carrier frequency generating circuit, for detecting at least one enable period and at least one disable period of the input signal, for controlling the carrier frequency generating circuit to output the carrier frequency signal during the at least one enable period, and for controlling the carrier frequency generating circuit to stop outputting the carrier frequency signal during the output period of at least one timing pulse during the at least one disable period, wherein the at least one timing pulse is generated in response to detecting the entry into the at least one disable period, and in the case where the output period of one of the at least one timing pulses does not overlap with one of the at least one enable periods adjacent to and following the at least one timing pulse, the output period of the next of the at least one timing pulses will be adjusted; as well as A modulation circuit, electrically coupled to the carrier frequency generating circuit, for receiving the input signal and the carrier frequency signal, and for outputting a modulation signal according to the input signal and the carrier frequency signal; An isolation circuit, coupled to the primary side circuit and used for transmitting the modulated signal; as well as The secondary side circuit is coupled to the isolation circuit, and is used for receiving the modulation signal through the isolation circuit, and for generating an output signal according to the modulation signal.
2. The isolated integrated circuit according to claim 1, characterized in that: The carrier frequency control circuit comprises: An edge detection circuit, configured to output at least one rising signal during the at least one enabling period, and to output at least one falling signal during the at least one disabling period; A timing pulse generating circuit, electrically coupled to the edge detection circuit, for outputting a frequency filtering signal, and for adjusting a voltage level of the frequency filtering signal according to the at least one falling signal to generate the at least one timing pulse; a switch control circuit, electrically coupled to the carrier frequency generating circuit, the edge detection circuit and the timing pulse generating circuit, for controlling the carrier frequency generating circuit to output the carrier frequency signal according to the at least one rising signal, and for controlling the carrier frequency generating circuit to stop outputting the carrier frequency signal according to the at least one timing pulse; as well as The delay judgment circuit is electrically coupled to the edge detection circuit and the timing pulse generating circuit, and is used to output a judgment signal to control the timing pulse generating circuit according to the frequency filtering signal, the at least one rising signal and the at least one falling signal.
3. The isolated integrated circuit according to claim 2, characterized in that: The at least one timing pulse comprises a current timing pulse corresponding to a current cycle of the input signal, and the at least one rising signal comprises a next rising signal corresponding to a next cycle after the current cycle; When the falling edge of the current timing pulse is detected and the next rising signal has not been received, the delay judgment circuit adjusts the voltage level of the judgment signal to generate a delay pulse to control the timing pulse generating circuit to increase the output period of the next timing pulse corresponding to the next cycle in the at least one timing pulse.
4. The isolated integrated circuit according to claim 2, characterized in that: The timing pulse generating circuit is used for adjusting the voltage level of the frequency filtering signal according to the at least one falling signal to sequentially generate at least one first buffer pulse, the at least one timing pulse and at least one second buffer pulse; The switch control circuit is used to control the carrier frequency generating circuit to output the carrier frequency signal according to the at least one first buffer pulse, and is used to control the carrier frequency generating circuit to output the carrier frequency signal according to the at least one second buffer pulse.
5. A carrier frequency control circuit, characterized in that: The device is electrically coupled to the carrier frequency generating circuit to receive an input signal and comprises: An edge detection circuit, configured to output at least one rising signal during at least one enabled period of the input signal, and to output at least one falling signal during at least one disabled period of the input signal; a timing pulse generating circuit, electrically coupled to the edge detection circuit, for outputting a frequency filtering signal, and for adjusting a voltage level of the frequency filtering signal according to the at least one falling signal to generate at least one timing pulse, wherein when an output period of one of the at least one timing pulses does not overlap with one of the at least one enabling periods adjacent to and following the at least one timing pulse, an output period of a next one of the at least one timing pulses will be adjusted; as well as The switch control circuit is electrically coupled to the carrier generating circuit, the edge detection circuit and the timing pulse generating circuit, and is used to control the carrier generating circuit to output the carrier signal according to the at least one rising signal, and to control the carrier generating circuit to stop outputting the carrier signal according to the at least one timing pulse.
6. The carrier frequency control circuit according to claim 5, characterized in that: The at least one timing pulse includes a current timing pulse corresponding to a current cycle of the input signal, and the input signal includes a next rising edge corresponding to a next cycle after the current cycle; In the case where the timing of the falling edge of the current timing pulse is before the timing of the next rising edge, the timing pulse generating circuit increases the output period of the next timing pulse corresponding to the next cycle in the at least one timing pulse, so that the output period of the next timing pulse is longer than the output period of the current timing pulse.
7. The carrier frequency control circuit according to claim 5, characterized in that: The timing pulse generating circuit is used for adjusting the voltage level of the frequency filtering signal according to the at least one falling signal to sequentially generate at least one first buffer pulse, the at least one timing pulse and at least one second buffer pulse; The switch control circuit is used to control the carrier frequency generating circuit to output the carrier frequency signal according to the at least one first buffer pulse, and is used to control the carrier frequency generating circuit to output the carrier frequency signal according to the at least one second buffer pulse.
8. The carrier frequency control circuit according to claim 5, characterized in that: Also includes: A delay judgment circuit is electrically coupled to the edge detection circuit and the timing pulse generating circuit, and is used to output a judgment signal to control the timing pulse generating circuit according to the frequency filtering signal, the at least one rising signal and the at least one falling signal; The delay judgment circuit is further used to adjust the voltage level of the judgment signal to generate at least one delay pulse to control the timing pulse generating circuit to adjust the output period of the at least one timing pulse.
9. A method for generating a modulation signal, characterized in that: The method is implemented by an isolated integrated circuit, wherein the isolated integrated circuit includes a carrier frequency generating circuit, a carrier frequency control circuit and a modulation circuit, and the modulation signal generating method includes: The carrier frequency control circuit detects at least one enable period and at least one disable period of the input signal; During the at least one enabling period, the carrier frequency control circuit controls the carrier frequency generating circuit to output a carrier frequency signal; During the at least one disable period, the carrier frequency control circuit controls the carrier frequency generating circuit to stop outputting the carrier frequency signal during the output period of at least one timing pulse, wherein the at least one timing pulse is generated in response to detecting the entry into the at least one disable period, and when the output period of one of the at least one timing pulses does not overlap with one of the at least one enable periods adjacent to and following the at least one timing pulse, the output period of the next one of the at least one timing pulses is adjusted; as well as The modulation circuit generates a modulation signal according to the input signal and the carrier signal.
10. The modulation signal generating method according to claim 9, wherein: The at least one timing pulse includes a current timing pulse corresponding to a current cycle of the input signal, the input signal includes a next rising edge corresponding to a next cycle after the current cycle, and the modulation signal generation method further includes: When the timing of the falling edge of the current timing pulse is before the timing of the next rising edge, the carrier frequency control circuit increases the output period of the next timing pulse corresponding to the next cycle in the at least one timing pulse, so that the output period of the next timing pulse is longer than the output period of the current timing pulse.