Root mean square voltage calculation circuit and nuclear radiation detector

Abstract

The invention discloses a root-mean-square voltage calculation circuit and a nuclear radiation detector. The root-mean-square voltage calculation circuit comprises an absolute value sub-circuit, a root-mean-square operation sub-circuit and a result output sub-circuit. The absolute value sub-circuit performs absolute value processing on an input voltage signal of the nuclear radiation detector so as to convert the input voltage signal into an absolute value current signal; the root-mean-square operation sub-circuit comprises a first input end, a second input end and a signal output end, the first input end is electrically connected with the absolute value sub-circuit, the signal output end is electrically connected with the second input end, and the root-mean-square operation sub-circuit is used for performing root-mean-square operation on the absolute value current signal by using the first root-mean-square current signal and outputting the absolute value current signal; the input voltage signal is converted into a second root-mean-square current signal, and the first root-mean-square current signal is a current signal fed back from the signal output end to the second input end; and the result output sub-circuit is electrically connected with the signal output end, converts the second root-mean-square current signal into a root-mean-square voltage signal, and outputs the root-mean-square voltage signal.

Description

Technical Field

[0001] The present application relates to the technical field of nuclear radiation detectors, and in particular to a root mean square voltage calculation circuit and a nuclear radiation detector. Background Art

[0002] In the field of nuclear radiation detector measurement, the nuclear instrumentation system of a nuclear power plant is one of the most critical systems of the reactor. The reactor neutron injection rate level is monitored by using the off-core nuclear measurement detectors distributed around the reactor pressure vessel, thereby monitoring the reactor power. The principle of neutron injection rate level detection is to form reaction products through nuclear reactions between neutrons and sensitive materials inside the nuclear radiation detector. These reaction products enter the gas-filled detector cavity to ionize gas molecules to form positive ion-electron pairs, which drift in a directional manner under the action of an external electric field to generate a voltage difference. In the case of a wide measurement range, the neutron flux can be calculated by measuring the root mean square voltage of the nuclear radiation detector and by the change in the root mean square voltage. In related technologies, the calculation of the root mean square voltage usually relies on the implementation of related software algorithms, and the design of software algorithms is usually complex, which leads to deviations in the calculation of the root mean square voltage, resulting in low calculation accuracy. Summary of the invention

[0003] The present application aims to propose a root mean square voltage calculation circuit and a nuclear radiation detector, which can solve the problem of low root mean square voltage calculation accuracy of software algorithms.

[0004] In a first aspect, an embodiment of the present application provides a root mean square voltage calculation circuit, comprising:

[0005] an absolute value subcircuit, the absolute value subcircuit being used to perform absolute value processing on an input voltage signal of the nuclear radiation detector so as to convert the input voltage signal into an absolute value current signal;

[0006] a root mean square operation subcircuit, the root mean square operation subcircuit comprising a first input terminal, a second input terminal and a signal output terminal, the first input terminal being electrically connected to the absolute value subcircuit, the signal output terminal being electrically connected to the second input terminal, the root mean square operation subcircuit being used to perform a root mean square operation on the absolute value current signal using a first root mean square current signal to convert the input voltage signal into a second root mean square current signal, the first root mean square current signal being a current signal fed back from the signal output terminal to the second input terminal;

[0007] A result output subcircuit is electrically connected to the signal output terminal, and is used for converting the second root mean square current signal into a root mean square voltage signal, and outputting the root mean square voltage signal.

[0008] According to some embodiments of the present application, the absolute value subcircuit includes:

[0009] A first operational amplifier, wherein a non-inverting input terminal of the first operational amplifier is used to input the input voltage signal;

[0010] a first transistor, wherein the output end of the first operational amplifier is electrically connected to the base of the first transistor, and the first transistor is configured to be turned on when the input voltage signal is positive;

[0011] a first resistor, wherein the emitter of the first transistor is electrically connected to one end of the first resistor, the inverting input end of the first operational amplifier is electrically connected to the one end of the first resistor, and the other end of the first resistor is grounded;

[0012] a first mirror current source subcircuit, the first mirror current source subcircuit being electrically connected to the collector of the first transistor, the first mirror current source subcircuit being electrically connected to the root mean square operation subcircuit, and the first mirror current source subcircuit being used for copying the collector current of the first transistor to obtain and output the absolute value current signal when the first transistor is turned on;

[0013] A second transistor, the output end of the first operational amplifier is electrically connected to the base of the second transistor, the emitter of the second transistor is electrically connected to the one end of the first resistor, the collector of the second transistor is electrically connected to the root mean square operation subcircuit, and the second transistor is used to be turned on when the input voltage signal is negative, so that the collector of the second transistor outputs the absolute value current signal.

[0014] According to some embodiments of the present application, the first mirror current source sub-circuit includes:

[0015] a third triode, wherein the emitter of the third triode is used to be electrically connected to the positive power supply terminal;

[0016] a fourth triode, wherein the collector of the third triode is electrically connected to the emitter of the fourth triode, the collector of the fourth triode is electrically connected to the collector of the first triode, and the collector of the fourth triode is electrically connected to the base of the fourth triode;

[0017] a fifth triode, wherein the emitter of the fifth triode is used to be electrically connected to the positive power supply terminal, the base of the fifth triode is electrically connected to the base of the third triode, and the base of the fifth triode is electrically connected to the collector of the fifth triode;

[0018] A sixth transistor, the collector of the fifth transistor is electrically connected to the emitter of the sixth transistor, and the collector of the sixth transistor is electrically connected to the root mean square operation sub-circuit.

[0019] According to some embodiments of the present application, the absolute value subcircuit further includes:

[0020] a first proportional amplification unit, wherein the output end of the first operational amplifier is electrically connected to the input end of the first proportional amplification unit, and the output end of the first proportional amplification unit is electrically connected to the base of the first transistor;

[0021] A second proportional amplification unit, wherein the output end of the first operational amplifier is electrically connected to the input end of the second proportional amplification unit, and the output end of the second proportional amplification unit is electrically connected to the base of the second transistor.

[0022] According to some embodiments of the present application, the root mean square operation subcircuit includes:

[0023] a square operation unit, the square operation unit being electrically connected to the absolute value sub-circuit, and the square operation unit being used to perform a square operation on the absolute value current signal to obtain a square current signal;

[0024] a division operation unit, the division operation unit being electrically connected to the square operation unit, and the division operation unit being used to perform a division operation using the square current signal and the first root mean square current signal to obtain a division current signal;

[0025] An averaging operation unit, the averaging operation unit is electrically connected to the division operation unit, and the averaging operation unit is used to perform an averaging operation on the division current signal to obtain the second root mean square current signal.

[0026] According to some embodiments of the present application, the square operation unit includes:

[0027] a seventh triode, wherein the emitter of the seventh triode is electrically connected to the absolute value sub-circuit, the emitter of the seventh triode is electrically connected to the division operation unit, and the base of the seventh triode is electrically connected to the collector of the seventh triode;

[0028] An eighth transistor, wherein the collector of the seventh transistor is electrically connected to the emitter of the eighth transistor, the collector of the eighth transistor is electrically connected to the base of the eighth transistor, and the collector of the eighth transistor is grounded.

[0029] According to some embodiments of the present application, the division operation unit includes:

[0030] a ninth triode, wherein the emitter of the ninth triode is electrically connected to the square operation unit, and the collector of the ninth triode is electrically connected to the average operation unit;

[0031] A logarithmic amplification subunit, the average operation unit is electrically connected to the logarithmic amplification subunit, the logarithmic amplification subunit is electrically connected to the base of the ninth transistor, the logarithmic amplification subunit is used to calculate the natural logarithm of the first root mean square current signal to obtain a logarithmic current signal, and input the logarithmic current signal to the base of the ninth transistor, so that the ninth transistor performs a division operation according to the square current signal and the logarithmic current signal to obtain the divided current signal.

[0032] According to some embodiments of the present application, the averaging operation unit includes:

[0033] a second resistor, the division operation unit being electrically connected to one end of the second resistor, and the other end of the second resistor being electrically connected to the result output subcircuit;

[0034] The dividing unit is electrically connected to one end of the capacitor, and the other end of the capacitor is grounded.

[0035] According to some embodiments of the present application, the result output subcircuit includes:

[0036] a second mirror current source subcircuit, the second mirror current source subcircuit being electrically connected to the root mean square operation subcircuit, and the second mirror current source subcircuit being used to replicate the second root mean square current signal;

[0037] A third resistor, one end of the third resistor is electrically connected to the second mirror current source sub-circuit, the other end of the third resistor is grounded, and the third resistor is used to output the root mean square voltage signal according to the second root mean square current signal.

[0038] In a second aspect, an embodiment of the present application provides a nuclear radiation detector, comprising a root mean square voltage calculation circuit as described above.

[0039] In the embodiment of the present application, the absolute value subcircuit performs absolute value processing on the input voltage signal to convert the input voltage signal into an absolute value current signal, the root mean square operation subcircuit uses the first root mean square current signal to perform a root mean square operation on the absolute value current signal to obtain a second root mean square current signal, and the result output subcircuit obtains and outputs a root mean square voltage signal according to the second root mean square current signal. In the embodiment provided by the present application, the root mean square voltage is calculated by the circuit with high calculation accuracy.

[0040] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The present application is further described below with reference to the accompanying drawings and embodiments, wherein:

[0042] Figure 1 A functional block diagram of an implementation of a root mean square voltage calculation circuit provided by the present application;

[0043] Figure 2 A functional block diagram of a second mirror current source sub-circuit, a third mirror current source sub-circuit, and a fourth mirror current source sub-circuit in an embodiment of a root mean square voltage calculation circuit provided by the present application;

[0044] Figure 3 A first circuit diagram of an embodiment of a root mean square voltage calculation circuit provided by the present application;

[0045] Figure 4 This is a second circuit diagram of an embodiment of the RMS voltage calculation circuit provided in the present application.

[0046] Reference numerals:

[0047] Absolute value sub-circuit 100, second mirror current source sub-circuit 200, third mirror current source sub-circuit 300, fourth mirror current source sub-circuit 400, root mean square operation sub-circuit 500, square operation unit 510, division operation unit 520, filtering unit 530, and follower unit 540. DETAILED DESCRIPTION

[0048] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0049] In the description of the present application, it should be understood that the descriptions involving orientation, such as the orientation or positional relationship indicated as up, down, etc., are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0050] In the description of this application, "a plurality" means more than two. If there is a description of "first" or "second", it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0051] In the description of this application, unless otherwise clearly defined, terms such as setting, installation, and electrical connection should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0052] Refer to the following Figures 1 to 4 A root mean square voltage calculation circuit and a nuclear radiation detector according to an embodiment of the present application are described.

[0053] The embodiment of the present application provides a root mean square voltage calculation circuit, including:

[0054] The absolute value subcircuit 100 is used to perform absolute value processing on the input voltage signal of the nuclear radiation detector to convert the input voltage signal into an absolute value current signal;

[0055] The root mean square operation subcircuit 500 includes a first input terminal, a second input terminal and a signal output terminal. The first input terminal is electrically connected to the absolute value subcircuit 100, and the signal output terminal is electrically connected to the second input terminal. The root mean square operation subcircuit 500 is used to perform a root mean square operation on the absolute value current signal using the first root mean square current signal to convert the input voltage signal into a second root mean square current signal. The first root mean square current signal is a current signal fed back from the signal output terminal to the second input terminal.

[0056] The result output subcircuit is electrically connected to the signal output terminal, and is used for converting the second root mean square current signal into a root mean square voltage signal, and outputting the root mean square voltage signal.

[0057] In the embodiment of the present application, the absolute value subcircuit 100 performs absolute value processing on the input voltage signal to convert the input voltage signal into an absolute value current signal, the root mean square operation subcircuit 500 uses the first root mean square current signal to perform a root mean square operation on the absolute value current signal to obtain a second root mean square current signal, and the result output subcircuit obtains and outputs a root mean square voltage signal according to the second root mean square current signal. In the embodiment provided by the present application, the root mean square voltage is calculated by the circuit with high calculation accuracy.

[0058] In some embodiments of the present application, the absolute value subcircuit 100 may use a diode precision full-wave rectifier circuit, an operational amplifier-based full-wave rectifier circuit, or a power supply half-wave and full-wave rectifier. The absolute value subcircuit 100 can convert a negative input voltage signal into a positive signal to implement absolute value operation, that is, convert the input voltage signal into an absolute value current signal, and the absolute value current signal is positive.

[0059] In some embodiments of the present application, Figure 1As shown, the absolute value subcircuit 100 is used to perform absolute value processing on the input voltage signal Vin of the nuclear radiation detector to convert the input voltage signal Vin into an absolute value voltage signal |Vin|. The root mean square operation subcircuit 500 includes a square operation unit 510, a division operation unit 520, a filter unit 530 and a follower unit 540 that are electrically connected in sequence. The square operation unit 510 is used to perform a square operation on the absolute value voltage signal |Vin| to obtain a square voltage signal |Vin| 2 The follower unit 540 is used to feed back the first RMS voltage signal to the division unit 520. The first RMS voltage signal is the voltage signal output by the RMS operation subcircuit 500. The division unit 520 uses the first RMS voltage signal to square the voltage signal |Vin| 2 Perform division operation to obtain the divided voltage signal |Vin| 2 / Vrms1, the filtering unit 530 divides the voltage signal |Vin| 2 / Vrms1 is filtered, that is, an averaging operation is performed to obtain and output a second root mean square voltage signal Vrms2, thereby realizing root mean square voltage calculation.

[0060] In one embodiment of the present application, Figure 3 As shown, the absolute value subcircuit 100 includes:

[0061] A first operational amplifier U3, wherein a non-inverting input terminal of the first operational amplifier U3 is used to input an input voltage signal;

[0062] A first transistor Q6, the output end of the first operational amplifier U3 is electrically connected to the base of the first transistor Q6, and the first transistor Q6 is used to be turned on when the input voltage signal is positive;

[0063] A first resistor R12, an emitter of the first transistor Q6 is electrically connected to one end of the first resistor R12, an inverting input end of the first operational amplifier U3 is electrically connected to one end of the first resistor R12, and the other end of the first resistor R12 is grounded;

[0064] A first mirror current source subcircuit, the first mirror current source subcircuit is electrically connected to the collector of the first transistor Q6, the first mirror current source subcircuit is electrically connected to the root mean square operation subcircuit 500, and the first mirror current source subcircuit is used to copy the collector current of the first transistor Q6 to obtain and output an absolute value current signal when the first transistor Q6 is turned on;

[0065] The second transistor Q7, the output end of the first operational amplifier U3 is electrically connected to the base of the second transistor Q7, the emitter of the second transistor Q7 is electrically connected to one end of the first resistor R12, the collector of the second transistor Q7 is electrically connected to the root mean square operation subcircuit 500, and the second transistor Q7 is used to be turned on when the input voltage signal is negative, so that the collector of the second transistor Q7 outputs an absolute current signal.

[0066] In this embodiment, the input voltage signal is output to the base of the first transistor Q6 and the base of the second transistor Q7 respectively through the first operational amplifier U3. When the input voltage signal is positive, the first transistor Q6 is turned on and the second transistor Q7 is turned off. The load current is provided by the first mirror current source subcircuit, and flows to the first resistor R12 through the first transistor Q6, thereby generating an absolute value current signal. The first mirror current source subcircuit copies the collector current of the first transistor Q6, obtains and outputs the absolute value current signal to the root mean square operation subcircuit 500, and the magnitude of the absolute value current signal is the ratio of the voltage value of the input voltage signal to the resistance value of the first resistor R12. When the input signal is negative, the first transistor Q6 is turned off, the second transistor Q7 is turned on, the current flows from the first resistor R12 to the second transistor Q7, and the absolute value current signal is output to the root mean square operation subcircuit 500 through the collector of the second transistor Q7. The magnitude of the absolute value current signal is the ratio of the voltage value of the input voltage signal to the resistance value of the first resistor R12. Therefore, whether the input voltage is positive or negative, the absolute value current signal flows from the absolute value sub-circuit 100 to the RMS operation sub-circuit 500 , that is, the absolute value current signal is positive, and the absolute value operation is implemented.

[0067] In one embodiment of the present application, Figure 3 As shown, the first mirror current source sub-circuit includes:

[0068] A third transistor Q1, wherein the emitter of the third transistor Q1 is used for electrically connecting to the positive power supply terminal;

[0069] a fourth triode Q3, wherein the collector of the third triode Q1 is electrically connected to the emitter of the fourth triode Q3, the collector of the fourth triode Q3 is electrically connected to the collector of the first triode Q6, and the collector of the fourth triode Q3 is electrically connected to the base of the fourth triode Q3;

[0070] a fifth triode Q2, wherein the emitter of the fifth triode Q2 is used to be electrically connected to the positive power supply terminal, the base of the fifth triode Q2 is electrically connected to the base of the third triode Q1, and the base of the fifth triode Q2 is electrically connected to the collector of the fifth triode Q2;

[0071] The collector of the sixth transistor Q4 and the fifth transistor Q2 are electrically connected to the emitter of the sixth transistor Q4 , and the collector of the sixth transistor Q4 is electrically connected to the RMS operation sub-circuit 500 .

[0072] In this embodiment, the positive power supply terminal provides a positive voltage. When the first transistor Q6 is turned on, the third transistor Q1, the fourth transistor Q3, the fifth transistor Q2 and the sixth transistor Q4 are all turned on, and the current flows from the fourth transistor Q3 to the first transistor Q6 and the first resistor R12. The collector current of the sixth transistor Q4 is the same as the collector current of the fourth transistor Q3, that is, the collector current of the fourth transistor Q3 is copied to obtain an absolute value current signal, which is then output to the root mean square operation sub-circuit 500.

[0073] In one embodiment of the present application, the absolute value subcircuit 100 further includes:

[0074] A first proportional amplification unit, wherein the output end of the first operational amplifier U3 is electrically connected to the input end of the first proportional amplification unit, and the output end of the first proportional amplification unit is electrically connected to the base of the first transistor Q6;

[0075] The second proportional amplification unit, the output end of the first operational amplifier U3 is electrically connected to the input end of the second proportional amplification unit, and the output end of the second proportional amplification unit is electrically connected to the base of the second transistor Q7.

[0076] In this embodiment, the input voltage signal is proportionally amplified by the first proportional amplification unit and then output to the base of the first transistor Q6. The input voltage signal is proportionally amplified by the second proportional amplification unit and then output to the base of the second transistor Q7. The first proportional amplification unit and the second proportional amplification unit can ensure that when the input voltage signal is very small, the root mean square voltage calculation circuit can also respond quickly and accurately perform root mean square calculation, and can also eliminate the crossover distortion caused by the first transistor Q6 and the second transistor Q7.

[0077] Some implementation methods of the present application, such as Figure 3 As shown, the first proportional amplification unit includes:

[0078] A second operational amplifier U1, an output end of the first operational amplifier U3 is electrically connected to a non-inverting input end of the second operational amplifier U1, and an output end of the second operational amplifier U1 is electrically connected to a base of a first transistor Q6;

[0079] A fourth resistor R4, an output end of the second operational amplifier U1 is electrically connected to one end of the fourth resistor R4;

[0080] a fifth resistor R3, wherein the other end of the fourth resistor R4 is electrically connected to one end of the fifth resistor R3;

[0081] A sixth resistor R2, the other end of the fifth resistor R3 is electrically connected to one end of the sixth resistor R2, and the other end of the sixth resistor R2 is electrically connected to the negative power supply end;

[0082] A seventh resistor R5, one end of the seventh resistor R5 is electrically connected to one end of the sixth resistor R2, and the other end of the seventh resistor R5 is grounded.

[0083] In this implementation, the negative power supply terminal provides a negative voltage, and the second operational amplifier U1, the fourth resistor R4, the fifth resistor R3, the sixth resistor R2 and the seventh resistor R5 form a proportional amplifier with a positive bias to achieve proportional amplification.

[0084] Some implementation methods of the present application, such as Figure 3 As shown, the second proportional amplification unit includes:

[0085] A third operational amplifier U4, an output end of the first operational amplifier U3 is electrically connected to a non-inverting input end of the third operational amplifier U4, and an output end of the third operational amplifier U4 is electrically connected to a base of a second transistor Q7;

[0086] An eighth resistor R9, an output end of the third operational amplifier U4 is electrically connected to one end of the eighth resistor R9;

[0087] a ninth resistor R8, wherein the other end of the eighth resistor R9 is electrically connected to one end of the ninth resistor R8;

[0088] The tenth resistor R7 and the other end of the ninth resistor R8 are electrically connected to one end of the tenth resistor R7, and the other end of the tenth resistor R7 is electrically connected to the positive power supply end;

[0089] The eleventh resistor R11 has one end electrically connected to one end of the tenth resistor R7 and the other end of the eleventh resistor R11 is grounded.

[0090] In this implementation, the positive power supply terminal provides a positive voltage, and the third operational amplifier U4, the eighth resistor R9, the ninth resistor R8, the tenth resistor R7 and the eleventh resistor R11 constitute a proportional amplifier with a negative bias to achieve proportional amplification.

[0091] In some implementation modes of the present application, Figure 4 As shown, a third mirror current source sub-circuit 300 is also included, and the third mirror current source sub-circuit 300 includes:

[0092] A first MOS tube M6, a drain of the first MOS tube M6 is electrically connected to the collector of the second transistor Q7, a drain of the first MOS tube M6 is electrically connected to the collector of the sixth transistor Q4, a source of the first MOS tube M6 is electrically connected to the negative power supply terminal, and a gate of the first MOS tube M6 is electrically connected to the drain of the first MOS tube M6;

[0093] The second MOS transistor M7 has a gate electrically connected to the gate of the first MOS transistor M6 , a source electrically connected to the negative power supply terminal, and a drain electrically connected to the RMS operation sub-circuit 500 .

[0094] In this embodiment, if Figure 2 As shown, the third mirror current source sub-circuit 300 copies the absolute value current signal. The absolute value current signal flows into the drain of the first MOS transistor M6, and then output to the RMS operation sub-circuit 500 through the drain of the second MOS transistor M7.

[0095] In one embodiment of the present application, the RMS operation subcircuit 500 includes:

[0096] A square operation unit 510, the square operation unit 510 is electrically connected to the absolute value sub-circuit 100, and the square operation unit 510 is used to perform a square operation on the absolute value current signal to obtain a square current signal;

[0097] A division operation unit 520, the division operation unit 520 is electrically connected to the square operation unit 510, and the division operation unit 520 is used to perform a division operation using the square current signal and the first root mean square current signal to obtain a division current signal;

[0098] An averaging operation unit, the averaging operation unit is electrically connected to the division operation unit 520, and the averaging operation unit is used to perform an averaging operation on the division current signal to obtain a second root mean square current signal.

[0099] In this embodiment, the square operation unit 510 performs a square operation on the absolute value current signal to obtain a square current signal, the division operation unit 520 performs a division operation on the square current signal and the first root mean square current signal to obtain a division current signal, and the averaging operation unit performs an average operation on the division current signal to obtain a second root mean square current signal.

[0100] In one embodiment of the present application, Figure 4 As shown, the square operation unit 510 includes:

[0101] a seventh transistor Q9, the emitter of the seventh transistor Q9 is electrically connected to the absolute value sub-circuit 100, the emitter of the seventh transistor Q9 is electrically connected to the division operation unit 520, and the base of the seventh transistor Q9 is electrically connected to the collector of the seventh transistor Q9;

[0102] The collector of the eighth transistor Q10 and the seventh transistor Q9 are electrically connected to the emitter of the eighth transistor Q10 , the collector of the eighth transistor Q10 is electrically connected to the base of the eighth transistor Q10 , and the collector of the eighth transistor Q10 is grounded.

[0103] In this embodiment, the absolute value current signal flows through the eighth transistor Q10 and the seventh transistor Q9, and the emitter voltage of the seventh transistor Q9 is calculated by the following formula:

[0104] U A =-U be9-U be10 =-V T *In(|Iin| / Is)-V T *In(|Iin| / Is)=-V T *In(|Iin| 2 / Is 2 ),

[0105] Among them, U A is the emitter voltage of the seventh transistor Q9, U be9 is the voltage between the base and emitter of the seventh transistor Q9, U be10 is the voltage between the base and the emitter of the eighth transistor Q10, VT is the temperature-voltage equivalent of the seventh transistor Q9, Is is the saturation current of the seventh transistor Q9, and |Iin| is the absolute value current signal.

[0106] Therefore, the absolute value current signal can be squared by the eighth transistor Q10 and the seventh transistor Q9 to obtain a square current signal.

[0107] Some implementation methods of the present application, such as Figure 4 As shown, the fourth operational amplifier U2 is also included, the emitter of the seventh transistor Q9 is electrically connected to the non-inverting input terminal of the fourth operational amplifier U2, the output terminal of the fourth operational amplifier U2 is electrically connected to the division operation unit 520, and the output terminal of the fourth operational amplifier U2 is electrically connected to the inverting input terminal of the fourth operational amplifier U2. The fourth operational amplifier U2 acts as a follower, and is used to input the square current signal to the division operation unit 520.

[0108] In one embodiment of the present application, Figure 4 As shown, the division unit 520 includes:

[0109] A ninth transistor Q5, the emitter of the ninth transistor Q5 is electrically connected to the square operation unit 510, and the collector of the ninth transistor Q5 is electrically connected to the average operation unit;

[0110] The logarithmic amplifier unit and the average operation unit are electrically connected to the logarithmic amplifier unit, and the logarithmic amplifier unit is electrically connected to the base of the ninth transistor Q5. The logarithmic amplifier unit is used to calculate the natural logarithm of the first root mean square current signal to obtain a logarithmic current signal, and input the logarithmic current signal to the base of the ninth transistor Q5, so that the ninth transistor Q5 performs a division operation according to the square current signal and the logarithmic current signal to obtain a division current signal.

[0111] In this embodiment, the square current signal is input to the emitter of the ninth transistor Q5, the logarithmic amplifier unit calculates the natural logarithm of the first root mean square current signal to obtain a logarithmic current signal, and inputs the logarithmic current signal to the base of the ninth transistor Q5, so that the ninth transistor Q5 performs a division operation based on the square current signal and the logarithmic current signal to obtain a divided current signal.

[0112] Some implementation methods of the present application, such as Figure 4 As shown, the logarithmic amplification subunit includes:

[0113] A fifth operational amplifier U5, wherein a non-inverting input terminal of the fifth operational amplifier U5 is grounded, an inverting input terminal of the fifth operational amplifier U5 is electrically connected to the averaging operation unit, and an output terminal of the fifth operational amplifier U5 is electrically connected to the base of the ninth transistor Q5;

[0114] The thirteenth transistor Q8, the collector of the thirteenth transistor Q8 is electrically connected to the inverting input terminal of the fifth operational amplifier U5, the base of the thirteenth transistor Q8 is grounded, and the emitter of the thirteenth transistor Q8 is electrically connected to the base of the ninth transistor Q5.

[0115] In this embodiment, the tenth transistor Q8 and the fifth operational amplifier U5 form a logarithmic amplifier, the current signal output by the average operation unit flows to the logarithmic amplifier, that is, the first root mean square current signal, and the logarithmic amplifier obtains the logarithmic current signal by calculating the natural logarithm of the first root mean square current signal. The seventh transistor Q9, the eighth transistor Q10, the ninth transistor Q5 and the tenth transistor Q8 can offset each other's temperature drift, thereby improving the temperature drift performance.

[0116] The emitter voltage of the ninth transistor Q5 is the same as the emitter voltage of the seventh transistor Q9, and the base voltage of the ninth transistor Q5 is calculated by the following formula:

[0117] U B =-U be8 =-V T *In(Irms1 / Is),

[0118] Among them, U be8 is the voltage between the base and emitter of the transistor Q8, V T is the temperature voltage equivalent of the transistor Q8, Is is the saturation current of the transistor Q8, and Irms1 is the first root mean square current signal.

[0119] The voltage between the base and emitter of the ninth transistor Q5 is calculated by the following formula:

[0120] U be5 =U B -U A =-V T*In(Irms1 / Is)+V T *In(|Iin| 2 / Is 2 )=V T *In(|Iin| 2 / Irms1 / Is 2 ),

[0121] It can be seen from the above formula that the ninth transistor Q5 performs a division operation on the square current signal and the logarithmic current signal. The collector current of the ninth transistor Q5 is then averaged by the average operation unit to obtain a second root mean square current signal, and the calculation formula is as follows:

[0122] I c5 =Irms2=mean(|Iin| 2 / Irms1),

[0123] Among them, I c5 is the collector current of the ninth transistor Q5, Irms2 is the second root mean square current signal, and mean is an operator for calculating the average value.

[0124] In one embodiment of the present application, Figure 4 As shown, the averaging operation unit includes:

[0125] A second resistor R1, a division unit 520 is electrically connected to one end of the second resistor R1, and the other end of the second resistor R1 is electrically connected to the result output sub-circuit;

[0126] The capacitor C1, the division unit 520 is electrically connected to one end of the capacitor C1, and the other end of the capacitor C1 is grounded.

[0127] In this embodiment, the second resistor R1 and the capacitor C1 form a first-order filter current. The first-order filter circuit averages the divided current signal to obtain a second RMS current signal. The current flowing through the second resistor R1 is the second RMS current signal.

[0128] Some embodiments of the present application further include a fourth mirror current source sub-circuit 400, and the fourth mirror current source sub-circuit 400 includes:

[0129] a third MOS tube M1, wherein the source of the third MOS tube M1 is electrically connected to the positive power supply terminal, the gate of the third MOS tube M1 is electrically connected to the drain of the third MOS tube M1, and the drain of the third MOS tube M1 is electrically connected to the other end of the second resistor R1;

[0130] A fourth MOS tube M2, a source of the fourth MOS tube M2 is electrically connected to the positive power supply terminal, a gate of the third MOS tube M1 is electrically connected to the gate of the fourth MOS tube M2, a drain of the fourth MOS tube M2 is electrically connected to the collector of the thirteenth transistor Q8, and a drain of the fourth MOS tube M2 is electrically connected to the inverting input terminal of the fifth operational amplifier U5;

[0131] The fifth MOS tube M3, the source of the fifth MOS tube M3 is electrically connected to the positive power supply terminal, the gate of the third MOS tube M1 is electrically connected to the gate of the fifth MOS tube M3, and the drain of the fifth MOS tube M3 is electrically connected to the result output sub-circuit.

[0132] In this embodiment, if Figure 2 As shown, the fourth mirror current source sub-circuit 400 replicates the second RMS current signal and inputs the logarithmic amplifier sub-unit through the drain of the fourth MOS tube M2, and inputs the result output sub-circuit through the drain of the fifth MOS tube M3.

[0133] In one embodiment of the present application, Figure 4 As shown, the result output subcircuit includes:

[0134] A second mirror current source subcircuit 200, the second mirror current source subcircuit 200 is electrically connected to the root mean square operation subcircuit 500, and the second mirror current source subcircuit 200 is used to replicate a second root mean square current signal;

[0135] The third resistor R14 has one end electrically connected to the second mirror current source sub-circuit 200 and the other end grounded. The third resistor R14 is used to output a root mean square voltage signal according to the second root mean square current signal.

[0136] In this embodiment, Figure 2 As shown, the second mirror current source subcircuit 200 replicates the second RMS current signal, and the second RMS current signal flows through the third resistor R14, thereby being converted into a RMS voltage signal output. The second mirror current source subcircuit 200 and the fourth mirror current source subcircuit 400 use symmetrical MOS transistors to eliminate the error introduced by the mirror current source to a certain extent, thereby providing measurement and calculation accuracy.

[0137] The root mean square voltage signal is calculated by the following formula:

[0138] Vrms=Irms2*R,

[0139] Wherein, Vrms is the root mean square voltage signal, and R is the resistance value of the third resistor R14.

[0140] Some implementation methods of the present application, such as Figure 4 As shown, the second mirror current source sub-circuit 200 includes:

[0141] a sixth MOS tube M4, wherein the drain of the sixth MOS tube M4 is electrically connected to the drain of the fifth MOS tube M3, the drain of the sixth MOS tube M4 is electrically connected to the gate of the sixth MOS tube M4, and the source of the sixth MOS tube M4 is electrically connected to the negative power supply terminal;

[0142] The seventh MOS tube M5 has a gate electrically connected to the gate of the sixth MOS tube M4, a drain electrically connected to the third resistor R14, and a source negative power supply terminal of the seventh MOS tube M5.

[0143] In this embodiment, the drain current of the sixth MOS tube M4 is the same as the drain current of the seventh MOS tube M5 , and the drain current of the sixth MOS tube M4 is the second RMS current signal, so the second RMS current signal is copied to the third resistor R14 .

[0144] In addition, an embodiment of the present application further provides a nuclear radiation detector, comprising the root mean square voltage calculation circuit as described above.

[0145] The nuclear radiation detector provided in the embodiment of the present application can implement each process implemented by the above-mentioned circuit embodiment and achieve the same beneficial effects. To avoid repetition, it will not be described here.

[0146] The embodiments of the present application are described in detail above in conjunction with the accompanying drawings, but the present application is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present application.

Claims

1. A root mean square voltage calculation circuit, characterized in that: include: an absolute value subcircuit, the absolute value subcircuit being used to perform absolute value processing on an input voltage signal of the nuclear radiation detector so as to convert the input voltage signal into an absolute value current signal; a root mean square operation subcircuit, the root mean square operation subcircuit comprising a first input terminal, a second input terminal and a signal output terminal, the first input terminal being electrically connected to the absolute value subcircuit, the signal output terminal being electrically connected to the second input terminal, the root mean square operation subcircuit being used to perform a root mean square operation on the absolute value current signal using a first root mean square current signal to convert the input voltage signal into a second root mean square current signal, the first root mean square current signal being a current signal fed back from the signal output terminal to the second input terminal; A result output subcircuit is electrically connected to the signal output terminal, and is used for converting the second root mean square current signal into a root mean square voltage signal, and outputting the root mean square voltage signal.

2. The RMS voltage calculation circuit according to claim 1, characterized in that: The absolute value subcircuit comprises: A first operational amplifier, wherein a non-inverting input terminal of the first operational amplifier is used to input the input voltage signal; a first transistor, wherein the output end of the first operational amplifier is electrically connected to the base of the first transistor, and the first transistor is configured to be turned on when the input voltage signal is positive; a first resistor, wherein the emitter of the first transistor is electrically connected to one end of the first resistor, the inverting input end of the first operational amplifier is electrically connected to the one end of the first resistor, and the other end of the first resistor is grounded; a first mirror current source subcircuit, the first mirror current source subcircuit being electrically connected to the collector of the first transistor, the first mirror current source subcircuit being electrically connected to the root mean square operation subcircuit, and the first mirror current source subcircuit being used for copying the collector current of the first transistor to obtain and output the absolute value current signal when the first transistor is turned on; A second transistor, the output end of the first operational amplifier is electrically connected to the base of the second transistor, the emitter of the second transistor is electrically connected to the one end of the first resistor, the collector of the second transistor is electrically connected to the root mean square operation subcircuit, and the second transistor is used to be turned on when the input voltage signal is negative, so that the collector of the second transistor outputs the absolute value current signal.

3. The RMS voltage calculation circuit according to claim 2, characterized in that: The first mirror current source sub-circuit comprises: a third triode, wherein the emitter of the third triode is used to be electrically connected to the positive power supply terminal; a fourth triode, wherein the collector of the third triode is electrically connected to the emitter of the fourth triode, the collector of the fourth triode is electrically connected to the collector of the first triode, and the collector of the fourth triode is electrically connected to the base of the fourth triode; a fifth triode, wherein the emitter of the fifth triode is used to be electrically connected to the positive power supply terminal, the base of the fifth triode is electrically connected to the base of the third triode, and the base of the fifth triode is electrically connected to the collector of the fifth triode; A sixth transistor, wherein the collector of the fifth transistor is electrically connected to the emitter of the sixth transistor, and the collector of the sixth transistor is electrically connected to the root mean square operation sub-circuit.

4. The RMS voltage calculation circuit according to claim 2, characterized in that: The absolute value subcircuit also includes: a first proportional amplification unit, wherein the output end of the first operational amplifier is electrically connected to the input end of the first proportional amplification unit, and the output end of the first proportional amplification unit is electrically connected to the base of the first transistor; A second proportional amplification unit, wherein the output end of the first operational amplifier is electrically connected to the input end of the second proportional amplification unit, and the output end of the second proportional amplification unit is electrically connected to the base of the second transistor.

5. The RMS voltage calculation circuit according to claim 1, characterized in that: The root mean square operation subcircuit comprises: a square operation unit, the square operation unit being electrically connected to the absolute value sub-circuit, and the square operation unit being used to perform a square operation on the absolute value current signal to obtain a square current signal; a division operation unit, the division operation unit being electrically connected to the square operation unit, and the division operation unit being used to perform a division operation using the square current signal and the first root mean square current signal to obtain a division current signal; An averaging operation unit, the averaging operation unit is electrically connected to the division operation unit, and the averaging operation unit is used to perform an averaging operation on the division current signal to obtain the second root mean square current signal.

6. The RMS voltage calculation circuit according to claim 5, characterized in that: The square operation unit comprises: a seventh triode, wherein the emitter of the seventh triode is electrically connected to the absolute value sub-circuit, the emitter of the seventh triode is electrically connected to the division operation unit, and the base of the seventh triode is electrically connected to the collector of the seventh triode; An eighth transistor, wherein the collector of the seventh transistor is electrically connected to the emitter of the eighth transistor, the collector of the eighth transistor is electrically connected to the base of the eighth transistor, and the collector of the eighth transistor is grounded.

7. The RMS voltage calculation circuit according to claim 5, characterized in that: The division operation unit comprises: a ninth triode, wherein the emitter of the ninth triode is electrically connected to the square operation unit, and the collector of the ninth triode is electrically connected to the average operation unit; A logarithmic amplification subunit, the average operation unit is electrically connected to the logarithmic amplification subunit, the logarithmic amplification subunit is electrically connected to the base of the ninth transistor, the logarithmic amplification subunit is used to calculate the natural logarithm of the first root mean square current signal to obtain a logarithmic current signal, and input the logarithmic current signal to the base of the ninth transistor, so that the ninth transistor performs a division operation according to the square current signal and the logarithmic current signal to obtain the divided current signal.

8. The RMS voltage calculation circuit according to claim 5, characterized in that: The averaging operation unit comprises: a second resistor, the division operation unit being electrically connected to one end of the second resistor, and the other end of the second resistor being electrically connected to the result output subcircuit; The dividing unit is electrically connected to one end of the capacitor, and the other end of the capacitor is grounded.

9. The RMS voltage calculation circuit according to claim 1, characterized in that: The result output subcircuit comprises: a second mirror current source subcircuit, the second mirror current source subcircuit being electrically connected to the root mean square operation subcircuit, and the second mirror current source subcircuit being used to replicate the second root mean square current signal; A third resistor, one end of the third resistor is electrically connected to the second mirror current source sub-circuit, the other end of the third resistor is grounded, and the third resistor is used to output the root mean square voltage signal according to the second root mean square current signal.

10. A nuclear radiation detector, characterized in that: The invention comprises a root mean square voltage calculation circuit as claimed in any one of claims 1 to 9.

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