Beam brake control circuit of electron beam exposure machine

Abstract

The invention discloses a beam gate control circuit of an electron beam exposure machine. The beam gate control circuit comprises a pattern generator, a delay circuit, a pulse generation circuit and a driving circuit, the pattern generator, the delay circuit, the pulse generation circuit and the driving circuit are connected in sequence; the driving circuit comprises a first driving unit and a second driving unit; the first driving unit is connected with a positive power supply and is connected with a polar plate L of the electron beam exposure machine; the second driving unit is connected with a negative power supply and is connected with a polar plate H of the electron beam exposure machine. The device has the advantages of low pole plate voltage, high beam brake switching speed and the like.

Description

Technical Field

[0001] The present invention mainly relates to the technical field of electron beam exposure machines, and in particular to a beam gate control circuit of an electron beam exposure machine. Background Art

[0002] Electron beam exposure machines are mainly used in the field of micro-nano processing. On the one hand, electron beam exposure can directly produce the required graphics under computer control, and it is easy to modify and has a short production cycle. Therefore, it is widely used in the production of photomasks and X-ray masks. It has become the main means of making masks in the microelectronics industry. On the other hand, the electron beam exposure system can achieve extremely high overlay accuracy using mark detection technology, so it can directly draw on the wafer, that is, directly manufacture devices on the wafer without a mask. Therefore, it is used in the development of new devices and new integrated circuits and the production of small batches of devices and integrated circuits.

[0003] The biggest feature of electron beam exposure is its extremely high resolution. Its graphic resolution mainly depends on the beam spot size and the scattering effect of the electron beam in the photosensitive resin material. The electron beam spot can be focused into several angstroms and is easy to control automatically. It is the highest resolution practical exposure method so far and the only known nano-processing technology. In addition, its graphics are easy to generate and modify, and the production cycle is short, so it is widely used in the production of high-resolution mask masters.

[0004] The beam gate is a system that controls the on and off of the electron beam. Its performance directly affects the speed of the exposure machine. If the speed of the beam gate is too slow, the exposed pattern will have a "tailing" phenomenon.

[0005] At present, beam gates mostly use half-bridge circuits, with PMOS for the upper tube and NMOS for the lower tube. The deflection voltage is not high, and the accuracy of exposure time control is not high. Figure 1 The figure shows the principle diagram of the electron beam exposure machine. The electron gun emits electrons, and the electron beam is moved through lens focusing, main deflection and sub-deflection coils, and then exposed at the corresponding position of the wafer to achieve the purpose of etching. The switch of the electron beam is realized by the beam gate and the aperture. When the beam gate is opened, the electron beam is deflected by the electric field or magnetic field generated by the beam gate, and the electron beam is blocked by the aperture to achieve the purpose of closing the electron beam; when the beam gate is closed, the electron beam is directly projected to the wafer and etching begins.

[0006] The working principle of the beam brake is as follows Figure 2 As shown. Figure 2 It can be seen that as long as a voltage ( Figure 2 100V), then use two switches ( Figure 2In the figure, K1 and K2 are used to realize the beam gate function in the electron beam exposure machine. This is also the implementation method of most beam gates at present. The two switches are generally implemented by a half-bridge circuit. K1 generally uses PMOS (P-type transistor) and K2 uses NMOS (N-type transistor). When K1 is closed and K2 is disconnected, the beam gate is opened and the electron beam cannot pass through; when K2 is closed and K1 is disconnected, the beam gate is closed and the electron beam passes through. There are two problems with this method: the first problem is that since the switch is realized by transistors, the transistors have internal resistance when they are turned on, so the left and right plates are not completely equipotential, that is, there is a voltage difference between the two plates, which will cause a slight deflection of the electrons; the second problem is that since the switching speed must be fast (to prevent the electron beam from tailing) and the voltage must be high (the deflection distance is large to achieve complete shutdown), it is difficult to take both into account. Summary of the invention

[0007] In view of the technical problems existing in the prior art, the present invention provides a beam gate control circuit of an electron beam exposure machine with a fast switching speed.

[0008] In order to solve the above technical problems, the technical solution proposed by the present invention is: A beam gate control circuit for an electron beam exposure machine comprises a pattern generator, a delay circuit, a pulse generating circuit and a driving circuit; the pattern generator, the delay circuit, the pulse generating circuit and the driving circuit are connected in sequence; the driving circuit comprises a first driving unit and a second driving unit; the first driving unit is connected to a positive power supply and is connected to a plate L of the electron beam exposure machine; the second driving unit is connected to a negative power supply and is connected to a plate H of the electron beam exposure machine.

[0009] Preferably, the first driving unit includes resistors R1-R4, capacitors C1-C3, switches Q1 and Q2; wherein one end of the resistor R1 is connected to the positive power supply +V, and the other end of the resistor R1 is grounded via capacitors C2 and C3 respectively; the source of the switch Q1 is grounded, and the drain is connected to one end of the resistor R4; the source of the switch Q2 is connected to the other end of R1, and the drain is connected to one end of the resistor R2; the other end of the resistor R2 and the other end of the resistor R4 are both connected to the plate L via the resistor R3.

[0010] Preferably, the second driving unit includes resistors R5-R8, capacitors C4-C6, switches Q3 and Q4; wherein one end of the resistor R5 is connected to the positive power supply -V, and the other end of the resistor R5 is grounded via capacitors C4 and C5 respectively; the source of the switch Q4 is grounded, and the drain is connected to one end of the resistor R8; the source of the switch Q3 is connected to the other end of R5, and the drain is connected to one end of the resistor R6; the other end of the resistor R6 and the other end of the resistor R8 are both connected to the plate H via the resistor R7.

[0011] Preferably, the switch Q1 and the switch Q4 are high-speed NMOS, and the switch Q2 and the switch Q3 are high-speed PMOS.

[0012] Preferably, the switch Q1 and the switch Q4 are packaged in one body.

[0013] Preferably, the pattern generator and the delay circuit communicate via a parallel port.

[0014] Preferably, the delay circuit includes FPGA1, FPGA2, a prefabricated number unit, a counter delay unit, a precise delay unit, and CPLD1-6; the FPGA1, FPGA2, the prefabricated number unit and the counter delay unit are connected in sequence; the counter delay unit is connected to the pulse generating circuit via CPLD1; FPGA2 is connected to the pulse generating circuit via CPLD1, and is connected to the precise delay unit via CPLD2-6 respectively, and the precise delay unit is connected to the pulse generating circuit.

[0015] Preferably, the FPGA1 is connected to the FPGA2 via an optocoupler isolation circuit and a data buffer in sequence.

[0016] Preferably, the delay circuit includes an FPGA and a precise delay unit, the input end of the FPGA is connected to the graphic generator, the output end of the FPGA is respectively connected to the input end of the precise delay unit and the pulse generating circuit, and the output end of the precise delay unit is connected to the pulse generating circuit.

[0017] Preferably, it also includes a beam detection system and a secondary detection electronic detection system, and both the beam detection system and the secondary detection electronic detection system are connected to the pattern generator.

[0018] Compared with the prior art, the advantages of the present invention are: The present invention uses a left-right symmetrical manner to control the voltage between the two plates through the first drive unit and the second drive unit. Only half the voltage of the existing beam gate is needed to generate the same electric field between the two plates, so the requirements for the device are greatly reduced. In this way, a power device with a faster switching speed can be selected to achieve a faster switching speed.

[0019] The pattern generator of the present invention communicates with the delay circuit via a parallel port, and the time length when the electron beam needs to be judged is directly transmitted to the delay circuit once via the parallel port, which greatly shortens the communication time and improves the switching speed.

[0020] The present invention sends time data, voltage and other signals to the delay circuit at one time through the parallel port. The delay circuit converts the trigger signal and time signal into a driving pulse to be exposed through the FPGA algorithm. The pulse accuracy can reach a resolution of 10pS, and the on-off control of the electron beam can be quickly realized. The communication realizes the transmission of data and commands, and has strong anti-interference ability and high speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The figure is a schematic diagram of an electron beam exposure machine in the prior art.

[0022] Figure 2 FIG. 4 is a diagram showing the working principle of a beam brake in the prior art.

[0023] Figure 3 FIG. 4 is a schematic diagram of a beam gate control circuit in an embodiment of the present invention.

[0024] Figure 4 FIG. 4 is a circuit diagram of a beam gate control circuit in an embodiment of the present invention.

[0025] Figure 5 FIG. 1 is a diagram showing an embodiment of the beam gate control circuit of the present invention in a specific application.

[0026] Figure 6 It is the principle diagram of centering of the present invention.

[0027] Figure 7 This is one of the embodiment diagrams of the delay circuit of the present invention in a specific application.

[0028] Figure 8 This is the second embodiment diagram of the delay circuit of the present invention in a specific application. DETAILED DESCRIPTION

[0029] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments.

[0030] like Figure 8 As shown, the beam gate control circuit of the electron beam exposure machine provided by the embodiment of the present invention includes a pattern generator, a delay circuit, a pulse generating circuit and a driving circuit; the pattern generator, the delay circuit, the pulse generating circuit and the driving circuit are connected in sequence; as shown Figure 3 As shown, the driving circuit includes a first driving unit and a second driving unit; the first driving unit is connected to a positive power supply and is connected to a plate L of an electron beam exposure machine; the second driving unit is connected to a negative power supply and is connected to a plate H of an electron beam exposure machine.

[0031] Specifically, the delay controller receives the control command sent by the pattern generator (including trigger signal, voltage value of adjustable power supply and beam gate closing time and other signals), and after coarse delay and fine delay, sends it to the pulse generation circuit to generate a drive pulse, which is then quickly charged and discharged by the drive circuit. The corresponding voltage on the beam gate generates a corresponding electric field to control the on and off of the electron beam.

[0032] The main function of the delay circuit (delay controller) is to delay the switch signal given by the pattern generator to the required time point through programmable pulse delay technology, and coordinate with the timing of various components of the exposure machine such as biasing, centering, and motion control platform to achieve the designed timing and expose at the appropriate time.

[0033] The present invention uses a left-right symmetrical manner to control the voltage between the two plates through the first drive unit and the second drive unit. Only half the voltage of the existing beam gate is needed to generate the same electric field between the two plates, so the requirements for the device are greatly reduced. In this way, a power device with a faster switching speed can be selected to achieve a faster switching speed.

[0034] like Figure 8 As shown, the pattern generator and the delay circuit communicate through the parallel port, and the length of time the electron beam needs to judge is directly transmitted to the delay circuit through the parallel port (the number of bits of the parallel port can be defined according to the length of time, such as the shutdown time is 10nS, and the time resolution is 10pS, so that the 10-bit data line can convey the required time signal at one time), which greatly shortens the communication time and improves the switching speed.

[0035] like Figure 4 As shown, the first driving unit includes resistors R1-R4, capacitors C1-C3, switches Q1 and Q2; one end of the resistor R1 is connected to the positive power supply +V, and the other end of the resistor R1 is grounded via capacitors C2 and C3 respectively; the source of the switch Q1 is grounded, and the drain is connected to one end of the resistor R4; the source of the switch Q2 is connected to the other end of R1, and the drain is connected to one end of the resistor R2; the other end of the resistor R2 and the other end of the resistor R4 are both connected to the plate L via the resistor R3.

[0036] Similarly, the circuit structure of the second driving unit is the same as that of the first driving unit. Specifically, the second driving unit includes resistors R5-R8, capacitors C4-C6, switches Q3 and Q4; one end of the resistor R5 is connected to the positive power supply -V, and the other end of the resistor R5 is grounded via capacitors C4 and C5 respectively; the source of the switch Q4 is grounded, and the drain is connected to one end of the resistor R8; the source of the switch Q3 is connected to the other end of R5, and the drain is connected to one end of the resistor R6; the other end of the resistor R6 and the other end of the resistor R8 are both connected to the plate H via the resistor R7.

[0037] R1 and R5 are mainly used for current limiting; Q1 and Q4 are high-speed NMOS, Q2 and Q3 are high-speed PMOS; because the on-resistance of PMOS is generally larger than that of NMOS, precision resistors R2-R4 and R6-R8 are added to adjust the loop to maintain the symmetry of the circuit during switching and achieve a good balance, that is, the electric field 0 point between the two plates is in the middle of the plates during switching. Q1 and Q4 are NMOS packaged together, and the difference in on-resistance is very small, which can reduce the impact on the electron beam when the beam gate is turned off.

[0038] In specific applications, for example, to generate an exposure pulse with an exposure time of 10uS, a 32-bit parallel port data line is used, and the pulse resolution is 10pS. 32*10pS=0.0429S=42.9uS, which is greater than 10uS. The pattern generator can transmit the exposure data to the delay controller through the parallel port at one time, and at the same time send the exposure trigger signal to the delay controller; at the same time, the pattern generator will also send the voltage required by the beam gate controller to the beam gate controller, and the beam gate controller will generate the corresponding voltage and send the corresponding voltage back to the pattern generator. The FPGA in the delay controller sends the exposure data to the exposure pulse generation circuit, converts it into the pulse width to be exposed, and then transmits the pulse to the drive circuit to drive the beam gate to realize the switch.

[0039] After exposure, use relevant detection instruments to detect the exposure results. If overexposure or underexposure occurs, the fine delay of the delay controller can be adjusted (the adjustable accuracy can reach 10pS) to achieve high-precision control of exposure and achieve a good exposure effect.

[0040] like Figure 5-Figure 6 As shown, during the centering adjustment, the pattern generator first sets a maximum voltage for the beam gate, and then slowly lowers the voltage of the beam gate. Each time the voltage is adjusted, the beam current and secondary electrons are detected simultaneously. When the beam current changes and the secondary electron imaging changes sharply, the position of the middle of the beam gate plate where the current electron beam is located is calculated. Then the centering coil is adjusted, and the above steps are repeated until the calculated distance from the perpendicular plane to the electron beam to the beam gate plate is equal to the actual designed distance, indicating that the electron beam coincides with the designed central axis and the alignment is completed.

[0041] like Figure 6 As shown in the figure, electron beam 2# is the position when it is not centered. The electron beam needs to be moved to Figure 6 The specific steps are as follows: through the beam gate control system, adjust the voltage of the beam gate from the maximum to the smaller direction. When it is found that the secondary electron or backscattered electron imaging changes sharply, the beam gate voltage value at this time is recorded. Then, when the electron passes through a certain acceleration voltage at a fixed acceleration voltage V and a distance H, D can be calculated and compared with the distance d required by the design. Then, through calculation, adjust the corresponding centering power supply voltage; then repeat the above steps until the error between the two is within the allowable range, the centering is completed, and the focusing is a similar step.

[0042] like Figure 7As shown, in the delay circuit, the beam gate is controlled by VME bus, and the microcontroller FPGA1 realizes VME communication. Through VME bus, it forms a control system with other boards to realize real-time control. The pattern generator sends the delay data to FPGA2 through optical coupling isolation. FPGA2 mainly realizes the formation of exposure pulses; specifically, FPGA2 sends the coarse delay data to the prefabricated counting circuit. At the same time, through the trigger pulse and system reset signal sent by the pattern generator, the counter delay circuit starts counting. When the count reaches the prefabricated value, an overflow signal is generated to CPLD1, which enters the pulse generation circuit after being processed by CPLD1. At the same time, FPGA2 controls the precise delay circuit to perform the corresponding fine delay through CPLD2-CPLD6 according to the data sent by the pattern generator. After the fine delay is completed, it enters the exposure pulse generation circuit, generates an exposure pulse with the above counter coarse delay, and then reaches the drive circuit, and then drives the beam gate switch to complete the exposure.

[0043] The above coarse delay adopts a counter solution, but it still has the following disadvantages in specific applications: 1. The frequency of the system clock determines the maximum delay resolution of the counting method. Due to the limitations of the current crystal oscillator process, the system designed using this method cannot achieve a very high delay resolution.

[0044] 2. The counter delay method is suitable for the delay of a single pulse. If the signal to be delayed is a periodic pulse, when the pulse interval is less than the delay time, the second pulse signal arrives before the first pulse signal reaches the start counter and the counting delay is completed. The counter will stop counting and delaying the first pulse signal and start technical delaying the second pulse. In this way, the delay of the first pulse entering the counter is not completed.

[0045] 3. Systems designed using various 74 series chips can achieve shorter delays, but if the delay time increases, multiple delay chips will need to be connected in series to complete the delay. This will increase the system wiring, the cost of circuit board production, the number of devices, and the PCB size. Moreover, the maximum delay time cannot be changed after the circuit board is manufactured, and the reuse rate is low.

[0046] Through the analysis of the advantages and disadvantages of the above solutions, combined with the development of new technologies, the present invention adopts a solution combining digital delay and analog delay. Considering the convenience of implementation and the development cycle, the digital delay is directly implemented by FPGA. The specific solution block diagram is shown in the figure. Figure 8As shown: the driving circuit adopts an H-bridge circuit, which can realize positive and negative power supply, and add positive and negative electricity to the two electrodes of the beam gate respectively to realize four different combinations of electric fields; the time data and voltage signals are sent to the delay circuit at one time through the parallel port. The delay circuit converts the trigger signal and time signal into the driving pulse to be exposed through the FPGA algorithm. The trigger signal is used to determine the start time of the exposure. The FPGA first generates a coarse delay, and then controls the digital delay chip to generate a fine delay through the FPGA. Then, through the pulse synthesis circuit, these three parts are synthesized into a pulse required for exposure. The pulse accuracy can reach a resolution of 10pS, which can quickly realize the on-off control of the electron beam, and the communication realizes the transmission of data and commands, with strong anti-interference and fast speed.

[0047] The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims

1. A beam gate control circuit for an electron beam exposure machine, characterized in that: It includes a pattern generator, a delay circuit, a pulse generating circuit and a driving circuit; the pattern generator, the delay circuit, the pulse generating circuit and the driving circuit are connected in sequence; the driving circuit includes a first driving unit and a second driving unit; the first driving unit is connected to a positive power supply and is connected to a plate L of an electron beam exposure machine; the second driving unit is connected to a negative power supply and is connected to a plate H of the electron beam exposure machine.

2. The beam gate control circuit of the electron beam exposure machine according to claim 1, characterized in that: The first driving unit includes resistors R1-R4, capacitors C1-C3, switches Q1 and Q2; one end of the resistor R1 is connected to the positive power supply +V, and the other end of the resistor R1 is grounded via capacitors C2 and C3 respectively; the source of the switch Q1 is grounded, and the drain is connected to one end of the resistor R4; the source of the switch Q2 is connected to the other end of R1, and the drain is connected to one end of the resistor R2; the other end of the resistor R2 and the other end of the resistor R4 are both connected to the plate L via the resistor R3.

3. The beam gate control circuit of the electron beam exposure machine according to claim 2, characterized in that: The second driving unit includes resistors R5-R8, capacitors C4-C6, switches Q3 and Q4; one end of the resistor R5 is connected to the positive power supply -V, and the other end of the resistor R5 is grounded via capacitors C4 and C5 respectively; the source of the switch Q4 is grounded, and the drain is connected to one end of the resistor R8; the source of the switch Q3 is connected to the other end of R5, and the drain is connected to one end of the resistor R6; the other end of the resistor R6 and the other end of the resistor R8 are both connected to the plate H via the resistor R7.

4. The beam gate control circuit of the electron beam exposure machine according to claim 3, characterized in that: The switch Q1 and the switch Q4 are high-speed NMOS, and the switch Q2 and the switch Q3 are high-speed PMOS.

5. The beam gate control circuit of the electron beam exposure machine according to claim 4, characterized in that: The switch Q1 and the switch Q4 are packaged in one body.

6. The beam gate control circuit of an electron beam exposure machine according to any one of claims 1 to 5, characterized in that: The pattern generator and the delay circuit communicate with each other via a parallel port.

7. The beam gate control circuit of an electron beam exposure machine according to any one of claims 1 to 5, characterized in that: The delay circuit includes FPGA1, FPGA2, a prefabricated number unit, a counter delay unit, a precise delay unit, and CPLD1-6; the FPGA1, FPGA2, the prefabricated number unit and the counter delay unit are connected in sequence; the counter delay unit is connected to the pulse generating circuit via CPLD1; FPGA2 is connected to the pulse generating circuit via CPLD1, and is connected to the precise delay unit via CPLD2-6 respectively, and the precise delay unit is connected to the pulse generating circuit.

8. The beam gate control circuit of the electron beam exposure machine according to claim 7, characterized in that: The FPGA1 is connected to the FPGA2 via an optical coupling isolation circuit and a data buffer in sequence.

9. The beam gate control circuit of an electron beam exposure machine according to any one of claims 1 to 5, characterized in that: The delay circuit includes an FPGA and a precise delay unit, the input end of the FPGA is connected to a pattern generator, the output end of the FPGA is respectively connected to the input end of the precise delay unit and a pulse generating circuit, and the output end of the precise delay unit is connected to the pulse generating circuit.

10. The beam gate control circuit of an electron beam exposure machine according to any one of claims 1 to 5, characterized in that: It also includes a beam detection system and a secondary detection electronic detection system, and both the beam detection system and the secondary detection electronic detection system are connected to the pattern generator.

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