Vector processor, operation method of vector processor and electronic equipment

Abstract

The invention discloses a vector processor, an operation method of the vector processor and electronic equipment. The vector processor comprises a scalar core used for executing a received scalar request instruction to obtain a first instruction execution result, and sending a received vector request instruction to a vector unit; the vector unit is connected with the scalar core through the communication interface unit and used for executing the vector request instruction to obtain a second instruction execution result; and the controller is respectively connected with the scalar core and the vector unit, and is used for configuring clock domains of the scalar core and the vector unit according to the first clock frequency and the second clock frequency, and configuring power supply domains of the scalar core and the vector unit according to the first working state and the second working state. The technical problem that the processing efficiency of a processor in the related technology is low is solved.

Description

Technical Field

[0001] The present application relates to the field of processors, and in particular, to a vector processor, an operating method of a vector processor, and an electronic device. Background Art

[0002] With the rapid development of artificial intelligence and machine learning, the demand for computing performance has increased dramatically, driving the innovation of processor architecture to meet the needs of large-scale parallel computing. Although traditional scalar processors perform well in processing single data elements, their performance improvement faces bottlenecks in the face of massive data processing in artificial intelligence (AI) applications. Vector processors can theoretically significantly improve computing efficiency by processing multiple data elements at a time. However, while increasing the vector length to achieve more efficient parallel computing, it also brings challenges such as increased design complexity, reduced energy efficiency, and bottlenecks in memory access bandwidth.

[0003] Specifically, the tightly coupled design of the vector unit and the scalar core makes the increase of vector length significantly increase the complexity and cost of the overall design; the constraint of operating at the same frequency leads to an increase in the system's power consumption per unit area and a decrease in energy efficiency when pursuing higher computing performance; and the calculation of large vector lengths requires high-bandwidth data transmission. Under the tightly coupled structure, the memory access capability of the vector unit is limited due to the sharing of memory access units, making it difficult to effectively support access to large-scale data sets, resulting in low processing efficiency of the processor.

[0004] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0005] The embodiments of the present application provide a vector processor, a method for operating a vector processor, and an electronic device to at least solve the technical problem of low processing efficiency of the processor in the related art.

[0006] According to one aspect of an embodiment of the present application, a vector processor is provided, comprising: a scalar core, configured to execute a received scalar request instruction, obtain a first instruction execution result, and send the received vector request instruction to a vector unit, wherein the scalar core has a first clock frequency and a first working state; a vector unit, connected to the scalar core via a communication interface unit, configured to execute the vector request instruction, obtain a second instruction execution result, wherein the vector unit has a second clock frequency and a second working state; a controller, respectively connected to the scalar core and the vector unit, configured to configure the clock domains of the scalar core and the vector unit according to the first clock frequency and the second clock frequency, and to configure the power supply domains of the scalar core and the vector unit according to the first working state and the second working state.

[0007] According to another aspect of an embodiment of the present application, a method for operating a vector processor is also provided, which is applied to a processor, including: in response to a scalar core receiving a scalar request instruction and a vector request instruction, executing the scalar request instruction through the scalar core to obtain a first instruction execution result, sending the vector request instruction to the vector unit, and obtaining a first clock frequency and a first working state of the scalar core; executing the vector request instruction through the vector unit to obtain a second instruction execution result, and obtaining a second clock frequency and a second working state of the vector unit; configuring clock domains for the scalar core and the vector unit based on the first clock frequency and the second clock frequency respectively; configuring power supply domains for the scalar core and the vector unit based on the first working state and the second working state respectively.

[0008] According to another aspect of the embodiments of the present application, a processor is further provided, comprising: a vector processor according to any one of the above embodiments.

[0009] According to another aspect of the embodiments of the present application, a system on chip is also provided, including: a vector processor according to any one of the above embodiments.

[0010] An electronic device according to an embodiment of the present application includes: a memory storing an executable program; and a processor for running the program, wherein the program executes any one of the methods in the above embodiments when running.

[0011] According to a computer-readable storage medium of an embodiment of the present application, the computer-readable storage medium includes a stored executable program, wherein when the executable program is running, the device where the storage medium is located is controlled to execute any one of the methods in the above embodiments.

[0012] According to another aspect of the embodiments of the present application, a computer terminal is further provided, including: a memory storing an executable program; and a processor for running the program, wherein the method in each embodiment of the present application is executed when the program is running.

[0013] According to another aspect of an embodiment of the present application, a computer-readable storage medium is also provided, the computer-readable storage medium including a stored executable program, wherein when the executable program is running, the device where the computer-readable storage medium is located is controlled to execute the methods in each embodiment of the present application.

[0014] According to another aspect of the embodiments of the present application, a computer program product is also provided, including a computer program, and when the computer program is executed by a processor, the method in each embodiment of the present application is implemented.

[0015] According to another aspect of an embodiment of the present application, a computer program product is also provided, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method in each embodiment of the present application is implemented.

[0016] According to another aspect of the embodiments of the present application, a computer program is also provided, and when the computer program is executed by a processor, the methods in the various embodiments of the present application are implemented.

[0017] In an embodiment of the present application, a vector processor includes: a scalar core, which is used to execute a received scalar request instruction, obtain a first instruction execution result, and send the received vector request instruction to a vector unit, wherein the scalar core has a first clock frequency and a first working state; a vector unit, which is connected to the scalar core through a communication interface unit, and is used to execute the vector request instruction and obtain a second instruction execution result, wherein the vector unit has a second clock frequency and a second working state; a controller, which is respectively connected to the scalar core and the vector unit, and is used to configure the clock domains of the scalar core and the vector unit according to the first clock frequency and the second clock frequency, and configure the power supply domains of the scalar core and the vector unit according to the first working state and the second working state, thereby achieving the purpose of improving processor efficiency. It is easy to notice that by introducing the communication interface unit to decouple the scalar core and the vector unit, the two can run independently at different clock frequencies. The scalar core remains at the first clock frequency and can run at a higher frequency to optimize the processing speed of the scalar task; the vector unit runs at the second clock frequency and can be adjusted to a better frequency according to the actual computing requirements to achieve efficient vector calculation. The controller can dynamically adjust the clock domain and power supply domain between the scalar core and the vector unit according to the working state and clock frequency of the scalar core and the vector unit, that is, when vector calculation is not required, the vector unit can be placed in a low power mode, and when the scalar core processes vector instructions, the vector unit can be quickly activated to match the required high-performance state, reducing unnecessary power consumption and improving energy efficiency. The loosely coupled operation of the scalar core and the vector unit allows the two to be independently optimized according to their respective task types and requirements, thereby solving the technical problem of low processor processing efficiency in the related art due to the shared restrictions on clock frequency and memory access bandwidth. At the same time, through the dynamic management of the controller, the efficient operation and good energy efficiency performance of the system are ensured, thereby solving the technical problem of low processor processing efficiency in the related art.

[0018] It is easy to notice that the above general description and the following detailed description are only for the purpose of exemplifying and explaining the present application, and do not constitute a limitation of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0020] Figure 1 It is a hardware structure block diagram of a RISC-V system for implementing an operation method of a vector processor according to an embodiment of the present application;

[0021] Figure 2 is a schematic diagram of a system on chip according to an embodiment of the present application;

[0022] Figure 3 is a schematic diagram of a vector processor according to an embodiment of the present application;

[0023] Figure 4 is a schematic diagram of a vector processor according to an embodiment of the present application;

[0024] Figure 5 is a schematic diagram of a structure in which a scalar core and a vector unit share the same clock domain according to an embodiment of the present application;

[0025] Figure 6 is a schematic diagram of a structure in which a scalar core and a vector unit use different clock domains according to an embodiment of the present application;

[0026] Figure 7 is a schematic diagram of a structure in which a scalar core and a vector unit share the same power supply domain according to an embodiment of the present application;

[0027] Figure 8 is a schematic diagram of a structure in which a scalar core and a vector unit use different power supply domains according to an embodiment of the present application;

[0028] Fig. 9 is a flowchart of a method for operating a vector processor according to an embodiment of the present application;

[0029] Fig.10 is a schematic diagram of maintaining a memory access sequence according to an embodiment of the present application;

[0030] Fig.11 is a schematic diagram of a structure of lightweight multithreading between a scalar core and a vector unit according to an embodiment of the present application;

[0031] Fig.12 is a schematic diagram of an operating device of a vector processor according to an embodiment of the present application;

[0032] Fig.13 It is a structural block diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0035] First, some nouns or terms that appear in the description of the embodiments of the present application are subject to the following explanations:

[0036] Scalar Core, in computer architecture, scalar core refers to the processor (Central Processing Unit, referred to as CPU) core that processes a single data element. It is mainly responsible for calculating scalar data such as integers (ScalarInteger) and floating-point numbers (Scalar Floating-Point). Scalar cores do not directly process vector or matrix operations, which are usually handled by dedicated vector units or floating-point units.

[0037] Vector Unit: A vector unit is an execution unit in the CPU architecture that is specifically used to process vector instructions. It can perform operations on multiple data elements (i.e., vectors) at the same time, such as vector addition, vector multiplication, etc., which is very important in parallel computing and high-performance computing. A vector unit not only contains a vector computing unit, but may also contain a memory access unit for vector data access.

[0038] The General Interface Unit (GIU) is a bridge between the scalar core and the vector unit. It manages data transfer and instruction delivery between the two. The GIU can contain a series of interfaces and communication mechanisms, allowing the scalar core to send vector instructions to the vector unit and receive calculation results or status feedback from the vector unit. This unit is important to ensure that different components in the CPU architecture work together.

[0039] The ever-growing demand for AI applications requires the CPU to provide greater computing power. The reduced instruction set (RISC-V) CPU can meet the computing power requirements by increasing the vector length. In the traditional CPU core structure, the Vector Unit is tightly coupled with the Scalar Core and shares the same clock. If the Vector Length is increased, the implementation complexity of the CPUCore will increase. At the same time, because the Vector Unit and the Scalar Core have the same frequency, the energy efficiency per unit area will decrease. In addition, a large Vector Length requires a larger memory access bandwidth. Because in the tightly coupled structure, the Vector Unit reuses the memory access unit of the Scalar Core, which will result in limited memory access capabilities of the Vector Unit and cannot support a large Vector Length, resulting in low processing efficiency of the processor.

[0040] In this application, by designing the scalar core and vector unit as a loosely coupled architecture, the operating frequency and power management of the two can be optimized independently, while maintaining the communication and data consistency between the two through the GIU unit. This design helps to improve the overall performance and energy efficiency of the CPU, especially when processing artificial intelligence (AI) computing and large-scale parallel computing tasks.

[0041] Example 1

[0042] According to an embodiment of the present application, a method for operating a vector processor is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0043] The method embodiment provided in Embodiment 1 of the present application can be executed in a RISC-V system, a RISC-V chip or a similar device. Figure 11 is a hardware structure block diagram of a RISC-V system for implementing an operation method of a vector processor according to an embodiment of the present application. Figure 1 As shown, the RISC-V system 100 can be divided from the bottom layer to the upper layer into a reduced instruction set architecture 101 (including a basic instruction set 101-1 and an extended instruction set 101-2), a hardware layer 102 (including a processor 102-1, a peripheral hardware circuit 102-2, etc.), an interface layer 103, an operating system layer 104 (supporting multiple operating systems 104-1, 104-2, ..., 104-n, such as Linux, FreeSBD, RT-Tread, etc.), a middleware and library layer 105 (including a system library 105-1, an API 105-2 and a middleware service 105-3) and an application layer 106 (including multiple user programs and services 106-1, 106-2, ..., 106-n). The RISC-V system 100 also includes a tool chain 107 from the underlying hardware to the application layer. The tool chain may include a compiler and assembler 107-1, a linker 107-2, a debugger 107-3, a simulator and emulator 107-4, an integrated development environment 107-5, a hardware description language tool 107-6, a performance analysis tool 107-7, and a version control system 107-8, etc.

[0044] The instruction set architecture 101 defines the basic operations and instruction sets supported by the processor 102-1, including a basic instruction set and an extended instruction set, wherein the basic instruction set represents a basic integer instruction set, such as RV32I and RV64I, and the extended instruction set can be floating point, atomic operations, compressed instructions, etc.

[0045] The interface layer 103 includes the specific design of the processor, such as pipeline design, cache structure, execution unit, branch prediction, etc. This layer is the process of mapping abstract instructions to physical hardware.

[0046] The operating system layer 104 is located at the hardware level and provides a hardware abstraction layer and management mechanism, so that applications can interact with the hardware through system calls. The operating system is responsible for managing processor resources, memory, device drivers, task scheduling, etc.

[0047] The middleware and library layer 105 provides a rich set of services and interfaces to help applications run more efficiently. For example, the standard library provides functions such as file operations and mathematical calculations, while the middleware can provide complex services such as network communications and graphical user interfaces.

[0048] The application layer 106 uses the functions and services provided by the lower layer to implement specific application logic. These applications can be command line tools, graphical interface applications, server-side services, etc.

[0049] The tool chain 107 is a key component that connects the underlying hardware to the upper-level software. Various tools in the tool chain 107 function at different levels to support the entire process from hardware design to software development, ensuring the consistency and effectiveness of the entire system design.

[0050] It should be noted that the layered design of the RISC-V architecture allows decoupling between different layers, so that each layer can be developed and optimized independently.

[0051] In an optional embodiment, Figure 2 Shown using the above Figure 1 Schematic diagram of the RISC-V architecture system on chip (SOC). Figure 2 is a schematic diagram of a system on chip according to an embodiment of the present application, such as Figure 2 As shown, the SOC includes at least one RISC-V core 202 (only one is shown in the figure), and the RISC-V core 202 is connected to peripheral devices through a bus 204, including but not limited to ROM 206, RAM 208, timer 210, UART (Universal Asynchronous Receiver / Transmitter) 212, GPIO (General Purpose Input / Output) 214, SPI (Serial Peripheral Interface Bus) 216, etc.

[0052] Under the above operating environment, this application provides Figure 3 The vector processor shown, Figure 3 is a schematic diagram of a vector processor according to an embodiment of the present application, such as Figure 3 The vector processor 300 includes: a scalar core 302 , a vector unit 304 , and a controller 306 .

[0053] Among them, the scalar core is used to execute the received scalar request instruction, obtain the first instruction execution result, and send the received vector request instruction to the vector unit, wherein the scalar core has a first clock frequency and a first working state; the vector unit is connected to the scalar core through a communication interface unit, and is used to execute the vector request instruction to obtain the second instruction execution result, wherein the vector unit has a second clock frequency and a second working state; the controller is connected to the scalar core and the vector unit respectively, and is used to configure the clock domains of the scalar core and the vector unit according to the first clock frequency and the second clock frequency, and configure the power supply domains of the scalar core and the vector unit according to the first working state and the second working state.

[0054] The Scalar Core mentioned above is a processor core that is specifically used to process scalar data, that is, to operate one data element at a time (such as an integer or floating point number). It is responsible for parsing and executing the scalar instruction set and providing basic computing capabilities. The scalar core can execute scalar instructions such as addition and multiplication, and its first clock frequency and first working state can be independently configured to optimize the processing speed and power consumption of scalar tasks.

[0055] The above-mentioned vector unit is an execution unit in the processor, which is specially used to process vector data, that is, to operate multiple data elements at a time. The vector unit usually contains vector registers, vector operation units and vector data paths, executes vector instruction sets, and provides parallel computing capabilities. The vector unit can perform vector operations such as vector addition, dot product, etc. The second clock frequency and second working state of the vector unit can be configured independently of the scalar core as needed to meet the needs of bandwidth and computationally intensive vector tasks.

[0056] The above-mentioned communication interface unit (General Interface Unit, GIU) can be a communication module connecting different processor cores or execution units, responsible for the transmission of instructions and data, and coordinating the communication and synchronization between different modules. Among them, GIU can transmit instructions between the scalar core and the vector unit, including passing the identified vector request instructions from the scalar core to the vector unit, and feeding back the execution results of the vector unit to the scalar core. GIU also supports handshake protocols (valid / ready) or credit mechanisms (credit mechanisms) to ensure the correctness and efficiency of instruction transmission.

[0057] The above-mentioned controller is the control logic in the processor, which is responsible for managing timing, instruction flow, state transition, etc., to ensure that the processor runs according to predetermined rules and processes. The controller can configure the corresponding clock domain and power domain according to the needs of the scalar core and vector unit. For example, when the vector unit needs to perform a large number of parallel calculations, the controller may configure a higher second clock frequency for the vector unit, while the scalar core may maintain a lower first clock frequency to balance overall performance and power consumption.

[0058] By designing the above-mentioned vector processor as a loosely coupled architecture, the scalar core and vector unit can be connected through the GIU, each with an independent clock domain and power supply domain. The controller dynamically configures these domains according to different operating requirements, allowing the scalar core and vector unit to operate independently in a better state, thereby improving the overall computing power and energy efficiency. By independently controlling the clock frequency and working state of the scalar core and vector unit, the high-bandwidth memory access capability of the vector unit can be achieved, which is not limited by the scalar core and meets the computing power requirements of AI applications. Lightweight multithreading can also be configured for the vector processor. Through lightweight multithreading capabilities, the scalar core can handle other tasks while waiting for the execution results of the vector unit, thereby improving processor utilization.

[0059] Exemplarily, the scalar core (first clock frequency = 2.8 GHz, first working state = full power) is responsible for processing control logic and a small amount of data operations, while the vector unit (second clock frequency = 1.8 GHz, second working state = energy-saving mode) specializes in processing a large number of vector calculations. When the AI ​​reasoning task has high requirements for vector calculations, the controller can dynamically adjust the clock frequency and power supply state of the vector unit, such as increasing the clock frequency to 2.5 GHz and adjusting the power supply state to full power to meet the computing needs. At the same time, the scalar core can remain running in energy-saving mode to process tasks unrelated to vector calculations. This design allows AI reasoning tasks to utilize the high computing power of the vector unit while maintaining low power consumption, significantly improving overall performance and efficiency. It should be noted that the specific values ​​of the clock frequencies of the above-mentioned scalar cores and vector units and the specific modes of the working states are only for example illustration, without specific limitation, and can be adjusted according to actual circumstances.

[0060] The processor can flexibly adjust the operating status of each component according to different task types and loads, thereby achieving a balance and optimization in computing power, power efficiency and multi-threading support, which can effectively improve the efficiency and energy efficiency of the processor.

[0061] In an embodiment of the present application, a vector processor includes: a scalar core, which is used to execute a received scalar request instruction, obtain a first instruction execution result, and send the received vector request instruction to a vector unit, wherein the scalar core has a first clock frequency and a first working state; a vector unit, which is connected to the scalar core through a communication interface unit, and is used to execute the vector request instruction and obtain a second instruction execution result, wherein the vector unit has a second clock frequency and a second working state; a controller, which is respectively connected to the scalar core and the vector unit, and is used to configure the clock domains of the scalar core and the vector unit according to the first clock frequency and the second clock frequency, and configure the power supply domains of the scalar core and the vector unit according to the first working state and the second working state, thereby achieving the purpose of improving processor efficiency. It is easy to notice that by introducing the communication interface unit to decouple the scalar core and the vector unit, the two can run independently at different clock frequencies. The scalar core remains at the first clock frequency and can run at a higher frequency to optimize the processing speed of the scalar task; the vector unit runs at the second clock frequency and can be adjusted to a better frequency according to the actual computing requirements to achieve efficient vector calculation. The controller can dynamically adjust the clock domain and power supply domain between the scalar core and the vector unit according to the working state and clock frequency of the scalar core and the vector unit, that is, when vector calculation is not required, the vector unit can be placed in a low power mode, and when the scalar core processes vector instructions, the vector unit can be quickly activated to match the required high-performance state, reducing unnecessary power consumption and improving energy efficiency. The loosely coupled operation of the scalar core and the vector unit allows the two to be independently optimized according to their respective task types and requirements, thereby solving the technical problem of low processor processing efficiency in the related art due to the shared restrictions on clock frequency and memory access bandwidth. At the same time, through the dynamic management of the controller, the efficient operation and good energy efficiency performance of the system are ensured, thereby solving the technical problem of low processor processing efficiency in the related art.

[0062] In the above embodiment of the present application, the vector processor also includes: a first memory access port, a first end of the first memory access port is connected to the interconnection network of the vector processor, and a second end of the first memory access port is connected to the scalar core, and is used to provide an access channel for the scalar core to communicate with the interconnection network; a second memory access port, a first end of the second memory access port is connected to the interconnection network, and a second end of the second memory access port is connected to the vector unit, and is used to provide an access channel for the vector unit to communicate with the interconnection network; a controller, which is respectively connected to the first memory access port and the second memory access port, and is used to provide an access channel for the scalar core to the interconnection network according to the scalar core memory access instruction, and to provide an access channel for the vector unit to the interconnection network according to the vector unit memory access instruction.

[0063] The above interconnect network can be a bus interconnect network (Interconnect Network), where the interconnect network refers to the communication network port inside the processor, which is used to exchange data with other components or cores. In a multi-core processor or system, the interconnect network is a key architectural component for achieving inter-core communication and shared resource access.

[0064] The first memory access port (First Memory Access Port) mentioned above is a dedicated port for data access between the scalar core and the interconnection network, so that the scalar core can independently access memory with other components in the system through this port.

[0065] The above-mentioned second memory access port is a dedicated port for data access between the vector unit and the interconnection network, ensuring that the vector unit can access the memory efficiently and meet its large bandwidth requirements.

[0066] The controller can coordinate and manage the memory access requests of the scalar core and the vector unit, ensure the correctness and orderliness of data access, and optimize the operating efficiency of the processor.

[0067] In an embodiment of the present application, a vector processor designs a loosely coupled architecture, and provides independent memory access channels for the scalar core and the vector unit by setting up a first memory access port and a second memory access port. This allows the two to access memory at different times and frequencies without interfering with each other, and the controller is responsible for managing these ports to ensure the correctness and orderliness of data access. The vector unit can run independently of the scalar core and is not limited by the latter's clock frequency, so that it can support a larger vector length and improve computing power. The scalar core does not need to process the complex logic related to vector instructions, which simplifies the design and helps to increase the operating frequency of the scalar core. The scalar core and the vector unit can run in independent power domains, dynamically adjust the power supply according to their respective needs, and improve the overall energy efficiency of the system. When the vector unit executes a vector program, the scalar core can handle other tasks, realizing a lightweight concurrent processing capability and improving the utilization and efficiency of the processor.

[0068] The scalar core runs control logic and data preprocessing programs, which mainly involve scalar data, such as control variables, pointers, etc., and can access memory through the first memory access port (Bus0). The vector unit is responsible for performing vector calculation tasks, such as matrix multiplication and convolution, which are data-intensive and computationally intensive. They can access memory through the second memory access port (Bus1) to obtain higher bandwidth.

[0069] When the scalar core sends vector instructions to the vector unit, these instructions first pass through the controller, which sends the instructions to the vector unit through the GIU's Request channel based on the current state of the vector unit and resource availability. When the vector unit executes the memory access instruction, for example, after reading a large amount of data for calculation, it returns the result to the scalar core through the GIU's response channel. The controller is responsible for managing this process to ensure that the vector unit's memory access operations do not conflict with the scalar core's memory access operations. In addition, when the system load is low and vector calculations are not required, energy can be saved by shutting down the power domain of the vector unit, while the scalar core can continue to run unaffected. When the vector unit is processing vector tasks, the scalar core can handle other tasks, realizing lightweight multithreading and improving the overall performance of the processor.

[0070] Through the collaborative work of independent memory access ports and controllers, the problem of mutual constraints between vector units and scalar cores in traditional tightly coupled vector processors is solved, computing power and efficiency are improved, while design complexity and energy consumption are reduced, achieving a dual improvement in processor performance and energy efficiency.

[0071] In the above embodiment of the present application, the communication interface unit includes: a request channel for sending a vector request instruction of the scalar core to the vector unit; and a response channel for writing the second instruction execution result of the vector unit back to the scalar core.

[0072] The communication interface unit is a bridge between the scalar core and the vector unit, responsible for the transmission of data and control signals between the two. The communication interface unit is designed to have a request channel (Request) and a response channel (Response), which are responsible for sending vector request instructions and writing back vector execution results respectively.

[0073] The above request channel is used to transmit the vector request instructions generated by the scalar core to the vector unit. These instructions usually contain the information required for vector operations, such as opcodes, source operand addresses, target operand addresses, etc., so that the vector unit can perform the corresponding vector operations. When the scalar core encounters a vector instruction, such as vector addition, it can send this instruction to the vector unit through the GIU's request channel. The instruction may contain information such as the opcode and the address of the operand. After the vector unit receives the instruction, it starts to perform the vector addition operation.

[0074] The above-mentioned response channel is used to transmit the results of the vector unit after executing the instruction back to the scalar core. These results may include calculation results, status information, etc., for further processing or recording by the scalar core. After the vector addition is completed, the vector unit will return the calculated vector addition result and status information to the scalar core through the response channel. After receiving this information, the scalar core can write the result back to the corresponding vector register and perform exception handling or schedule the next task based on the status information.

[0075] The request channel and response channel can be used for orderly and efficient data transmission through the valid / ready handshake communication mechanism. In this mechanism, the sender sends data when the data is valid, and the receiver accepts data only when it is ready to receive. This mechanism ensures that data is processed correctly at the right time and avoids deadlock or waste of resources.

[0076] When the scalar core has a vector instruction to send, the scalar core can mark the data as valid on the request channel and wait for the vector unit to be ready to receive it. Once the vector unit is ready, it can receive and process the instruction. The same logic is applied to the response channel to ensure that the results of the vector unit execution are written back to the scalar core at the right time.

[0077] The credit communication mechanism is a credit-based flow control protocol that allows the receiver to send a credit signal to the sender to indicate how much data the sender can send. This mechanism can prevent the receiver's buffer from overflowing, thereby avoiding data loss.

[0078] In the case of limited buffer memory in the vector unit, it can tell the scalar core how many vector instructions it can currently receive through a credit signal. After receiving the credit signal, the scalar core will send vector instructions according to the indicated number to ensure that the vector unit can safely process these instructions while avoiding buffer overflow.

[0079] In an embodiment of the present application, the communication interface unit adopts a valid / ready handshake communication mechanism or a credit communication mechanism through its request channel and response channel to ensure the correctness and efficiency of the instruction transmission and result write-back process between the scalar core and the vector unit. This architectural design allows the scalar core and the vector unit to work independently under different clock and power domains, while ensuring the correct order of their operations in memory. By decoupling the scalar core from the vector unit and adopting a valid / ready handshake communication mechanism or a credit communication mechanism, this solution can significantly improve the efficiency and flexibility of vector processing, reduce the overall implementation complexity, and improve energy efficiency. This architectural design enables the vector unit to independently and parallelly execute vector programs after the scalar core has sent all vector instructions, thereby realizing lightweight multithreading and further improving processing speed and efficiency.

[0080] For example, in AI applications, suppose a task requires the scalar core to first process some preloaded scalar data, and then requires the vector unit to process a large amount of vector data. After completing the preprocessing, the scalar core sends the vector instructions to the vector unit through the request channel of the GIU using the valid / ready handshake communication mechanism. After receiving the instructions, the vector unit independently executes these instructions under its own clock and power domain. After the execution is completed, the vector unit writes the execution results back to the scalar core through the response channel of the GIU, also using a handshake or credit mechanism. Throughout the process, the scalar core and the vector unit can work asynchronously, and each has independent resource management, which not only improves computing efficiency, but also optimizes the energy efficiency ratio, and truly realizes the efficient use of hardware resources and lightweight multi-threaded processing of tasks.

[0081] In the above embodiment of the present application, the scalar core includes: a vector sorting table, which is connected to the request channel and the response channel respectively, wherein the vector sorting table is used to maintain the memory access order between the scalar core and the vector unit.

[0082] The Vector Ordering Table (VOT) is a table used to track and maintain the memory access order between the scalar core and the vector unit. VOT ensures the order and consistency of memory operations in a concurrent execution environment and prevents potential memory access conflicts.

[0083] Exemplarily, when a vector processor executes a deep learning model, the scalar core is responsible for processing the control flow logic of the model, while the vector unit processes a large amount of data in parallel (such as matrix multiplication). The scalar core sends vector load and store instructions to the vector unit through the request channel. These instructions carry the index of a VOT entry to identify the memory access order to which they correspond. When the vector unit completes the memory access and is ready to feed the result back to the scalar core, the index of the VOT entry can be sent back through the response channel, indicating that the memory access operation has been completed and can be observed globally. Based on this feedback, the scalar core can update the VOT to release the relevant entries, and then continue to execute subsequent instructions that depend on the memory access, or another set of vector instructions.

[0084] Maintaining the memory access order between the scalar core and the vector unit is achieved through the vector sort table. Whenever a vector load or store instruction is issued, the VOT allocates an entry and associates the index of the entry with the instruction to ensure that the instructions are executed in the correct order in the vector unit. The completed vector instruction returns the index of the entry to the scalar core through the response channel to update the VOT and release the entry to ensure the correct execution of subsequent instructions. This method avoids direct synchronization between the scalar core and the vector unit, improving the concurrent performance and efficiency of the processor.

[0085] The memory access order maintenance between the scalar core and the vector unit is achieved through the vector sort table. This not only solves the performance bottleneck caused by the vector unit and the scalar core sharing the memory access unit, but also reduces the complexity of the scalar core, allowing it to run at a higher frequency, thereby improving the computing power and energy efficiency of the entire processing system. In addition, lightweight multi-threading support further improves the throughput and flexibility of the processor by allowing the scalar core to perform other tasks while waiting for the response of the vector unit.

[0086] In the implementation of the RISC-V Vector processor, for example, when processing image recognition tasks, the scalar core is responsible for identifying and managing high-level logic, such as loop control and conditional judgment, while the vector unit processes the feature extraction of image data in parallel. When the scalar core requires the vector unit to execute a vector load instruction, an entry can be allocated in the VOT, and the instruction and the index of the entry can be sent to the vector unit through the request channel. After the vector unit executes the instruction, it returns the index of the VOT entry to the scalar core through the response channel, indicating that the memory operation has been completed. The scalar core updates the VOT based on the returned index, releases the entry, and ensures the correct execution order of subsequent instructions (such as vector storage instructions). This mechanism allows the vector unit to operate at a higher degree of parallelism while ensuring the sequentiality and consistency of memory access, improving the performance and energy efficiency of the entire system.

[0087] In the above embodiment of the present application, the vector unit includes: an instruction cache connected to the request channel and used to cache a preset number of vector request instructions.

[0088] The instruction cache mentioned above is a high-speed cache in the processor used to store instructions to be executed, with the purpose of reducing the delay of reading instructions from the main memory and improving the execution efficiency of the processor. The instruction cache contained in the vector unit is used to store vector instructions passed from the scalar core through the request channel of the GIU, so that the vector unit can process these instructions independently without the scalar core waiting continuously.

[0089] In an embodiment of the present application, the vector unit may include an instruction cache connected to a request channel. When the scalar core encounters vector instructions, these instructions may be passed to the instruction cache of the vector unit through the request channel. This allows the vector unit to independently process and execute these vector instructions without direct intervention from the scalar core. The above design allows the vector unit to independently execute vector instructions, and the vector unit can continue to run even when the scalar core is processing other tasks. Since the vector unit and the scalar core can be separated in the clock and power domains, the vector unit can adopt a higher degree of parallelism and a longer vector length to provide greater computing power while maintaining the high efficiency and energy efficiency of the scalar core. The lightweight multi-threaded feature allows the scalar core to process other computing tasks while waiting for the execution of vector instructions, thereby improving the overall utilization and performance of the processor.

[0090] Exemplarily, when the scalar core encounters vector instructions for convolution operations, the scalar core will not execute these instructions immediately, but will send these instructions to the instruction cache of the vector unit through the request channel of the GIU. At this point, the scalar core can continue to process other operations, such as data preprocessing or post-processing, without having to wait for the completion of the vector instructions. After receiving the instructions, the vector unit uses its specialized computing resources and larger memory access bandwidth to independently execute the vector instructions for convolution operations, thereby significantly accelerating the data processing speed. When the vector instruction is executed, the vector unit returns the result to the scalar core through the response channel of the GIU, and the scalar core continues to execute subsequent programs based on the result. The above design can ensure the decoupling between the scalar core and the vector unit, improve the flexibility and energy efficiency of the processor, and more efficiently utilize processor resources and improve computing performance when processing AI applications.

[0091] In the above embodiments of the present application, the vector processor adopts a reduced instruction set computer architecture.

[0092] The Reduced Instruction Set Architecture (RISC-V) can create a simple, scalable, easy to understand and implement instruction set while maintaining powerful functions and customizability. The RISC architecture is characterized by having fewer instruction types and fewer cycles for each instruction to execute, which can usually simplify processor design and improve execution efficiency and predictability.

[0093] The present application proposes a loosely coupled vector processor that can decouple the scalar core and the vector unit, and has the following characteristics: the scalar core and the vector unit can share or each have an independent clock domain (Clock Domain); the scalar core and the vector unit can share or each have an independent power domain (Power Domain); the scalar core and the vector unit have independent memory access ports respectively; the memory access order (Memory Access Ordering) between the scalar core and the vector unit can be maintained by hardware or by software.

[0094] The scalar cores and vector units can be decoupled in terms of clock domains, power domains, memory access ports, and memory access order to optimize performance and improve energy consumption.

[0095] A clock domain refers to the collection of all components in a circuit or system that use the same clock signal. In processor design, clock signals are used to synchronize the operations of different components. Typically, the entire processor core runs in the same clock domain, which means that all components run at the same frequency. When scalar cores and vector units share the same clock domain, it means that they run at the same frequency. This design simplifies timing analysis and synchronization issues, but may limit the flexibility of performance optimization. Placing scalar cores and vector units in different clock domains allows each to run at a better frequency without being limited by the other. For example, a scalar core may require a higher frequency to handle control-intensive tasks, while a vector unit may be more efficient at a lower frequency to handle data-intensive tasks.

[0096] Power domains define areas of a circuit that are managed by the same power supply. Different power domains can independently control power, so that when a part of the circuit is not needed (such as a vector unit when there is no vector calculation task), its power can be turned off to save energy. In a shared power domain, the scalar core and the vector unit are controlled by the same power supply. This design simplifies power management, but may not reduce power consumption when there is no vector task. Independent power domains allow the power of the vector unit to be turned off when there is no vector calculation demand, keeping only the scalar core working. This strategy is beneficial to improve the energy efficiency of the system during non-vector tasks and save energy, especially for mobile or battery-powered devices.

[0097] The memory access port is the channel for the processor to communicate with the memory. Usually, all memory accesses in the processor are performed through a unified port, which may cause access conflicts and performance bottlenecks. Providing independent memory access ports for scalar cores and vector units can avoid memory access contention between them and improve memory access efficiency. For example, a vector unit may require higher bandwidth to process a large amount of data, while the memory access requirements of a scalar core are relatively low. Independent ports can optimize their respective memory access performance and avoid bottlenecks.

[0098] Memory access order refers to the order in which the processor performs memory operations (such as reading and writing), which is directly related to data consistency and program correctness. The hardware automatically maintains the memory access order, usually through hardware mechanisms inside the core (such as queues or buffers), to ensure that the execution order of instructions is consistent with the write order of the program. This simplifies the complexity of software programming. The software maintains the memory access order, and appropriate programming techniques (such as memory barrier instructions) are needed to ensure the sequentiality of memory operations. This puts the control of memory access order in the hands of software, which can reduce the burden on hardware.

[0099] Balancing complexity and efficiency and choosing the right clock domain, power domain, memory access port, and memory access order strategy are the keys to designing high-performance computing systems. By decoupling the vector unit from the scalar core in these aspects, the RISC-V Vector processor can more flexibly adapt to different workloads and energy efficiency requirements.

[0100] Figure 4 is a schematic diagram of a vector processor according to an embodiment of the present application, such as Figure 4 As shown in the figure, it includes Scalar Core, Vector Unit, and General Interface Unit (GIU). The Scalar Core is a key component of the processor. The Scalar Integer Register File and Scalar Floating Register File are maintained in the Scalar Core. The Scalar Core mainly maintains the life cycle of Scalar Integer and Scalar Floating-Point instructions, including instruction fetch, decoding, execution, write-back, exception handling, etc. The Vector Unit is a specially designed execution unit. The Vector Register File is maintained in the Vector Unit.

[0101] For vector instructions, the Scalar Core is responsible for fetching instructions, performing rough decoding, and identifying vector instructions. If it is a vector instruction, the instruction is passed from the scalar core to the vector unit through the request channel (Request) of the general interface unit (GIU). Some vector instructions require writing back scalar integer registers and scalar floating point registers. The vector unit passes them to the scalar core through the response channel (Response) of the general interface unit and completes the write back of the registers.

[0102] Scalar integer and scalar floating point memory access instructions are accessed through the independent memory access port (Bus0) of the scalar core. Vector memory access instructions are accessed through the independent memory access port (Bus1) of the vector unit. Bus0 and Bus1 are connected to the interconnect network.

[0103] Since the memory access requirements of the scalar core and the vector unit are different, Bus0 and Bus1 can use the same bus protocol or different bus protocols. The data width of the bus can also be different. For example, if the Vector Unit requires a larger memory access bandwidth, the data width of Bus1 can be 1024-bit, while the Scalar Core does not require such a large memory access bandwidth, and the data width of Bus0 can be 256-bit. The data width of Bus1 and Bus0 is only used as an example here, without specific limitation. The data width of Bus0 and Bus1 can be set according to actual needs.

[0104] The general interface unit is the communication interface between the scalar core and the vector unit. The request channel and response channel of the general interface unit can adopt a valid / ready handshake communication mechanism or a credit communication mechanism. Taking the valid / ready handshake mechanism as an example, the signals of the Request and Response channels of the GIU are shown below. This mechanism ensures the validity of the data and the readiness of the receiver, thereby achieving efficient communication between the vector unit and the scalar core.

[0105] Request channel signal:

[0106] req0_vld: Indicates that the 0th request is valid, that is, the scalar core is preparing to send a vector request instruction.

[0107] req0_payload: carries the payload information of the 0th request, including the instruction code and related scalar operands.

[0108] req0_rdy: Indicates that the vector unit is ready to receive the 0th request.

[0109] req1_vld: indicates that the first request is valid.

[0110] req1_payload: carries the payload information of the first request.

[0111] req1_rdy: Indicates that the vector unit is ready to receive the first request. ...

[0113] reqN_vld: indicates that the Nth request is valid.

[0114] reqN_payload: carries the payload information of the Nth request.

[0115] reqN_rdy: Indicates that the vector unit is ready to receive the Nth request.

[0116] These signals allow the scalar core to send vector instructions to the vector unit in sequence or out of sequence, and the vector unit can receive these instructions dynamically based on its own state.

[0117] Response channel signal:

[0118] resp0_vld: indicates that the 0th response is valid, that is, the vector unit is ready to send an instruction execution result.

[0119] resp0_payload: carries the payload information of the 0th response, including the vector register value and status written back.

[0120] response0_rdy: Indicates that the scalar core is ready to receive the 0th response.

[0121] resp1_vld: indicates that the first response is valid.

[0122] resp1_payload: carries the payload information of the first response.

[0123] response1_rdy: Indicates that the scalar core is ready to receive the first response. ...

[0125] respM_vld: indicates that the Mth response is valid.

[0126] respM_payload: carries the payload information of the Mth response, including the data value and status information stored in the write-back register.

[0127] responseM_rdy: Indicates that the scalar core is ready to receive the Mth response.

[0128] In some designs, the response channel does not need the response{X}_rdy signal because the scalar core will receive the response information.

[0129] Figure 5 is a schematic diagram of a structure in which a scalar core and a vector unit share the same clock domain according to an embodiment of the present application, such as Figure 5 As shown, it includes a scalar core, a vector unit, a general interface unit, a request channel, a response channel, an independent memory access port of the scalar core, an independent memory access port of the vector unit, and an interconnection network, wherein the scalar core and the vector unit share the same clock domain.

[0130] Figure 6 is a schematic diagram of a structure in which a scalar core and a vector unit use different clock domains according to an embodiment of the present application, such as Figure 6 As shown, it includes a scalar core, a vector unit, a general interface unit, a request channel, a response channel, an independent memory access port of the scalar core, an independent memory access port of the vector unit, and an interconnection network, wherein the scalar core and the vector unit use different clock domains independently. When the operating frequency of the scalar core is higher and the vector unit does not need to maintain the same frequency as the scalar core, the two can use different clock domains. This allows the vector unit to run at a frequency that is more suitable for its workload and energy efficiency requirements. For example, a lower frequency may be required when processing vector operations to reduce power consumption or heat generation, especially when the computationally intensive tasks performed by the vector unit do not match the frequency requirements of the tasks performed by the scalar core.

[0131] Using independent clock domains, designers can optimize the frequency according to the performance and power requirements of each component, thereby improving the energy efficiency and performance of the overall system. Different computing units may require different clock frequencies to operate in a better state.

[0132] Figure 7 is a schematic diagram of a structure in which a scalar core and a vector unit share the same power supply domain according to an embodiment of the present application, such as Figure 7 As shown, it includes a scalar core, a vector unit, a general interface unit, a request channel, a response channel, an independent memory access port of the scalar core, an independent memory access port of the vector unit, and an interconnection network, wherein the scalar core and the vector unit share the same power domain, the scalar core and the vector unit can be turned on or off at the same time, and share the same power management strategy.

[0133] Figure 8 is a schematic diagram of a structure in which a scalar core and a vector unit use different power supply domains according to an embodiment of the present application, such as Figure 8As shown, it includes a scalar core, a vector unit, a general interface unit, a request channel, a response channel, an independent memory access port of the scalar core, an independent memory access port of the vector unit, and an interconnection network, wherein the scalar core and the vector unit use different power domains independently. When the system does not need to use the functions of the core unit, such as when processing tasks that do not require vector operations, the power of the core unit can be selectively turned off. In this case, the scalar core and the vector unit will be in different power domains, the scalar core continues to run, and the vector unit is placed in a low-power or off state to save power. This design provides higher flexibility and energy efficiency, and can dynamically adjust the power state of the vector unit according to actual computing needs, thereby reducing power consumption when vector processing capabilities are not needed.

[0134] Under the above operating environment, this application provides Fig. 9 The operation method of the vector processor shown in FIG. Fig. 9 is a flowchart of a method for operating a vector processor according to an embodiment of the present application, such as Fig. 9 As shown, the method includes:

[0135] Step S902, in response to the scalar core receiving the scalar request instruction and the vector request instruction, executing the scalar request instruction through the scalar core to obtain a first instruction execution result, sending the vector request instruction to the vector unit, and obtaining a first clock frequency and a first working state of the scalar core;

[0136] When the scalar core receives scalar request instructions and vector request instructions, for scalar request instructions, the scalar core will be responsible for processing scalar integer and scalar floating point instructions, which includes steps such as instruction fetching, decoding, execution, writeback, and exception handling, thereby obtaining the first instruction execution result. For vector request instructions, the scalar core is responsible for identifying and passing it to the vector unit through the GIU's Request channel.

[0137] The system needs to obtain the current clock frequency (first clock frequency) and working state (first working state) of the scalar core so as to be used for dynamically configuring independent clock domains and power supply domains in subsequent steps.

[0138] Step S904, executing the vector request instruction through the vector unit to obtain a second instruction execution result, and obtaining a second clock frequency and a second working state of the vector unit;

[0139] The vector unit executes the received vector request instruction, which may include vector calculation and storage access of vector data. After the execution is completed, a second instruction execution result is obtained.

[0140] The current clock frequency (second clock frequency) and working state (second working state) of the vector unit may be acquired so as to be used for subsequent clock domain and power supply domain configuration.

[0141] Step S906, configuring clock domains for the scalar core and the vector unit respectively based on the first clock frequency and the second clock frequency;

[0142] A clock signal suitable for the operation of the scalar core can be set according to the current demand of the scalar core (first clock frequency). For example, if the operation demand of the scalar core is low, its clock frequency can be set relatively low to save energy. A clock signal suitable for the operation of the vector unit can be set according to the current demand of the vector unit (second clock frequency). The vector unit may require a higher clock frequency to increase the processing speed, especially when processing large vector data.

[0143] Step S908: configuring power supply domains for the scalar core and the vector unit respectively based on the first working state and the second working state.

[0144] The power supply requirements of the scalar core can be dynamically adjusted according to the current working state (first working state), such as reducing the power supply at low load to improve overall energy efficiency. The power supply domain can be configured based on the current working state (second working state) of the vector unit. Under high load, the vector unit may require more power to support its operation, and when not in use, it can be turned off or the power supply can be reduced to reduce energy consumption.

[0145] By dynamically configuring the clock domain and power domain of the scalar cores and vector units, the system can more flexibly adjust resources to match the performance and power consumption requirements of the scalar cores and vector units when processing different types of workloads, thereby achieving higher energy efficiency and processing capabilities.

[0146] Through the above steps, in response to the scalar core receiving a scalar request instruction and a vector request instruction, the scalar request instruction is executed by the scalar core to obtain a first instruction execution result, the vector request instruction is sent to the vector unit, and a first clock frequency and a first working state of the scalar core are obtained; the vector request instruction is executed by the vector unit to obtain a second instruction execution result, and a second clock frequency and a second working state of the vector unit are obtained; clock domains are configured for the scalar core and the vector unit based on the first clock frequency and the second clock frequency respectively; power supply domains are configured for the scalar core and the vector unit based on the first working state and the second working state respectively, thereby achieving the purpose of improving processor efficiency. It is easy to notice that by introducing the communication interface unit to decouple the scalar core and the vector unit, the two can run independently at different clock frequencies. The scalar core remains at the first clock frequency and can run at a higher frequency to optimize the processing speed of the scalar task; the vector unit runs at the second clock frequency and can be adjusted to a better frequency according to the actual computing requirements to achieve efficient vector calculation. The controller can dynamically adjust the clock domain and power supply domain between the scalar core and the vector unit according to the working state and clock frequency of the scalar core and the vector unit, that is, when vector calculation is not required, the vector unit can be placed in a low power mode, and when the scalar core processes vector instructions, the vector unit can be quickly activated to match the required high-performance state, reducing unnecessary power consumption and improving energy efficiency. The loosely coupled operation of the scalar core and the vector unit allows the two to be independently optimized according to their respective task types and requirements, thereby solving the technical problem of low processor processing efficiency in the related art due to the shared restrictions on clock frequency and memory access bandwidth. At the same time, through the dynamic management of the controller, the efficient operation and good energy efficiency performance of the system are ensured, thereby solving the technical problem of low processor processing efficiency in the related art.

[0147] In the above embodiments of the present application, clock domains are configured for the scalar core and the vector unit respectively based on the first clock frequency and the second clock frequency, including: in response to the first clock frequency and the second clock frequency being different, different clock domains are configured for the scalar core and the vector unit; in response to the first clock frequency and the second clock frequency being different, the same clock domain is configured for the scalar core and the vector unit.

[0148] The first clock frequency mentioned above is the operating frequency of the scalar core, that is, the frequency of the internal clock of the scalar core, which determines the speed at which the scalar core processes instructions.

[0149] The second clock frequency mentioned above is the operating frequency of the vector unit, that is, the frequency of the internal clock of the vector unit, which determines the speed at which the vector unit processes vector instructions.

[0150] Scalar cores and vector units may require different processing speeds to optimize performance and energy efficiency. For example, scalar cores may run at a higher frequency to quickly process control flow and scalar operations, while vector units may run at a lower frequency to reduce power consumption while processing a large amount of parallel data. In this case, the system can configure independent clock domains for scalar cores and vector units, so that the scalar cores and vector units can independently run at their respective best frequencies. If the clock frequencies of the scalar cores and vector units are the same, they can be configured in the same clock domain, simplifying the design and reducing the complexity of synchronization.

[0151] When the system detects that the scalar core and vector unit require different clock frequencies, independent clock domains can be configured for the two according to the frequency difference. This means that different units can adjust their operating frequencies independently to achieve better performance and energy efficiency. When the system detects that the clock frequencies of the two are the same or do not require independent frequencies, the scalar core and vector unit can be configured in the same clock domain to simplify circuit design and management and reduce unnecessary hardware overhead. By configuring independent clock domains for the scalar core and vector unit, the system can more flexibly adjust the operating frequency of each unit to optimize overall performance and energy efficiency. For example, when performing intensive vector operations, the clock frequency of the vector unit can be increased, while the scalar core is kept at a lower frequency to save energy. When executing simple scalar instructions, the clock frequency of the scalar core can be increased, and the vector unit can be reduced or turned off to reduce unnecessary power consumption. This design allows each part to achieve its best working state when needed, while reducing power consumption when not needed, improving the adaptability and energy efficiency of the processor under different workloads.

[0152] In the above embodiments of the present application, power supply domains are configured for the scalar core and the vector unit respectively based on the first working state and the second working state, including: in response to the first working state and the second working state being different, different power supply domains are configured for the scalar core and the vector unit; in response to the first working state and the second working state being the same, the same power supply domain is configured for the scalar core and the vector unit.

[0153] The above working status indicators measure the operating modes of the core and vector unit at a specific point in time, including active, sleep, low power and other modes.

[0154] The first working state mentioned above refers to the operating mode of the scalar core, and the second working state refers to the operating mode of the vector unit. For example, when there are fewer AI computing tasks, the Vector Unit may be in a low-power state, while the ScalarCore may remain active to handle regular tasks.

[0155] The above-mentioned power domain refers to the area inside the processor where the power supply can be independently controlled. Different areas can be configured with different power management strategies, such as voltage, frequency, power supply status, etc.

[0156] In an optional embodiment, the power domain involves Scalar Core and Vector Unit, allowing the Scalar Core and Vector Unit to independently adjust the power strategy according to their respective working states. For example, when the Vector Unit performs a large number of operations, it may require a higher voltage and frequency, so an independent high-power power domain is configured; while when the Scalar Core handles light tasks, a low-power power domain can be configured.

[0157] When the working states of the scalar core and vector unit are different, the system can configure independent power domains according to their respective needs. This means that the Vector Unit can be configured with a high-power power domain when high performance is required, and the ScalarCore can be configured with a low-power power domain when processing lightweight tasks, and vice versa. If the working states of the two are the same, the same power domain is configured to simplify power management. By dynamically configuring the power domain, the power supply strategy can be adjusted according to the workload to maximize the energy efficiency ratio. Improve flexibility and allow Scalar Core and Vector Unit to independently optimize their performance and power consumption. Reduce the energy waste of the overall system and improve energy utilization efficiency.

[0158] For example, in AI reasoning tasks, Vector Unit needs to perform intensive vector operations, while Scalar Core is mainly responsible for task scheduling and data management. At this time, Vector Unit is in a high-power, high-performance working state, while Scalar Core is in a low-power, low-load working state.

[0159] An independent high-power domain can be configured for the Vector Unit to provide sufficient power to support its vector operations; at the same time, an independent low-power domain can be configured for the Scalar Core to reduce its energy consumption in light task states. In this way, even when the task requirements change, each part can be guaranteed to obtain a better power configuration according to its current working state, thereby improving the energy efficiency and performance of the entire system.

[0160] When the AI ​​inference task is completed, the system switches to normal operation mode. At this time, the working status of Scalar Core and Vector Unit may become similar, both processing non-intensive tasks. At this time, the same power domain can be configured to simplify power management while still maintaining good energy efficiency and performance.

[0161] In the above embodiment of the present application, the scalar core includes a vector sorting table. After sending the vector request instruction to the vector unit, the method also includes: allocating a first entry in the vector sorting table to the vector request instruction through the scalar core, wherein the vector request instruction carries first identification information of the first entry; in response to the scalar core receiving a second instruction execution result fed back by the vector unit, releasing a second entry corresponding to the second identification information in the vector sorting table through the scalar core according to the second identification information carried by the second instruction execution result.

[0162] The above-mentioned vector sort table is a data structure maintained in the scalar core, which is used to track the order of vector request instructions executed by the vector unit, ensuring the correctness and consistency of the instruction execution order even when the scalar core and the vector unit are decoupled. VOT can be regarded as an execution sorting mechanism, which assigns entries to vector instructions to be sent to the vector unit to facilitate tracking and maintaining the execution order of instructions.

[0163] The above-mentioned vector request instructions are part of the RISC-V vector instruction set. Such instructions require a vector unit to execute, including vector load and vector store operations.

[0164] The first entry and the second entry are records in the vector sort table, which are used to store sort information related to the vector request instruction, such as the unique identifier and status of the instruction. Each vector request instruction is assigned a VOT entry, which is the key to ensuring the execution order of the instruction.

[0165] The first identification information and the second identification information are usually the index or specific mark of the entry in the VOT, which is used to uniquely identify the VOT entry corresponding to each vector request instruction. The first identification information is generated when the scalar core allocates the VOT entry, and the second identification information is carried when the vector unit completes the instruction execution and feeds back the result.

[0166] In an embodiment of the present application, when a vector request instruction (such as a vector load or store instruction) is recognized by a scalar core and is ready to be sent to a vector unit, the scalar core will allocate an entry in a vector sort table for the instruction, and this entry contains the first identification information of the instruction, ensuring that the instruction has a traceable identification when it is sent. After the vector unit executes this vector request instruction, it will send the execution result and the second identification information back to the scalar core through a response channel. After receiving the execution result, the scalar core will check the second identification information, find the corresponding entry in the vector sort table, and then release the entry. In this way, the scalar core can ensure that the instruction execution order of the vector unit is consistent with the order of the allocated entries, even in asynchronous and multi-threaded environments.

[0167] By decoupling the scalar core and the vector unit in the above manner, the vector unit can operate independently of the clock frequency and power domain of the scalar core, thereby improving the flexibility and efficiency of the vector unit when executing vector instructions. Secondly, through the maintenance of VOT, the order and consistency of instruction execution can be guaranteed even in asynchronous execution and multi-threaded environments, which directly improves the performance and energy efficiency of the processor, especially in AI applications, and can more effectively utilize the computing power of the vector unit.

[0168] Exemplarily, a portion of the computationally intensive tasks of an AI application are programmed as vector instructions, while another portion of the tasks can be processed by scalar instructions. In this case, the scalar core first recognizes that a vector load instruction needs to be sent to the vector unit for execution. It allocates an entry for this instruction in the VOT and attaches the entry index (first identification information) to the instruction. After that, the vector unit starts executing this instruction, and after completing the vector load, it sends the result back to the scalar core through the response channel, carrying the VOT entry index (second identification information) corresponding to the executed instruction. When the scalar core receives the result, it finds the relevant entry in the VOT based on the second identification information, confirms that the instruction has been safely executed and writes back the result, and then releases the entry. This mechanism enables the scalar core and the vector unit to work together efficiently, especially when processing complex AI tasks. The scalar core can perform other tasks at the same time, while the vector unit focuses on the execution of vector instructions with high computing power requirements. The decoupling and independent operation of the two significantly improves the overall processing power and energy efficiency.

[0169] In the above embodiment of the present application, the vector unit includes an instruction cache. After executing the vector request instruction and obtaining the second instruction execution result, the method further includes: sending the cache status of the instruction cache to the scalar core through the vector unit.

[0170] The above instruction cache is a type of cache located inside the processor and is used to store recently used or upcoming instructions to reduce the number and time of reading instructions from the main memory. For example, when the processor executes a certain vector instruction, the instruction cache will temporarily store this instruction. If there is a subsequent identical instruction, it can be directly read from the cache to speed up the execution process.

[0171] The above-mentioned second instruction execution result refers to the result generated after the vector unit executes the vector request instruction, which can be the calculation result of vector data or the status information. For example, after the vector unit executes vector multiplication, the result vector or the status information of the multiplication operation is obtained.

[0172] In an optional embodiment, when the vector unit completes the execution of the vector request instruction and obtains the second instruction execution result, the cache state of the instruction cache can be sent to the scalar core. This process is to ensure that the scalar core understands the instruction execution status of the vector unit so that effective scheduling and management can be performed, for example, to determine whether the instruction needs to be reloaded or whether other tasks can be assigned to the vector unit.

[0173] By understanding the instruction cache status of the vector unit, the scalar core can manage the instruction cache more effectively, avoid repeatedly loading existing instructions, save memory access time, and reduce power consumption. After knowing the current instruction execution status of the vector unit, the scalar core can make more reasonable task allocation, such as sending new vector tasks when the vector unit is idle, or processing other scalar tasks when the vector unit is busy, which helps to improve the parallel processing efficiency of the entire processor. Sharing the instruction cache status helps maintain data consistency in the processor, especially in a multi-threaded or multi-tasking environment, ensuring the correct instruction execution order between the vector unit and the scalar core to avoid data conflicts.

[0174] For example, the scalar core is executing the control logic of an Al algorithm, while the vector unit is responsible for performing vector multiplication operations. When the scalar core encounters a vector multiplication instruction, it sends the instruction to the vector unit. After the vector unit executes the instruction, in addition to returning the multiplication result, it also sends the status information related to the multiplication instruction in the instruction cache (such as cache hit status) back to the scalar core. After receiving this status, the scalar core determines the subsequent execution strategy based on the cache status. For example, if the cache hit rate is high, the scalar core can continue to send vector tasks to make full use of the performance of the vector unit; if the cache status indicates that more instructions need to be loaded, the scalar core can first process some scalar tasks that do not require the vector unit to avoid waiting for the vector unit.

[0175] Through the above methods, the processor can achieve more efficient resource utilization and task scheduling, and can significantly improve the processing speed for large-scale vector data processing while maintaining a good energy consumption ratio. This design is also particularly suitable for AI application scenarios, because AI algorithms often involve a large number of vector calculations, which can be accelerated by vector units. At the same time, the scalar core can handle the control flow of the algorithm. The decoupling of the two enables the entire system to run in a more efficient manner.

[0176] In the above embodiment of the present application, the scalar request instruction includes a new scalar request instruction and a historical scalar request instruction, and the vector request instruction includes a new vector request instruction and a historical vector request instruction. The method also includes: in response to receiving the new scalar request instruction and the historical scalar request instruction, after the historical scalar request instruction is executed by the scalar core, the new scalar request instruction is executed; in response to receiving the new scalar request instruction and the historical vector request instruction, after the historical vector request instruction is sent to the vector unit by the scalar core, the new scalar request instruction is executed; in response to receiving the new vector request instruction and the historical scalar request instruction, after the historical scalar request instruction is executed by the scalar core, the new vector request instruction is sent to the vector unit; in response to receiving the new vector request instruction and the historical vector request instruction, after the historical vector request instruction is sent to the vector unit by the scalar core, the new vector request instruction is sent to the vector unit.

[0177] Scalar request instructions are instructions that process scalar data, that is, instructions for a single data element, including integer and floating-point operations. Vector request instructions are instructions that process vector data, that is, instructions that perform the same operation on multiple data elements at the same time, mainly used to accelerate data-intensive calculations.

[0178] The new scalar / vector request instruction mentioned above is a scalar or vector request instruction that needs to be processed currently, that is, an instruction that is about to be executed or is being executed in the program.

[0179] The above-mentioned historical scalar / vector request instructions refer to scalar or vector request instructions that have been processed but whose results have not been completed or need to be further processed in the vector unit, that is, instructions that have been issued before but have not completed their life cycle.

[0180] Exemplarily, in a RISC-V processor, the Scalar Core receives a series of instructions, including scalar and vector types. When the Scalar Core receives a new scalar request instruction and a historical scalar request instruction that has not been processed before, it first completes the execution of the historical scalar request instruction to ensure data consistency, and then executes the new scalar request instruction. If the Scalar Core receives a new scalar request instruction and a historical vector request instruction, it will first send the historical vector request instruction to the vector unit for processing, and then execute the new scalar request instruction. For the processing of the new vector request instruction, if there are still historical scalar request instructions that have not been completed in the Scalar Core, it will first execute and complete these historical scalar request instructions, and then send the new vector request instruction to the vector unit. If a new vector request instruction and a historical vector request instruction are received at the same time, the Scalar Core will first send the historical vector request instruction to the vector unit, and then send the new vector request instruction to ensure that the order of operations in the vector unit is correct.

[0181] The scalar core and vector unit work together to ensure the correct order of instruction execution, and the order between scalar and vector load / store instructions to maintain the consistency and correctness of memory access. In this way, even if the scalar core and vector unit work in different clock domains and power domains, the sequentiality of memory access can be guaranteed, which is the key to realizing an efficient and reliable Vector processor. Through the design of the above instruction processing logic, not only the computing performance of the system is improved, but also the correct access order of data is ensured, data competition and consistency problems are avoided. At the same time, due to the independent operation of ScalarCore and Vector Unit, the energy efficiency and processing flexibility of the system are also improved. In AI and data-intensive applications, this loosely coupled design allows the Scalar Core to perform other tasks while waiting for vector operations to complete, thereby realizing multi-threaded lightweight processing, further improving the parallel computing capability and response speed of the system.

[0182] In AI applications, there are programs that process scalar and vector data at the same time. At a certain moment, the Scalar Core receives a new scalar request instruction (such as scalar addition) while it is processing a historical scalar request instruction (such as scalar multiplication). According to the steps, the Scalar Core will first complete the multiplication calculation of the historical scalar request instruction before executing the new scalar addition instruction. Then, the Scalar Core receives a new vector request instruction (such as vector dot multiplication), but there are still unfinished historical vector request instructions (such as vector addition). The Scalar Core will send the historical vector addition instruction to the vector unit for processing, and then send the new vector dot multiplication instruction to the vector unit. Throughout the process, the memory access order is maintained using the Vector Ordering Table to ensure the correct execution order of all scalar and vector instructions. At the same time, this loosely coupled design allows the Scalar Core to perform other scalar tasks while waiting for the vector operation to complete, improving computing efficiency and energy efficiency.

[0183] In the above embodiment of the present application, the method also includes: in response to the scalar core receiving a scalar request instruction and a vector request instruction at the same time, executing the scalar request instruction through the scalar core, obtaining a first instruction execution result, and generating a masking instruction; after obtaining the first instruction execution result, sending the vector request instruction to the vector unit through the scalar core, wherein the masking instruction is used to mask the vector request instruction before receiving the execution result corresponding to the scalar request instruction.

[0184] The above-mentioned mask instruction is used to control the execution timing of the vector request instruction, ensuring that the vector request instruction will not be executed by the vector unit before the scalar request instruction is executed and the result is obtained.

[0185] When the scalar core receives a scalar request instruction and a vector request instruction at the same time, the scalar request instruction is executed first and a mask instruction is generated. The function of the mask instruction is to prevent the vector request instruction from being sent to the vector unit for execution before the result of the scalar request instruction is returned. Once the result of the scalar request instruction is obtained, the mask instruction is released, and the scalar core continues to send the vector request instruction to the vector unit for execution. By ensuring the sequential execution of instructions and the consistency of data, data access conflicts and out-of-order execution can be avoided even when a loosely coupled architecture is adopted between the scalar core and the vector unit. At the same time, by introducing the mask instruction, the scalar core can be allowed to complete the current scalar task before processing the vector request instruction, thereby achieving the priority scheduling of tasks and the enhancement of concurrent processing capabilities to a certain extent, and improving the overall efficiency and performance of the processor.

[0186] For example, in an AI application, the scalar core receives a scalar request instruction, which requires reading a scalar value from the memory for calculation. At the same time, the scalar core also receives a vector request instruction, which requires reading a vector from the same area of ​​memory for processing. In order to avoid the vector unit starting to perform vector operations before the scalar core has completed the scalar operation, resulting in possible data errors or inconsistencies, the scalar core will first execute the scalar request instruction and generate a mask instruction.

[0187] The shielding instruction prevents the vector request instruction from being sent to the vector unit immediately. When the scalar core completes the execution of the scalar request instruction and obtains the execution result of the first instruction, it releases the shielding instruction. At this time, the vector request instruction can be safely sent to the vector unit for execution through the Request channel of the GIU (general interface unit) without conflicting with the scalar operation. After the vector unit completes the vector operation, it returns the result to the scalar core through the Response channel of the GIU to complete the entire operation process. This mechanism not only ensures the orderliness of data access, but also makes full use of the concurrent processing capabilities of the processor's internal resources. Especially in AI applications, it can significantly improve the throughput and efficiency of the processor and ensure the stability and performance of the system.

[0188] Table 1

[0189]

[0190] The above table describes how to maintain the order of memory access between different instructions when the scalar core and vector unit are independent of each other in this application. The order of memory access refers to the order in which these operations appear in the memory when the processor performs read and write operations. In a multi-processor or multi-threaded environment, the correctness of the memory access order is crucial to ensuring the consistency of the program. YOUNGER: refers to the newer instruction in time, that is, the instruction executed later in the program. OLDER: refers to the older instruction in time, that is, the instruction executed first in the program.

[0191] Fig.10 is a schematic diagram of maintaining a memory access sequence according to an embodiment of the present application, such as Fig.10 As shown in the figure, the hardware can maintain the memory access order between the scalar core and the vector unit, and the vector ordering table (VOT) can be implemented in the scalar core. The maintenance of the vector ordering table includes two aspects: allocation and deallocation. During the allocation process, when a vector load / store instruction needs to be sent to the vector unit for execution, the vector ordering table will allocate a new entry. At the same time, these vector load / store instructions will carry the index of the VOT entry for tracking and management in subsequent processing. During the deallocation process, when the execution result of the vector load / store instruction has been globally visible to the entire system, that is, the associated processing has been completed and the system status has been updated, the carried VOT entry index can be returned to the scalar core through the response channel. After receiving these indexes, the scalar core will release the corresponding entries, thereby releasing resources and maintaining the efficiency of VOT maintenance.

[0192] The above method ensures the memory access order between vector instructions and scalar instructions, ensuring the consistency and correctness of the program, which is very critical, especially in parallel processing or vector computing. Through VOT, the load and data dependency of the vector unit can be effectively managed to avoid data competition and inconsistency problems. The following Table 1 describes the process of maintaining the memory access order between the scalar core and the vector unit.

[0193] Scalar load / store: For scalar load and store instructions, they are executed inside the scalar core, so the ordering between these instructions is guaranteed. This means that if two scalar store instructions are issued one after another, the store operation of the older instruction will be completed in memory before the store operation of the newer instruction.

[0194] Vector Load / Store: For vector class load and store instructions, they are executed by the vector unit. Special considerations are required when these instructions interact with scalar instructions.

[0195] When a vector load / store instruction (YOUNGER) interacts with a scalar load / store instruction (OLDER), the vector instruction needs to wait for all preceding scalar instructions to complete before it can be sent to the Vector Unit for execution. This is to maintain the memory access order of the scalar instruction and prevent the vector unit from executing ahead of the scalar instruction and destroying data consistency. When a scalar load / store instruction (YOUNGER) interacts with a vector load / store instruction (OLDER), the scalar instruction needs to wait for the entry of the vector ordering table (VOT) related to the preceding vector instruction to be released before it can be executed. This is because the order in which the vector unit executes may be different from the order in the program due to internal parallelism, and VOT is used to track and maintain the memory access order of the vector unit. Only when the memory access of all vector instructions is globally visible, that is, the VOT entry is released, can the scalar instruction be executed safely to avoid data competition and consistency issues.

[0196] In the above way, when processing vector instructions, the vector sort table tracks and maintains the memory access order of the vector unit, and ensures that the scalar instructions are executed at the appropriate time point and will not be completed before the related vector instructions, thereby avoiding potential data inconsistency problems. This mechanism is suitable for AI applications, especially when scalar programs and vector programs may access the same data, ensuring system stability and data correctness.

[0197] In many AI applications, Scalar programs and Vector programs will not use the same variables in most cases. Even if they do, it is rare. In this case, the hardware does not need to maintain the memory access order of Scalar programs and Vector programs, but the software is responsible for maintaining the order. In this case, VOT can be removed.

[0198] For example, the following pseudo code:

[0199] Scalar_Load_Store (scalar load and store).

[0200] FENCE RW,RW (read-write barrier).

[0201] Vector_Load_Store (vector load and store).

[0202] Scalar_Load_Store and Vector_Load_Store in the pseudocode represent the memory access operations of the Scalar core and the Vector unit respectively. FENCE RW,RW is a memory barrier instruction that ensures that all read and write operations before the execution of this instruction are completed and visible to the entire system, and all operations after the execution of this instruction must be completed before it can be executed. This means that all Scalar_Load_Store instructions before FENCE RW,RW will be completed before the Vector_Load_Store instruction is executed, thus ensuring data consistency between Scalar and Vector operations.

[0203] Fig.11 is a schematic diagram of a lightweight multithreading structure between a scalar core and a vector unit according to an embodiment of the present application, such as Fig.11 As shown, lightweight multithreading allows the scalar core and the vector unit to perform different tasks in parallel, thereby improving the efficiency and throughput of the processor. An instruction buffer can be implemented inside the vector unit, which can be used to cache a certain number of vector instructions. After sending all vector instructions, the scalar core can execute other workloads, and the vector unit can execute vector programs at the same time. The vector unit can return the status of the vector unit to the scalar core through the response channel. The scalar core can obtain the status of the vector unit by periodic polling, thereby determining the next task. Lightweight multithreading can be achieved in the above manner.

[0204] The Instruction Buffer inside the Vector Unit is used to temporarily store the Vector instructions sent by the Scalar Core through the GIU's Request channel. The existence of this buffer allows the Vector Unit to work independently of the Scalar Core. Instead of waiting for every instruction from the Scalar Core, it can load a certain number of Vector instructions in advance for preprocessing and execution. In this way, when the Scalar Core completes sending the Vector instructions, it can immediately switch to other tasks (such as executing a new Scalar instruction sequence or handling interrupts), while the Vector Unit can continue to execute the Vector instructions in the cache without synchronizing with the Scalar Core.

[0205] Since Scalar Core and Vector Unit can run in different Clock Domains, it means they can work independently at different frequencies. This asynchronous execution mode enables Vector Unit to maintain efficient operation while Scalar Core is processing other tasks, without being limited by the frequency of Scalar Core. At the same time, through the Response channel, Vector Unit can feedback the execution status (such as instruction completion status, exception status, etc.) to Scalar Core, so that Scalar Core can monitor the work progress of Vector Unit.

[0206] Scalar Core can learn whether Vector Unit has completed the scheduled Vector instruction set and whether it needs to handle any exceptions or status updates returned by Vector Unit by polling periodically, that is, periodically querying the status of Vector Unit. This method allows Scalar Core to dynamically adjust its task scheduling. For example, when VectorUnit's buffer is idle, Scalar Core can send more Vector instructions, or when Vector Unit needs Scalar Core's assistance (such as handling exceptions), Scalar Core can suspend the current task and handle VectorUnit's needs instead.

[0207] The introduction of lightweight multi-threading mechanism enables the processor to support parallel processing at the hardware level without the need for complex operating system-level thread scheduling. Vector Unit and Scalar Core can process different tasks at the same time, thereby improving overall computing efficiency. Vector Unit can independently execute Vector instructions while Scalar Core is processing other tasks, reducing the waiting time between tasks. Vector Unit and Scalar Core can run at their most suitable frequencies and power management strategies, improving the energy efficiency and adaptability of the system. By decoupling vector processing and scalar processing, the design of Scalar Core can be simplified, allowing it to focus more on the efficient execution of scalar tasks. The lightweight multi-threading mechanism decouples Scalar Core and Vector Unit, allowing them to work in parallel and asynchronously, thereby improving processor performance while also optimizing energy efficiency and design complexity.

[0208] This application proposes an implementation scheme for a RISC-V Vector processor, which can decouple Scalar from Vector, fully release the capabilities of Vector, and greatly expand Vector Length to achieve greater computing power. This application can effectively reduce the implementation complexity of Scalar Core and allow Scalar Core to run at a higher frequency. Scalar and Vector can be asynchronous and have independent power domains, which can effectively improve energy efficiency. This application can also achieve lightweight multi-threading.

[0209] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0210] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0211] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0212] According to an embodiment of the present application, a vector processor operation device for implementing the above-mentioned vector processor operation method is also provided. Fig.12 is a schematic diagram of an operating device of a vector processor according to an embodiment of the present application, such as Fig.12 As shown, the device 1200 includes: a sending module 1202 , an execution module 1204 , a first configuration module 1206 , and a second configuration module 1208 .

[0213] Among them, the sending module is used to respond to the scalar core receiving a scalar request instruction and a vector request instruction, execute the scalar request instruction through the scalar core, obtain a first instruction execution result, send the vector request instruction to the vector unit, and obtain a first clock frequency and a first working state of the scalar core; the execution module is used to execute the vector request instruction through the vector unit, obtain a second instruction execution result, and obtain a second clock frequency and a second working state of the vector unit; the first configuration module is used to configure the clock domain for the scalar core and the vector unit respectively based on the first clock frequency and the second clock frequency; the second configuration module is used to configure the power supply domain for the scalar core and the vector unit respectively based on the first working state and the second working state.

[0214] It should be noted that the sending module 1202, the execution module 1204, the first configuration module 1206, and the second configuration module 1208 correspond to steps S902 to S908 in the above embodiment, and the four modules and the corresponding steps implement the same examples and application scenarios, but are not limited to the contents disclosed in the above embodiment. It should be noted that the above modules or units can be hardware components or software components stored in a memory (e.g., memory 104) and processed by one or more processors (e.g., processors 102a, 102b, ..., 102n), and the above modules can also be part of the device and can be run in the computer terminal 10 provided in the above embodiment.

[0215] In the above embodiments of the present application, the first configuration module is used to configure different clock domains for the scalar core and the vector unit in response to the difference between the first clock frequency and the second clock frequency; and to configure the same clock domain for the scalar core and the vector unit in response to the difference between the first clock frequency and the second clock frequency.

[0216] In the above embodiments of the present application, the second configuration module configures different power supply domains for the scalar core and the vector unit in response to the first working state and the second working state being different; and configures the same power supply domain for the scalar core and the vector unit in response to the first working state and the second working state being the same.

[0217] In the above embodiments of the present application, the device further includes: an allocation module and a release module.

[0218] Among them, the allocation module is used to allocate the first entry in the vector sorting table to the vector request instruction through the scalar core, wherein the vector request instruction carries the first identification information of the first entry; the release module is used to respond to the scalar core receiving the second instruction execution result feedback from the vector unit, and release the second entry corresponding to the second identification information in the vector sorting table through the scalar core according to the second identification information carried by the second instruction execution result.

[0219] In the above embodiments of the present application, the vector unit includes an instruction cache, and the sending module is further used to send the cache status of the instruction cache to the scalar core through the vector unit.

[0220] In the above embodiments of the present application, the execution module is also used to respond to receiving a new scalar request instruction and a historical scalar request instruction, and execute the new scalar request instruction after the historical scalar request instruction is completed through the scalar core; respond to receiving a new scalar request instruction and a historical vector request instruction, and execute the new scalar request instruction after the historical vector request instruction is sent to the vector unit through the scalar core; respond to receiving a new vector request instruction and a historical scalar request instruction, and send the new vector request instruction to the vector unit after the historical scalar request instruction is completed through the scalar core; respond to receiving a new vector request instruction and a historical vector request instruction, and send the new vector request instruction to the vector unit after the historical vector request instruction is sent to the vector unit through the scalar core.

[0221] In the above embodiment of the present application, the execution module is also used to respond to the scalar core receiving a scalar request instruction and a vector request instruction at the same time, execute the scalar request instruction through the scalar core, obtain a first instruction execution result, and generate a masking instruction; after obtaining the first instruction execution result, send the vector request instruction to the vector unit through the scalar core, wherein the masking instruction is used to mask the vector request instruction before receiving the execution result corresponding to the scalar request instruction.

[0222] The embodiment of the present application may provide an electronic device, which may be any electronic device in a group of electronic devices. Optionally, in this embodiment, the electronic device may also be replaced by a terminal device such as a mobile terminal.

[0223] Optionally, in this embodiment, the electronic device may be located in at least one network device among a plurality of network devices of a computer network.

[0224] In this embodiment, the computer terminal can execute the program code in the method.

[0225] Optionally, Fig.13 is a structural block diagram of an electronic device according to an embodiment of the present application. Fig.13 As shown, the electronic device A may include: one or more ( Fig.13 (only one is shown) processor 102, memory 104, storage controller, and peripheral interface, wherein the peripheral interface is connected to the radio frequency module, audio module and display.

[0226] Among them, the memory can be used to store software programs and modules, such as program instructions / modules corresponding to the methods and devices in the embodiments of the present application. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory, that is, implementing the methods in the above embodiments. The memory may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory may further include a memory remotely arranged relative to the processor, and these remote memories may be connected to the terminal A via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0227] The processor can call the information and application programs stored in the memory through the transmission device to perform the following steps: in response to the scalar core receiving a scalar request instruction and a vector request instruction, execute the scalar request instruction through the scalar core to obtain a first instruction execution result, send the vector request instruction to the vector unit, and obtain a first clock frequency and a first working state of the scalar core; execute the vector request instruction through the vector unit to obtain a second instruction execution result, and obtain a second clock frequency and a second working state of the vector unit; configure clock domains for the scalar core and the vector unit based on the first clock frequency and the second clock frequency respectively; configure power supply domains for the scalar core and the vector unit based on the first working state and the second working state respectively.

[0228] In an embodiment of the present application, a vector processor includes: a scalar core, which is used to execute a received scalar request instruction, obtain a first instruction execution result, and send the received vector request instruction to a vector unit, wherein the scalar core has a first clock frequency and a first working state; a vector unit, which is connected to the scalar core through a communication interface unit, and is used to execute the vector request instruction and obtain a second instruction execution result, wherein the vector unit has a second clock frequency and a second working state; a controller, which is respectively connected to the scalar core and the vector unit, and is used to configure the clock domains of the scalar core and the vector unit according to the first clock frequency and the second clock frequency, and configure the power supply domains of the scalar core and the vector unit according to the first working state and the second working state, thereby achieving the purpose of improving processor efficiency. It is easy to notice that by introducing the communication interface unit to decouple the scalar core and the vector unit, the two can run independently at different clock frequencies. The scalar core remains at the first clock frequency and can run at a higher frequency to optimize the processing speed of the scalar task; the vector unit runs at the second clock frequency and can be adjusted to a better frequency according to the actual computing requirements to achieve efficient vector calculation. The controller can dynamically adjust the clock domain and power supply domain between the scalar core and the vector unit according to the working state and clock frequency of the scalar core and the vector unit, that is, when vector calculation is not required, the vector unit can be placed in a low power mode, and when the scalar core processes vector instructions, the vector unit can be quickly activated to match the required high-performance state, reducing unnecessary power consumption and improving energy efficiency. The loosely coupled operation of the scalar core and the vector unit allows the two to be independently optimized according to their respective task types and requirements, thereby solving the technical problem of low processor processing efficiency in the related art due to the shared restrictions on clock frequency and memory access bandwidth. At the same time, through the dynamic management of the controller, the efficient operation and good energy efficiency performance of the system are ensured, thereby solving the technical problem of low processor processing efficiency in the related art.

[0229] Those skilled in the art will understand that Fig.13 The structure shown is for illustration only. The electronic device may also be a smart phone (such as an Android phone, an iOS phone, etc.), a tablet computer, a PDA, a mobile Internet device (MID), a PAD, or other terminal devices. The figure does not limit the structure of the above electronic devices. For example, the electronic device A may include more or fewer components (such as a network interface, a display device, etc.) than those shown in the figure, or have the same Fig.13 Different configurations are shown.

[0230] A person of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing the hardware related to the terminal device through a program, and the program can be stored in a computer-readable storage medium, and the storage medium may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0231] The embodiment of the present application further provides a computer-readable storage medium. Optionally, in this embodiment, the computer-readable storage medium can be used to store the program code executed by the method provided in the above embodiment.

[0232] Optionally, in this embodiment, the above storage medium may be located in any electronic device in a group of electronic devices in a computer network, or in any mobile terminal in a group of mobile terminals.

[0233] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for performing the following steps: in response to the scalar core receiving a scalar request instruction and a vector request instruction, executing the scalar request instruction through the scalar core to obtain a first instruction execution result, sending the vector request instruction to the vector unit, and obtaining a first clock frequency and a first working state of the scalar core; executing the vector request instruction through the vector unit to obtain a second instruction execution result, and obtaining a second clock frequency and a second working state of the vector unit; configuring clock domains for the scalar core and the vector unit based on the first clock frequency and the second clock frequency respectively; configuring power supply domains for the scalar core and the vector unit based on the first working state and the second working state respectively.

[0234] In an embodiment of the present application, a vector processor includes: a scalar core, which is used to execute a received scalar request instruction, obtain a first instruction execution result, and send the received vector request instruction to a vector unit, wherein the scalar core has a first clock frequency and a first working state; a vector unit, which is connected to the scalar core through a communication interface unit, and is used to execute the vector request instruction and obtain a second instruction execution result, wherein the vector unit has a second clock frequency and a second working state; a controller, which is respectively connected to the scalar core and the vector unit, and is used to configure the clock domains of the scalar core and the vector unit according to the first clock frequency and the second clock frequency, and configure the power supply domains of the scalar core and the vector unit according to the first working state and the second working state, thereby achieving the purpose of improving processor efficiency. It is easy to notice that by introducing the communication interface unit to decouple the scalar core and the vector unit, the two can run independently at different clock frequencies. The scalar core remains at the first clock frequency and can run at a higher frequency to optimize the processing speed of the scalar task; the vector unit runs at the second clock frequency and can be adjusted to a better frequency according to the actual computing requirements to achieve efficient vector calculation. The controller can dynamically adjust the clock domain and power supply domain between the scalar core and the vector unit according to the working state and clock frequency of the scalar core and the vector unit, that is, when vector calculation is not required, the vector unit can be placed in a low power mode, and when the scalar core processes vector instructions, the vector unit can be quickly activated to match the required high-performance state, reducing unnecessary power consumption and improving energy efficiency. The loosely coupled operation of the scalar core and the vector unit allows the two to be independently optimized according to their respective task types and requirements, thereby solving the technical problem of low processor processing efficiency in the related art due to the shared restrictions on clock frequency and memory access bandwidth. At the same time, through the dynamic management of the controller, the efficient operation and good energy efficiency performance of the system are ensured, thereby solving the technical problem of low processor processing efficiency in the related art.

[0235] The embodiment of the present application further provides a computer program product. Optionally, in this embodiment, the computer program product may include a computer program, and the computer program implements the method provided in the embodiment when executed by a processor.

[0236] The embodiments of the present application also provide a computer program product. Optionally, the computer program product may include a non-volatile computer-readable storage medium, which may be used to store a computer program, and when the computer program is executed by a processor, the method provided in the embodiments is implemented.

[0237] The embodiment of the present application further provides a computer program. Optionally, in this embodiment, when the computer program is executed by a processor, the method provided in the above embodiment is implemented.

[0238] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0239] In the above embodiments of the present application, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0240] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0241] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0242] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0243] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk and other media that can store program codes.

[0244] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A vector processor, characterized in that: include: A scalar core, configured to execute the received scalar request instruction, obtain a first instruction execution result, and send the received vector request instruction to the vector unit, wherein the scalar core has a first clock frequency and a first working state; The vector unit is connected to the scalar core via a communication interface unit, and is used to execute the vector request instruction to obtain a second instruction execution result, wherein the vector unit has a second clock frequency and a second working state; A controller is connected to the scalar core and the vector unit, respectively, and is used to configure the clock domains of the scalar core and the vector unit according to the first clock frequency and the second clock frequency, and to configure the power supply domains of the scalar core and the vector unit according to the first working state and the second working state.

2. The vector processor according to claim 1, characterized in that The vector processor also includes: A first memory access port, wherein a first end of the first memory access port is connected to an interconnection network of the vector processor, and a second end of the first memory access port is connected to the scalar core, and is used to provide an access channel for the scalar core to communicate with the interconnection network; a second memory access port, wherein a first end of the second memory access port is connected to the internet network, and a second end of the second memory access port is connected to the vector unit, and is used to provide an access channel for the vector unit to communicate with the internet network; The controller is connected to the first memory access port and the second memory access port respectively, and is used to provide an access channel to the interconnect network for the scalar core according to a scalar core memory access instruction, and to provide an access channel to the interconnect network for the vector unit according to a vector unit memory access instruction.

3. The vector processor according to claim 1, characterized in that The communication interface unit comprises: a request channel for sending the vector request instruction of the scalar core to the vector unit; A response channel is used to write the second instruction execution result of the vector unit back to the scalar core.

4. The vector processor according to claim 3, characterized in that: The scalar core includes: A vector sorting table is connected to the request channel and the response channel respectively, wherein the vector sorting table is used to maintain a memory access order between the scalar core and the vector unit.

5. The vector processor according to claim 3, characterized in that: The vector unit comprises: An instruction cache is connected to the request channel and is used to cache a preset number of vector request instructions.

6. The vector processor according to claim 1, characterized in that: The vector processor adopts a reduced instruction set computer architecture.

7. A method for operating a vector processor, characterized in that: Applicable to processors, including: In response to the scalar core receiving a scalar request instruction and a vector request instruction, executing the scalar request instruction by the scalar core to obtain a first instruction execution result, sending the vector request instruction to a vector unit, and obtaining a first clock frequency and a first working state of the scalar core; Executing the vector request instruction by the vector unit to obtain a second instruction execution result, and acquiring a second clock frequency and a second working state of the vector unit; respectively configuring clock domains for the scalar core and the vector unit based on the first clock frequency and the second clock frequency; Power supply domains are configured for the scalar core and the vector unit based on the first working state and the second working state, respectively.

8. The method for operating a vector processor according to claim 7, characterized in that: Configuring clock domains for the scalar core and the vector unit based on the first clock frequency and the second clock frequency, respectively, includes: In response to the first clock frequency and the second clock frequency being different, configuring different clock domains for the scalar core and the vector unit; In response to the first clock frequency and the second clock frequency being different, configuring the same clock domain for the scalar core and the vector unit.

9. The method for operating a vector processor according to claim 7, characterized in that: Configuring the power supply domain for the scalar core and the vector unit based on the first working state and the second working state respectively includes: In response to the first working state and the second working state being different, configuring different power supply domains for the scalar core and the vector unit; In response to the first working state and the second working state being the same, configuring the same power supply domain for the scalar core and the vector unit.

10. The method for operating a vector processor according to claim 7, characterized in that: The scalar core includes a vector sort table, and after sending the vector request instruction to the vector unit, the method further includes: Allocating, by the scalar core, a first entry in the vector sorting table to the vector request instruction, wherein the vector request instruction carries first identification information of the first entry; In response to the scalar core receiving the second instruction execution result fed back by the vector unit, the scalar core releases the second entry corresponding to the second identification information in the vector sorting table according to the second identification information carried by the second instruction execution result.

11. The method for operating a vector processor according to claim 7, characterized in that: The vector unit includes an instruction cache. After executing the vector request instruction and obtaining a second instruction execution result, the method further includes: The cache status of the instruction cache is sent to the scalar core through the vector unit.

12. The method for operating a vector processor according to claim 7, characterized in that: The scalar request instruction includes a new scalar request instruction and a historical scalar request instruction, the vector request instruction includes a new vector request instruction and a historical vector request instruction, and the method further includes: In response to receiving the new scalar request instruction and the historical scalar request instruction, executing the new scalar request instruction after the historical scalar request instruction is completed by the scalar core; In response to receiving the new scalar request instruction and the historical vector request instruction, after sending the historical vector request instruction to the vector unit through the scalar core, the new scalar request instruction is executed; In response to receiving the new vector request instruction and the historical scalar request instruction, after executing the historical scalar request instruction through the scalar core, sending the new vector request instruction to the vector unit; In response to receiving the new vector request instruction and the historical vector request instruction, the scalar core sends the historical vector request instruction to the vector unit and then sends the new vector request instruction to the vector unit.

13. The method for operating a vector processor according to claim 7, characterized in that: The method further comprises: In response to the scalar core receiving the scalar request instruction and the vector request instruction at the same time, executing the scalar request instruction by the scalar core to obtain a first instruction execution result and generating a mask instruction; After obtaining the first instruction execution result, the vector request instruction is sent to the vector unit through the scalar core, wherein the mask instruction is used to mask the vector request instruction before receiving the execution result corresponding to the scalar request instruction.

14. A processor, characterized in that: include: A vector processor as claimed in any one of claims 1 to 6.

15. A system on chip, characterized in that: include: A vector processor as claimed in any one of claims 1 to 6.

16. An electronic device, characterized in that: include: A memory storing an executable program; A processor, configured to run the program, wherein the program executes the method according to any one of claims 7 to 13 when running.

17. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored executable program, wherein when the executable program is executed, the device where the storage medium is located is controlled to execute the method according to any one of claims 7 to 13.

18. A computer program product, characterized in that It comprises a computer program which, when executed by a processor, implements the method according to any one of claims 7 to 13.

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