Code automatic vectorization optimization method and device and medium

Abstract

The invention discloses an automatic code vectorization optimization method and device and a medium, belongs to the technical field of high-performance computing, and aims at solving the problems that existing automatic code vectorization is inconvenient, the manual operation proportion is large, vectorization of irregular codes or codes with a load dependency relationship is difficult to support, and the vectorization efficiency is high. And improvement of calculation performance and reduction of energy consumption are not facilitated. The method comprises the steps of obtaining a scalar instruction diagram of a calculation task according to a calculation kernel of parallel calculation; performing protocol conversion processing on the scalar instruction diagram to obtain a protocol instruction diagram; according to the high-level organization structure of the instruction, grouping processing related to mapping vectors is carried out on the protocol instruction graph, and a grouping graph is obtained; based on the limited vector length of hardware, performing splitting matching processing on instruction vectors in the grouping graph to obtain a vector matching grouping graph; and executing configuration on each group of elements in the vector matching grouping graph to obtain a vector operation graph.

Description

Technical Field

[0001] The present application relates to the field of high performance computing, and in particular to a method, device and medium for automatic code vectorization optimization. Background Art

[0002] In the field of high-performance computing, parallel computing was initially widely used in scientific computing. In recent years, with the development of artificial intelligence and machine learning, the need to use parallel computing to widely and effectively use computing resources has become more urgent. Vectorization is an important feature of parallel computing in modern computer architecture, which allows a single instruction to be executed on multiple data, that is, single instruction multiple data.

[0003] To take advantage of this feature, the program must explicitly use vector instructions. Currently, this requirement mostly relies on professional programmers engaged in high-performance computing to manually vectorize the code in assembly language or using built-in functions. In order to reduce the expertise required for code vectorization and improve the portability of the code, the back-end compiler is required to vectorize the program when generating machine code or at runtime.

[0004] Therefore, developing smarter compilers and tools to more widely support automatic vectorization is an important research direction in the current high-performance computing field. There is an urgent need for a code automatic vectorization optimization system that supports vectorization of irregular or load-dependent codes, thereby improving computing performance and reducing energy consumption. Summary of the invention

[0005] The embodiments of the present application provide a method, device and medium for automatic code vectorization optimization, which are used to solve the following technical problems: the existing automatic code vectorization is relatively inconvenient, manual operation accounts for a large proportion, and it is difficult to support vectorization of irregular or load-dependent codes, which is not conducive to improving computing performance and reducing energy consumption.

[0006] The present application embodiment adopts the following technical solutions: On the one hand, an embodiment of the present application provides a method for automatic vectorization optimization of code, including: obtaining a scalar instruction graph of a computing task according to a computing kernel of parallel computing; performing protocol conversion processing on the scalar instruction graph to obtain a protocol instruction graph; grouping the protocol instruction graph with relevant mapping features according to a high-level organizational structure of instructions to obtain a group graph; based on a hardware-limited vector length, splitting and matching the instruction vectors in the group graph to obtain a vector matching group graph; executing and configuring the elements of each group in the vector matching group graph to obtain a vector operation graph.

[0007] The embodiment of the present application converts scalar instructions into vector instructions, and the method can significantly improve the speed of data processing, especially when processing large amounts of data. Vectorized operations can usually reduce the number of memory accesses because they can process multiple data elements in one operation, thereby reducing the pressure on memory bandwidth. Since vectorized operations can more effectively utilize processor resources, energy consumption can be reduced while increasing computing speed. Vectorized instructions can often make better use of processor caches because they can process multiple data items at a time, reducing cache misses. Through protocol conversion and group processing, the method can automatically optimize the code without the need for programmers to manually perform complex optimization work. Vectorization technology is usually closely related to a specific hardware architecture. This method can improve the portability of code on different hardware platforms because it can automatically apply vectorization on a variety of hardware. Vectorization is a form of parallel processing, and this method can enhance the parallel processing capabilities of an application, especially when processing vector or matrix operations. Automatic vectorization can simplify the programming model because it reduces the complexity of manual optimization required by programmers. Through automated processing, vectorized optimization becomes easier to implement, especially for developers who are not familiar with vectorized programming.

[0008] In a feasible implementation, according to the computing kernel of parallel computing, a scalar instruction graph of a computing task is obtained, specifically including: through the computing kernel, assigning and configuring the relevant registers of the computing task, and determining the assignment nodes between the scalar instructions in the computing task; performing storage configuration on the registers in the computing task by specifying address data, and determining the loading nodes between the scalar instructions; determining the operation nodes between the scalar instructions based on the operation logic corresponding to the input and output in the register; performing external memory processing of the operation results in the register at the specified storage address, and generating storage nodes between the scalar instructions; according to the data dependency order and data execution order between the scalar instructions, and based on the assignment nodes, the loading nodes, the operation nodes and the storage nodes, performing tree analysis processing on each scalar instruction in the computing task under the logical operation relationship, to obtain the scalar instruction graph.

[0009] In a feasible implementation, the scalar instruction graph is subjected to a protocol conversion process to obtain a reduced instruction graph, specifically including: performing parallel loading processing on each load array in the scalar instruction graph; performing graph node reduction processing on element attributes in the load array through a preset reduction operation to obtain a load array element graph node; performing graph node reduction processing on the load execution algorithm of each element in the load array to obtain an element execution algorithm graph node; performing graph node reduction processing on the storage result of each element in the load array to obtain an element storage graph node; performing corresponding conversion on the load array element graph node, the element execution algorithm graph node and the element storage graph node and integrating them into the scalar instruction graph to generate the reduced instruction graph.

[0010] In a feasible implementation manner, the reduction operation is a single operation combined with an arithmetic operation and a logical operation on multiple elements.

[0011] In a feasible implementation, according to the high-level organizational structure of instructions, the reduction instruction graph is grouped according to the mapping characteristics to obtain a group graph, specifically including: according to the type characteristics and dependency characteristics of the element attributes, the element attributes in the same load array in the reduction instruction graph are grouped and divided to obtain an element attribute group; according to the loading characteristics of the input array, the input arrays under the same load instruction in the reduction instruction graph are grouped and divided to obtain a load instruction group; according to the storage characteristics of the output array, the output arrays under the same storage instruction in the reduction instruction graph are grouped and divided to obtain a storage instruction group; according to each node in the scalar instruction graph, the corresponding elements at the same processing node in each scalar instruction array are grouped and processed to obtain a node structure group; through the high-level organizational structure, the element attribute group, the load instruction group, the storage instruction group and the node structure group are integrated and processed to obtain the group graph.

[0012] In a feasible implementation, based on the limited vector length of the hardware, the instruction vectors in the grouping diagram are split and matched to obtain a vector matching grouping diagram, which specifically includes: comparing and judging the instruction vector length of the instruction vector in the group diagram with the limited vector length; if each of the instruction vector lengths is less than the limited vector length, the limited vector length is used as a matching template, and the next instruction vector length is split and matched to obtain a supplementary instruction vector length; the supplementary instruction vector length is merged and matched with the current instruction vector length to obtain a merged instruction vector length; wherein the merged instruction vector length is equal to the limited vector length; if each of the instruction vector lengths is greater than the limited vector length , then based on the limited vector length as a matching template, the current instruction vector length is split and matched to obtain a split instruction vector length; wherein the split instruction vector length is equal to the limited vector length; based on the split instruction vector length and the merged instruction vector length, the instruction vector length that is less than the limited vector length is determined as the remaining instruction vector length; wherein the remaining instruction vector length is the value of the residual instruction vector after the splitting and / or merging processing is completed; based on the split instruction vector length, the merged instruction vector length and the remaining instruction vector length, the vector matching grouping diagram after completing the vector length matching is obtained; wherein the vector matching grouping diagram is a grouping diagram after the array instruction partition matching.

[0013] In a feasible implementation, the elements of each group in the vector matching grouping diagram are executed and configured to obtain a vector operation diagram, which specifically includes: identifying the elements of each array in the vector matching grouping diagram, and sorting the elements according to the data execution format and the data loading order to obtain the element order in each array; according to the element order, the elements in each array are correspondingly replaced or extracted to obtain the vector operation diagram; wherein the vector operation diagram is used to guide the vector instructions to be loaded into the register.

[0014] In a feasible implementation, after executing and configuring the elements of each group in the vector matching grouping diagram to obtain a vector operation diagram, the method further includes: converting the vector operation diagram into a vector instruction list through a parallel computing backend; wherein the vector instruction table contains the vector instructions that need to be executed on the target hardware; and vectorizing the code in the computing task through the vector instruction list to complete the compilation processing of the parallel computing data.

[0015] In a second aspect, an embodiment of the present application further provides a code automatic vectorization optimization device, the device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor so that the at least one processor can execute a code automatic vectorization optimization method described in any of the above embodiments.

[0016] In a third aspect, an embodiment of the present application further provides a non-volatile computer storage medium, wherein the storage medium is a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores at least one program, each of which includes instructions, and when the instructions are executed by a terminal, the terminal executes a code automatic vectorization optimization method described in any of the above-mentioned embodiments.

[0017] The present application provides a method, device and medium for automatic code vectorization optimization. Compared with the prior art, the embodiments of the present application have the following beneficial technical effects: 1. Improve computing efficiency: By converting scalar instructions into vector instructions, this method can significantly increase the speed of data processing, especially when processing large amounts of data.

[0018] 2. Reduced memory accesses: Vectorized operations generally reduce the number of memory accesses because they can process multiple data elements in a single operation, thus reducing the pressure on memory bandwidth.

[0019] 3. Reduced energy consumption: Since vectorized operations can more efficiently utilize processor resources, they can increase computing speed while reducing energy consumption.

[0020] 4. Improved cache utilization: Vectorized instructions tend to make better use of processor caches because they can process multiple data items at a time, reducing cache misses.

[0021] 5. Code optimization: Through protocol conversion and group processing, this method can automatically optimize the code without the need for programmers to manually perform complex optimization work.

[0022] 6. Improve portability: Vectorization techniques are usually closely tied to specific hardware architectures. This approach can improve the portability of code across different hardware platforms because it can automatically apply vectorization on a variety of hardware.

[0023] 7. Enhanced parallel processing capabilities: Vectorization is a form of parallel processing that can enhance the parallel processing capabilities of an application, especially when processing vector or matrix operations.

[0024] 8. Simplified programming model: Automatic vectorization can simplify the programming model because it reduces the complexity that programmers need to manually optimize.

[0025] 9. Compatibility: The approach may be designed to be compatible with existing programming languages ​​and compilers, allowing existing code bases to gain performance improvements through optimization.

[0026] 10. Ease of implementation: Through automation, vectorization optimization becomes easier to implement, especially for developers who are not familiar with vectorized programming. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings: Figure 1 A flow chart of a code automatic vectorization optimization method provided in an embodiment of the present application; Figure 2 A schematic diagram of the structure of a scalar instruction graph obtained for a given computing task provided in an embodiment of the present application; Figure 3 A schematic diagram of the structure of a mapping vector grouping diagram provided in an embodiment of the present application; Figure 4 A schematic diagram of the structure of a code automatic vectorization optimization device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application.

[0029] The present application embodiment provides a method for automatic code vectorization optimization, such as Figure 1 As shown, the code automatic vectorization optimization method specifically includes steps S101-S105: S101. Obtain a scalar instruction graph of a computing task according to a computing kernel of parallel computing.

[0030] Specifically, it is necessary to first use the computing kernel to configure the assignment of relevant registers to the computing task and determine the assignment nodes between scalar instructions in the computing task.

[0031] Furthermore, by specifying address data, the registers in the computing task are stored and configured, and the load nodes between the scalar instructions are determined.

[0032] Furthermore, based on the operation logic corresponding to the input and output in the register, the operation nodes between the scalar instructions are determined.

[0033] Furthermore, the operation result in the register is processed in the external memory of the designated storage address, and the storage node between the scalar instructions is generated.

[0034] Furthermore, according to the data dependency order and data execution order between scalar instructions, and based on assignment nodes, load nodes, operation nodes and storage nodes, each scalar instruction in the computing task is subjected to tree analysis processing under the logical operation relationship to obtain a scalar instruction graph.

[0035] As a feasible implementation method, Figure 2 A schematic diagram of the structure of a scalar instruction graph obtained for a given computing task provided in an embodiment of the present application, such as Figure 2 As shown in Figure 1, the scalar instruction graph represents the dependency order and execution order between all scalar instructions in the kernel. The scalar instruction graph consists of four nodes: assignment, load, operation, and storage. Assignment means assigning a specified register to a given value, loading means taking the data at the specified address out of the external memory and storing it in the register, operation means using the values ​​in one or more registers as input to obtain the corresponding output value through certain arithmetic or logical operations, and storage means writing the value in the register back to the specified address in the external memory.

[0036] In one embodiment, Figure 2 As shown in FIG. 1 , it is assumed that the computing task is as follows: obtain the sum of all elements of array a and array b, each of which has 6 elements, and store the calculation result in array c. The hardware-limited vector size used to perform the computing task is 4. First, according to the given computing kernel, its scalar instruction map is obtained during the compilation process of the optimization system.

[0037] S102, performing protocol conversion processing on the scalar instruction graph to obtain a protocol instruction graph.

[0038] Specifically, each load array in the scalar instruction graph is loaded in parallel.

[0039] Furthermore, the element attributes in the loading array are reduced by a preset reduction operation to obtain a loading array element graph node, wherein the reduction operation is a single operation combined with arithmetic operations and logical operations on multiple elements.

[0040] Furthermore, the loading execution algorithm of each element in the loading array is subjected to graph node reduction processing to obtain an element execution algorithm graph node.

[0041] Furthermore, the storage results of each element in the loaded array are subjected to graph node reduction processing to obtain an element storage graph node.

[0042] Furthermore, the loading array element graph nodes, the element execution algorithm graph nodes and the element storage graph nodes are all converted accordingly and merged into the scalar instruction graph to generate a reduced instruction graph.

[0043] As a feasible implementation method, the scalar instruction graph is converted using a reduction to obtain a reduced instruction graph. A reduction is a single operation that combines arithmetic and logical operations on multiple elements. If there are arithmetic and logical operations in the scalar instruction graph, the scalar instruction graph is converted so that these reduction operations can be more effectively used in the subsequent vectorization process.

[0044] In one embodiment, Figure 2 As shown, in the computing task, the elements of array a and array b can be loaded in parallel, because the specification can convert the element attributes of the loaded array into a graph node, convert the arithmetic addition of the corresponding elements into a graph node, and convert the stored result into a graph node.

[0045] S103. According to the high-level organizational structure of the instructions, the protocol instruction graph is grouped according to the mapping features to obtain a grouping graph.

[0046] Specifically, according to the type characteristics and dependency characteristics of the element attributes, the element attributes in the same load array in the specification instruction graph are grouped and divided to obtain element attribute groups.

[0047] Furthermore, according to the loading characteristics of the input arrays, the input arrays under the same loading instruction in the specification instruction graph are grouped and divided to obtain loading instruction groups.

[0048] Furthermore, according to the storage characteristics of the output arrays, the output arrays under the same storage instruction in the protocol instruction graph are grouped and divided to obtain storage instruction groups.

[0049] Furthermore, according to each node in the scalar instruction graph, corresponding elements in the same processing node in each scalar instruction array are grouped and processed to obtain a node structure group.

[0050] Furthermore, through a high-level organizational structure, the element attribute group, the loading instruction group, the storage instruction group and the node structure group are integrated and processed to obtain a grouping graph.

[0051] As a feasible implementation method, Figure 2 As shown, the instructions of the reduced instruction graph need to be grouped according to the mapping features to obtain a grouping graph. This grouping graph represents the higher-level organizational structure of the instructions, so that the instructions can be mapped to vector instructions more easily in the future. When grouping, the dependencies and data types between instructions are considered to ensure that the grouped instructions can be executed in parallel. For example, the load instructions for the same input array are grouped into one group, and the storage instructions for the same output array are grouped into another group.

[0052] In one embodiment, Figure 2 In the calculation task, the 6 elements of the loaded array a are first divided into one group, the 6 elements of the loaded array b are divided into one group, the arithmetic addition operations of the corresponding elements of the two arrays are divided into one group, the accumulation operations of the elements of the new array obtained after the arithmetic addition calculation of the two arrays are completed are divided into one group, and the storage of the final result is divided into one group.

[0053] S104. Based on the limited vector length of the hardware, split and match the instruction vectors in the grouping graph to obtain a vector matching grouping graph.

[0054] Specifically, it is also necessary to compare the instruction vector length of the instruction vector in the group diagram with the limited vector length: If the length of each instruction vector is less than the limited vector length, the limited vector length is used as a matching template, and the next instruction vector length is split and matched to obtain a supplementary instruction vector length.

[0055] Furthermore, the supplementary instruction vector length is merged and matched with the current instruction vector length to obtain a merged instruction vector length, wherein the merged instruction vector length is equal to the limited vector length.

[0056] If the length of each instruction vector is greater than the limited vector length, the current instruction vector length is split and matched based on the limited vector length as a matching template to obtain a split instruction vector length, wherein the split instruction vector length is equal to the limited vector length.

[0057] Further, based on the split instruction vector length and the merge instruction vector length, the instruction vector length that is less than the limited vector length is determined as the remaining instruction vector length, wherein the remaining instruction vector length is the value of the remaining instruction vector after the split and / or merge process is completed.

[0058] Further, based on the split instruction vector length, the merged instruction vector length and the remaining instruction vector length, a vector matching grouping graph after completing the vector length matching is obtained, wherein the vector matching grouping graph is a grouping graph after the array instruction partition matching.

[0059] As a feasible implementation method, the instruction vectors in the grouping diagram also need to be split to match the given vector size. This vector size (limited vector length) is determined by the vector register size of the target hardware. For example: since the number of instructions in the group grouped in the previous step (instruction vector length) may exceed the given vector size (limited vector length) and is not an integer multiple of the vector size, it is necessary to split the instructions in the group into multiple columns according to the vector size, that is, split and match the current instruction vector length, and each column length is the limited vector size, and the instruction column that is less than the vector size (remaining instruction vector length) does not exceed one.

[0060] In one embodiment, since the number of array elements is 6 and the limited vector size is 4, the optimization system splits the instructions in the group according to the limited vector size. First, the instructions in the group are used to fill the instruction sequence of the given limited vector size, and preferably, the remaining instructions in the array are used to form an instruction sequence that is less than the limited vector size, that is, the remaining instruction vector length.

[0061] S105 , performing execution configuration on the elements of each group in the vector matching grouping graph to obtain a vector operation graph.

[0062] Specifically, firstly, the elements of each array in the vector matching grouping diagram are identified, and the elements are sorted according to the data execution format and the data loading order to obtain the order of elements in each array.

[0063] Furthermore, the elements in each array are replaced or extracted and configured accordingly according to the element order to obtain a vector operation graph, wherein the vector operation graph is used to guide the vector instructions to be loaded into the register.

[0064] Furthermore, the vector operation graph is converted into a vector instruction list through the parallel computing backend. The vector instruction list contains the vector instructions that need to be executed on the target hardware; through the vector instruction list, the code in the computing task is vectorized to complete the compilation of the parallel computing data.

[0065] In one embodiment, Figure 3 A schematic diagram of a structure of a mapping vector grouping diagram provided in an embodiment of the present application, such as Figure 3As shown, the execution order is first set for the elements of each array in the vector matching grouping graph, and the necessary permutation or extraction operations are performed to ensure that the data is loaded into the vector register in the correct format and order. The final generated vector operation graph is then converted into a vector instruction list using the back end. This vector instruction list contains vector instructions that can be executed on the target hardware and can efficiently process data in parallel.

[0066] In addition, the embodiment of the present application also provides a code automatic vectorization optimization device, such as Figure 4 As shown, the code automatic vectorization optimization device 400 specifically includes: At least one processor 401. And a memory 402 in communication with the at least one processor 401. The memory 402 stores instructions that can be executed by the at least one processor 401, so that the at least one processor 401 can execute: According to the computing kernel of the parallel computing, a scalar instruction graph of the computing task is obtained; Performing protocol conversion processing on the scalar instruction graph to obtain a protocol instruction graph; According to the high-level organizational structure of the instructions, the specification instruction graph is grouped according to the mapping features to obtain a grouping graph; Based on the limited vector length of the hardware, the instruction vectors in the grouping graph are split and matched to obtain a vector matching grouping graph; The elements of each group in the vector matching grouping graph are configured for execution to obtain a vector operation graph.

[0067] The embodiment of the present application can support vectorization of irregular or load-dependent codes, thereby improving computing performance and reducing energy consumption. At the same time, by converting scalar instructions into vector instructions, the method can significantly improve the speed of data processing, especially when processing large amounts of data. Vectorized operations can usually reduce the number of memory accesses because they can process multiple data elements in one operation, thereby reducing the pressure on memory bandwidth. Since vectorized operations can more effectively utilize processor resources, energy consumption can be reduced while increasing computing speed. Vectorized instructions can often make better use of processor caches because they can process multiple data items at a time, reducing cache misses. Through protocol conversion and group processing, the method can automatically optimize the code without the need for programmers to manually perform complex optimization work. Vectorization technology is usually closely related to a specific hardware architecture. This method can improve the portability of code on different hardware platforms because it can automatically apply vectorization on a variety of hardware. Vectorization is a form of parallel processing, and this method can enhance the parallel processing capabilities of applications, especially when processing vector or matrix operations. Automatic vectorization can simplify the programming model because it reduces the complexity that programmers need to manually optimize.

[0068] Each embodiment in this application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device and medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0069] The devices and media provided in the embodiments of the present application correspond one-to-one to the methods. Therefore, the devices and media also have similar beneficial technical effects as the corresponding methods. Since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the devices and media will not be repeated here.

[0070] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0071] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0072] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0073] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0074] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0075] Memory may include non-permanent storage in a computer-readable medium, in the form of random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0076] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0077] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0078] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the specification of the present application.

Claims

1. A method for automatic code vectorization optimization, characterized in that: The method comprises: According to the computing kernel of the parallel computing, a scalar instruction graph of the computing task is obtained; Performing protocol conversion processing on the scalar instruction graph to obtain a protocol instruction graph; According to the high-level organizational structure of the instructions, the protocol instruction graph is grouped according to the mapping features to obtain a grouping graph; Based on the limited vector length of the hardware, the instruction vectors in the grouping graph are split and matched to obtain a vector matching grouping graph; The elements of each group in the vector matching grouping graph are configured for execution to obtain a vector operation graph.

2. A method for automatic code vectorization optimization according to claim 1, characterized in that: According to the computing kernel of parallel computing, the scalar instruction graph of the computing task is obtained, including: By means of the computing kernel, the computing task is assigned a value to a register, and an assignment node between scalar instructions in the computing task is determined; By specifying address data, the registers in the computing task are configured for storage, and a load node between the scalar instructions is determined; Determining the operation nodes between the scalar instructions based on the operation logic corresponding to the input and output in the register; Performing external memory processing of the operation result in the register at a designated storage address, and generating storage nodes between the scalar instructions; According to the data dependency order and data execution order between the scalar instructions, and based on the assignment node, the load node, the operation node and the storage node, each scalar instruction in the computing task is subjected to tree analysis processing under a logical operation relationship to obtain the scalar instruction graph.

3. A method for automatic code vectorization optimization according to claim 1, characterized in that: Performing protocol conversion processing on the scalar instruction graph to obtain a protocol instruction graph specifically includes: Performing parallel loading processing on each load array in the scalar instruction graph; By means of a preset reduction operation, the element attributes in the loading array are subjected to a graph node reduction process to obtain a loading array element graph node; The loading execution algorithm of each element in the loading array is subjected to graph node specification processing to obtain an element execution algorithm graph node; Performing graph node reduction processing on the storage results of each element in the loading array to obtain an element storage graph node; The load array element graph nodes, the element execution algorithm graph nodes and the element storage graph nodes are all converted accordingly and merged into the scalar instruction graph to generate the reduced instruction graph.

4. A method for automatic code vectorization optimization according to claim 3, characterized in that: The reduction operation is a single operation that combines arithmetic operations and logical operations on multiple elements.

5. The method for automatic code vectorization optimization according to claim 1, characterized in that: According to the high-level organizational structure of the instructions, the protocol instruction graph is grouped according to the mapping features to obtain a grouping graph, which specifically includes: According to the type characteristics and dependency characteristics of the element attributes, the element attributes in the same load array in the protocol instruction graph are grouped and divided to obtain element attribute groups; According to the loading characteristics of the input array, the input arrays under the same loading instruction in the protocol instruction graph are divided into groups to obtain loading instruction groups; According to the storage characteristics of the output arrays, the output arrays under the same storage instruction in the protocol instruction graph are grouped and divided to obtain storage instruction groups; According to each node in the scalar instruction graph, corresponding elements in the same processing node in each scalar instruction array are grouped and processed to obtain a node structure group; The element attribute group, the loading instruction group, the storage instruction group and the node structure group are integrated and processed through the high-level organizational structure to obtain the grouping graph.

6. The method for automatic code vectorization optimization according to claim 1, characterized in that: Based on the limited vector length of the hardware, the instruction vectors in the grouping graph are split and matched to obtain a vector matching grouping graph, which specifically includes: Compare and judge the instruction vector length of the instruction vector in the group diagram with the limited vector length; If the length of each instruction vector is less than the limited vector length, the limited vector length is used as a matching template, and the next instruction vector length is split and matched to obtain a supplementary instruction vector length; The supplementary instruction vector length is merged and matched with the current instruction vector length to obtain a merged instruction vector length; wherein the merged instruction vector length is equal to the limited vector length; If the length of each instruction vector is greater than the limited vector length, then based on the limited vector length as a matching template, split matching processing is performed on the current instruction vector length to obtain a split instruction vector length; wherein the split instruction vector length is equal to the limited vector length; Based on the split instruction vector length and the merge instruction vector length, the instruction vector length that is less than the limited vector length is determined as the remaining instruction vector length; wherein the remaining instruction vector length is the value of the residual instruction vector after the splitting and / or merging process is completed; Based on the split instruction vector length, the merged instruction vector length and the remaining instruction vector length, the vector matching grouping graph after completing the vector length matching is obtained; wherein the vector matching grouping graph is a grouping graph after the array instruction partition matching.

7. The method for automatic code vectorization optimization according to claim 1, characterized in that: The elements of each group in the vector matching grouping graph are executed and configured to obtain a vector operation graph, which specifically includes: Identify the elements of each array in the vector matching grouping diagram, and sort the elements according to the data execution format and the data loading order to obtain the order of elements in each array; The elements in each array are correspondingly replaced or extracted and configured according to the element sequence to obtain the vector operation graph; wherein the vector operation graph is used to guide the vector instructions to be loaded into the register.

8. A method for automatic code vectorization optimization according to claim 7, characterized in that: After executing and configuring the elements of each group in the vector matching grouping graph to obtain a vector operation graph, the method further includes: The vector operation graph is converted into a vector instruction list through a parallel computing backend; wherein the vector instruction list includes vector instructions to be executed on the target hardware; The code in the computing task is vectorized through the vector instruction list to complete the compilation process of the parallel computing data.

9. A code automatic vectorization optimization device, characterized in that: The device comprises: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, so that the at least one processor can execute the code automatic vectorization optimization method according to any one of claims 1-8.

10. A non-volatile computer storage medium, characterized in that: The storage medium is a non-volatile computer-readable storage medium, and the non-volatile computer-readable storage medium stores at least one program, each of which includes instructions, and when the instructions are executed by a terminal, the terminal executes a code automatic vectorization optimization method according to any one of claims 1-8.

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