Read-write separated high-performance DMA (Direct Memory Access) system architecture based on TILELINK bus

Abstract

The invention provides a read-write separated high-performance DMA (direct memory access) system architecture based on a TILELINK bus, the DMA system is used in an SOC (system on chip) system based on the TILELINK bus, and comprises two bus main nodes, namely a read total node and a write total node, which are respectively connected with the TILELINK bus and are respectively used for performing data reading and writing on the TILELINK bus; the two bus main nodes are respectively in bidirectional connection with the plurality of DMA channels through an arbiter ARB, and the arbiter ARB is used for managing read-write requests of all the DMA channels; and the other end of the DMA channel is connected with a configuration register block REG and is used for configuring the DMA channel to be in different working modes.

Description

Technical Field

[0001] The invention relates to a DMA system architecture, in particular to a high-performance DMA system architecture with read-write separation based on a TILELINK bus. Background Art

[0002] This section merely provides background information related to the present disclosure and is not necessarily prior art.

[0003] In the SOC (system-on-chip) system of the TILELINK (bus protocol) bus, since TILELINK needs to complete the A channel before operating on the D channel, a data operation requires at least two cycles to complete. Due to the principle of DMA (direct memory access), the data must be read before the next write operation can be performed. Ideally, two operations require four cycles to complete, and the maximum channel utilization (the number of times data is moved within N cycles) is up to 50%, but it will be even less efficient in actual situations.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] Purpose of the invention: The technical problem to be solved by the present invention is to provide a high-performance DMA system architecture with read-write separation based on TILELINK bus in view of the deficiencies in the prior art.

[0006] In order to solve the above technical problems, the present invention discloses a high-performance DMA system architecture with read-write separation based on TILELINK bus. The DMA system is used in a SOC chip system based on TILELINK bus, comprising:

[0007] Two bus master nodes respectively connected to the TILELINK bus, namely a read master node and a write master node, for reading and writing data from the TILELINK bus respectively;

[0008] The two bus master nodes are bidirectionally connected to a plurality of DMA channels through an arbiter ARB, respectively, and the arbiter ARB is used to manage read and write requests of all DMA channels;

[0009] The other end of the DMA channel is connected to the configuration register block REG, which is used to configure the DMA channel to be in different working modes.

[0010] Furthermore, there are two arbiters ARB, which are used to manage read requests and write requests respectively.

[0011] Furthermore, the arbiter ARB manages the read and write requests using a method combining polling priority and fixed priority.

[0012] Furthermore, the method of combining the polling priority and the fixed priority specifically includes:

[0013] Step 1, setting a fixed priority, among all DMA channels, setting one or more DMA channels to a fixed priority, the fixed priority being a high priority, and other DMA channels being a low priority;

[0014] Step 2, setting the loop priority, and setting the loop priority order for other DMA channels other than the DMA channels set to fixed priority;

[0015] Step 3, the arbiter ARB responds preferentially to the read and write requests of the DMA channels with fixed priorities according to the order of fixed priorities;

[0016] Step 4: After completing the read and write requests of the DMA channel with a fixed priority, respond to the read and write requests of the corresponding DMA channel in order of cyclic priority.

[0017] Furthermore, the DMA channel includes:

[0018] Read module, write module and synchronous FIFO module; among them,

[0019] The synchronous FIFO module is used to store the data read by the read module during the storage read operation;

[0020] The write module initiates a write operation request when there is data in the synchronous FIFO module.

[0021] Furthermore, the FIFO depth in the synchronous FIFO module is set to be modifiable.

[0022] Furthermore, the DMA channel includes a secondary operation mode and a block operation mode, and adopts a read-write separation method to perform read operations and write operations.

[0023] Furthermore, the secondary operation mode includes:

[0024] When receiving a read request, the waiting arbitration module first arbitrates the DMA channel. When the read request is the highest priority, the read module occupies the bus of the top-level TILELINK read module and performs a read operation. After the read operation, the read data is pushed into the synchronous FIFO module. When there is data in the synchronous FIFO module, a write operation request is started.

[0025] Write and read operations can be performed simultaneously and relatively independently;

[0026] When a write request is received, it waits for the arbitration module to arbitrate the DMA channel. When the write request is the highest priority, the top-level TILELINK write module is occupied to perform a write operation, writing the data in the synchronous FIFO module to the corresponding address, completing a write operation.

[0027] Furthermore, the block operation mode includes:

[0028] When receiving a read request, the waiting arbitration module first arbitrates the DMA channel. When the read request is the highest priority, the read module occupies the bus of the top-level TILELINK read module and performs a read operation. The read operation performs multiple reads and continuously writes data into the synchronous FIFO module. At the same time, when the synchronous FIFO module is not empty, a write request is triggered.

[0029] When receiving a write request, it waits for the arbitration module to arbitrate the DMA channel. When the write request is the highest priority, the write module occupies the bus of the top-level TILELINK write module and performs a write operation to write the data in the synchronous FIFO module to the corresponding address. It completes multiple write operations until all write operations in the block operation mode are completed.

[0030] Among them, the read operation and the write operation occupy their own TILELINK bus respectively to complete the related operations.

[0031] Furthermore, the read and write separation method is used to perform read operations and write operations, and the specific method includes:

[0032] When a read request arrives, the priority of the read request is checked. If the highest priority of the DMA channel is the read request, the read operation is executed immediately, and after all read operations are completed, the state of waiting for all transfers to be completed is entered; if the priority of the read request in the current DMA channel is not the highest, the read request is not processed temporarily, and the next highest priority request is continued to be waited for;

[0033] When writing and reading at the same time, you need to wait for the write request. When the synchronous FIFO module is not empty, the write request is turned on. When the write request in DMA has the highest priority at this time, the write operation is executed immediately. After all write operations are completed, the state of waiting for all transfers to be completed is entered. If the priority of the write request in the current DMA channel is not high enough, the request is not processed temporarily, and the next highest priority request is continued to be waited.

[0034] It ends when all read and write requests are completed.

[0035] Beneficial effects:

[0036] 1. The present invention is used for a DMA module dedicated to the TILELINK bus, which significantly improves the overall data transfer speed while taking into account the bandwidth utilization rate, thereby improving the overall working efficiency of the SOC chip.

[0037] 2. The present invention designs a DMA of the TILELINK bus with dual master nodes, one master node for read operation and the other master node for write operation. This design can complete both read and write in the same time, effectively improving the efficiency of data transfer. Ideally, 100% channel utilization can be achieved, and its read and write efficiency becomes twice that of a single master node. Such an operation mechanism effectively saves transmission waiting time and improves the utilization of bus transmission frequency band. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments, and the above and / or other advantages of the present invention will become more clear.

[0039] Figure 1 It is a DMA framework diagram based on TILELINK.

[0040] Figure 2 This is a schematic diagram of mixed priority judgment.

[0041] Figure 3 It is a read-write priority work map.

[0042] Figure 4 This is a schematic diagram of the internal architecture of the DMA channel.

[0043] Figure 5 It is a flowchart of the DMA channel reading and writing method. DETAILED DESCRIPTION

[0044] The present invention is mainly applied to SOC chip systems based on TILELINK bus, solving the problem of data transfer from different locations and freeing up CPU for other computational work. During operation, the CPU is used to configure the DMA control register through the TILELINK bus, and after completion, it waits for other modules in the chip to trigger the condition and start to automatically transfer data. After the work is completed, the system is automatically shut down and waits for the next instruction from the CPU.

[0045] The present invention supports three kinds of operation strengths, namely byte, word and double word, and supports brust mode transmission of TILELINK bus and other transmission modes. The priority of the DMA channel can be configured as two modes, namely fixed priority and cyclic priority, and a channel can be designated as the highest priority. There are two ways to request DMA, and a group of data can be requested to be completed at one time, or a single data can be requested to be completed at one time. For the overall framework of DMA, two groups of non-interfering master nodes are selected to hang on the TILELINK bus for maximum resource utilization. The two groups of nodes only complete read and write operations respectively, and the two groups of nodes do not interfere with each other. Ideally, the handling of N data can be completed in N+1 cycles, effectively solving the problem of low efficiency of data handling on the TILELINK bus.

[0046] The specific technical solutions of the present invention are as follows:

[0047] A DMA (Direct Memory Access) controller using the TILELINK protocol, whose main purpose is to improve data transmission efficiency and channel utilization. Figure 1 As shown in the figure, the design framework includes: selecting two bus master nodes, TILELINK READ and TILELINK WRITE, which are responsible for data reading and writing operations respectively. The core component of the DMA controller is the arbiter (ARB), which is responsible for managing the requests of multiple DMA channels and ensuring that these requests can efficiently access the TILELINK bus. The arbiter determines the order of processing requests through a polling algorithm, thereby avoiding multiple requests competing for bus resources at the same time. This design greatly improves the utilization efficiency of the bus.

[0048] The DMA controller contains multiple independently working DMA channels, which are marked as dma0, dma1, ..., dmaN, dmaN+1. Each channel is responsible for the transmission of different data blocks and is connected to the arbitrator to issue data transfer requests. After the arbitrator processes the request, it returns the signal to the corresponding DMA channel to complete the data transfer operation. The register block (REG) is used to store the configuration information or status register of the DMA controller, allowing different DMA channels to realize configuration and status query by reading or writing registers. These registers can be used to monitor and control the status and configuration information of each DMA channel in real time to ensure the efficiency and stability of data transmission.

[0049] First, through the existence of the arbitrator, multiple DMA channels can issue data transfer requests at the same time. The arbitrator effectively manages these requests to prevent bus resource conflicts, thereby reducing waiting time and achieving parallel data transfer. This greatly improves channel efficiency and bus utilization. Secondly, the multi-DMA channel design allows the system to handle multiple different data transfer tasks at the same time, greatly improving the data handling capacity and throughput. In addition, through the register block, users can flexibly obtain and modify the status and configuration information of each channel, which enhances the flexibility and manageability of the system. Finally, this design framework is highly scalable, allowing the number of DMA channels to be increased or decreased according to actual needs to adapt to different loads and data transfer requirements. Therefore, this design can not only significantly improve data transmission efficiency and system performance, but also provide flexible management methods and high scalability. It is an ideal solution for efficient DMA controller design.

[0050] In addition, the benefits of using this dual master node for DMA are mainly the following two points:

[0051] Parallel processing capability: The dual-node design significantly improves the system's parallel processing capability. Two nodes can perform data read and write operations at the same time, allowing data transfer tasks to be executed in parallel, reducing the waiting time between tasks. For example, in a storage system, one node can focus on processing read requests while the other node processes write requests, thereby improving overall data throughput. This parallel processing enables the system to efficiently cope with large amounts of data transfer requirements, significantly improving performance.

[0052] Load balancing: A dual-node system can achieve more effective load balancing. By properly distributing tasks to two nodes, the system can avoid the problem of a single node becoming a bottleneck under high load. Each node shares part of the tasks to ensure that the system can still operate efficiently in high-concurrency scenarios. This design not only improves the data processing speed, but also reduces the risk of single-node overload, and improves the response speed and stability of the overall system. For example, in a server cluster, the dual-node design can effectively share user requests and ensure that the system can run smoothly even during peak hours.

[0053] The arbitration module (ARB) in this design mainly uses a mode that combines polling priority and fixed priority.

[0054] Fixed priority: During the whole priority determination process, a certain channel is designated as high priority, and the rest are low priority. At this time, if there is a transport demand in this channel, it will respond to the demand of this channel immediately after the current channel completes the transport.

[0055] Round-robin priority: After each channel handling task is completed, the priority order is switched.

[0056] Figure 2 A DMA (direct memory access) priority management system using a mixed scheduling algorithm of partial fixed priority and round-robin priority is shown. There are five DMA channels in the figure, labeled as dma0, dma1, dma2, dma3 and dma4. At the beginning, the priority of each channel is arranged in the order of dma0, dma1, dma2, dma3 and dma4. However, dma4 always maintains the highest priority position and its priority does not change with round-robin scheduling. The other channels rotate in turn within a complete cycle to ensure fairness in resource allocation.

[0057] First of all, this scheduling algorithm with fixed priority and cyclic priority can ensure that critical tasks are processed first. Because DMA4 always maintains the highest priority, high-priority tasks can be processed first to ensure that these critical data are transmitted in time. This is very important for application scenarios with high real-time requirements. For example, in a multimedia transmission system, high-priority audio and video data must be transmitted in real time to ensure the continuity and real-time nature of the transmission, thereby avoiding jamming or delays. This fixed high priority mechanism ensures the efficient execution of critical tasks and improves the reliability and responsiveness of the system.

[0058] Secondly, the cyclic priority part can effectively avoid resource monopoly problems and improve the concurrent processing capabilities of the system. In the fixed priority mechanism, in addition to the fixed high-priority channels, other channels take turns to obtain resource allocation opportunities, so that each channel can get processing opportunities within a period of time, avoiding the situation where low-priority channels cannot be processed for a long time. This design ensures that the system can handle other tasks fairly while processing high-priority tasks, improving resource utilization and overall processing efficiency.

[0059] Finally, this hybrid scheduling algorithm improves the flexibility and scalability of the system. As business needs increase, new DMA channels can be easily added and their priorities can be reasonably adjusted without affecting the overall performance of the system. The combination of fixed priority and cyclic priority makes resource allocation more flexible and more applicable. Newly added channels can be quickly integrated into the current system and perform data transmission tasks, ensuring a smooth transition of system expansion. When dealing with tasks of different priorities, this hybrid scheduling mechanism can respond flexibly, ensuring the priority processing of critical tasks, and making efficient use of system resources, improving the processing capacity and efficiency of the overall system. Therefore, this scheduling algorithm with coexistence of fixed priority and cyclic priority not only improves the reliability and performance of the existing system, but also provides strong support for future expansion and changes.

[0060] In arbitration, the reading and writing are completed using two ARBs respectively, so that the reading and writing operations of different channels can be performed simultaneously.

[0061] like Figure 3 The figure shows a scheduling mechanism for arbitrating read and write operations in a DMA (direct memory access) system. In this system, there are four DMA channels, labeled dma0, dma1, dma2, and dma3. The read and write operations of each channel are scheduled independently to more effectively manage memory resources and data transfer, avoid conflicts, and improve overall performance.

[0062] First of all, this scheduling mechanism of separate arbitration for read and write can significantly improve the concurrent processing capability of the system. By arbitrating the read operation and the write operation separately, different DMA channels can perform read and write tasks at the same time without interfering with each other. For example, while dma0 is performing a read operation, dma1 can perform a write operation, which greatly reduces the waiting time and improves the utilization rate of the channel and the overall data transmission efficiency. In some high-concurrency application environments, this mechanism can significantly improve the response speed and processing capability of the system.

[0063] Secondly, this scheduling mechanism can reduce data transmission conflicts. The traditional single arbitration mechanism is prone to bottlenecks when processing read and write requests, resulting in data transmission conflicts and delays. By arbitrating read and write operations separately, the system can manage and allocate resources more flexibly and efficiently to avoid conflicts. For example, in the read and write tasks of DMA2 and DMA3, read and write operations are executed in different time windows, reducing conflicts and waiting time caused by resource contention.

[0064] This scheduling mechanism can also support system expansion and flexible configuration. As system requirements increase and change, resources can be flexibly configured by adding DMA channels or adjusting read and write priorities. New channels can be easily integrated into the current arbitration mechanism without major modifications to the existing architecture. At the same time, this mechanism provides more possibilities for overall system resource management and optimization, ensuring system stability and reliability while maintaining high efficiency. This is especially important for various application scenarios with strong dynamic requirements.

[0065] This separate read-write arbitration not only improves the parallelism of data transmission and the utilization of system resources, reduces data transmission conflicts, but also enhances the flexibility and scalability of the system. Such a scheduling mechanism provides excellent performance and reliability support for complex systems and high-concurrency environments, allowing various tasks to be executed efficiently and stably. It is also closely linked to the two main node designs, which will enable DMA to perform at its best in high-concurrency operations.

[0066] In order to complete the above-mentioned polling method of read-write separation, the present invention adds a synchronous FIFO module inside the DMA channel to completely isolate the read and write (the depth of the FIFO can be modified). Figure 4 As shown in the figure, the DMA channel includes a read module, a synchronous FIFO module and a write module. When the DMA channel is working, it needs to wait for the arbitration module to arbitrate the channel first. When the read request is the highest priority, the read module occupies the bus of the top-level TILELINK read module and performs a read operation. After the read operation, the read data will be pushed into the synchronous FIFO module. When there is data in the synchronous FIFO module, the write operation request is turned on. The write operation and the read operation can be performed simultaneously and relatively independently. Similarly, when writing, an existing write operation request is required, and then wait for the arbitration module to arbitrate the channel. When the write request is the highest priority, the top-level TILELINK write module will then perform a write operation to write the data obtained in the FIFO to the corresponding address to complete a write, and switch to the priority of other channels.

[0067] There are two operation modes for DMA channels. The above is the secondary operation mode, and the other is the block operation mode, which is to read or write multiple data at the highest priority at one time. In the block operation mode, you need to wait for the arbitration module to arbitrate the channel first. When the read operation is the highest priority, the read module occupies the bus of the top-level TILELINK read module to perform the read operation. The read operation will perform multiple reads and continuously write data to the FIFO. At the same time, when the FIFO is not empty, a write operation request is triggered. During the write operation, an existing write operation request is required, and then wait for the arbitration module to arbitrate the channel. When the write request is the highest priority, the top-level TILELINK write module will then perform a write operation to write the data obtained in the FIFO to the corresponding address to complete multiple writes until all the write operations of the block operation are completed. The read operation and write operation occupy their own TILELINK buses respectively to complete the relevant operations.

[0068] This design is closely related to the design of the arbitrator, which can isolate the read and write operations and effectively reduce the coupling between the read and write operations. The depth of the synchronous FIFO module needs to be defined in more specific scenarios. Figure 4 The typical design is just listed in the figure. When the reading and writing are stalled, it may cause the reading card to freeze. At this time, it is necessary to increase the depth of the synchronous FIFO to increase the storage capacity inside the DMA.

[0069] Figure 5The data reading and writing process is presented in the form of a flowchart. The core is to achieve efficient request processing through priority management. In the data reading process, the system starts from the "start" node and then enters the waiting state to receive the source request. When the request arrives, the system will first check the read priority. If the channel has the highest read priority, the system will immediately perform the relevant data reading operation. This process will enter the waiting state after all read data are transferred. If the priority of the current request is not high enough, the system will not process the request temporarily, but continue to wait for the next highest priority to arrive. This priority system ensures that each channel will be polled, and each channel content will be responded to, reducing data congestion. This mechanism not only improves the system's response speed, but also effectively optimizes the order of data processing and resource allocation. At the same time, when an active request comes, the writing process will also be carried out. Compared with the reading process, the writing process needs to wait for the write request to arrive. When there is data in the FIFO, the write request is opened. When it is the highest write priority at this time, the system will immediately perform the relevant data writing operation. This process will enter the waiting state after all write data are transferred. If the priority of the current request is not high enough, the system will not process the request temporarily, but continue to wait for the next highest priority. When all read and write data are completed, the end process will be entered. This design strategy ensures that important read operations will not be delayed due to write operations when system resources are limited. By properly allocating priorities, read requests can usually be responded to faster than write requests. This is very suitable for various applications with high data concurrency, ensuring the efficiency of read tasks and the rationality of processing order.

[0070] The advantages of this design lie in many aspects of improvement. First, through the priority management mechanism, the response speed of key read requests is greatly improved, and low latency can be maintained even under high load conditions, thereby enhancing system performance and user experience. Secondly, the circular waiting strategy ensures that the system can continuously receive and process new requests, avoiding the blocking of other requests by the current operation, thereby improving the system throughput and resource utilization efficiency. In addition, this design has great flexibility, and the priority can be dynamically adjusted according to business needs, making the deployment in different situations simpler and more intuitive. In terms of system stability and reliability, clear logical steps and judgment conditions enable the system to operate in an orderly manner under abnormal circumstances, reducing concerns about data conflicts and consistency. In general, a system that integrates these design considerations can not only significantly improve processing efficiency, but also adapt well to different application requirements and achieve comprehensive performance and effectiveness.

[0071] In a specific implementation, the present application provides a computer storage medium and a corresponding data processing unit, wherein the computer storage medium can store a computer program, and when the computer program is executed by the data processing unit, the invention content of a high-performance DMA system architecture with read-write separation based on a TILELINK bus provided by the present invention and some or all of the steps in each embodiment can be provided. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0072] Those skilled in the art can clearly understand that the technical solutions in the embodiments of the present invention can be implemented by means of computer programs and their corresponding general hardware platforms. Based on such an understanding, the technical solutions in the embodiments of the present invention can be essentially or partly contributed to the prior art in the form of computer programs, i.e., software products, which can be stored in a storage medium and include several instructions for enabling a device including a data processing unit (which can be a personal computer, a server, a single-chip microcomputer, an MCU or a network device, etc.) to execute the methods described in various embodiments of the present invention or certain parts of the embodiments.

[0073] The present invention provides a high-performance DMA system architecture based on the TILELINK bus with read-write separation. There are many methods and ways to implement the technical solution. The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention. All components not specified in this embodiment can be implemented by existing technologies.

Claims

1. A high-performance DMA system architecture with read-write separation based on TILELINK bus, characterized in that: The DMA system is used in a SOC chip system based on a TILELINK bus, and includes: Two bus master nodes respectively connected to the TILELINK bus, namely a read master node and a write master node, for reading and writing data from the TILELINK bus respectively; The two bus master nodes are bidirectionally connected to a plurality of DMA channels through an arbiter ARB, respectively, and the arbiter ARB is used to manage read and write requests of all DMA channels; The other end of the DMA channel is connected to the configuration register block REG, which is used to configure the DMA channel to be in different working modes.

2. According to claim 1, a high-performance DMA system architecture with read-write separation based on TILELINK bus is characterized in that: There are two arbiters ARB, which are used to manage read requests and write requests respectively.

3. According to claim 1, a high-performance DMA system architecture with read-write separation based on TILELINK bus is characterized in that: The arbiter ARB manages the read and write requests by combining the polling priority and the fixed priority.

4. According to claim 3, a high-performance DMA system architecture with read-write separation based on TILELINK bus is characterized in that: The method of combining the polling priority and the fixed priority specifically includes: Step 1, setting a fixed priority, among all DMA channels, setting one or more DMA channels to a fixed priority, the fixed priority being a high priority, and other DMA channels being a low priority; Step 2, setting the loop priority, and setting the loop priority order for other DMA channels other than the DMA channels set to fixed priority; Step 3, the arbiter ARB responds preferentially to the read and write requests of the DMA channels with fixed priorities according to the order of fixed priorities; Step 4: After completing the read and write requests of the DMA channel with a fixed priority, respond to the read and write requests of the corresponding DMA channel in order of cyclic priority.

5. According to claim 1, a high-performance DMA system architecture with read-write separation based on TILELINK bus is characterized in that: The DMA channel includes: Read module, write module and synchronous FIFO module; among them, The synchronous FIFO module is used to store the data read by the read module during the storage read operation; The write module initiates a write operation request when there is data in the synchronous FIFO module.

6. A high-performance DMA system architecture with read-write separation based on TILELINK bus according to claim 5, characterized in that: The FIFO depth in the synchronous FIFO module is set to be modifiable.

7. A high-performance DMA system architecture with read-write separation based on TILELINK bus according to claim 1, characterized in that: The DMA channel includes a secondary operation mode and a block operation mode, and adopts a read-write separation method to perform read operations and write operations.

8. A high-performance DMA system architecture with read-write separation based on TILELINK bus according to claim 7, characterized in that: The secondary operation mode includes: When receiving a read request, the waiting arbitration module first arbitrates the DMA channel. When the read request is the highest priority, the read module occupies the bus of the top-level TILELINK read module and performs a read operation. After the read operation, the read data is pushed into the synchronous FIFO module. When there is data in the synchronous FIFO module, a write operation request is started. Write and read operations can be performed simultaneously and relatively independently; When a write request is received, it waits for the arbitration module to arbitrate the DMA channel. When the write request is the highest priority, the top-level TILELINK write module is occupied to perform a write operation, writing the data in the synchronous FIFO module to the corresponding address, completing a write operation.

9. The high-performance DMA system architecture with read-write separation based on TILELINK bus according to claim 7, characterized in that: The block operation mode includes: When receiving a read request, the waiting arbitration module first arbitrates the DMA channel. When the read request is the highest priority, the read module occupies the bus of the top-level TILELINK read module and performs a read operation. The read operation performs multiple reads and continuously writes data into the synchronous FIFO module. At the same time, when the synchronous FIFO module is not empty, a write request is triggered. When receiving a write request, it waits for the arbitration module to arbitrate the DMA channel. When the write request is the highest priority, the write module occupies the bus of the top-level TILELINK write module and performs a write operation to write the data in the synchronous FIFO module to the corresponding address. It completes multiple write operations until all write operations in the block operation mode are completed. Among them, the read operation and the write operation occupy their own TILELINK bus respectively to complete the related operations.

10. A high-performance DMA system architecture with read-write separation based on TILELINK bus according to claim 9, characterized in that: The method of using read-write separation to perform read operations and write operations includes: When a read request arrives, the priority of the read request is checked. If the highest priority of the DMA channel is the read request, the read operation is executed immediately, and after all read operations are completed, the state of waiting for all transfers to be completed is entered; if the priority of the read request in the current DMA channel is not the highest, the read request is not processed temporarily, and the next highest priority request is continued to be waited for; When writing and reading at the same time, you need to wait for the write request. When the synchronous FIFO module is not empty, the write request is turned on. When the write request in DMA has the highest priority at this time, the write operation is executed immediately. After all write operations are completed, the state of waiting for all transfers to be completed is entered. If the priority of the write request in the current DMA channel is not high enough, the request is not processed temporarily, and the next highest priority request is continued to be waited. It ends when all read and write requests are completed.

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