Complex instruction set verification method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a plural instruction set verification method and device, electronic equipment and a storage medium. The method comprises the steps that a target excitation signal is acquired; according to the target excitation signal, random data corresponding to the target excitation signal is determined, and the random data at least comprises input instruction data and operable input instruction data; determining a random calculation result corresponding to the random data according to the random data; and according to the random calculation result and the preset output result, determining a verification result corresponding to the target excitation signal. According to the embodiment of the invention, the verification platform is constructed by adopting the UVM verification methodology, and the chip complex instruction set is verified; the method aims at verifying the complex instruction set through all input instruction data in a sufficient random complex instruction set calculation process and judging the correctness of the complex instruction set in the chip, the verification efficiency of the instruction set in the chip is improved, and manpower and material resources are saved.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and more specifically, to a method, device, electronic device and storage medium for verifying a plurality of instruction sets. Background Art

[0002] With the progress of society, chip technology is developing more and more rapidly, and the requirements for chips are getting higher and higher. The more complex the chip, the more complicated the verification work is, resulting in verification work occupying most of the time in the entire chip design cycle.

[0003] The traditional verification method is to use the Verilog language to build a verification platform. After the verification platform is built, the chip's instruction set is verified. In actual applications, the chip can be used in different projects, and the instructions corresponding to the different functions of the chip need to be verified. This requires professionals to modify the verification code of the verification platform, which has poor portability and requires a lot of manpower and material resources for maintenance. Therefore, how to improve the efficiency of chip instruction verification is an urgent problem to be solved. Summary of the invention

[0004] Some embodiments of the present application aim to provide a method, device, electronic device and storage medium for verifying a complex instruction set. Through the technical solutions of the embodiments of the present application, a target excitation signal is obtained; random data corresponding to the target excitation signal is determined according to the target excitation signal, wherein the random data at least includes input instruction data and operations that can be performed in the input instruction; a random calculation result corresponding to the random data is determined according to the random data; a verification result corresponding to the target excitation signal is determined according to the random calculation result and a preset output result, wherein the preset output result is determined according to a pre-stored reference model. In the embodiments of the present application, a verification platform is constructed by adopting UVM verification methodology to verify the complex instruction set of a chip, aiming to verify the complex instruction set through all input instruction data in the calculation process of a sufficient random complex instruction set, and judge the correctness of the complex instruction set in the chip, thereby improving the verification efficiency of the instruction set in the chip and saving manpower and material resources.

[0005] In a first aspect, some embodiments of the present application provide a method for verifying a plurality of instruction sets, including:

[0006] Obtaining a target excitation signal;

[0007] Determine random data corresponding to the target excitation signal according to the target excitation signal, wherein the random data at least includes input instruction data and operable operations in the input instruction;

[0008] Determine, according to the random data, a random calculation result corresponding to the random data;

[0009] A verification result corresponding to the target excitation signal is determined according to the random calculation result and a preset output result, wherein the preset output result is determined according to a pre-stored reference model.

[0010] Some embodiments of the present application use the UVM verification methodology to build a verification platform to verify the chip's complex instruction set, aiming to verify the complex instruction set through all input instruction data in the calculation process of sufficient random complex instruction sets, and to determine the correctness of the complex instruction set in the chip, thereby improving the verification efficiency of the instruction set in the chip and saving manpower and material resources.

[0011] Optionally, determining a verification result corresponding to the target excitation signal according to the random calculation result and a preset output result includes:

[0012] If the random calculation result matches the preset output result, then according to the target stimulus signal, the verification of the instruction set to be verified is successful;

[0013] If the random calculation result does not match the preset output result, then according to the target stimulus signal, the verification of the instruction set to be verified fails.

[0014] Some embodiments of the present application compare the actually calculated random calculation results with the preset output results to judge the instruction set to be verified, thereby improving the accuracy of instruction set verification.

[0015] Optionally, the pre-stored reference model at least includes a corresponding relationship between an excitation signal and a preset output result.

[0016] Optionally, matching the random calculation result with the preset output result includes:

[0017] Generate a first array with the preset output result;

[0018] Generate a second array using the random calculation results;

[0019] The first array and the second array are output to a scoreboard, so that the scoreboard matches the first array and the second array.

[0020] Optionally, the method further comprises:

[0021] According to the target excitation signal and the random calculation result, a function coverage rate corresponding to the target excitation signal is determined.

[0022] Some embodiments of the present application count the coverage of all input data and ensure that the corresponding ranges of all input data are covered after sufficient verification.

[0023] In a second aspect, some embodiments of the present application provide a plurality of instruction set verification devices, including:

[0024] An acquisition module, used for acquiring a target excitation signal;

[0025] A generating module, configured to determine random data corresponding to the target excitation signal according to the target excitation signal, wherein the random data at least includes input instruction data and operable operations in the input instruction;

[0026] A calculation module, used to determine a random calculation result corresponding to the random data according to the random data;

[0027] A verification module is used to determine a verification result corresponding to the target excitation signal according to the random calculation result and a preset output result, wherein the preset output result is determined according to a pre-stored reference model.

[0028] Some embodiments of the present application use the UVM verification methodology to build a verification platform to verify the chip's complex instruction set, aiming to verify the complex instruction set through all input instruction data in the calculation process of sufficient random complex instruction sets, and to determine the correctness of the complex instruction set in the chip, thereby improving the verification efficiency of the instruction set in the chip and saving manpower and material resources.

[0029] Optionally, the verification module is used to:

[0030] Matching the random calculation result with the preset output result;

[0031] If the random calculation result matches the preset output result, then according to the target stimulus signal, the verification of the instruction set to be verified is successful;

[0032] If the random calculation result does not match the preset output result, then according to the target stimulus signal, the verification of the instruction set to be verified fails.

[0033] Some embodiments of the present application compare the actually calculated random calculation results with the preset output results to judge the instruction set to be verified, thereby improving the accuracy of instruction set verification.

[0034] Optionally, the pre-stored reference model at least includes a corresponding relationship between an excitation signal and a preset output result.

[0035] Optionally, the verification module is used to:

[0036] Generate a first array with the preset output result;

[0037] Generate a second array using the random calculation results;

[0038] The first array and the second array are output to a scoreboard, so that the scoreboard matches the first array and the second array.

[0039] Optionally, the verification module is used to:

[0040] According to the target excitation signal and the random calculation result, a function coverage rate corresponding to the target excitation signal is determined.

[0041] Some embodiments of the present application count the coverage of all input data and ensure that the corresponding ranges of all input data are covered after sufficient verification.

[0042] In a third aspect, some embodiments of the present application provide an electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein when the processor executes the program, the multiple instruction set verification method as described in any embodiment of the first aspect can be implemented.

[0043] In a fourth aspect, some embodiments of the present application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, can implement the multiple instruction set verification method as described in any embodiment of the first aspect.

[0044] In a fifth aspect, some embodiments of the present application provide a computer program product, comprising a computer program, wherein the computer program, when executed by a processor, can implement the multiple instruction set verification method as described in any embodiment of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of some embodiments of the present application, the drawings required for use in some embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0046] Figure 1 A flowchart of a method for verifying a plurality of instruction sets provided in an embodiment of the present application;

[0047] Figure 2 A flowchart of another method for verifying a plurality of instruction sets provided in an embodiment of the present application;

[0048] Figure 3 A flowchart of another method for verifying a plurality of instruction sets provided in an embodiment of the present application;

[0049] Figure 4A schematic diagram of the structure of a multiple instruction set verification device provided in an embodiment of the present application;

[0050] Figure 5 A schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] The technical solutions in some embodiments of the present application will be described below in conjunction with the drawings in some embodiments of the present application.

[0052] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0053] With the progress of society, chip technology is developing more and more rapidly, and the requirements for chips are getting higher and higher. The more complex the chip, the more complicated the verification work is, resulting in verification work occupying most of the time in the entire chip design cycle.

[0054] The traditional verification method is to use the Verilog language to build a verification platform. After the verification platform is built, the instruction set of the chip is verified. In practical applications, the chip can be applied to different projects, and the instructions corresponding to the different functions of the chip need to be verified. This requires professionals to modify the verification code of the verification platform, which has poor portability and requires a lot of manpower and material resources for maintenance. Therefore, how to improve the efficiency of chip instruction verification is an urgent problem to be solved. In view of this, some embodiments of the present application provide a complex instruction set verification method, which includes obtaining a target excitation signal; determining random data corresponding to the target excitation signal according to the target excitation signal, Among them, the random data at least includes input instruction data and operations that can be performed in the input instructions; according to the random data, a random calculation result corresponding to the random data is determined; according to the random calculation result and the preset output result, a verification result corresponding to the target excitation signal is determined, wherein the preset output result is determined based on a pre-stored reference model. In the embodiment of the present application, a verification platform is constructed by adopting the UVM verification methodology to verify the chip complex instruction set, aiming to verify the complex instruction set through all input instruction data in the calculation process of sufficient random complex instruction sets, and judge the correctness of the complex instruction set in the chip, thereby improving the verification efficiency of the instruction set in the chip and saving manpower and material resources.

[0055] like Figure 1 As shown, an embodiment of the present application provides a method for verifying a plurality of instruction sets, the method comprising:

[0056] S101, obtaining a target excitation signal;

[0057] Specifically, a simulation platform is installed on the terminal device, which is connected to the chip to be verified through the simulation platform. According to project requirements, a target excitation signal of the chip to be verified is set, wherein the target excitation signal can be a digital signal, such as a square wave signal, or other data to be tested.

[0058] S102, determining random data corresponding to the target excitation signal according to the target excitation signal, wherein the random data at least includes input instruction data and operable operations in the input instruction;

[0059] Specifically, the terminal device searches for random data corresponding to the target excitation signal in a pre-stored instruction set based on the input target excitation signal, and the random data includes input instruction data and operations that can be performed in the input instruction, wherein the operations that can be performed in the input instruction include at least saturation and rounding.

[0060] Exemplarily, if the input target excitation signal is a digital signal, the input instruction data corresponding to the digital signal is determined according to the digital signal, and the random number of times the input instruction data is generated is set.

[0061] S103, determining a random calculation result corresponding to the random data according to the random data;

[0062] Specifically, the terminal device transmits the random data to the design to be tested, and obtains a random calculation result corresponding to the random data by executing the design to be tested.

[0063] S104. Determine a verification result corresponding to the target excitation signal according to the random calculation result and the preset output result, wherein the preset output result is determined according to a pre-stored reference model.

[0064] Specifically, a reference model is pre-stored on the terminal device, and the excitation signal is input into the reference model to obtain a preset output result. After obtaining the random calculation result, the terminal device compares the random calculation result with the preset output result, and determines the verification result corresponding to the target excitation signal based on the comparison result.

[0065] Some embodiments of the present application construct a verification platform by adopting UVM (Universal Verification Methodology) verification methodology to verify the chip's complex instruction set, aiming to verify the complex instruction set through all input instruction data in the calculation process of sufficient random complex instruction sets, and to determine the correctness of the complex instruction set in the chip, thereby improving the verification efficiency of the instruction set in the chip and saving manpower and material resources.

[0066] Another embodiment of the present application further supplements the multiple instruction set verification method provided in the above embodiment.

[0067] Optionally, determining a verification result corresponding to a target excitation signal according to a random calculation result and a preset output result includes:

[0068] Matching the random calculation result with the preset output result;

[0069] If the random calculation result matches the preset output result, the verification of the instruction set to be verified is successful according to the target stimulus signal;

[0070] If the random calculation result does not match the preset output result, the verification of the instruction set to be verified fails according to the target stimulus signal.

[0071] Some embodiments of the present application compare the actually calculated random calculation results with the preset output results to judge the instruction set to be verified, thereby improving the accuracy of instruction set verification.

[0072] Optionally, the pre-stored reference model at least includes a corresponding relationship between an excitation signal and a preset output result.

[0073] Optionally, matching the random calculation result with the preset output result includes:

[0074] Generate a first array with the preset output result;

[0075] Generate a second array using the random calculation results;

[0076] The first array and the second array are output to a scoreboard, so that the scoreboard matches the first array and the second array.

[0077] Specifically, the comparison function is performed by the scoreboard. The comparison method is to give the output results, inputs and random calculation results in the reference model to the scoreboard for data comparison. By giving the two parts of data to the array, the array is compared.

[0078] Optionally, the method further comprises:

[0079] According to the target stimulus signal and the random calculation result, the functional coverage corresponding to the target stimulus signal is determined.

[0080] Some embodiments of the present application count the coverage of all input data and ensure that the corresponding ranges of all input data are covered after sufficient verification.

[0081] Figure 2 A flowchart of another method for verifying a plurality of instruction sets provided in an embodiment of the present application is shown as follows: Figure 2As shown, the embodiment of the present application provides a complex instruction set verification method based on UVM, which verifies the complex instruction set by building a verification platform using UVM verification methodology, aiming to verify the correctness of the complex instruction set calculation through all input data in the calculation process of the complex instruction set by fully randomizing it, and ensure that the data within the 32-bit range is randomized to ensure the adequacy of the verification through functional coverage. The verification method is simple, highly reusable, and greatly improves the verification efficiency.

[0082] A verification platform is installed on the terminal device in the embodiment of the present application, and the verification platform includes at least the following modules: 1. DUT-design under test, 2. interface-interface, 3. hdl-top, hvl-top-verification top layer, 4. testcase-test case, 5. sequence-stimulus, 6. virtual-virtual stimulus, 7. sequencer-stimulus generator, 8. virtualsequencer-virtual stimulus generator, 9. reference model-reference model, 10. scoreboard-scoreboard, 11. cov-functional coverage, 12. driver-driver, 13. monitor-monitor, 14. env-verification environment, 15. agent transaction, 16. seq_item-randomly generate data according to the input used for calculation of the instruction set, 17. agent_config-parameter configuration;

[0083] in:

[0084] hdl-top - Verify the top level, used to instantiate the driver, monitor, and interface and generate clock and reset signals.

[0085] hvl-top - Verification top level, used to launch the entire verification bench via run_test.

[0086] Interface-Interface, used to verify the communication between the platform and the design under test DUT.

[0087] testcase-test case, used to select the appropriate virtual stimulus generator virtual sequence to implement a function. Each test case represents the implementation of a complex instruction.

[0088] sequence-stimulus, used to generate instruction types and random times.

[0089] Virtual sequence-virtual stimulus is used to collect the stimulus sequence required for a random instruction to implement hierarchical verification and make the platform more eye-catching.

[0090] Sequencer-stimulus generator, used to generate stimuli to send random data generated by seq_item (randomly generate data based on the input used in the instruction set calculation) to the driver driver.

[0091] virtual sequencer-virtual stimulus generator, used to organize and manage virtual sequence virtual stimulus generators.

[0092] Rreference model-reference model, used to perform the same function as the design under test (DUT).

[0093] scoreboard-The scoreboard is used to compare the calculation results of the reference model with the data obtained from the monitor, and judge whether the design DUT under test is correct based on the comparison results.

[0094] cov-functional coverage, which is used to count the coverage of all input data and ensure that the corresponding ranges of all input data are covered after sufficient verification.

[0095] driver-driver, used to apply stimulus to the design under test DUT through the interface based on random input data from seq_item (randomly generates data based on input used in instruction set calculations) received from the stimulus sequencer.

[0096] monitor-monitor, used to collect port data of the design under test DUT through the interface and send it to the scoreboard.

[0097] env-verification environment, used to instantiate the transaction agent, reference model, scoreboard and connect the monitor monitor and scoreboard scoreboard as well as the virtual stimulus generator virtualsequencer and sequencer.

[0098] agent-transaction base, used to instantiate driver driver, monitor monitor and sequencer stimulus, used to connect the virtual interface seq_item_port in the driver driver to the output interface seq_item_export in the stimulus sequencer.

[0099] agent_config-parameter configuration, used to standardize the parameters used in all verification platforms, such as the number of instructions generated for each use case.

[0100] Figure 3A flowchart of another method for verifying a plurality of instruction sets provided in an embodiment of the present application is shown as follows: Figure 3 As shown, the process of implementing the specific instruction calculation function provided by this application includes:

[0101] Step 1: Select the stimulus sequence, i.e. the target stimulus signal, on the simulation platform according to the project requirements. The target stimulus signal can be a digital signal or data, etc. The stimulus sequence random seq_item (randomly generates data based on the input used for instruction set calculation) and then all the contents used in the random instruction calculation include: input data and operations that can be performed in the input instruction, such as saturation, rounding, etc.

[0102] Step 2: The driver continuously requests seq_item from the sequencer stimulus generator until it obtains seq_item, and then sends it to the design DUT under test for calculation.

[0103] Step 3: The monitor collects the input data and output data of the DUT and sends the collected input data and output data to the scoreboard.

[0104] Step 4: The scoreboard calls the reference model to obtain the preset output result, performs calculations based on the input data obtained from the monitor, and compares the calculated result, i.e., the random calculation result, with the preset output result to obtain the verification result.

[0105] Step 5: If the result is correct, the verification is successful. If it is wrong, the verification fails and needs to be recalculated.

[0106] It should be noted that each implementable method in this embodiment may be implemented separately, or may be implemented in combination in any combination without conflict, and this application is not limited thereto.

[0107] Another embodiment of the present application provides a plurality of instruction set verification apparatus, which is used to execute the plurality of instruction set verification method provided by the above embodiment.

[0108] like Figure 4 , which is a schematic diagram of the structure of a complex instruction set verification device provided in an embodiment of the present application. The complex instruction set verification device includes an acquisition module 401, a generation module 402, a calculation module 403 and a verification module 404, wherein:

[0109] The acquisition module 401 is used to acquire a target excitation signal;

[0110] The generating module 402 is used to determine random data corresponding to the target excitation signal according to the target excitation signal, wherein the random data at least includes input instruction data and operable operations in the input instruction;

[0111] The calculation module 403 is used to determine the random calculation result corresponding to the random data according to the random data;

[0112] The verification module 404 is used to determine a verification result corresponding to the target excitation signal according to the random calculation result and the preset output result, wherein the preset output result is determined according to a pre-stored reference model.

[0113] Regarding the device in this embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0114] Some embodiments of the present application use the UVM verification methodology to build a verification platform to verify the chip's complex instruction set, aiming to verify the complex instruction set through all input instruction data in the calculation process of sufficient random complex instruction sets, and to determine the correctness of the complex instruction set in the chip, thereby improving the verification efficiency of the instruction set in the chip and saving manpower and material resources.

[0115] Another embodiment of the present application further supplements the description of the multiple instruction set verification device provided in the above embodiment.

[0116] Optionally, a verification module is used to:

[0117] Matching the random calculation result with the preset output result;

[0118] If the random calculation result matches the preset output result, the verification of the instruction set to be verified is successful according to the target stimulus signal;

[0119] If the random calculation result does not match the preset output result, the verification of the instruction set to be verified fails according to the target stimulus signal.

[0120] Some embodiments of the present application compare the actually calculated random calculation results with the preset output results to judge the instruction set to be verified, thereby improving the accuracy of instruction set verification.

[0121] Optionally, the pre-stored reference model at least includes a corresponding relationship between an excitation signal and a preset output result.

[0122] Optionally, a verification module is used to:

[0123] Generate a first array with the preset output result;

[0124] Generate a second array using the random calculation results;

[0125] The first array and the second array are output to a scoreboard, so that the scoreboard matches the first array and the second array.

[0126] Optionally, a verification module is used to:

[0127] According to the target stimulus signal and the random calculation result, the functional coverage corresponding to the target stimulus signal is determined.

[0128] Some embodiments of the present application count the coverage of all input data and ensure that the corresponding ranges of all input data are covered after sufficient verification.

[0129] Regarding the device in this embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0130] It should be noted that each implementable method in this embodiment may be implemented separately, or may be implemented in combination in any combination without conflict, and this application is not limited thereto.

[0131] An embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the operation of the method corresponding to any embodiment of the multiple instruction set verification method provided in the above embodiments can be implemented.

[0132] An embodiment of the present application also provides a computer program product, which includes a computer program, wherein when the computer program is executed by a processor, it can implement the operations of the method corresponding to any embodiment of the multiple instruction set verification method provided in the above embodiments.

[0133] like Figure 5 As shown, some embodiments of the present application provide an electronic device 500, which includes: a memory 510, a processor 520, and a computer program stored in the memory 510 and executable on the processor 520, wherein the processor 520 can implement a method of any embodiment included in the above-mentioned multiple instruction set verification method when reading the program from the memory 510 through a bus 530 and executing the program.

[0134] Processor 520 can process digital signals and can include various computing structures, such as complex instruction set computer structure, reduced instruction set computer structure, or a structure that implements a combination of multiple instruction sets. In some examples, processor 520 can be a microprocessor.

[0135] The memory 510 may be used to store instructions executed by the processor 520 or data related to the execution of instructions. These instructions and / or data may include codes for implementing some or all functions of one or more modules described in the embodiments of the present application. The processor 520 of the disclosed embodiment may be used to execute instructions in the memory 510 to implement the method shown above. The memory 510 includes a dynamic random access memory, a static random access memory, a flash memory, an optical memory, or other memory known to those skilled in the art.

[0136] The above are only embodiments of the present application and are not intended to limit the scope of protection of the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0137] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0138] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

Claims

1. A method for verifying a plurality of instruction sets, characterized in that: The method comprises: Obtaining a target excitation signal; Determine random data corresponding to the target excitation signal according to the target excitation signal, wherein the random data at least includes input instruction data and operable operations in the input instruction; Determine, according to the random data, a random calculation result corresponding to the random data; A verification result corresponding to the target excitation signal is determined according to the random calculation result and a preset output result, wherein the preset output result is determined according to a pre-stored reference model.

2. The multiple instruction set verification method according to claim 1, characterized in that: The step of determining a verification result corresponding to the target excitation signal according to the random calculation result and the preset output result includes: Matching the random calculation result with the preset output result; If the random calculation result matches the preset output result, then according to the target stimulus signal, the verification of the instruction set to be verified is successful; If the random calculation result does not match the preset output result, then according to the target stimulus signal, the verification of the instruction set to be verified fails.

3. The multiple instruction set verification method according to claim 1, characterized in that: The pre-stored reference model at least includes a corresponding relationship between an excitation signal and a preset output result.

4. The multiple instruction set verification method according to claim 2, characterized in that: The matching of the random calculation result and the preset output result includes: Generate a first array with the preset output result; Generate a second array using the random calculation results; The first array and the second array are output to a scoreboard, so that the scoreboard matches the first array and the second array.

5. The multiple instruction set verification method according to claim 1, characterized in that: The method further comprises: According to the target excitation signal and the random calculation result, a function coverage rate corresponding to the target excitation signal is determined.

6. A multiple instruction set verification device, characterized in that: The device comprises: An acquisition module, used for acquiring a target excitation signal; A generating module, configured to determine random data corresponding to the target excitation signal according to the target excitation signal, wherein the random data at least includes input instruction data and operable operations in the input instruction; A calculation module, used to determine a random calculation result corresponding to the random data according to the random data; A verification module is used to determine a verification result corresponding to the target excitation signal according to the random calculation result and a preset output result, wherein the preset output result is determined according to a pre-stored reference model.

7. The multiple instruction set verification device according to claim 6, characterized in that: The verification module is used to: If the random calculation result matches the preset output result, then according to the target stimulus signal, the verification of the instruction set to be verified is successful; If the random calculation result does not match the preset output result, then according to the target stimulus signal, the verification of the instruction set to be verified fails.

8. The multiple instruction set verification device according to claim 1, characterized in that: The pre-stored reference model at least includes a corresponding relationship between an excitation signal and a preset output result.

9. An electronic device, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor can implement the multiple instruction set verification method as claimed in any one of claims 1 to 5 when executing the program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein when the program is executed by a processor, the method for verifying a plurality of instruction sets described in any one of claims 1 to 5 can be implemented.

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