Signal measurement method, multiple power consumption measurement method and related device

Abstract

The embodiment of the invention provides a signal measurement method, a plurality of power consumption measurement methods and related devices, and the method comprises the steps: obtaining the power consumption simulation data and overturning simulation data of a to-be-tested functional module in a plurality of pre-silicon test scenes; according to the power consumption simulation data of each pre-silicon test scene, determining the simulation dynamic power consumption of each pre-silicon test scene, and according to the flip simulation data of each pre-silicon test scene, determining the flip rate of a plurality of flip signals of the function module in each pre-silicon test scene; performing fitting processing on the simulation dynamic power consumption of each pre-silicon test scene and the overturning rate of the plurality of overturning signals in each pre-silicon test scene based on a linear relation between the dynamic power consumption and signal overturning to obtain overturning weights of the plurality of overturning signals of the functional module; the overturning weight is used for determining the post-silicon dynamic power consumption of the functional module. According to the method and the device, the post-silicon dynamic power consumption can be calculated by using an estimated value with a relatively large error when the post-silicon dynamic power consumption is calculated, so that the calculation precision of the post-silicon dynamic power consumption is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and specifically to a signal measurement method, multiple power consumption measurement methods, and related devices. Background Art

[0002] As the complexity of the circuits in integrated circuit products increases, the power consumption of the chip is also increasing. The increase in chip power consumption will lead to an increase in chip heat generation and a decrease in reliability. The existing low-power solution to reduce chip power consumption requires the chip to have the function of real-time and accurate monitoring of the current power consumption of the chip. Therefore, how to improve the accuracy of power consumption calculation has become a problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0003] In view of this, embodiments of the present application provide a signal measurement method, multiple power consumption measurement methods and related devices to improve the accuracy of power consumption calculation.

[0004] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0005] In a first aspect, an embodiment of the present application provides a signal measurement method, including:

[0006] Obtain power consumption simulation data and flip simulation data of the functional modules of the design under test in multiple pre-silicon test scenarios;

[0007] Determine the simulated dynamic power consumption of each pre-silicon test scenario according to the power consumption simulation data of each pre-silicon test scenario, and determine the flip rate of multiple flip signals of the functional module in each pre-silicon test scenario according to the flip simulation data of each pre-silicon test scenario;

[0008] Based on the linear relationship between dynamic power consumption and signal flipping, the simulated dynamic power consumption of each pre-silicon test scenario and the flipping rate of the multiple flipping signals in each pre-silicon test scenario are fitted to obtain the flipping weights of the multiple flipping signals of the functional module; the flipping weights are used to determine the post-silicon dynamic power consumption of the functional module.

[0009] In a second aspect, an embodiment of the present application provides a dynamic power consumption measurement method, including:

[0010] When the circuit under test is in post-silicon operation, obtaining post-silicon flip rates of multiple flip signals of functional modules of the circuit under test;

[0011] The post-silicon dynamic power consumption of the circuit under test is determined according to the post-silicon flip rate of each flip signal of the functional module and the flip weight of each flip signal of the functional module; wherein the flip weight of each flip signal of the functional module is determined based on the signal measurement method as described above.

[0012] In a third aspect, an embodiment of the present application provides a signal measurement method, including:

[0013] Obtain power consumption simulation data and flip simulation data of the design under test in multiple idle state scenarios;

[0014] Determine the simulated background power consumption of the design under test in each idle state scenario and the clock frequencies of multiple clock signals of the design under test in each pre-silicon test scenario according to the power consumption simulation data of each idle state scenario;

[0015] Based on the linear relationship between background power consumption and clock frequency, the simulated background power consumption of each idle state scenario and the clock frequencies of the multiple clock signals in each idle state scenario are fitted to obtain clock weights of the multiple clock signals; the clock weights are used to determine the post-silicon background power consumption of the design to be tested.

[0016] In a fourth aspect, an embodiment of the present application provides a background power consumption measurement method, including:

[0017] When the circuit under test is running in post-silicon, obtaining post-silicon clock frequencies of a plurality of clock signals of the circuit under test;

[0018] The post-silicon background power consumption of the circuit under test is determined according to the post-silicon clock frequency of each clock signal and the clock weight of each clock signal; wherein the clock weight of each clock signal is obtained based on the signal measurement method as described above.

[0019] In a fifth aspect, an embodiment of the present application provides a method for measuring operating power consumption, including:

[0020] Obtaining the post-silicon dynamic power consumption and the post-silicon background power consumption of the circuit under test during post-silicon operation; the post-silicon dynamic power consumption is obtained based on the dynamic power consumption measurement method described above, and the post-silicon background power consumption is obtained based on the background power consumption measurement method described above;

[0021] The operating power consumption of the circuit to be tested is determined according to the post-silicon dynamic power consumption and the post-silicon background power consumption.

[0022] In a sixth aspect, an embodiment of the present application provides a signal measuring device, including:

[0023] A first simulation data acquisition module is used to acquire power consumption simulation data and flip simulation data of a functional module of the design to be tested in multiple pre-silicon test scenarios;

[0024] A first simulation data processing module, used to determine the simulated dynamic power consumption of each pre-silicon test scenario according to the power consumption simulation data of each pre-silicon test scenario, and to determine the flip rate of multiple flip signals of the functional module in each pre-silicon test scenario according to the flip simulation data of each pre-silicon test scenario;

[0025] The flip weight calculation module is used to fit the simulated dynamic power consumption of each pre-silicon test scenario and the flip rate of the multiple flip signals in each pre-silicon test scenario based on the linear relationship between dynamic power consumption and signal flip, so as to obtain the flip weights of the multiple flip signals of the functional module; the flip weights are used to determine the post-silicon dynamic power consumption of the functional module.

[0026] In a seventh aspect, an embodiment of the present application provides a signal measuring device, including:

[0027] A second simulation data acquisition module is used to acquire power consumption simulation data of the design to be tested in multiple idle state scenarios;

[0028] A second simulation data processing module, used to determine the simulated background power consumption of the design to be tested in each idle state scenario and the clock frequencies of multiple clock signals of the design to be tested in each pre-silicon test scenario according to the power consumption simulation data of each idle state scenario;

[0029] A clock weight calculation module is used to fit the simulated background power consumption of each idle state scenario and the clock frequency of the multiple clock signals in each idle state scenario based on the linear relationship between background power consumption and clock frequency, so as to obtain clock weights of the multiple clock signals; the clock weights are used to determine the post-silicon background power consumption of the design to be tested.

[0030] In an eighth aspect, an embodiment of the present application provides a dynamic power consumption measurement device, including:

[0031] A flip rate acquisition module, used for acquiring post-silicon flip rates of multiple flip signals of a functional module of the circuit under test when the circuit under test is running post-silicon;

[0032] A post-silicon dynamic power consumption calculation module is used to determine the post-silicon dynamic power consumption of the circuit under test according to the post-silicon flip rate of each flip signal of the functional module and the flip weight of each flip signal of the functional module; wherein the flip weight of each flip signal of the functional module is determined based on the signal measurement method as described above.

[0033] In a ninth aspect, an embodiment of the present application provides a background power consumption measurement device, including:

[0034] A clock frequency acquisition module, used for acquiring post-silicon clock frequencies of multiple clock signals of the circuit under test when the circuit under test is running post-silicon;

[0035] The post-silicon background power consumption calculation module is used to determine the post-silicon background power consumption of the circuit under test according to the post-silicon clock frequency of each clock signal and the clock weight of each clock signal; wherein the clock weight of each clock signal is obtained based on the signal measurement method as described above.

[0036] In a tenth aspect, an embodiment of the present application provides an operating power consumption measurement device, including:

[0037] The dynamic power consumption measurement device as described above is used to obtain the post-silicon dynamic power consumption of the circuit under test during post-silicon operation;

[0038] The background power consumption measuring device as described above is used to obtain the post-silicon background power consumption of the circuit under test during post-silicon operation;

[0039] The operating power consumption calculation module is used to determine the operating power consumption of the circuit to be tested according to the post-silicon dynamic power consumption and the post-silicon background power consumption.

[0040] In the eleventh aspect, an embodiment of the present application provides a computing device, including a memory and a processor, the memory storing computer instructions, the processor calling the computer instructions stored in the memory to execute the signal measurement method as described above, and / or the dynamic power consumption measurement method as described above, and / or the signal measurement method as described above, and / or the background power consumption measurement method as described above, and / or the operating power consumption measurement method as described above.

[0041] In a twelfth aspect, an embodiment of the present application provides a storage medium, wherein the storage medium stores a design program of a chip, and when the design program is executed, the signal measurement method as described above is implemented, and / or the dynamic power consumption measurement method as described above is implemented, and / or the signal measurement method as described above is implemented, and / or the background power consumption measurement method as described above is implemented, and / or the operating power consumption measurement method as described above is implemented.

[0042] In a thirteenth aspect, an embodiment of the present application provides a computer program product, which, when executed, implements the signal measurement method as described above, and / or the dynamic power consumption measurement method as described above, and / or the signal measurement method as described above, and / or the background power consumption measurement method as described above, and / or the operating power consumption measurement method as described above.

[0043] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0044] The signal measurement method provided by the embodiment of the present invention obtains power consumption simulation data and flip simulation data of a functional module to be tested in multiple pre-silicon test scenarios; determines the simulated dynamic power consumption of each pre-silicon test scenario according to the power consumption simulation data of each pre-silicon test scenario, and determines the flip rate of multiple flip signals of the functional module in each pre-silicon test scenario according to the flip simulation data of each pre-silicon test scenario; based on the linear relationship between dynamic power consumption and signal flipping, the simulated dynamic power consumption of each pre-silicon test scenario and the flip rate of the multiple flip signals in each pre-silicon test scenario are fitted to obtain the flip weights of the multiple flip signals of the functional module; the flip weights are used to determine the post-silicon dynamic power consumption of the functional module.

[0045] It can be seen that the technical solution provided by the embodiment of the present invention can accurately obtain the simulated dynamic power consumption of the design to be tested during the simulation process, and the flip rate of multiple flip signals, and then calculate the flip weight related to the flip rate of the flip signal based on the linear relationship between the dynamic power consumption of the functional module and the signal flip. Since the simulated dynamic power consumption used when obtaining the flip weight is accurate, when the design to be tested is used after silicon, the post-silicon dynamic power consumption of the functional module calculated by the flip weight and the accurately measured flip rate of the flip signal, and the post-silicon dynamic power consumption of the design to be tested are also determined to be accurate values. This avoids using an estimated value with a large error to calculate the post-silicon dynamic power consumption when calculating the post-silicon dynamic power consumption, thereby improving the calculation accuracy of the post-silicon dynamic power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0047] Figure 1 A first flow chart of a signal measurement method provided in an embodiment of the present application;

[0048] Figure 2 A partial structural schematic diagram of a design to be tested is provided for an embodiment of the present application;

[0049] Figure 3 A second flow chart of the signal measurement method provided in an embodiment of the present application;

[0050] Figure 4 A third flow chart of the signal measurement method provided in an embodiment of the present application;

[0051] Figure 5A schematic diagram of a flow chart of a method for obtaining dynamic power consumption provided in an embodiment of the present application;

[0052] Figure 6 A schematic diagram of a first process flow of a background signal measurement method provided in an embodiment of the present application;

[0053] Figure 7 A second flow chart of the background signal measurement method provided in an embodiment of the present application;

[0054] Figure 8 A third flow chart of the background signal measurement method provided in an embodiment of the present application;

[0055] Fig. 9 A schematic diagram of a first process flow of a method for obtaining background power consumption provided in an embodiment of the present application;

[0056] Fig.10 A second flow chart of the background power consumption acquisition method provided in an embodiment of the present application;

[0057] Fig.11 A flowchart of a method for obtaining operating power consumption provided in an embodiment of the present application;

[0058] Fig.12 A schematic diagram of the structure of a signal measuring device provided in an embodiment of the present application;

[0059] Fig.13 A schematic diagram of the structure of another signal measuring device provided in an embodiment of the present application;

[0060] Fig.14 A schematic diagram of the structure of the operating power consumption acquisition device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0061] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0062] As the chip scale expands, the power consumption of the chip is also increasing. Excessive power consumption of the chip will lead to increased heat generation and decreased reliability. Therefore, whether the power consumption of the chip is reasonable is an important consideration in integrated circuit design. Chip design not only pursues high performance and small area, but also has comprehensive requirements for performance, area, and power consumption. Low-power design that reduces the power consumption of the internal chip has become an important technology in chip design.

[0063] One low-power solution is to monitor the current power consumption of the chip in real time and adjust the frequency and voltage of the chip according to the current power consumption of the chip. Specifically, TDP (Thermal Design Power) is the thermal design power consumption index of the chip, which is usually used to identify how much heat the chip is designed to dissipate to ensure that it can work stably at the nominal frequency. Without exceeding TDP, the maximum operating frequency and maximum operating voltage need to be set to achieve optimal performance. Otherwise, the clock frequency and voltage can only be set by retaining a large margin, which will cause performance loss. When adjusting the frequency and voltage of the chip, it is usually combined with AVFS (Adaptive Voltage Frequency Scaling) or DVFS (Dynamic Voltage Frequency Scaling) technology. This low-power solution requires that the chip has the function of accurately monitoring the current power consumption of the chip in real time.

[0064] The power consumption of a chip usually consists of dynamic power consumption and background power consumption. Dynamic power consumption consists of switch power consumption and short-circuit power consumption. Background power consumption is exponentially related to voltage and temperature.

[0065] Dynamic power consumption accounts for a large proportion of chip power consumption, but as the process changes, background power consumption also accounts for a large proportion. Since the overall background power consumption is exponentially related to voltage and temperature, and the technology for measuring voltage and temperature is simple and highly accurate, the background power consumption can be accurately calculated by real-time monitoring of temperature and voltage.

[0066] There are many factors that affect the dynamic power consumption of a chip, including chip voltage, chip manufacturing process, chip circuit scale, clock frequency, signal flip rate, circuit working status, etc., which will affect the dynamic power consumption of the chip. Therefore, estimating dynamic power consumption is relatively difficult and requires the establishment of a reasonable mathematical model.

[0067] Furthermore, the dynamic power consumption of the chip is mainly composed of the flip power consumption and short circuit power consumption in the chip. The calculation formula of flip power consumption is: switch =C eff ×V 2 ×F. The formula for calculating short-circuit power consumption is: The calculation formula of dynamic power consumption is the sum of flip power consumption and short-circuit power consumption, that is, P dyn =P switch +P short Among them, C eff is the effective capacitance, V is the voltage, F is the frequency, t scis the short circuit time, V is the power supply voltage, V t is the transistor threshold voltage, and τ is the transistor gain factor.

[0068] After further simplifying the calculation formula of dynamic power consumption, we can get the formula: P dyn =(C m ×V+Cx)×V 2 ×F, where C b =C eff ,

[0069] In the above formula, information such as effective capacitance and short-circuit time cannot be measured in the chip, so they can be combined into two parameters, Cm and Cb, which can be obtained through post-silicon testing. The voltage value V of the chip can be directly obtained by directly measuring the voltage of the circuit. The frequency F is proportional to the dynamic power consumption, so as long as the frequency F can be accurately obtained, the dynamic power consumption can be estimated more accurately.

[0070] In one power estimation method, the frequency F is directly set to the clock frequency in the chip, which will cause a large error because the frequency F represents the flip rate of the circuit. The clock frequency is only an independent variable that is positively correlated with the flip rate of the circuit and is not sufficient to accurately reflect the flip rate of the circuit. The switching activities in the chip are not only the jumps of the clock signal, but also include the signal flips of many logic circuits. Therefore, if it is simply set to the clock frequency, the signal flips of the logic circuit cannot be calculated, resulting in a large error in the estimated power consumption value.

[0071] To solve the above problems, the embodiment of the present application provides a signal measurement method, which obtains the flip rate of multiple flip signals of each functional module in the chip to accurately calculate the dynamic power consumption. As an optional implementation, Figure 1 FIG. 1 is a flow chart of a signal measurement method provided in an embodiment of the present application. Figure 1 As shown, the signal measurement method provided in the embodiment of the present application includes the following steps.

[0072] Step S11: obtaining power consumption simulation data and flip simulation data of the functional module of the design to be tested in multiple pre-silicon test scenarios.

[0073] It should be noted that the design to be tested is the program code or digital circuit obtained by the above-mentioned chip during the design stage. The pre-silicon is the time node before the actual sample of the design to be tested is obtained during the production and manufacturing process of the chip. The pre-silicon test scenario is the test scenario used in the pre-silicon simulation of the design to be tested. Correspondingly, the post-silicon is the time node after the actual sample of the design to be tested is obtained during the production and manufacturing process of the chip.

[0074] In an optional implementation, the functional modules are modules divided according to the logic functions in the design to be tested. In a complete design to be tested, a flip signal that flips can only act on a single logic function. Therefore, the design to be tested needs to be divided into multiple functional modules according to the logic functions, and the flip rate of the flip signal in each functional module is obtained to calculate the dynamic power consumption of each functional module. Finally, the dynamic power consumption of all functional modules is summarized to obtain the dynamic power consumption of the design to be tested.

[0075] The flip simulation data includes multiple state data of the design to be tested during the test, and these data are used to calculate the relevant information of the design to be tested in subsequent steps. Specifically, in an optional implementation, the simulation data includes: the flip counts of multiple flip signals of the functional modules of the design to be tested in each pre-silicon test scenario. The flip counts are used to subsequently calculate the flip rate of the flip signal in each pre-silicon test scenario.

[0076] For the design under test, the flip rate of the flip signal can be obtained from the waveform fsdb (Full-Scale Digital Bandwidth) file during the simulation process. However, for the circuit under test when it is used after silicon, there is no waveform fsdb file or other data file. Therefore, if Figure 2 As shown, the design to be tested 10 includes multiple functional modules 0 to 4. Each functional module needs to be connected to at least one counter, and the four functional modules are connected to a total of 7 counters, namely counters 11 to 17. Each counter corresponds to a flip signal of the functional module, namely flip signal 0 to flip signal 6. Each time a flip signal flips, the counter corresponding to the flip signal accumulates 1, and the counting result of the counter is stored in the register as the flip number of the flip signal for the software to read. During the simulation process, the flip number of the flip signal can be read as flip simulation data.

[0077] It should be noted that in order to ensure that the flip rate of the flip signal obtained during the simulation process is consistent with that obtained during post-silicon use, in an optional implementation, the design to be tested also includes the counter as described above, and the flip rates of the multiple flip signals in each pre-silicon test scenario are also obtained through the counter as described above.

[0078] Step S12: Determine the simulated dynamic power consumption of each pre-silicon test scenario according to the power consumption simulation data of each pre-silicon test scenario, and determine the flip rate of multiple flip signals of the functional module in each pre-silicon test scenario according to the flip simulation data of each pre-silicon test scenario.

[0079] Furthermore, in an optional implementation, the power consumption simulation data includes: a waveform fsdb file of the design to be tested in a pre-silicon test scenario. The waveform fsdb file is a file that represents the complete spectrum width of a waveform in digital signal processing and is used in electronic design automation tools to store and analyze simulation results of digital circuits. The waveform fsdb file can effectively process a large amount of waveform data, which is convenient for designing and verifying complex digital systems. The waveform fsdb file can accurately obtain the simulated dynamic power consumption of the design to be tested during the simulation process, as well as the simulated dynamic power consumption of each functional module in the design to be tested.

[0080] Further, based on the obtained waveform fsdb file, in an optional implementation, such as Figure 3 As shown, step S12 may include step S121: for any pre-silicon test scenario, according to the power consumption simulation data of the pre-silicon test scenario, obtain the waveform file of the pre-silicon test scenario; and, through the electronic design automation tool, perform power consumption analysis on the waveform file of the pre-silicon test scenario to obtain the simulated dynamic power consumption of the pre-silicon test scenario. Because the waveform fsdb file is a file used in the electronic design automation software to store and analyze the simulation results of the digital circuit, the accurate dynamic power consumption of the design to be tested can be easily obtained through the simulation tool, such as the electronic design automation software.

[0081] Further, based on the acquired flip rate, in an optional implementation, such as Figure 3 As shown, the step S12 may include step S122: for any pre-silicon test scenario, according to the flip simulation data of the pre-silicon test scenario, the number of flips per unit time of each flip signal in the pre-silicon test scenario is obtained as the flip rate of each flip signal in the pre-silicon test scenario. After the flip rates of multiple flip signals of the functional module are obtained, these flip signals are recorded as ACT_rate0, ACT_rate1, ACT_rate2, etc., and so on.

[0082] In an optional implementation, for any pre-silicon test scenario, the number of flips per unit time of each flip signal in the pre-silicon test scenario can be obtained according to the flip simulation data of the pre-silicon test scenario, as the flip rate of each flip signal in the pre-silicon test scenario. For example, when calculating the flip rate, a preset time window can be set, and the number of flips of the flip signal in the time window can be counted, and then the number of signal flips of the flip signal in a time period can be calculated, which is converted into a flip rate. Further, the time window for counting the number of flips of the flip signal can be set as a unit time, for example, the time of the time window is uniformly set to 1us, so as to detect the number of flips of each flip signal within 1us during the operation of the circuit to calculate the flip rate. For example, a flip signal flips once within 1us, and the flip rate of the flip signal is 1 time / 1us=1MHz, and the unit of the count value is MHz. For example, if a signal flips 200 times within 1us, then the flip rate of the signal is 200MHz.

[0083] It should be noted that, in an optional implementation, the flip signal includes a bus control signal and / or a read / write enable signal of the functional module. When selecting multiple flip signals of the functional module, it is necessary to select a flip signal that can fully reflect the flip activity of the functional module. Such flip signals are usually some signals related to data transmission, and can continuously jump and flip with the transmission of the flip signal, such as the control signal used to manage and coordinate the data transmission between the master device and the slave device in the AXI (Advanced eXtensible Interface, an on-chip bus) protocol, such as AWVALID (Address Write VALID) signal, ARVALID (Address Read VALID) signal, RVALID (Read Data VALID) signal, and WVALID (Write Data VALID) signal, or some read enable signals and write enable signals, such as WEN (Write Enable), REN (Read Enable), etc.

[0084] Please continue to refer to Figure 1 The signal measurement method further includes step S13: based on the linear relationship between the dynamic power consumption of the functional module and the signal flip, the simulated dynamic power consumption of each pre-silicon test scenario and the flip rate of the multiple flip signals in each pre-silicon test scenario are fitted to obtain the flip weights of the multiple flip signals of the functional module. The flip weights are used to determine the post-silicon dynamic power consumption of the functional module.

[0085] It should be noted that the post-silicon dynamic power consumption is the dynamic power consumption generated by the signal flipping of the functional module during the operation of the circuit obtained after the siliconization of the design to be tested.

[0086] Since there are multiple flip signals in a functional module, the influence of each flip signal on the dynamic power consumption of the entire functional module is different, and the influence of the flip signal is linearly proportional to the size of the circuit associated with the flip signal. Therefore, in an optional implementation, Figure 3 As shown, the step S13 may include step S131: based on the weighted sum relationship between the dynamic power consumption of the functional module and the flip rate and flip weight of the flip signal, the simulated dynamic power consumption of each pre-silicon test scenario and the flip rate of the multiple flip signals in each pre-silicon test scenario are fitted to obtain the flip weights of the multiple flip signals of the functional module.

[0087] At this time, the dynamic power consumption formula of the functional module can be expressed as follows: dyn =(C m ×V+C b )×V 2 ×F, transformed into Where ACT_rate i That is, the flip rate of the i-th flip signal obtained above; ACT_weight i That is, the weight value corresponding to the i-th flip signal, that is, the flip weight; N is the number of flip signals of the functional module.

[0088] Further, the number N of all flip signals in the design to be tested is a value obtained based on experience. In an optional implementation, the value of N needs to be greater than 16. Optionally, the value of N is 32.

[0089] Furthermore, in order to calculate the flip rate of the flip signal, it is necessary to obtain the simulated dynamic power consumption of the functional module in multiple pre-silicon test scenarios and the flip rate of the flip signal in each pre-silicon test scenario. Assume that the number of the multiple pre-silicon test scenarios is M. At this time, corresponding to each pre-silicon test scenario, a total of M formulas can be obtained: Used to calculate the flip rate of the flip signal, where j in the formula = 0, 1, 2, ... M-1. In an optional implementation, the number M of the pre-silicon test scenarios is greater than the number N of all flip signals in the functional module. Optionally, the number M of the pre-silicon test scenarios is more than twice the number N of all flip signals in the functional module.

[0090] After the obtained simulated dynamic power consumption in each pre-silicon test scenario and the flip rate of multiple flip signals in each pre-silicon test scenario are substituted into the above M formulas, the flip weights of the multiple flip signals can be solved. The flip weights of the multiple flip signals can be used to calculate the post-silicon dynamic power consumption of the functional module based on the above formula according to the flip rate of the multiple flip signals of the functional module when the design to be tested is used, and then the post-silicon dynamic power consumption of the design to be tested is obtained.

[0091] In this way, the simulated dynamic power consumption of the design to be tested, which can be accurately obtained during the simulation process, and the flip rate of multiple flip signals, are used to calculate the flip weight related to the flip rate of the flip signal based on the linear relationship between the dynamic power consumption of the functional module and the signal flip. Since the simulated dynamic power consumption used when obtaining the flip weight is accurate, when the design to be tested is used after silicon, the post-silicon dynamic power consumption of the functional module calculated by the flip weight and the flip rate of the flip signal accurately measured, and the post-silicon dynamic power consumption of the design to be tested are also determined to be accurate values. This avoids using an estimated value with a large error to calculate the post-silicon dynamic power consumption when calculating the post-silicon dynamic power consumption, thereby improving the calculation accuracy of the post-silicon dynamic power consumption.

[0092] Furthermore, based on the above formula In an alternative implementation, Figure 4 As shown, the specific calculation method of step S131 includes the following steps.

[0093] Step S132: constructing a toggle rate matrix according to the number M of the plurality of pre-silicon test scenarios and the number N of the plurality of toggle signals to represent the toggle rates of the plurality of toggle signals of the functional module in each pre-silicon test scenario.

[0094] The method for constructing the flip rate matrix is ​​to aggregate all flip signals into a flip rate matrix A. The data of each row of the flip rate matrix A is the flip rate of all flip signals in a pre-silicon test scenario; each column of the flip rate matrix A is the flip rate of the same flip signal in different pre-silicon test scenarios. Specifically, the flip rate matrix A is: where α j,i is the toggle rate of the i-th toggle signal in the j-th pre-silicon test scenario.

[0095] Step S133: constructing a dynamic power consumption vector according to the number of the plurality of pre-silicon test scenarios to represent the simulated dynamic power consumption of each of the pre-silicon test scenarios.

[0096] The method for constructing the dynamic power consumption vector P is to aggregate the simulated dynamic power consumption of each pre-silicon test scenario into a column vector with M rows and 1 column. Specifically, the dynamic power consumption vector P is: Among them, P j is the simulated dynamic power consumption in the jth pre-silicon test scenario, j=0, 1, 2, …, M-1.

[0097] Step S134: with the goal of minimizing the difference between the dynamic power consumption prediction vector and the dynamic power consumption vector, predict the flip weights of the multiple flip signals according to the flip rate matrix and the dynamic power consumption vector. The dynamic power consumption prediction vector is the product of the flip rate matrix and the flip weight vector, the flip weight vector is composed of the predicted flip weights of each flip signal, and the flip weights of the multiple flip signals are non-negative numbers.

[0098] Specifically, the flip weight vector W is to aggregate the flip weights of each flip signal into a column vector with N rows and 1 column. The flip weight vector W is specifically: Among them, w i ACT_weight is the weight of the flip rate of the i-th flip signal i , i=0,1,2,…N-1.

[0099] Furthermore, the above M formulas After expansion, a flip rate matrix operation P=A*W calculated by the flip rate matrix A, the dynamic power consumption vector P and the flip weight vector W can be obtained. Specifically, the flip rate matrix operation is: By performing a linear fit on the flip rate matrix operation, the flip weight ACT_weight of each flip signal can be obtained. i .

[0100] It should be noted that in real circuits, the flipping of the flip signal only consumes energy and generates power consumption, but cannot generate energy. Therefore, the linear fitting method for the above flip rate matrix operation needs to use a linear fitting method with a non-negative result, such as non-negative least squares (NNLS), non-negative matrix factorization (NMF), regularized least squares and other linear fitting methods.

[0101] Furthermore, in an optional implementation, the step S134 includes: using a non-negative least squares algorithm to minimize the difference between the dynamic power consumption prediction vector and the dynamic power consumption vector, and predicting the flip weights of the multiple flip signals according to the flip rate matrix and the dynamic power consumption vector.

[0102] Using the non-negative least squares algorithm, on the basis of achieving a non-negative result, the difference between the dynamic power consumption prediction vector and the dynamic power consumption vector can also be minimized, that is, the residual sum of squares of the calculated flip weights is reduced. The residual sum of squares is a commonly used indicator for measuring the goodness of model fit in statistics and regression analysis. It represents the sum of squares of the difference between the model prediction value and the post-silicon observation value, and is used to evaluate the prediction accuracy of the model. The smaller the residual sum of squares, the better the model fit effect. Therefore, using the non-negative least squares algorithm, an accurate fitting result can be obtained.

[0103] Furthermore, in an optional implementation, the signal at the set position of the multiple flip signals is the clock signal of the functional module. The signal measurement method further includes: when determining the flip rate of the multiple flip signals of the functional module in each pre-silicon test scenario, also determining the clock frequency of the clock signal in each pre-silicon test scenario, so that the clock frequency of the clock signal in each pre-silicon test scenario participates in the fitting process; and when obtaining the flip weights of the multiple flip signals of the functional module, using the flip weight of the signal at the set position as the clock weight of the clock signal.

[0104] It should be noted that the set position is the position of the clock signal in the flip signal sequence predetermined by the designer, and the optional clock signal is located at the last position of the flip signal. The jump of the clock signal in the functional module will also affect the post-silicon dynamic power consumption of the functional module. Therefore, in order to supplement the impact of the main clock signal on the post-silicon dynamic power consumption, the clock signal is regarded as a separate flip signal and participates in the calculation of the flip rate of the flip signal. At this time, the calculation formula for the dynamic power consumption generated by the clock signal is F×F_weight, where F is the clock frequency of the main clock signal, and the clock frequency of the clock signal is equivalent to the flip rate of the main clock signal; F_weight is the flip weight of the main clock signal.

[0105] Then, the calculation formula of the post-silicon dynamic power consumption of the above functional module is combined with the clock signal, and the calculation formula becomes: Since the clock signal is regarded as the flip signal of a single functional module, the clock frequency of the clock signal can be regarded as the flip rate of a flip signal, that is, F = ACT_rate N Similarly, the flip weight of the clock signal can also be F_weight = ACT_weight N Therefore, when the flip rate of the flip signal is obtained, the clock frequency of the clock signal is obtained at the same time, and when the flip weight is obtained, the flip weight of the signal at the set position is used as the clock weight of the clock signal.

[0106] Therefore, the formula for the post-silicon dynamic power consumption of the above functional modules can be converted into It can be seen that the number of products of the flip signals and the flip weights that need to be summed changes from N to N+1, and the product of the added set of flip signals and the flip weights is the product of the clock frequency of the main clock signal and the flip weight of the main clock signal.

[0107] The embodiment of the present application also provides a dynamic power consumption measurement method to accurately calculate the post-silicon dynamic power consumption of the design to be tested based on the flip weights obtained by the signal measurement method as described above. As an optional implementation, Figure 5 FIG. 1 is a flow chart showing a method for measuring dynamic power consumption according to an embodiment of the present application. Figure 5 As shown, the dynamic power consumption measurement method provided in the embodiment of the present application includes the following steps.

[0108] Step S21: When the circuit to be tested is running post-silicon, the post-silicon flip rate of multiple flip signals of the functional module of the circuit to be tested is obtained. The post-silicon flip rate is the flip rate of multiple flip signals of the functional module in the circuit obtained after silicon. The post-silicon flip rate of the multiple flip signals is obtained in the same way as the flip rate of the flip signal in the above step S12, which is also obtained by obtaining the number of flips per unit time through a counter, and will not be repeated here.

[0109] Step S22: Determine the post-silicon dynamic power consumption of the circuit under test according to the post-silicon flip rate of each flip signal of the functional module and the flip weight of each flip signal of the functional module, wherein the flip weight of each flip signal of the functional module is the flip weight calculated by the above signal measurement method.

[0110] It should be noted that, from the above content, the calculation formula for the post-silicon dynamic power consumption of a single functional module is: For a circuit under test having multiple functional modules, after obtaining the post-silicon dynamic power consumption of all functional modules, it is necessary to aggregate and sum the dynamic power consumption of all functional modules to obtain the post-silicon dynamic power consumption of the design under test.

[0111] Furthermore, the post-silicon dynamic power consumption of a functional module is the weighted sum of the flip rate of the flip signal in each functional module. Therefore, after summing up the dynamic power consumption of all functional modules, the dynamic power consumption of the circuit under test is equal to the weighted sum of all the flip signals and flip rates in the circuit under test. The calculation formula for the dynamic power consumption of the design under test can be obtained as follows: Wherein, K is the number of all flip signals in the design to be tested. For example, if there are G functional modules in the design to be tested, and each functional module includes N flip signals, then the number of all flip signals in the design to be tested is K=G*N.

[0112] In this way, by performing linear fitting based on the accurate simulated dynamic power consumption and the flip rate of the flip signal in the above signal measurement method, the flip weight obtained is used in the calculation of the post-silicon dynamic power consumption, and a more accurate dynamic power consumption can be obtained. In the post-silicon circuit to be tested, the flip signal of the functional module is also connected to a counter, so that the flip rate of the flip signal can be accurately obtained.

[0113] Furthermore, in the circuit to be tested, in addition to the power consumption generated by the clock signal of the functional module, there may be other power consumption that cannot be counted when obtaining the power consumption of the functional module. For example, some functional modules or functional logic are not suitable for estimating power consumption using the flip rate-based method. For example, some functional modules are small in scale, and it is impossible to estimate the power consumption of the smaller functional modules separately. Or the power consumption of some functional modules accounts for a small proportion, and they are in an idle state most of the time in post-silicon applications, that is, these functional modules are in a state where no functional work has been started in the design to be tested, so the function of flip signal statistics is not implemented. In addition, there are also some interconnected logic functions between functional modules. The above-mentioned power consumption cannot be counted based on the above method.

[0114] To solve this problem, the embodiment of the present application also provides another signal measurement method to count the power consumption that cannot be counted by the signal measurement method and dynamic power consumption measurement method described above, that is, background power consumption. These background power consumptions include: dynamic power consumption of functional modules that cannot be counted by flip rate, dynamic power consumption of functional modules that cannot be estimated individually, dynamic power consumption of logical functions between functional modules, and dynamic power consumption of each module in idle state. As an optional implementation, Figure 6 FIG. 2 is a flow chart showing a background signal measurement method provided in an embodiment of the present application. Figure 6 As shown, the background signal measurement method provided in the embodiment of the present application includes the following steps.

[0115] Step S31: Obtain power consumption simulation data and flip simulation data of the design to be tested in multiple idle state scenarios.

[0116] It should be noted that when the design to be tested is in an idle state, only the clock signal of the functional module in the design to be tested is jumping, and the flip signals of the functional modules that can be counted by the signal measurement method of the above steps S11 to S134 are all static in the idle state. The idle state scenario is a pre-silicon test scenario of the design to be tested in an idle state, that is, a pre-silicon test scenario in which only the clock signal of the functional module of the design to be tested jumps. The difference between the multiple idle state scenarios is only the different frequencies of the clock signals of the functional modules.

[0117] Step S32: Determine the simulated background power consumption of the design under test in each idle state scenario and the clock frequencies of the clock signals of the multiple functional modules of the design under test in each pre-silicon test scenario according to the power consumption simulation data of each idle state scenario.

[0118] It should be noted that the power consumption simulation data in step S32 also includes the waveform file of the design to be tested, but at this time the design to be tested is in an idle state. Therefore, the waveform file included in the power consumption simulation data in step S32 only reflects the jump of the clock signal in the design to be tested and the logic signal between the functional modules, and cannot reflect the flipping of the flip signal in the functional module. Furthermore, only the simulated background power consumption of the design to be tested can be obtained through the waveform file included in the power consumption simulation data in step S32, and the simulated background power consumption of each functional module cannot be obtained. At the same time, since the dynamic power consumption of the functional module in the idle state scenario is proportional to the clock frequency, and the scope of the clock signal of each functional module is only the current functional module. The simulated background power consumption of the design to be tested is also proportional to the clock frequency of the clock signal of each functional module in the design to be tested.

[0119] Step S33: Based on the linear relationship between background power consumption and clock frequency, the simulated background power consumption of each idle state scenario and the clock frequencies of the clock signals of the multiple functional modules in each idle state scenario are fitted to obtain clock weights of the multiple clock signals; the clock weights are used to determine the post-silicon background power consumption of the design to be tested.

[0120] It should be noted that the post-silicon background power consumption is the dynamic power consumption generated by the clock signal of the circuit obtained after the silicon of the design to be tested during operation. Since the background power consumption of the design to be tested is also linearly related to the clock frequency, similar to the above-mentioned signal measurement method, in an optional implementation, the step S33 includes: based on the background power consumption being expressed as the weighted sum of the clock frequency and clock weight of the clock signal, the simulated background power consumption of each idle state scenario and the clock frequency of the multiple clock signals in each idle state scenario are fitted to obtain the clock weights of the clock signals of the multiple functional modules.

[0121] The calculation formula for background power consumption in the idle state scenario is: Among them, is the frequency of the i-th clock signal, F_weight i is the clock weight corresponding to the i clock signal, and T is the total number of clock signals.

[0122] Furthermore, the above formula still cannot calculate the dynamic power consumption of the logic functions between the functional modules. When all the selected clock signals do not jump, some logic signals may still jump, such as PLL (Phase-Locked Loop) and RTC (Real-Time Clock). The dynamic power consumption of this part of the logic signal is often small and is a fixed value for a design to be tested. Therefore, this part of the power consumption can be included in the power consumption bias for acquisition.

[0123] The power bias is the power consumed by bias circuits and components in electronic circuit and system design. These bias circuits are usually used to set the operating point of the device to ensure that it operates stably under the required voltage and current conditions. The power bias can be obtained in advance during the simulation process of the design to be tested.

[0124] After adding the power consumption bias, in an optional implementation, such as Figure 7 As shown, step S33 includes step S331: based on the background power consumption expressed as the weighted sum of the clock frequency and clock weight of the clock signal, plus the relationship of the preset power consumption bias, the simulated background power consumption of each idle state scene, the clock frequency of the multiple clock signals in each idle state scene, and the preset power consumption bias are fitted to obtain the clock weights of the clock signals of the multiple functional modules. At this time, the complete formula for calculating the background power consumption is Among them, P os That is, the power consumption bias of the design to be tested, which is a pre-acquired fixed value.

[0125] Furthermore, in an optional implementation, if Figure 8 As shown, step S331 includes the following steps.

[0126] Step S332: Construct a clock frequency matrix based on the number of the multiple idle state scenarios, the preset power consumption bias, and the number of clock signals of the multiple functional modules to represent the clock frequencies of the multiple clock signals in each idle state scenario, wherein the setting column of the clock frequency matrix is ​​set to a first value.

[0127] The method for constructing the clock frequency matrix is ​​to aggregate all clock frequencies into a clock frequency matrix F. The data of each row of the clock frequency matrix F is the clock frequency of all clock signals in a pre-silicon test scenario; each column of the clock frequency matrix F is the clock frequency of the same clock signal in different pre-silicon test scenarios. Specifically, the clock frequency matrix F is: where f j,1 is the clock frequency of the i-th clock signal in the j-th pre-silicon test scenario.

[0128] Furthermore, since the above formula needs to be combined with a fixed power consumption bias P after the summation calculation, os To facilitate subsequent fitting, the power consumption can be offset by P os Considered as an equivalent change, that is, P os =1*w N , so that the power consumption bias can be integrated into the weighted sum calculation, thereby adding the power consumption bias P to the clock frequency matrix F. os The corresponding column is the setting column. The optional setting column is the last column of the clock frequency matrix F.

[0129] Step S333: constructing a background power consumption vector according to the number of the plurality of idle state scenarios to represent the simulated background power consumption of each idle state scenario.

[0130] Assuming that the number of idle state scenarios is M', the method for constructing the background power consumption vector P' is to aggregate the simulated dynamic power consumption of each idle state scenario into a clock frequency matrix with M' rows and 1 column. Specifically, the background power consumption vector P' is: Among them, P j is the simulated dynamic power consumption in the jth idle state scenario, j=0, 1, 2, …, M-1.

[0131] Step S334: With the goal of minimizing the difference between the background power consumption prediction vector and the background power consumption vector, predict the clock weights of the clock signals of the multiple functional modules according to the clock frequency matrix and the background power consumption vector. The background power consumption prediction vector is the product of the clock frequency matrix and the clock weight vector, the clock weight vector is composed of the predicted clock weights of each clock signal and the preset power consumption bias, the setting bits corresponding to the setting columns of the clock weight vector and the clock frequency matrix are set to the preset power consumption bias, and the clock weights of the clock signals of the multiple functional modules are non-negative numbers.

[0132] Specifically, the clock weight vector W' is to aggregate the clock weights of each clock signal into a clock frequency matrix with N rows and 1 column. The clock weight vector W' is specifically: Among them, w i is the clock weight F_weight of the i-th clock signal i , i=0,1,2,…N-1. And the last w N The value is equal to the power bias P os The value of .

[0133] Then, after obtaining M' idle state scenarios, the M' formulas corresponding to the M' idle state scenarios are After expansion, a clock frequency matrix operation P'=F*W' calculated by the clock frequency matrix F, the background power consumption vector P and the clock weight vector W' can be obtained. Specifically, the clock frequency matrix operation is: By performing linear fitting on the clock frequency matrix operation, the clock weight F_weight of each clock signal can be obtained. i .

[0134] Further, in an optional implementation, the step S334 includes: using a non-negative least squares algorithm to minimize the difference between the background power consumption prediction vector and the background power consumption vector, and predicting the clock weights of the clock signals of the multiple functional modules based on the clock frequency matrix and the background power consumption vector.

[0135] Using the non-negative least squares algorithm, on the basis of achieving a non-negative result, the difference between the background power consumption prediction vector and the background power consumption vector can also be minimized, that is, the residual sum of squares of the calculated flip weights is reduced. The residual sum of squares is a commonly used indicator to measure the goodness of model fit in statistics and regression analysis. It represents the sum of squares of the difference between the model prediction value and the post-silicon observation value, and is used to evaluate the prediction accuracy of the model. The smaller the residual sum of squares, the better the model fitting effect. Therefore, using the non-negative least squares algorithm, an accurate fitting result can be obtained.

[0136] In this way, the simulated dynamic power consumption of the design to be tested, which can be accurately obtained during the simulation process, and the clock frequencies of multiple clock signals, are used to calculate the clock weight related to the clock frequency of the clock signal based on the linear relationship between the background power consumption of the design to be tested and the clock frequency. Since the simulated background power consumption used to obtain the clock weight is accurate, when the design to be tested is used after silicon, the background power consumption of the design to be tested is calculated through the clock weight and the clock frequency of the accurately measured clock signal, and is determined to be an accurate value. This makes up for the background power consumption that is omitted when calculating the dynamic power consumption of the design to be tested, thereby improving the calculation accuracy of the post-silicon dynamic power consumption.

[0137] The embodiment of the present application also provides a background power consumption measurement method to accurately calculate the background dynamic power consumption of the design to be tested based on the clock weight obtained by the background signal method as described above. As an optional implementation, Fig. 9 FIG. 1 is a flow chart of a method for measuring background power consumption provided by an embodiment of the present application. Fig. 9 As shown, the background power consumption measurement method provided in the embodiment of the present application includes the following steps.

[0138] Step S41: when the circuit under test is post-silicon operated, obtaining post-silicon clock frequencies of a plurality of clock signals of the circuit under test.

[0139] Step S42: Determine the post-silicon background power consumption of the circuit under test according to the post-silicon clock frequency of each clock signal and the clock weight of each clock signal, wherein the clock weight of each clock signal is obtained based on the signal measurement method described in steps S31 to S334 above.

[0140] In this way, by performing linear fitting based on the accurate simulated dynamic power consumption and the clock frequency of the clock signal in the above signal measurement method, the obtained clock weight is used in the calculation of the background power consumption, so that more accurate background power consumption can be obtained.

[0141] Furthermore, in an optional implementation, if Fig.10 As shown, the background power consumption measurement method further includes step S411: obtaining a preset power consumption bias of the circuit under test. Step S42 may include step S421: performing weighted summation processing according to the post-silicon clock frequency of each clock signal and the clock weight of each clock signal, combining the weighted summation result with the preset power consumption bias, and calculating the post-silicon background power consumption of the circuit under test.

[0142] The embodiment of the present application also provides a method for measuring operating power consumption, which calculates the operating power consumption when the design is running based on the post-silicon dynamic power consumption obtained by the dynamic power consumption measurement method described above and the post-silicon background power consumption obtained by the background power consumption measurement method described above. As an optional implementation, Fig.11 FIG. 1 is a flow chart showing a method for measuring power consumption in operation provided by an embodiment of the present application. Fig.11 As shown, the operating power consumption measurement method provided in the embodiment of the present application includes the following steps.

[0143] Step S51: Obtaining the post-silicon dynamic power consumption and post-silicon background power consumption of the circuit under test during post-silicon operation. The post-silicon dynamic power consumption is obtained based on the dynamic power consumption measurement method described above, and the post-silicon background power consumption is obtained based on the background power consumption measurement method described above.

[0144] Step S52: determining the operating power consumption of the design to be tested according to the dynamic power consumption based on the toggle rate and the background power consumption in the idle state.

[0145] In this way, the simulated dynamic power consumption of the design to be tested, which can be accurately obtained during the simulation process, and the clock frequencies of multiple clock signals, are used to calculate the clock weight related to the clock frequency of the clock signal based on the linear relationship between the background power consumption of the functional module and the clock frequency. Since the simulated background power consumption used to obtain the clock weight is accurate, when the design to be tested is used after silicon, the background power consumption of the functional module calculated through the clock weight and the clock frequency of the accurately measured clock signal, and the background power consumption of the design to be tested are also determined to be accurate values. And the background power consumption omitted when calculating the dynamic power consumption of the design to be tested is supplemented, thereby improving the calculation accuracy of the dynamic power consumption after silicon.

[0146] Furthermore, if the circuit under test is in normal working conditions, such as full-load working state, the jump of the clock signal in the functional module will also generate power consumption in the functional module. If the dynamic power consumption based on the flip rate is directly added to the background power consumption, the power consumption generated by the clock signal will be calculated repeatedly. Therefore, it is necessary to deduplicate this part of the repeated power consumption.

[0147] Specifically, when calculating the dynamic power consumption of the functional module based on the flip rate, the clock signal of the functional module can be used as a flip signal and involved in the fitting to obtain the flip weight corresponding to the flip signal and the clock weight corresponding to the clock signal. In this way, when obtaining the flip weight, the influence of the clock signal is additionally considered, and the influence of the clock signal on the power consumption can be separated from the influence of the flip signal on the power consumption. Therefore, when the flip signal is subsequently used to calculate the dynamic power consumption, only the flip rate and flip weight of the flip signal are used, and the clock frequency and clock weight of the clock signal are not used, so that the calculated dynamic power consumption does not include the power consumption caused by the clock signal jump.

[0148] Based on the above ideas, in an optional implementation, in the above signal measurement method, the signal at the set position of the multiple flip signals is the clock signal of the functional module. The signal measurement method also includes: when determining the flip rate of the multiple flip signals of the functional module in each pre-silicon test scenario, also determining the clock frequency of the clock signal in each pre-silicon test scenario, so that the clock frequency of the clock signal in each pre-silicon test scenario participates in the fitting process; and when obtaining the flip weights of the multiple flip signals of the functional module, the flip weight of the signal at the set position is used as the clock weight of the clock signal.

[0149] It should be noted that the setting position is the position of the clock signal in the flip signal sequence predetermined by the designer, and the optional clock signal is located at the last position of the flip signal. By treating the clock signal as a single flip signal and participating in the calculation of the flip rate of the flip signal. At this time, the calculation formula for the dynamic power consumption generated by the clock signal is F×F_weight, where F is the clock frequency of the main clock signal, the clock frequency of the clock signal is equivalent to the flip rate of the main clock signal; F_weight is the flip weight of the main clock signal.

[0150] Then, the calculation formula of the post-silicon dynamic power consumption of the above functional module is combined with the clock signal, and the calculation formula becomes: Since the clock signal is regarded as the flip signal of a single functional module, the clock frequency of the clock signal can be regarded as the flip rate of a flip signal, that is, F = ACT_rate N Similarly, the flip weight of the clock signal can also be F_weight = ACT_weight N Therefore, when the flip rate of the flip signal is obtained, the clock frequency of the clock signal is obtained at the same time, and when the flip weight is obtained, the flip weight of the signal at the set position is used as the clock weight of the clock signal.

[0151] Therefore, the formula for the post-silicon dynamic power consumption of the above functional modules can be converted into It can be seen that the number of products of the flip signals and the flip weights that need to be summed changes from N to N+1, and the product of the added set of flip signals and the flip weights is the product of the clock frequency of the clock signal and the flip weight of the clock signal.

[0152] The embodiment of the present application also provides a signal measurement device to accurately calculate dynamic power consumption. As an optional implementation, Fig.12 The structure of the signal measuring device provided in the embodiment of the present application is shown. Fig.12 As shown, the signal measuring device provided in the embodiment of the present application includes the following modules.

[0153] The first simulation data acquisition module 101 is used to acquire power consumption simulation data and flip simulation data of a functional module of a design to be tested in a plurality of pre-silicon test scenarios.

[0154] The first simulation data processing module 102 is used to determine the simulated dynamic power consumption of each pre-silicon test scenario based on the power consumption simulation data of each pre-silicon test scenario, and to determine the flip rate of multiple flip signals of the functional module in each pre-silicon test scenario based on the flip simulation data of each pre-silicon test scenario.

[0155] The flip weight calculation module 103 is used to fit the simulated dynamic power consumption of each pre-silicon test scenario and the flip rate of the multiple flip signals in each pre-silicon test scenario based on the linear relationship between the dynamic power consumption of the functional module and the signal flip, so as to obtain the flip weights of the multiple flip signals of the functional module; the flip weights are used to determine the post-silicon dynamic power consumption of the functional module.

[0156] It should be noted that the power consumption simulation data and the flip simulation data are obtained and stored by the software program used in the simulation process, so as to be read by the first simulation data acquisition module 101. The first simulation data acquisition module 101, the first simulation data processing module 102, and the flip weight calculation module 103 are modules in the processor.

[0157] The present application embodiment also provides another signal measurement device to calculate the background of the design to be tested. As an optional implementation, Fig.13 FIG. 2 shows the structure of another signal measuring device provided by an embodiment of the present application. Fig.13 As shown, the operating power consumption measurement device provided in the embodiment of the present application includes the following modules.

[0158] The second simulation data acquisition module 201 is used to acquire power consumption simulation data of the design under test in multiple idle state scenarios.

[0159] The second simulation data processing module 202 is used to determine the simulated background power consumption of the design under test in each idle state scenario and the clock frequencies of multiple clock signals of the design under test in each pre-silicon test scenario according to the power consumption simulation data of each idle state scenario.

[0160] The clock weight calculation module 203 is used to fit the simulated background power consumption of each idle state scenario and the clock frequency of the multiple clock signals in each idle state scenario based on the linear relationship between the background power consumption and the clock frequency, so as to obtain the clock weights of the multiple clock signals; the clock weights are used to determine the post-silicon background power consumption of the design to be tested.

[0161] It should be noted that the power consumption simulation data is obtained and stored by a software program used in the simulation process for reading by the first simulation data acquisition module 101. The second simulation data acquisition module 201, the second simulation data processing module 202 and the clock weight calculation module 203 are modules in the processor.

[0162] The embodiment of the present application also provides a dynamic power consumption measurement device to calculate the dynamic power consumption of the design to be tested. As an optional implementation, Fig.14 The structure of the dynamic power consumption measurement device provided by the embodiment of the present application is shown. Fig.14As shown, the dynamic power consumption measurement device 501 provided in the embodiment of the present application includes the following modules.

[0163] The toggle rate acquisition module 301 is used to acquire post-silicon toggle rates of multiple toggle signals of functional modules of the circuit under test when the circuit under test is post-silicon operated.

[0164] The post-silicon dynamic power consumption calculation module 302 is used to determine the post-silicon dynamic power consumption of the circuit under test according to the post-silicon flip rate of each flip signal of the functional module and the flip weight of each flip signal of the functional module; wherein the flip weight of each flip signal of the functional module is determined based on the signal measurement method described in steps S31 to S334.

[0165] It should be noted that the flip rate acquisition module 301 and the post-silicon dynamic power consumption calculation module 302 are modules in the processor. When acquiring the post-silicon dynamic power consumption, the flip rate acquisition module 301 needs to first obtain the number of flips of the flip signal of the circuit under test in a unit time stored by the counter, and then obtain the post-silicon flip rate according to the number of flips. In the circuit under test, the counter is the physical hardware after the silicon.

[0166] The embodiment of the present application also provides a background power consumption measurement device to calculate the background power consumption of the design to be tested. As an optional implementation, Fig.14 The structure of the background power consumption measurement device provided by the embodiment of the present application is shown. Fig.14 As shown, the background power consumption measurement device 502 provided in the embodiment of the present application includes the following modules.

[0167] The clock frequency acquisition module 401 is used to acquire the post-silicon clock frequencies of multiple clock signals of the circuit under test when the circuit under test is running post-silicon.

[0168] The post-silicon background power consumption calculation module 402 is used to determine the post-silicon background power consumption of the circuit under test according to the post-silicon clock frequency of each clock signal and the clock weight of each clock signal; wherein the clock weight of each clock signal is obtained based on the signal measurement method described in steps S41 to S421.

[0169] It should be noted that the clock frequency acquisition module 401 and the post-silicon background power consumption calculation module 402 are modules in the processor. The clock frequency acquisition module 401 can directly acquire the post-silicon clock frequency of the clock signal through the internal program of the processor.

[0170] The embodiment of the present application also provides an operating power consumption measurement device to calculate the operating power consumption of the design to be tested. As an optional implementation, Fig.14 The structure of the running power consumption measurement device provided by the embodiment of the present application is shown. Fig.14As shown, the operating power consumption measurement device provided in the embodiment of the present application includes the following modules.

[0171] The dynamic power consumption measurement device 501 as described above is used to obtain the post-silicon dynamic power consumption of the circuit under test during post-silicon operation;

[0172] The background power consumption measuring device 502 as described above is used to obtain the post-silicon background power consumption of the circuit under test during post-silicon operation;

[0173] The operating power consumption calculation module 503 is used to determine the operating power consumption of the circuit under test according to the post-silicon dynamic power consumption and the post-silicon background power consumption.

[0174] It should be noted that the dynamic power consumption measurement device 501 , the post-silicon background power consumption measurement device 502 , and the power consumption calculation module 503 are modules within the processor.

[0175] An embodiment of the present application also provides a computer device, including a memory and a processor, the memory storing computer instructions, the processor calling the computer instructions stored in the memory to execute the signal measurement method such as steps S1 to S134, and / or the dynamic power consumption measurement method such as steps S1 and S22, and / or the signal measurement method such as steps S31 to S334, and / or the background power consumption measurement method such as steps S41 to S421, and / or the operating power consumption measurement method such as steps S51 and S52.

[0176] An embodiment of the present application also provides a storage medium, wherein the storage medium stores a design program of a chip, and when the design program is executed, the signal measurement method as described in steps S1 to S134 is implemented, and / or the dynamic power consumption measurement method as described in steps S1 and S22, and / or the signal measurement method as described in steps S31 to S334, and / or the background power consumption measurement method as described in steps S41 to S421, and / or the operating power consumption measurement method as described in steps S51 and S52 is implemented.

[0177] An embodiment of the present application also provides a computer program product, which, when executed, implements the signal measurement method as described in steps S1 to S134, and / or the dynamic power consumption measurement method as described in steps S1 and S22, and / or the signal measurement method as described in steps S31 to S334, and / or the background power consumption measurement method as described in steps S41 to S421, and / or the operating power consumption measurement method as described in steps S51 and S52.

[0178] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A signal measurement method, characterized in that: include: Obtain power consumption simulation data and flip simulation data of the functional modules of the design under test in multiple pre-silicon test scenarios; Determine the simulated dynamic power consumption of each pre-silicon test scenario according to the power consumption simulation data of each pre-silicon test scenario, and determine the flip rate of multiple flip signals of the functional module in each pre-silicon test scenario according to the flip simulation data of each pre-silicon test scenario; Based on the linear relationship between dynamic power consumption and signal flipping, the simulated dynamic power consumption of each pre-silicon test scenario and the flipping rate of the multiple flipping signals in each pre-silicon test scenario are fitted to obtain the flipping weights of the multiple flipping signals of the functional module; the flipping weights are used to determine the post-silicon dynamic power consumption of the functional module.

2. The signal measurement method according to claim 1, characterized in that: Based on the linear relationship between dynamic power consumption and signal flipping, the simulated dynamic power consumption of each pre-silicon test scenario and the flipping rate of the multiple flipping signals in each pre-silicon test scenario are fitted to obtain the flipping weights of the multiple flipping signals of the functional module, including: Based on the weighted sum relationship between dynamic power consumption and the flip rate and flip weight of the flip signal, the simulated dynamic power consumption of each pre-silicon test scenario and the flip rate of the multiple flip signals in each pre-silicon test scenario are fitted to obtain the flip weights of the multiple flip signals of the functional module.

3. The signal measurement method according to claim 2, characterized in that: The weighted summation relationship between the dynamic power consumption and the flip rate and flip weight of the flip signal is based on the dynamic power consumption, and the simulated dynamic power consumption of each pre-silicon test scenario and the flip rate of the multiple flip signals in each pre-silicon test scenario are fitted to obtain the flip weights of the multiple flip signals of the functional module. The method includes: According to the number of the plurality of pre-silicon test scenarios and the number of the plurality of flip signals, construct a flip rate matrix to represent the flip rates of the plurality of flip signals in each pre-silicon test scenario; and, constructing a dynamic power consumption vector according to the number of the plurality of pre-silicon test scenarios to represent the simulated dynamic power consumption of each of the pre-silicon test scenarios; With the goal of minimizing the difference between the dynamic power consumption prediction vector and the dynamic power consumption vector, the flip weights of the multiple flip signals are predicted based on the flip rate matrix and the dynamic power consumption vector; wherein the dynamic power consumption prediction vector is the product of the flip rate matrix and the flip weight vector, the flip weight vector is composed of the predicted flip weights of each flip signal, and the flip weights of the multiple flip signals are non-negative numbers.

4. The signal measurement method according to claim 1, characterized in that: The functional modules are logic blocks divided according to the logic functions of the design to be tested.

5. The signal measurement method according to claim 1, characterized in that: The flip signal includes a bus control signal and / or a read / write enable signal of the functional module.

6. The signal measurement method according to claim 1, characterized in that: The step of determining the simulated dynamic power consumption of each pre-silicon test scenario according to the power consumption simulation data of each pre-silicon test scenario includes: For any pre-silicon test scenario, a waveform file of the pre-silicon test scenario is obtained according to the power consumption simulation data of the pre-silicon test scenario; and power consumption analysis is performed on the waveform file of the pre-silicon test scenario through an electronic design automation tool to obtain the simulated dynamic power consumption of the pre-silicon test scenario.

7. The signal measurement method according to any one of claims 1 to 6, characterized in that: The method further comprises: Determine the clock frequency of the clock signal in each pre-silicon test scenario according to the flip simulation data of each pre-silicon test scenario; The step of fitting the simulated dynamic power consumption of each pre-silicon test scenario and the flip rate of the multiple flip signals in each pre-silicon test scenario based on the linear relationship between dynamic power consumption and signal flipping to obtain the flip weights of the multiple flip signals of the functional module includes: Based on the linear relationship between dynamic power consumption and signal flipping, the simulated dynamic power consumption of each pre-silicon test scenario, and the flipping rate of the multiple flipping signals in each pre-silicon test scenario and the clock frequency are fitted to obtain the flipping weights of the multiple flipping signals of the functional module and the clock weight.

8. The signal measurement method according to claim 7, characterized in that: The flip simulation data includes: the flip times of multiple flip signals of the functional module in various pre-silicon test scenarios; The step of determining the flip rates of multiple flip signals of the functional modules in each pre-silicon test scenario according to the flip simulation data of each pre-silicon test scenario comprises: For any pre-silicon test scenario, the number of flips per unit time of each flip signal in the pre-silicon test scenario is obtained according to the flip simulation data of the pre-silicon test scenario as the flip rate of each flip signal in the pre-silicon test scenario.

9. A method for measuring dynamic power consumption, characterized in that: include: When the circuit under test is in post-silicon operation, obtaining post-silicon flip rates of multiple flip signals of functional modules of the circuit under test; The post-silicon dynamic power consumption of the circuit under test is determined according to the post-silicon flip rate of each flip signal of the functional module and the flip weight of each flip signal of the functional module; wherein the flip weight of each flip signal of the functional module is determined based on the signal measurement method described in any one of claims 1-8.

10. A signal measurement method, characterized in that: include: Obtain power consumption simulation data and flip simulation data of the design under test in multiple idle state scenarios; Determine the simulated background power consumption of the design under test in each idle state scenario and the clock frequencies of multiple clock signals of the design under test in each pre-silicon test scenario according to the power consumption simulation data of each idle state scenario; Based on the linear relationship between background power consumption and clock frequency, fitting processing is performed on the simulated background power consumption of each idle state scenario and the clock frequencies of the multiple clock signals in each idle state scenario to obtain clock weights of the multiple clock signals; The clock weights are used to determine the post-silicon background power consumption of the design under test.

11. The signal measurement method according to claim 10, characterized in that: The step of fitting the simulated background power consumption of each idle state scenario and the clock frequencies of the multiple clock signals in each idle state scenario based on the linear relationship between the background power consumption and the clock frequency to obtain the clock weights of the clock signals of the multiple functional modules includes: Based on the background power consumption expressed as the weighted sum of the clock frequency and clock weight of the clock signal, the simulated background power consumption of each idle state scenario and the clock frequencies of the multiple clock signals in each idle state scenario are fitted to obtain the clock weights of the clock signals of the multiple functional modules.

12. The signal measurement method according to claim 11, characterized in that: The background power consumption is expressed as a weighted sum of the clock frequency and the clock weight of the clock signal, and the simulated background power consumption of each idle state scenario and the clock frequencies of the multiple clock signals in each idle state scenario are fitted to obtain the clock weights of the clock signals of the multiple functional modules, including: Based on the background power consumption expressed as the weighted sum of the clock frequency and clock weight of the clock signal, plus the relationship of the preset power consumption bias, the simulated background power consumption of each idle state scenario, the clock frequency of the multiple clock signals in each idle state scenario, and the preset power consumption bias are fitted to obtain the clock weights of the clock signals of the multiple functional modules.

13. The signal measurement method according to claim 12, characterized in that: The background power consumption is expressed as a weighted sum of the clock frequency and the clock weight of the clock signal, and the relationship of the preset power consumption bias is added, and the simulated background power consumption of each idle state scenario, the clock frequency of the multiple clock signals in each idle state scenario, and the preset power consumption bias are fitted to obtain the clock weights of the clock signals of the multiple functional modules, including: According to the number of the plurality of idle state scenarios, the preset power consumption bias, and the number of clock signals of the plurality of functional modules, a clock frequency matrix is ​​constructed to represent the clock frequencies of the plurality of clock signals in each idle state scenario, wherein a setting column of the clock frequency matrix is ​​set to a first value; and, constructing a background power consumption vector according to the number of the plurality of idle state scenarios to represent the simulated background power consumption of each of the idle state scenarios; With the goal of minimizing the difference between the background power consumption prediction vector and the background power consumption vector, the clock weights of the clock signals of the multiple functional modules are predicted based on the clock frequency matrix and the background power consumption vector; wherein the background power consumption prediction vector is the product of the clock frequency matrix and the clock weight vector, the clock weight vector is composed of the predicted clock weights of each clock signal, and the preset power consumption bias, the setting bits corresponding to the setting columns of the clock weight vector and the clock frequency matrix are set to the preset power consumption bias, and the clock weights of the clock signals of the multiple functional modules are non-negative numbers.

14. A background power consumption measurement method, characterized in that: include: When the circuit under test is running in post-silicon, obtaining post-silicon clock frequencies of a plurality of clock signals of the circuit under test; The post-silicon background power consumption of the circuit under test is determined based on the post-silicon clock frequency of each clock signal and the clock weight of each clock signal; wherein the clock weight of each clock signal is obtained based on the signal measurement method described in any one of claims 10-13.

15. The background power consumption measurement method according to claim 14, characterized in that: Also includes: Obtaining a preset power consumption bias of the circuit to be tested; The step of determining the post-silicon background power consumption of the circuit under test according to the post-silicon clock frequency of each clock signal and the clock weight of each clock signal comprises: A weighted summation process is performed according to the post-silicon clock frequency of each clock signal and the clock weight of each clock signal, and the weighted summation result is combined with the preset power consumption bias to calculate the post-silicon background power consumption of the circuit under test.

16. A method for measuring operating power consumption, characterized in that: include: Obtaining post-silicon dynamic power consumption and post-silicon background power consumption of the circuit under test during post-silicon operation; The post-silicon dynamic power consumption is obtained based on the dynamic power consumption measurement method described in right 9, and the post-silicon background power consumption is obtained based on the background power consumption measurement method described in any one of right 14-15; The operating power consumption of the circuit to be tested is determined according to the post-silicon dynamic power consumption and the post-silicon background power consumption.

17. A signal measuring device, characterized in that: include: A first simulation data acquisition module is used to acquire power consumption simulation data and flip simulation data of a functional module of the design to be tested in multiple pre-silicon test scenarios; A first simulation data processing module, used to determine the simulated dynamic power consumption of each pre-silicon test scenario according to the power consumption simulation data of each pre-silicon test scenario, and to determine the flip rate of multiple flip signals of the functional module in each pre-silicon test scenario according to the flip simulation data of each pre-silicon test scenario; The flip weight calculation module is used to fit the simulated dynamic power consumption of each pre-silicon test scenario and the flip rate of the multiple flip signals in each pre-silicon test scenario based on the linear relationship between dynamic power consumption and signal flip, so as to obtain the flip weights of the multiple flip signals of the functional module; the flip weights are used to determine the post-silicon dynamic power consumption of the functional module.

18. A signal measuring device, characterized in that: include: A second simulation data acquisition module is used to acquire power consumption simulation data of the design to be tested in multiple idle state scenarios; A second simulation data processing module, used to determine the simulated background power consumption of the design to be tested in each idle state scenario and the clock frequencies of multiple clock signals of the design to be tested in each pre-silicon test scenario according to the power consumption simulation data of each idle state scenario; A clock weight calculation module, configured to perform fitting processing on the simulated background power consumption of each idle state scenario and the clock frequencies of the multiple clock signals in each idle state scenario based on the linear relationship between the background power consumption and the clock frequency, so as to obtain clock weights of the multiple clock signals; The clock weights are used to determine the post-silicon background power consumption of the design under test.

19. A dynamic power consumption measurement device, characterized in that: include: A flip rate acquisition module, used for acquiring post-silicon flip rates of multiple flip signals of a functional module of the circuit under test when the circuit under test is running post-silicon; A post-silicon dynamic power consumption calculation module is used to determine the post-silicon dynamic power consumption of the circuit under test according to the post-silicon flip rate of each flip signal of the functional module and the flip weight of each flip signal of the functional module; wherein the flip weight of each flip signal of the functional module is determined based on the signal measurement method described in any one of claims 1-8.

20. A background power consumption measurement device, characterized in that: include: A clock frequency acquisition module, used for acquiring post-silicon clock frequencies of multiple clock signals of the circuit under test when the circuit under test is running post-silicon; A post-silicon background power consumption calculation module is used to determine the post-silicon background power consumption of the circuit under test based on the post-silicon clock frequencies of each clock signal and the clock weights of each clock signal; wherein the clock weights of each clock signal are obtained based on the signal measurement method described in any one of claims 10-13.

21. An operating power consumption measurement device, characterized in that: include: The dynamic power consumption measurement device according to claim 19, used to obtain the post-silicon dynamic power consumption of the circuit under test during post-silicon operation; The background power consumption measuring device according to claim 20, used to obtain the post-silicon background power consumption of the circuit under test during post-silicon operation; The operating power consumption calculation module is used to determine the operating power consumption of the circuit to be tested according to the post-silicon dynamic power consumption and the post-silicon background power consumption.

22. A computing device, characterized in that It includes a memory and a processor, the memory stores computer instructions, and the processor calls the computer instructions stored in the memory to execute the signal measurement method as described in any one of claims 1 to 8, and / or the dynamic power consumption measurement method as described in claim 9, and / or the signal measurement method as described in any one of claims 10 to 13, and / or the background power consumption measurement method as described in any one of claims 15 to 15, and / or the operating power consumption measurement method as described in claim 16.

23. A storage medium, characterized in that: The storage medium stores a design program of the chip, and when the design program is executed, it implements the signal measurement method as described in any one of claims 1 to 8, and / or the dynamic power consumption measurement method as described in claim 9, and / or the signal measurement method as described in any one of claims 10 to 13, and / or the background power consumption measurement method as described in any one of claims 14 to 15, and / or the operating power consumption measurement method as described in claim 16.

24. A computer program product, characterized in that When the computer program product is executed, it implements the signal measurement method as described in any one of claims 1 to 8, and / or the dynamic power consumption measurement method as described in claim 9, and / or the signal measurement method as described in any one of claims 10 to 13, and / or the background power consumption measurement method as described in any one of claims 14 to 15, and / or the operating power consumption measurement method as described in claim 16.

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