Simulation method and device for chip design and related equipment

Abstract

The embodiment of the invention provides a simulation method and device for chip design and related equipment, and the method comprises the steps: obtaining the design data of each partition in the chip design; for each partition, determining a corresponding data extraction strategy based on the type of the design data; extracting the design data of the corresponding type by using the data extraction strategy to obtain extracted data; the data extraction of each type of design data is performed in parallel; merging the extracted data corresponding to each type of design data to form chip power consumption model data of each partition; and performing simulation of chip design by using the chip power consumption model data of each partition. According to the technical scheme provided by the embodiment of the invention, the extraction efficiency of the chip power consumption model data can be optimized, and the simulation efficiency of chip design is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and specifically to a simulation method, device and related equipment for chip design. Background Art

[0002] Chip Power Model (CPM) data is an important tool in chip design and simulation. It can help designers understand and optimize the power consumption characteristics of chip designs and ensure the performance and reliability of chip designs in actual applications.

[0003] However, as the integration of chip design continues to increase, the complexity of chip design and simulation also increases, resulting in a longer time-consuming extraction of chip power consumption model data, which in turn affects the simulation efficiency of chip design. Therefore, in this context, how to provide a technical solution to optimize the extraction efficiency of chip power consumption model data and improve the simulation efficiency of chip design has become a technical problem that technicians in this field need to solve urgently. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a chip design simulation method, apparatus and related equipment to optimize the extraction efficiency of chip power consumption model data and improve the chip design simulation efficiency.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present invention provides a simulation method for chip design, comprising:

[0007] Obtain design data for each partition in chip design;

[0008] For each partition, based on the type of the design data, determine a corresponding data extraction strategy;

[0009] Using the determined data extraction strategy, extract data from the corresponding type of design data to obtain extracted data corresponding to each type of design data; and the data extraction of each type of design data is performed in parallel;

[0010] Merge the extracted data corresponding to each type of design data to form chip power consumption model data for each partition;

[0011] The chip power consumption model data of each partition is used to simulate the chip design.

[0012] In a second aspect, an embodiment of the present invention provides a simulation device for chip design, comprising:

[0013] A data acquisition module, used to acquire design data of each partition in chip design;

[0014] A data extraction strategy determination module, used for determining a corresponding data extraction strategy for each partition based on the type of the design data;

[0015] A data extraction module is used to extract data from the corresponding type of design data using the determined data extraction strategy to obtain extracted data corresponding to each type of design data; and the data extraction of each type of design data is performed in parallel;

[0016] The power consumption model data forming module is used to merge the extracted data corresponding to each type of design data to form the chip power consumption model data of each partition;

[0017] The chip design simulation module is used to simulate chip design using chip power consumption model data of each partition.

[0018] In a third aspect, an embodiment of the present invention provides an electronic device, including a memory and a processor, wherein the memory stores a program, and the processor calls the program stored in the memory to execute the simulation method for chip design as described in the first aspect.

[0019] In a fourth aspect, an embodiment of the present invention provides a storage medium, wherein the storage medium stores a program, and when the program is executed, the simulation method for chip design as described in the first aspect is implemented.

[0020] In a fifth aspect, an embodiment of the present invention provides a computer program product, including a computer program, which, when executed by a processor, implements the simulation method for chip design as described in the first aspect.

[0021] A chip design simulation method provided by an embodiment of the present invention includes: obtaining design data of each partition in the chip design; for each partition, determining a corresponding data extraction strategy based on the type of the design data; using the determined data extraction strategy, extracting data of the corresponding type of design data to obtain extracted data corresponding to each type of design data; and the data extraction of each type of design data is performed in parallel; merging the extracted data corresponding to each type of design data to form chip power consumption model data of each partition; and simulating the chip design using the chip power consumption model data of each partition.

[0022] It can be seen that the technical solution provided by the embodiment of the present invention first distinguishes the types of design data of each partition in the process of extracting chip power consumption model data; then uses the data extraction strategy corresponding to each type to complete the execution of the data extraction process under the design data of this type, and finally merges the data extraction results (extracted data) under each type to obtain the chip power consumption model data of each partition. Since the data extraction strategy is defined in a one-to-one correspondence with the type of design data, the data extraction strategies of different types of design data are independent, and the data extraction of each type of design data is performed in parallel; therefore, when extracting data from each partition, the data extraction strategy corresponding to the type of design data can be used to independently and parallelly execute the data extraction steps, thereby increasing the number of subtasks (programs for executing data extraction) used to execute the data extraction steps in a partition, improving the execution speed of the data extraction steps, and reducing the time consumption when extracting chip power consumption model data, so as to achieve the purpose of optimizing the extraction efficiency of chip power consumption model data and improving the simulation efficiency of chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0024] Figure 1 It is a schematic diagram of a flow chart of a simulation method for chip design provided by an embodiment of the present invention;

[0025] Figure 2a is a schematic diagram of a chip power consumption model provided by an embodiment of the present invention;

[0026] Figure 2b yes Figure 2a The simplified model corresponding to the chip power consumption model shown;

[0027] Figure 3 It is a schematic diagram of an implementation process of obtaining chip power consumption model data based on a unified extraction method provided by an embodiment of the present invention;

[0028] Figure 4 It is a schematic diagram of an implementation process of obtaining chip power consumption model data by an independent extraction method provided by an embodiment of the present invention;

[0029] Figure 5 is another schematic flow chart of the chip design simulation method provided by an embodiment of the present invention;

[0030] Figure 6is a schematic diagram of a chip design provided by an embodiment of the present invention;

[0031] Figure 7 is Figure 3 Schematic diagram of the chip power consumption model data extraction process for each partition under the unified extraction method shown;

[0032] Figure 8 is Figure 4 Schematic diagram of the process of extracting chip power consumption model data of each partition under the independent extraction mode shown;

[0033] Fig. 9 It is a structural schematic diagram of a chip design simulation device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] As chip designs grow in size, designs become more complex. By dividing large chip designs into smaller, more manageable modules or subsystems (Partitions), designers can handle complexity more effectively, and each design engineer can focus on one or a few modules, thereby improving design efficiency and manageability.

[0036] At the same time, with the improvement of chip design level, on the one hand, the functions integrated in a single chip design and the scale of the chip design formed are getting larger and larger, which makes the power consumption of chip design increase continuously; on the other hand, with the improvement of chip design manufacturing process, the supply voltage of chip design is constantly reduced, and the voltage noise tolerance is also reduced. The power supply noise caused by the flip of the digital circuit in the chip design will interfere with the logic circuit inside the chip design, resulting in signal transmission errors or missing pulse information, which may lead to unstable chip design functions. Therefore, considering the simulation of power integrity (PI) in large-scale chip design and analyzing based on the results of PI simulation to eliminate or reduce the impact of noise on power supply has become a bottleneck and problem in chip design.

[0037] The analysis of the results of power integrity simulation is related to the performance, reliability and signal integrity of the chip design. Its main purpose is to ensure that the power distribution network (PDN) can provide stable and noise-free power to each part of the chip design.

[0038] When performing PI simulation, the front-end engineer can generate the signal waveform of the corresponding scenario through simulation according to the function of the chip design; the back-end engineer is responsible for extracting the chip power consumption model data corresponding to the wafer (Die) of the chip design based on the design data such as waveform files provided by the front-end engineer; the system platform engineer extracts the S parameters (Scatter Parameters) of the packaging model and the printed circuit board (PCB), and builds the circuit board model according to the S parameters of the PCB; finally, based on the network model formed by the cascade of the chip power consumption model data, the packaging model and the PCB model, the collaborative simulation of the PCB with the chip design and packaging is carried out.

[0039] Among them, the chip power consumption model data is used as the input data of PI simulation, and is verified in the package model and PCB model to realize power integrity analysis. Therefore, the chip power consumption model data is crucial for power integrity analysis of power integrity simulation, and the extraction of chip power consumption model data is also very important. As the scale and function of chip design continue to increase, the overall design of chip design is usually carried out in a partitioned manner. Therefore, when performing PI simulation, the input chip power consumption model data is the design data based on each partition in the chip design.

[0040] The chip power consumption model data usually includes the partition-level power distribution network (PDN) parasitic parameters (RLC) and partition-level current distribution information of each partition in the chip design; wherein the partition-level current distribution information can be represented by a piece-wise linear waveform (PWL).

[0041] When extracting chip power consumption model data, it is usually achieved by directly extracting data in a unified manner based on the design data of each partition in the chip design. However, as the scale and function of chip design continue to increase, the amount of design data of each partition in the chip design also continues to increase, thereby increasing the time consumption of extracting power consumption chip model data; at the same time, since the chip design needs to be constantly adjusted and updated during the design process to meet the design requirements of the chip design, the content of the corresponding design data of each partition is also constantly changing. For the unified extraction method, as long as the chip design changes (partial changes will occur in the design data of each partition), the extraction process of the chip power consumption model data of each partition must be re-executed, thereby increasing the number of iterations for extracting the chip power consumption model data of each partition.

[0042] To solve the above problems, an embodiment of the present invention provides a simulation method for chip design to optimize the extraction efficiency of chip power consumption model data and improve the simulation efficiency of chip design.

[0043] Please refer to Figure 1 , Figure 1 It is a flow chart of a simulation method for chip design provided by an embodiment of the present invention.

[0044] like Figure 1 As shown, the method comprises the following steps:

[0045] Step S101, obtaining design data of each partition in chip design.

[0046] The design data of each partition in the chip design can be provided by engineers (such as the front-end engineers and back-end engineers mentioned above) after the chip is designed and simulated.

[0047] The number of partitions obtained after a chip design is divided can be determined based on the design requirements of the chip design and the simulation tool used to simulate the chip design (such as PI simulation), so that the number of partitions after division can meet both the design requirements of the chip design and the number of partitions that can be analyzed by the simulation tool at one time.

[0048] Step S102: for each partition, determine a corresponding data extraction strategy based on the type of the design data.

[0049] The data extraction strategy defines an extraction method for extracting chip power consumption model data for each type of design data.

[0050] The chip design process includes both front-end logic design and back-end physical design. Therefore, different types of design data can be generated based on different design processes.

[0051] In an embodiment of the present invention, before extracting chip power consumption model data, the types of design data of each partition are distinguished in advance. Then, data extraction is performed based on the data extraction strategy of each type of design data. Therefore, the extraction process of different types of design data in the design data of a partition can be divided to ensure that the data extraction processes of the design data can be executed independently of each other. Compared with the unified extraction method, the independent extraction method of the data extraction strategy corresponding to each type of design data in the embodiment of the present invention can reduce the data dependency between input data and result data when extracting data based on different types of design data (input data) to form the final chip power consumption model data (result data).

[0052] Step S103: extract data from the corresponding type of design data using the determined data extraction strategy to obtain extracted data corresponding to each type of design data.

[0053] Data extraction for each type of design data is performed in parallel.

[0054] When extracting the power consumption model data, the data extraction process of the design data of each partition is executed in parallel. Therefore, when extracting the design data of each partition using a unified extraction method, the same number of subtasks as the number of partitions (assuming the number of partitions is i) are called to perform the data extraction process in parallel; and when extracting data for each type of design data of each partition using the data extraction strategy provided by the embodiment of the present invention, it is equivalent to splitting the data extraction process of the design data of each partition into calling two subtasks to execute in parallel. Therefore, when the number of partitions i remains unchanged, in the embodiment of the present invention, 2i subtasks can be called to execute the data extraction process of the design data of each partition in parallel, thereby improving the overall running time of the data extraction process.

[0055] Step S104 , merging the extracted data corresponding to each type of design data to form chip power consumption model data of each partition.

[0056] Based on the above content, it can be known that the chip power consumption model data contains the partition-level power distribution network parasitic parameters (PDN RLC) and partition-level current distribution information (PWL) of each partition in the chip design. After analysis, it is found that the partition-level power network parasitic parameters and partition-level current distribution information are related to the type of design data. Therefore, data extraction can be completed based on different types of design data using corresponding data extraction strategies, and then the extracted data can be merged to obtain the final chip power consumption model data.

[0057] Step S105 , using the chip power consumption model data of each partition to perform chip design simulation.

[0058] It can be seen that the technical solution provided by the embodiment of the present invention first distinguishes the types of design data of each partition in the process of extracting chip power consumption model data; then uses the data extraction strategy corresponding to each type to complete the execution of the data extraction process under the design data of that type, and finally merges the data extraction results (extracted data) under each type to obtain the final chip power consumption model data. Since the data extraction strategy is defined in a one-to-one correspondence with the type of design data, the data extraction strategies of different types of design data are independent, and the data extraction of each type of design data is performed in parallel; therefore, when extracting data from each partition, the data extraction strategy corresponding to the type of design data can be used to independently and parallelly execute the data extraction steps, thereby increasing the number of subtasks (programs for executing data extraction) used to execute the data extraction steps in a partition, improving the execution speed of the data extraction steps, and reducing the time consumption when extracting chip power consumption model data, thereby achieving the purpose of optimizing the extraction efficiency of chip power consumption model data and improving the simulation efficiency of chip design.

[0059] In order to smoothly implement data extraction of different types of design data, the definition of different types of data extraction strategies can be completed in advance.

[0060] Please continue to refer to Figure 1 ,like Figure 1 As shown, the method may further include the following steps:

[0061] Step S100, defining a corresponding data extraction strategy based on the type of design data.

[0062] When extracting different types of design data to form the final chip power consumption model data, the extraction methods or extraction steps used are different. Therefore, in the embodiment of the present invention, based on the specific type of design data, a data extraction strategy is defined in a targeted manner, so that when data is subsequently extracted based on the data extraction strategy, the correctness and reliability of the data extraction process for each type of design data can be guaranteed.

[0063] Step S100 may include:

[0064] Based on the type of design data, a processing path for processing each type of design data is determined; in each processing path, an extraction method for extracting design data is defined to form a corresponding data extraction strategy; wherein the extracted data obtained after extraction using the extraction method in each processing path is merged to form chip power consumption model data.

[0065] Each processing path corresponds to obtaining a portion of the chip power consumption model data.

[0066] An extraction method used by the processing path for data extraction is defined on each processing path, and the extraction method meets the processing requirements of each type of design data when forming a part of the chip power consumption model data.

[0067] Different types of design data can form part of the chip power consumption model data after data extraction. Therefore, in the process of data extraction using the independent extraction method provided in the embodiment of the present invention, after each processing path completes the extraction of the corresponding type of design data using its defined extraction method, the various extracted data can be merged to obtain the final chip power consumption model data.

[0068] The chip design includes front-end logic design and back-end physical design. After the front-end logic design is completed, logic design data can be obtained. Therefore, in one embodiment, the type of the design data may include: logic design type; the processing path for processing each type of design data based on the type of the design data includes:

[0069] Determining, based on the logic design data of the logic design type, a first processing path for processing the logic design data;

[0070] In each processing path, an extraction method for extracting design data is defined to form a corresponding data extraction strategy, including:

[0071] In the first processing path, a first extraction method for extracting logic design data is defined as:

[0072] Converting the logic design data to form module-level logic design data;

[0073] Processing the module-level logic design data according to the partition division information of the chip design to obtain first extracted data, wherein the partition division information includes each partition after the chip design is divided, and the modules in each partition;

[0074] A first data extraction strategy is formed.

[0075] The data extraction strategy is used to extract each type of design data, that is, the data extraction process of each type of design data is performed independently, and the data extraction processes of different types of design data in a partition are executed in parallel. Therefore, after obtaining the extracted data corresponding to each type of design data, the chip power consumption model data is finally formed based on each extracted data.

[0076] After analysis, it was found that the partition-level current distribution information in the chip power consumption model data is related to the logic design data of the logic type in the design data. Therefore, in the embodiment of the present invention, after the design data is differentiated by type, a corresponding data extraction strategy is set for each type of design data, thereby reducing the dependence of the design data when extracting the chip power consumption model data, and forming the final chip power consumption model data without affecting the simulation of subsequent chip design.

[0077] The relationship between partition-level current distribution information and logic design data is discussed below:

[0078] According to the chip power consumption analysis principle, the chip power consumption is divided into the following two parts:

[0079] (1) Static power consumption (leakage power): that is, the power consumption of a cell when there is no signal switching and it is in an inactive or standby state. The static power consumption includes the leakage current power consumption caused by the source-to-drain leakage current, and also includes the leakage current power consumption between the diffusion layer and the substrate. The leakage power value is related to the process characteristics of the cell.

[0080] (2) Dynamic power refers to the power consumption of a circuit when it is active, including internal power and switching power.

[0081] Among them, internal power refers to the charging and discharging of the capacitor inside the standard cell, and the momentary short circuit current between the PN nodes. The momentary short circuit current is the momentary current generated from VDD to GND when the P transistor and the N transistor are short-circuited at a certain moment during the process of closing and opening. Therefore, the main factors affecting internal power are the cell input signal jump time (input transition time) and the output load (output load) value.

[0082] Switching power is caused by the charging and discharging of the load capacitance at the output end of a cell. The main factors affecting switching power are chip voltage, cell load capacitance, and cell toggle rate. Among them, the cell load capacitance includes the intrinsic input pin capacitance of the output to the next level cell and the parasitic capacitance of the signal net (conductive path in the circuit for transmitting electrical signals) connected to the output.

[0083] It can be seen that the partition-level current distribution information included in the chip power consumption model data: Partition PWL is essentially the relationship between power consumption information and simulation time. Among them, power consumption information is related to logical design data (cell quantity and type, cell flip rate in waveform, working clock frequency, cell output load and other factors), and simulation time comes from the input waveform. In other words, the partition-level current distribution information is related to the logical design data of each module (i.e., cell) in the partition, and does not depend on the physical design data of each partition in the chip design.

[0084] Based on the above analysis, in an embodiment of the present invention, a corresponding data extraction strategy is designed based on the type characteristics of the design data of each partition, so that when the chip power consumption model data is extracted based on the design data of each partition, each type of design data can be extracted in a targeted manner, thereby making the extraction process of the design data of each partition independent.

[0085] The partition division information of the chip design described above can be determined based on the design requirements of the chip design and the simulation tool for simulating the chip design. In other words, the partition division information includes each partition divided according to the design requirements of the chip design, and the division of each partition meets the simulation analysis of the simulation tool for the chip design.

[0086] Therefore, for the logic design data of the logic design type, an embodiment of the present invention proposes a first data extraction strategy, in which a corresponding first extraction method is defined to extract the logic design data through the first extraction method to form partial data in the chip power consumption model data (i.e., partition-level current distribution information).

[0087] Based on the above content, it can be known that the partition-level current distribution information in the chip power consumption model data is extracted based on the partitions after the chip design is divided. Partitioning usually refers to dividing a large chip design into smaller, more manageable parts. These partitions can be divided based on different functional modules, power domains, clock domains, etc. The purpose of partitioning is to simplify the design process, improve design efficiency, and optimize power consumption management. Each partition can be independently synthesized, laid out, and routed, and can have different design constraints and requirements.

[0088] In chip design, a cell usually refers to a predefined, reusable hardware building block, which can be a logic gate, a flip-flop, a multiplier, a memory unit, etc. In the hierarchical design of a chip, a cell is the basic unit that makes up a larger circuit. At different stages of chip design, a cell can refer to different levels of modules, from the logic unit in the logic synthesis stage to the placement unit in the physical design stage.

[0089] That is, in the design of the chip, a partition after the chip design is divided can contain multiple cells. In other words, a partition is a logical or physical division of a part of the chip design, and a cell is the basic module or unit that constitutes a partition. At the same time, according to the above analysis, it can be seen that the partition-level current distribution information is related to the logic design data (cell quantity and type, cell flip rate in the waveform, working clock frequency, cell output load and other factors). Therefore, the first extraction method defined in the embodiment of the present invention preliminarily converts the logic design data of each partition into module-level logic design data, and then processes the corresponding module-level logic design data based on the modules included in each partition in the partition division information to obtain the first extracted data of each partition (i.e., partition-level current distribution information).

[0090] In some other implementations, the type of the design data may further include: a physical design type; and determining, based on the type of the design data, a processing path for processing each type of the design data includes:

[0091] determining a second processing path for the physical design data based on the physical design data of the physical design type;

[0092] In each processing path, an extraction method for extracting design data is defined to form a corresponding data extraction strategy, including:

[0093] In the second processing path, a second extraction method for extracting the physical design data is defined as:

[0094] Extracting the parasitic parameters of the power distribution network at the partition level from the physical design data to obtain second extracted data;

[0095] A second data extraction strategy is formed.

[0096] Chip design also includes back-end physical design. When simulating chip design, the back-end physical design must also be simulated. At this time, the type of design data of chip design is physical design type. Therefore, in order to be able to independently extract the design data, the embodiment of the present invention also defines a targeted data extraction strategy for the physical design data of the physical design type.

[0097] For physical design data of a physical design type, a second data extraction strategy using a second extraction method on a second processing path is defined.

[0098] Based on the above content, it can be known that the chip power consumption model data includes not only the partition-level current distribution information, but also the partition-level power distribution network parasitic parameters (Partition PDN RLC).

[0099] Among them, parasitic parameters RLC (resistance R, inductance L and capacitance C) are parameters that describe the characteristics of non-ideal components in the circuit, and they have an important impact on the performance of the circuit. Since the physical design data describes the complete physical design information of the chip design, the parasitic parameters of the partition-level power distribution network can be extracted directly based on the physical design data to provide more accurate and comprehensive parasitic parameters.

[0100] In other words, the extraction of the parasitic parameters of the partition-level power distribution network in the chip power consumption model data mainly depends on the physical design data. This is because:

[0101] From a typical PDN perspective, when observing the chip design from a PCB perspective, the circuit of the chip design can be equivalent to a series RLC circuit with a series resistor.

[0102] Please refer to Figure 2a and Figure 2b , Figure 2a is a schematic diagram of a chip power consumption model provided by an embodiment of the present invention, Figure 2b yes Figure 2a The simplified model corresponding to the chip power consumption model shown.

[0103] like Figure 2a As shown, in a power distribution network (PDN) within a chip design (Die), each cell (unit or module) can be regarded as a circuit formed by a decoupling capacitor (Decap), an inductor, a metal wire (wire), and a cell switching current (cell switching current).

[0104] like Figure 2b As shown, for Figure 2a The chip power consumption model shown can be simplified into an RLC model. The RLC model is an equivalent circuit model and can be regarded as a simplified model of the chip power consumption model.

[0105] Among them, R Die Indicates the PG (Power Grid) parasitic resistance and L Die represents the parasitic inductance of the metal conductor, C Die Represents parasitic capacitance. The total switching current represents all circuit units in the chip design and can be equivalent to a current source model.

[0106] Parasitic resistance comes from the metal lines of the PG power network (the network structure used for power supply in chip design). For large-scale chip design, the PG power network consists of two parts: high-level PGRDL (power routing in the high-level metal layer) and PG mesh (the power network structure built inside the chip design, usually composed of horizontal and vertical power straps), which are generated and planned according to a fixed pattern.

[0107] After the pattern is determined, the parasitic resistance information of the power grid will not change. The parasitic capacitance in the chip design includes PG cap (Power Grid capacitance, parasitic capacitance in the power grid) and Std cell cap (Standard Cell capacitance, parasitic capacitance in the standard cell). Among them, the total parasitic capacitance in the chip design mainly comes from PG cap.

[0108] PG cap is directly related to the physical pattern of PG power network. Changes in logic design will cause changes in the number of instances in chip design, which will affect the number of Decap (decoupling capacitor) cells in the standard cell library. However, from the order of magnitude of capacitance, the capacitance value of PG cap is much larger than that of Decap cell in the standard cell library. The slight change in the number of Decap cells caused by logic design changes can be ignored for the total parasitic capacitance in the full chip die.

[0109] Since the inductance has little effect on power consumption, the parasitic inductance of the chip design has limited impact on the chip power consumption model.

[0110] It can be seen that the PDN RLC parasitic parameters in the chip power consumption model data are strongly correlated with the physical design data of the chip power network and weakly correlated with the logical design. Based on this, the embodiment of the present invention defines an independent second data extraction strategy for the physical design data of the physical design type.

[0111] That is, in the second processing path, the second extraction method only extracts the physical design data.

[0112] After the definition of the first data extraction strategy and the second data extraction strategy is completed, the first data extraction strategy can be used to extract the logical design data of the logical design type, and the second data extraction strategy can be used to extract the physical design data of the physical design type. Therefore, in one embodiment, step S102 may include:

[0113] For each partition, determining a first data extraction strategy based on the logical design data of the logical design type; and determining a second data extraction strategy based on the physical design data of the physical design type;

[0114] Step S103 includes:

[0115] The first data extraction strategy is used to extract data from the logic design data to obtain first extracted data; and the second data extraction strategy is used to extract data from the physical design data to obtain second extracted data.

[0116] After determining that the type of the design data is a logic design type, a defined first data extraction strategy is used to extract data from the logic design data to obtain first extracted data (partition-level current distribution information) used to form chip power consumption model data.

[0117] The second extracted data is the partition-level power distribution network parasitic parameters in the chip power consumption model data.

[0118] The embodiment of the present invention implements corresponding independent data extraction strategies for different types of design data. On the one hand, the data extraction process can be independent, reducing the dependence on input data (physical design data and logical design data) when extracting the chip power consumption model data of each partition, thereby reducing the number of iterations for extracting the chip power consumption model data; on the other hand, the data extraction process of each partition is split into two parts according to the type of design data, increasing the number of subtasks for data type division and data extraction, thereby improving the overall running time and reducing the time for generating chip power consumption model data.

[0119] In one implementation, the logic design data includes signal waveform data formed after simulation of the chip design in different working scenarios and working modes, and logical connection relationship data of modules in each partition in the chip design; extracting data from the logic design data using the first data extraction strategy to obtain the first extracted data may include:

[0120] Generate module-level power consumption waveform data using the signal waveform data and the logic connection relationship data of the module;

[0121] Converting the module-level power consumption waveform data into module-level power consumption time relationship data, wherein the module-level power consumption time relationship data describes a change trend of power consumption and time of each module;

[0122] Converting the power consumption value in the module-level power consumption time relationship data into a current value to form module-level current time relationship data as the module-level logic design data;

[0123] Determine each partition divided in the chip design and each module in each partition according to the partition division information of the chip;

[0124] For each partition, determine the modules used in different working scenarios and working modes, merge the module-level current-time relationship data corresponding to each determined module, and obtain the partition-level current distribution information of each partition as the first extracted data.

[0125] The signal waveform data is generated after the chip design is simulated under different working scenarios and working modes. Therefore, it can meet the needs of determining the usage of each module contained in each partition under various working scenarios and working modes in the subsequent chip design simulation process, thereby ensuring the accuracy of the first extracted data.

[0126] For example, a partition P includes three modules: module A, module B and module C. In different working scenarios and working modes, the modules used by partition P are different. For example, when the partition P is in the working scenario and working mode of data processing and calculation, it may use a module that can perform arithmetic operations (such as module C). Module C can be a logic unit (ALU), a multiplier, an accumulator, a register, etc., which is responsible for performing various mathematical operations, such as addition, subtraction, multiplication, division, and more complex algorithm operations.

[0127] If the partition P is in a working scenario and working mode for data transmission, a large number of interface modules (such as module B and module A) may be used, such as serial interfaces, Ethernet controllers, etc. These modules are responsible for transmitting data between the chip and external devices.

[0128] It can be seen that in different working scenarios and working modes, the same partition uses different modules, and the module-level current-time relationship data used when obtaining the first extracted data is also different. Therefore, using the signal waveform data formed after the chip design is simulated in different working scenarios and working modes as the input data for extracting the first extracted data can ensure the accuracy of the first extracted data.

[0129] Since the module-level current-time relationship data can describe the changing trend of the power consumption and time of each module, and the module-level current-time relationship data is obtained based on the signal waveform data formed after simulation in different working scenarios and working modes, as well as the logical connection relationship data of each module in the chip, the module-level current-time relationship data corresponds to the working scenario and working mode of the chip. In the process of obtaining the first extracted data based on the module-level current-time relationship data, the module-level current-time relationship data can be accurately merged according to the usage of each partition for the modules it contains in different working scenarios and working modes of the chip.

[0130] Continuing with the aforementioned partition P including module A, module B and module C, partition P is in a working scenario and working mode of data transmission, and module A and module B are used as an example for explanation.

[0131] Utilizing the first data extraction strategy, the signal waveform data A11 of module A in the working scenario and working mode of data transmission and the logical connection relationship data of each module are processed through an EDA (Electronic Design Automation) tool to generate module-level power consumption waveform data A12 of module A; the module-level power consumption waveform data A12 is then converted into module-level power consumption time relationship data A13, wherein A13 describes how the power consumption of module A changes with time during the working process under the working scenario and working mode of data transmission, that is, describes the power consumption value pi generated by module A at each time point ti during the working time period (data transmission time period), where i is the time point divided within the time period.

[0132] The power consumption value in A13 is then converted into a current value, thereby forming module-level current-time relationship data A14 (module-level logic design data).

[0133] Similarly, the module-level current-time relationship data B14 (module-level logic design data) of module B in the working scenario and working mode of the data transmission can be obtained.

[0134] In the working scenario and working mode for data transmission, when the module-level current-time relationship data A14 and B14 of module A and module B are merged, the power consumption values ​​at the same time point can be accumulated to obtain the partition-level current distribution information of partition P (first extraction data).

[0135] Complete the extraction of partition-level current distribution information in the chip power consumption model data.

[0136] In one embodiment, the signal waveform data is obtained based on a waveform file obtained during signal simulation during the logic design process of the chip design; the logical connection relationship data of each module in the chip design is obtained based on a netlist file formed during the logic design process of the chip design and used to describe the logical connection relationship of the circuit.

[0137] The logic design data is input data when extracting chip power consumption model data. For example, it can provide waveform files and netlist files that describe the circuit logic connection relationship of each module to front-end engineers. Front-end engineers can perform simulations based on different working modes and working scenarios according to the power supply design and power consumption optimization target requirements of the chip design, and generate waveform files formed by corresponding gate-level waveforms according to changes in the logical connection relationship of the modules.

[0138] Waveform files are used to record the changes of circuit signals over time, including the changes in signal values ​​during simulation, and can be used to analyze the behavior and performance of circuits. Waveform files are usually generated by simulation tools after the simulation is completed and can be opened and analyzed with a specific waveform viewer.

[0139] Common formats of waveform files include VCD (Value Change Dump), FSDB (Fast Signal Database), WLF (Wave Log File), etc. These file formats can record complete signal change information, allowing users to reproduce the behavior of the circuit after simulation and perform detailed analysis. For example, a VCD file is an ASCII file defined in the IEEE1364 standard. It contains header information, predefined variables, and variable value change information, and can be used to reproduce simulations and display waveforms.

[0140] A netlist file is a file used to describe the connection relationship between circuit elements (circuit logical connection relationship), usually a text file. It contains the cells used in the chip design circuit, their electrical characteristics, and their connection information. In digital IC design, the netlist file describes the logical function and connection relationship of the circuit in the chip design, including various logic gates, registers, triggers and other components and the connections between them.

[0141] The netlist file can be generated by a logic synthesis tool based on the design input (usually RTL design, Register Transfer Level) and Lib file. It contains the logic and connection information of the chip design and can be used for subsequent simulation, imported into other tools for subsequent processing, or directly downloaded to an FPGA (Field-Programmable Gate Array) for verification and deployment.

[0142] By processing the above-mentioned files, logic design data is obtained, which is used as input data for subsequent extraction to obtain first extracted data.

[0143] Therefore, after acquiring the logic design data, the first data extraction strategy provided by the embodiment of the present invention can be adopted, and the first extraction method defined on the first processing path can be used to extract the logic design data to obtain the partition-level current distribution information.

[0144] To achieve accurate acquisition of the second extracted data, the physical design data includes physical package layout data of the chip design; the step of extracting data from the physical design data using the second data extraction strategy to obtain the second extracted data includes:

[0145] The physical data extraction strategy is used to extract data from the physical package layout data to obtain partition-level power distribution network parasitic parameters as second extracted data.

[0146] The physical package layout data corresponds to the physical package design of the chip and describes the back-end physical design of the chip design.

[0147] In one embodiment, the physical package layout data is obtained based on a solder joint location file, a power / ground redistribution layer design exchange format file, and a physical information description file of the module formed during the chip design packaging and circuit board layout process.

[0148] The solder point location file may be a Bump ploc (Bump Location) file provided by a back-end top-level design engineer after completing the solder bump (Bump) planning of the full-chip design and the PGRDL connection of the full-chip design, which contains the PG power source information of the full-chip design; the power / ground redistribution layer design exchange format file may be a PG RDL def (Power Grid Redistribution Layer definition file) file provided by a top-level design engineer in the back-end physical design, which contains the PGRDL physical information of the full chip; the physical information description file of the module may be a Block DEF File generated after the back-end module engineer completes the module-level layout and routing, which contains the module-level physical design information.

[0149] By processing the above-mentioned files, physical design data is obtained, which is used as input data for subsequent extraction to obtain second extracted data.

[0150] In the existing solutions for extracting chip power consumption model data, the input files are also solder joint location files, power / ground redistribution layer design exchange format files, module physical information description files, waveform files under different working scenarios and working models, and netlist files. Figure 3 As shown, Figure 3 It is a schematic diagram of an implementation process of obtaining chip power consumption model data based on a unified extraction method provided by an embodiment of the present invention.

[0151] like Figure 3 As shown, the process includes:

[0152] Step 1: Obtain design data of each partition in the chip design based on each read file.

[0153] The files read in step 1 are those mentioned above: solder point location file, power / ground redistribution layer design exchange format file, module physical information description file, waveform files under different working scenarios and working models, and netlist file; data is extracted from each file to obtain design data for each partition.

[0154] Step 2: extract the design data of each partition.

[0155] Step 2 can use EDA tools to directly extract chip power consumption model data from the design data of each partition in each file read;

[0156] Step 3: Obtain chip power consumption model data of each partition.

[0157] The chip power consumption model data includes: partition-level current distribution information (Partition PWL) and partition-level power distribution network parasitic parameters (Partition PDN RLC).

[0158] It can be seen that in the commonly used scheme of the CPM data extraction process, the above-mentioned files are usually read in based on the default process of the EDA tool, and the EDA tool directly performs unified data extraction, and generates a chip power consumption model data containing partition-level current distribution information and partition-level power distribution network parasitic parameters by default.

[0159] During chip simulation (PI simulation), the impact of current distribution information on chip design simulation is mainly reflected in improving simulation accuracy and efficiency. Current distribution information can more accurately simulate current changes in actual circuits by providing piecewise linear current waveforms, especially in the time domain noise analysis of power distribution networks (PDNs). Chip simulation engineers can use current distribution information as the current load for transient analysis, combined with the PDN RLC parasitic parameters (power distribution network parasitic parameters) obtained by C4 bump (ControlledCollapse Chip Connection) to provide more realistic and accurate noise values.

[0160] but, Figure 3 In the process shown, extracting chip power consumption model data once needs to rely on multiple input files at the same time, that is, logical design data or physical design data in multiple data files. When any type of design data is changed or adjusted, the entire CPM data extraction process needs to be iterated again. As the scale of chip design continues to increase and the complexity of design increases, the amount of design data partitioned in each file will also increase, thereby increasing the time to generate chip power consumption model data and the iteration time to generate chip power consumption model data after each chip design update.

[0161] Based on this, an embodiment of the present invention provides an improved method for extracting chip power consumption model data, so that the extraction process of different types of design data for each partition can be carried out independently, so as to reduce the iteration of the entire CPM data extraction process when the design data is changed or adjusted, and at the same time increase the data extraction strategy execution steps that can execute data extraction in parallel, thereby improving the overall running time of a data extraction.

[0162] Please refer to Figure 4 , Figure 4 It is a schematic diagram of an implementation process of obtaining chip power consumption model data by an independent extraction method provided by an embodiment of the present invention.

[0163] like Figure 4 As shown, the process includes:

[0164] Step 1: Obtain design data of each partition in the chip design based on each read file.

[0165] Step 1 can also be obtained by reading the above-mentioned files. Among them, each file can be read by PTPX (PrimeTimePX, used for power consumption evaluation of chip design) tool.

[0166] For each type of design data, perform the following two steps in parallel:

[0167] Step 2.1, determining the waveform files obtained by simulation under different working scenarios and working models and the data read from the netlist file as logic design data of the logic design type;

[0168] Step 2.2, determining the data read from the solder point location file, the power / ground redistribution layer design exchange format file, and the module physical information description file as physical design data of a physical design type.

[0169] Step 3 consists of two steps performed in parallel:

[0170] Step 3.1, adopting a first data extraction strategy for logic design data to obtain partition-level current distribution information as first extracted data.

[0171] Wherein, in step 3.1, a first data extraction strategy is adopted, and data is extracted using a first extraction method on a first processing path, including:

[0172] Step 3.11, using an EDA tool to generate a module-level power consumption waveform file based on the waveform file and the netlist file, the module-level power consumption waveform file contains module-level power consumption waveform data.

[0173] In this step, the PTPX tool can be used to read in the netlist file containing the design timing constraints and the netlist corresponding to the module's logic design. Based on the waveform file under the corresponding working mode and working scenario (the waveform file contains gate-level waveforms), the power consumption analysis engine of the EDA tool is called to generate a module-level power consumption waveform file (a curve showing the relationship between power consumption and time) related to the gate-level waveform in the waveform file.

[0174] Step 3.12, converting the power consumption value in the module-level power consumption time relationship data into a current value to form module-level current time relationship data as module-level logic design data.

[0175] In this step, the generated power consumption waveform file can be converted into a text format of a power consumption and time curve using the interface processed by FSDB. In step 3.12, a script file can be defined by the user to convert the power consumption value into a current value to obtain the circuit time relationship data.

[0176] Step 3.13, determine the partitions and modules within each partition based on the partition division information of the chip design; and for each partition, determine the modules used by the chip design in different working scenarios and working modes, merge the module-level current-time relationship data, and obtain the partition-level current distribution information as the first extracted data.

[0177] That is, according to the information of the modules included in the partition planning, based on different working scenarios and working modes, the module-level current distribution information of each module in the partition is superimposed in the same time period to generate the partition-level current distribution information.

[0178] Step 3.2, adopting a second data extraction strategy for the physical design data to obtain the parasitic parameters of the partition-level power distribution network as the second extracted data.

[0179] For the physical design data of the physical design type, the second data extraction strategy is adopted. On the second processing path, the second extraction method is used to directly extract the partition-level power distribution network parasitic parameters from the physical design data through the EDA tool as the second extracted data. The extraction of the partition-level power distribution network parasitic parameters does not rely on the logical design data such as the waveform file generated by the front end, but is only related to the physical design data of the chip design.

[0180] Step 4: merge the first extracted data and the second extracted data to obtain chip power consumption model data.

[0181] based on Figure 3 and Figure 4 It can be seen from the flow that, compared with the implementation flow corresponding to the unified extraction method, the implementation flow corresponding to the improved independent extraction method proposed in the embodiment of the present invention can divide the extraction process (generation process) of the chip power consumption model data into two branches for independent and parallel execution. Therefore, in the process of obtaining the chip power consumption model data of each partition, it will not rely on both the logical design data and the physical design data at the same time.

[0182] Therefore, if one of the logical design data is changed or adjusted, only the first data extraction strategy needs to be adopted, and the first extraction method is used on the first processing path to update the generated partition-level current distribution information. Conversely, if one of the physical design data is changed or adjusted, only the second data extraction strategy needs to be adopted, and the second extraction method is used on the second processing path to update the generated partition-level power distribution network parasitic parameters.

[0183] To facilitate understanding of the chip design simulation method provided by the embodiment of the present invention, when the chip design is updated, the number of iterations of data extraction is reduced, please refer to Figure 5 , Figure 5 It is another flowchart of the simulation method for chip design provided by an embodiment of the present invention.

[0184] like Figure 5 As shown, the method may include the following steps:

[0185] Step S300, defining a corresponding data extraction strategy based on the type of design data.

[0186] Step S301, obtaining design data of each partition in chip design.

[0187] Step S302, determining whether the chip design has been updated, if not, executing step S303, if yes, executing step S305.

[0188] Step S303: for each partition, determine a corresponding data extraction strategy based on the type of the design data.

[0189] Step S304: extract data from the corresponding type of design data using the determined data extraction strategy to obtain extracted data corresponding to each type of design data.

[0190] Step S305 , determining the design data changed due to the design update in the design data of each partition, and determining a corresponding data extraction strategy based on the type of the changed design data.

[0191] A data extraction strategy is determined based on the type of changed design data, so that data is extracted from the changed design data but not from the unchanged design data.

[0192] Step S306, extracting data from the changed design data using the determined data extraction strategy to obtain extracted data corresponding to the type of the changed design data, and obtaining extracted data corresponding to the type of the unchanged design data obtained before the chip design is updated.

[0193] When a design update occurs in the chip design, a corresponding data extraction strategy is determined based on the type of design data changed by the design update, so as to extract data from the changed design data and not extract data from the unchanged design data.

[0194] For example, after extracting chip power consumption model data for a chip design, if the chip design is updated (for example, a module in the chip design is optimized), the type of the changed design data can be determined based on the design data that is changed due to the design update, and then the data extraction strategy corresponding to the type of the changed design data is used to re-extract data only for the changed design data; while for the unchanged design data (that is, the design data of the part of the chip design that has not been updated), data extraction is no longer performed, thereby achieving independent data extraction for each type of design data, avoiding data extraction for all design data when the chip design is updated, and reducing the number of data extraction iterations.

[0195] The type of the changed design data may be a logical design type or a physical design type.

[0196] Step S307 , merging the extracted data corresponding to each type of design data to form chip power consumption model data of each partition.

[0197] Step S308 , using the chip power consumption model data of each partition to simulate chip design.

[0198] Based on the above Figure 3 and Figure 4 The basic implementation process of extracting chip power consumption model data for each partition shown is different in the corresponding process and efficiency when extracting chip power consumption model data for large-scale chip design.

[0199] Please combine Figure 6 refer to Figure 7 , Figure 6 It is a structural schematic diagram of a chip design provided by an embodiment of the present invention. Figure 7 is Figure 3 FIG. 1 is a schematic diagram of the chip power consumption model data extraction process for each partition under the unified extraction method. FIG.

[0200] As the size of chip design increases, for large-scale chip design, there are multiple modules in the full chip design, and the same module is reused, such as Figure 6 The modules A_0 and A_1 shown are the multiplexing of module A.

[0201] Therefore, the hierarchical relationship of chip design becomes more complicated. At the same time, due to the limitations of chip simulation tools, the extraction of chip power consumption model data for full chip design needs to be processed in multiple partitions.

[0202] like Figure 6As shown, for the sake of convenience, a chip design including two partitions: Partition_1 and Partition_2, and three modules: Block A, Block B, and Block C is taken as an example for explanation.

[0203] Block A is reused twice in the chip design, and the corresponding instantiation names are A_0 and A_1. Based on the design requirements of chip design and the limitations of simulation tools, Figure 6 As shown in the figure, Block A (A_0) and Block B are divided into a partition named Partition_1, and Block A (A_1) and Block C are divided into a partition named Partition_2.

[0204] by Figure 6 Taking the structure of the chip design shown in the figure as an example, the process of extracting the chip power consumption model data of the chip design using a unified extraction method is as follows: Figure 7 shown.

[0205] like Figure 7 As shown, the design data of Partition_1 is obtained based on the above files, including: physical design data (Block A_physical) of module A (A_0), logical design data (Block A_logic) of module A, physical design data (Block B_physical) of module B, and logical design data (Block B_logic) of module B.

[0206] The design data of Partition_2 is also obtained based on the above files, including: physical design data of module A (A_1) (Block A_physical), logical design data of module A (Block A_logic), physical design data of module C (Block C_physical), and logical design data of module C (Block C_logic).

[0207] For each partition, the chip power consumption model data is uniformly extracted based on the corresponding input data to obtain the chip power consumption model data of each partition: the chip power consumption model data of Partition_1 and the chip power consumption model data of Partition_2.

[0208] visible, Figure 7In the flowchart shown, the design data acquisition step for each partition includes the processing of both logical design data and physical design data. In the data extraction process for each partition, the extraction of partition-level current distribution information and partition-level power distribution network parasitic parameters are coupled together for execution.

[0209] Therefore, from Figure 7 As can be seen from the flowchart, the step of obtaining the design data of Partition_1 depends on the logical design data and physical design data of module A and module B, that is, reading four input variables at a time: Block A_physical, Block A_logic, Block B_physical, Block B_logic. When one of the four input variables changes, it is necessary to perform the process iteration of obtaining the design data of Partition_1 -> extracting the chip power consumption model data of Partition_1 -> obtaining the chip power consumption model data of Partition_1.

[0210] Similarly, the step of obtaining the design data of Partition_2 depends on the logical design data and physical design data of module A and module C, that is, reading four input variables at a time: Block A_physical, Block A_logic, Block C_physical, Block C_logic. When one of the four input variables changes, it is necessary to perform the process iteration of obtaining the design data of Partition_2 -> extracting the chip power consumption model data of Partition_2 -> obtaining the chip power consumption model data of Partition_2.

[0211] The amount of design data processed in each iteration is large, which increases the time for generating chip power consumption model data.

[0212] Continue with Figure 6 The structure of the chip design shown in the figure is used to illustrate the independent extraction method provided by the embodiment of the present invention to extract the chip power consumption model data of each partition. Figure 8 , Figure 8 is Figure 4 Schematic diagram of the chip power consumption model data extraction process for each partition under the independent extraction mode shown.

[0213] like Figure 8As shown, the design data of Partition_1 obtained based on the above files are: physical design data (Block A_physical) of module A (A_0), logical design data (Block A_logic) of module A, physical design data (Block B_physical) of module B, and logical design data (Block B_logic) of module B.

[0214] The input data of Partition_2 obtained based on the above files are: physical design data of module A (A_1) (Block A_physical), logical design data of module A (Block A_logic), physical design data of module C (Block C_physical), and logical design data of module C (Block C_logic).

[0215] After obtaining the design data of each partition, the types of the obtained design data are distinguished in each partition. For example, in Partition_1, the physical design data Block A_physical of module A (A_0) and the physical design data Block B_physical of module B are determined as physical design data of the physical design type; the logical design data Block A_logic of module A and the logical design data Block B_logic of module B are determined as logical design data of the logical design type.

[0216] Similarly, in Partition_2, the physical design data Block A_physical of module A (A_1) and the physical design data Block B_physical of module B are determined as physical design data of the physical design type; the logical design data Block A_logic of module A and the logical design data Block B_logic of module B are determined as logical design data of the logical design type.

[0217] It can be seen that within each partition, the determination of the type of design data is performed in two parallel parts.

[0218] Next, perform independent data extraction on the design data after the type is determined:

[0219] In Partition_1, the first data extraction strategy is adopted for the logic design data to extract the partition-level current distribution information as the first extracted data;

[0220] A second data extraction strategy is adopted for the physical design data to extract the parasitic parameters of the partition-level power distribution network as the second extracted data.

[0221] Similarly, perform the same operation on Partition_2, which will not be repeated here.

[0222] It can be seen that in the case where each partition has a data extraction process executed in parallel, the data extraction process for each partition in the embodiment of the present invention is further divided into two independent parallel data extraction processes: the execution of the first data extraction strategy and the execution of the second data extraction strategy. Therefore, when the number of partitions is the first, the number of subtasks used to execute the data extraction process in parallel in the embodiment of the present invention is twice the number of subtasks used to perform the data extraction process in the unified extraction method.

[0223] The first extracted data and the second extracted data are combined to obtain complete partition-level chip power consumption model data.

[0224] therefore, Figure 8 The process shown is similar to Figure 7 Compared with the process shown in the figure, the design data acquisition step and the chip power consumption model data extraction step have changed from the original parallel execution of generating chip power consumption model data for two partitions to the parallel execution of four parts for two partitions, which improves the running time of data acquisition and data extraction. At the same time, the design data acquisition step of the partition only depends on part of the data of each module in the partition (either logical design data or physical design data), reducing the interactive dependency between the module design data and the output extracted data, and reducing the number of iterations and generation time of chip power consumption model data for each partition of the full chip design.

[0225] Figure 6 The chip design shown includes 3 modules, and 2 partitions are only for example. In actual chip design, the simulation method of chip design provided by the embodiment of the present invention can be used to simulate chip design according to the specific partition division and the use of modules in the partition, so as to bring more obvious benefits in running time and iteration of generating chip power consumption model data.

[0226] The embodiment of the present invention further provides a chip design simulation device, which is used to implement the chip design simulation method described in the above embodiment. Fig. 9 , Fig. 9 It is a structural schematic diagram of a chip design simulation device provided by an embodiment of the present invention.

[0227] like Fig. 9 As shown, the device comprises:

[0228] A data acquisition module 21 is used to acquire design data of each partition in chip design;

[0229] A data extraction strategy determination module 22, configured to determine a corresponding data extraction strategy for each partition based on the type of the design data;

[0230] The data extraction module 23 is used to extract data from the corresponding type of design data using the determined data extraction strategy to obtain extracted data corresponding to each type of design data; and the data extraction of each type of design data is performed in parallel;

[0231] The power consumption model data forming module 24 is used to merge the extracted data corresponding to each type of design data to form chip power consumption model data of each partition;

[0232] The chip design simulation module 25 is used to simulate chip design using the chip power consumption model data of each partition.

[0233] Optionally, the device further comprises:

[0234] A data extraction strategy definition module 20, used to define a corresponding data extraction strategy based on the type of design data;

[0235] The data extraction strategy definition module 20 is used to define corresponding data extraction strategies based on the type of design data, including:

[0236] Based on the type of the design data, determining a processing path for processing each type of the design data;

[0237] In each processing path, an extraction method for extracting design data is defined to form a corresponding data extraction strategy;

[0238] The extracted data obtained by extraction in each processing path using the extraction method are combined to form chip power consumption model data.

[0239] Optionally, the type of the design data includes: a logic design type; the data extraction strategy definition module 20 is used to determine a processing path for processing each type of design data based on the type of the design data, including:

[0240] Determining, based on the logic design data of the logic design type, a first processing path for processing the logic design data;

[0241] The data extraction strategy definition module 20 is used to define an extraction method for extracting design data in each processing path to form a corresponding data extraction strategy, including:

[0242] In the first processing path, a first extraction method for extracting logic design data is defined as:

[0243] Converting the logic design data to form module-level logic design data;

[0244] Processing the module-level logic design data according to the partition division information of the chip design to obtain first extracted data, wherein the partition division information includes each partition after the chip design is divided, and the modules in each partition;

[0245] A first data extraction strategy is formed.

[0246] Optionally, the type of the design data further includes: a physical design type; the data extraction strategy definition module 20 is used to determine a processing path for processing each type of design data based on the type of the design data, including:

[0247] determining a second processing path for the physical design data based on the physical design data of the physical design type;

[0248] The data extraction strategy definition module 20 is used to define an extraction method for extracting design data in each processing path to form a corresponding data extraction strategy, including:

[0249] In the second processing path, a second extraction method for extracting the physical design data is defined as:

[0250] Extracting the parasitic parameters of the power distribution network at the partition level from the physical design data to obtain second extracted data; the physical design data describes complete physical design information of the chip design;

[0251] A second data extraction strategy is formed.

[0252] Optionally, the data extraction strategy determination module 22 is used to determine a corresponding data extraction strategy for each partition based on the type of the design data, including:

[0253] For each partition, determining a first data extraction strategy based on the logical design data of the logical design type; and determining a second data extraction strategy based on the physical design data of the physical design type;

[0254] The data extraction module 23 is used to extract data from the corresponding type of design data using the determined data extraction strategy to obtain the extracted data corresponding to each type of design data, including:

[0255] The first data extraction strategy is used to extract data from the logic design data to obtain first extracted data; and the second data extraction strategy is used to extract data from the physical design data to obtain second extracted data.

[0256] Optionally, the device further comprises:

[0257] A chip design update judgment module, used to judge whether the chip design has a design update;

[0258] If yes, then, in the design data of each partition, the design data changed due to the design update is determined, and based on the type of the changed design data, a corresponding data extraction strategy is determined to extract data for the changed design data, but not for the unchanged design data;

[0259] If not, the data extraction strategy determination module 22 is used to determine a corresponding data extraction strategy for each partition based on the type of the design data.

[0260] Optionally, the logic design data includes signal waveform data formed after simulation of the chip design in different working scenarios and working modes, and logical connection relationship data of modules in each partition in the chip design; the data extraction module 23 is used to extract data from the logic design data using the first data extraction strategy to obtain first extracted data, including:

[0261] Generate module-level power consumption waveform data using the signal waveform data and the logic connection relationship data of the module;

[0262] Converting the module-level power consumption waveform data into module-level power consumption time relationship data, wherein the module-level power consumption time relationship data describes a change trend of power consumption and time of each module;

[0263] Converting the power consumption value in the module-level power consumption time relationship data into a current value to form module-level current time relationship data as the module-level logic design data;

[0264] Determine each partition in the chip design and each module in each partition according to the partition division information of the chip design;

[0265] For each partition, determine the modules used in different working scenarios and working modes, merge the module-level current-time relationship data corresponding to each determined module, and obtain the partition-level current distribution information of each partition as the first extracted data.

[0266] Optionally, the chip design simulation module 25 is a power integrity verification module.

[0267] The power integrity verification module PI takes the chip power consumption model data as input and simulates the chip.

[0268] It can be seen that the technical solution provided by the embodiment of the present invention first distinguishes the types of design data of each partition in the process of extracting chip power consumption model data; then uses the data extraction strategy corresponding to each type to complete the execution of the data extraction process under the design data of that type, and finally merges the data extraction results (extracted data) under each type to obtain the final chip power consumption model data. Since the data extraction strategy is defined in a one-to-one correspondence with the type of design data, the data extraction strategies of different types of design data are independent, and the data extraction of each type of design data is performed in parallel; therefore, when extracting data from each partition, the data extraction strategy corresponding to the type of design data can be used to independently and parallelly execute the data extraction steps, thereby increasing the number of subtasks (programs for executing data extraction) used to execute the data extraction steps in a partition, improving the execution speed of the data extraction steps, and reducing the time consumption when extracting chip power consumption model data, thereby achieving the purpose of optimizing the extraction efficiency of chip power consumption model data and improving the simulation efficiency of chip design.

[0269] An embodiment of the present invention provides an electronic device, such as a terminal device, a server device, or other computer device, comprising a memory and a processor, wherein the memory stores a program, and the processor calls the program stored in the memory to execute a chip design simulation method as described in any of the aforementioned embodiments.

[0270] An embodiment of the present invention provides a storage medium storing a program, and when the program is executed, the simulation method for chip design as described in any of the above embodiments is implemented.

[0271] An embodiment of the present invention provides a computer program product, including a computer program, which, when executed by a processor, implements the chip design simulation method as described in any one of the above embodiments.

[0272] The above describes multiple implementation schemes provided by the embodiments of the present invention. The various optional methods introduced in the implementation schemes can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present invention.

[0273] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A chip design simulation method, characterized in that: include: Obtain design data for each partition in chip design; For each partition, based on the type of the design data, determine a corresponding data extraction strategy; Using the determined data extraction strategy, extract data from the corresponding type of design data to obtain extracted data corresponding to each type of design data; and the data extraction of each type of design data is performed in parallel; Merge the extracted data corresponding to each type of design data to form partitioned chip power consumption model data; The chip power consumption model data of each partition is used to simulate the chip design.

2. The chip design simulation method according to claim 1, characterized in that: Before determining the corresponding data extraction strategy for each partition based on the type of the design data, the method further includes: defining the corresponding data extraction strategy based on the type of the design data; The method of defining a corresponding data extraction strategy based on the type of design data includes: Based on the type of the design data, determining a processing path for processing each type of the design data; In each processing path, an extraction method for extracting design data is defined to form a corresponding data extraction strategy; The extracted data obtained by extraction in each processing path using the extraction method are combined to form chip power consumption model data.

3. The chip design simulation method according to claim 2, characterized in that: The type of the design data includes: a logic design type; and determining a processing path for processing each type of the design data based on the type of the design data includes: Determining, based on the logic design data of the logic design type, a first processing path for processing the logic design data; In each processing path, an extraction method for extracting design data is defined to form a corresponding data extraction strategy, including: In the first processing path, a first extraction method for extracting logic design data is defined as: Converting the logic design data to form module-level logic design data; Processing the module-level logic design data according to the partition division information of the chip design to obtain first extracted data, wherein the partition division information includes each partition after the chip design is divided, and the modules in each partition; A first data extraction strategy is formed.

4. The chip design simulation method according to claim 3, characterized in that: The type of the design data further includes: a physical design type; and determining a processing path for processing each type of the design data based on the type of the design data includes: determining a second processing path for the physical design data based on the physical design data of the physical design type; In each processing path, an extraction method for extracting design data is defined to form a corresponding data extraction strategy, including: In the second processing path, a second extraction method for extracting the physical design data is defined as: Extracting the parasitic parameters of the power distribution network at the partition level from the physical design data to obtain second extracted data; the physical design data describes complete physical design information of the chip design; A second data extraction strategy is formed.

5. The chip design simulation method according to any one of claims 1 to 4, characterized in that: The step of determining a corresponding data extraction strategy for each partition based on the type of the design data includes: For each partition, determining a first data extraction strategy based on the logical design data of the logical design type; and determining a second data extraction strategy based on the physical design data of the physical design type; The method of extracting data from the corresponding type of design data by using the determined data extraction strategy to obtain the extracted data corresponding to each type of design data includes: Extracting data from the logic design data using the first data extraction strategy to obtain first extracted data; And, extracting data from the physical design data using the second data extraction strategy to obtain second extracted data.

6. The chip design simulation method according to claim 5, characterized in that: The logic design data includes signal waveform data formed after simulation of the chip design in different working scenarios and working modes, and logical connection relationship data of modules in each partition in the chip design; The step of extracting data from the logic design data using the first data extraction strategy to obtain first extracted data includes: Generate module-level power consumption waveform data using the signal waveform data and the logic connection relationship data of the module; Converting the module-level power consumption waveform data into module-level power consumption time relationship data, wherein the module-level power consumption time relationship data describes a change trend of power consumption and time of each module; Converting the power consumption value in the module-level power consumption time relationship data into a current value to form module-level current time relationship data as the module-level logic design data; Determine each partition in the chip design and each module in each partition according to the partition division information of the chip design; For each partition, determine the modules used in different working scenarios and working modes, merge the module-level current-time relationship data corresponding to each determined module, and obtain the partition-level current distribution information of each partition as the first extracted data.

7. The chip design simulation method according to claim 6, characterized in that: The signal waveform data is obtained based on the waveform file obtained during signal simulation in the logic design process of the chip design; the logical connection relationship data of each module in the chip design is obtained based on the netlist file formed in the logic design process of the chip design and used to describe the circuit logical connection relationship.

8. The chip design simulation method according to claim 5, characterized in that: The physical design data includes physical package layout data of chip design; The step of extracting data from the physical design data using the second data extraction strategy to obtain second extracted data includes: The physical data extraction strategy is used to extract data from the physical package layout data to obtain partition-level power distribution network parasitic parameters as second extracted data.

9. The chip design simulation method according to claim 8, characterized in that: The physical package layout data is obtained based on the solder joint location file, the power / ground redistribution layer design exchange format file, and the physical information description file of the module formed during the chip design packaging and circuit board layout process.

10. The chip design simulation method according to any one of claims 1 to 4, characterized in that: After the step of obtaining the design data of each partition in the chip design, the method further includes: Determining whether there is a design update of the chip design; If yes, then, in the design data of each partition, the design data changed due to the design update is determined, and based on the type of the changed design data, a corresponding data extraction strategy is determined to extract data for the changed design data, but not for the unchanged design data; If not, the step of determining a corresponding data extraction strategy for each partition based on the type of the design data is executed.

11. A chip design simulation device, characterized in that: include: A data acquisition module, used to acquire design data of each partition in chip design; A data extraction strategy determination module, used for determining a corresponding data extraction strategy for each partition based on the type of the design data; A data extraction module is used to extract data from the corresponding type of design data using the determined data extraction strategy to obtain extracted data corresponding to each type of design data; and the data extraction of each type of design data is performed in parallel; The power consumption model data forming module is used to merge the extracted data corresponding to each type of design data to form the chip power consumption model data of each partition; The chip design simulation module is used to simulate chip design using chip power consumption model data of each partition.

12. The chip design simulation device according to claim 11, characterized in that: Also includes: A data extraction strategy definition module is used to define corresponding data extraction strategies based on the type of design data; The data extraction strategy definition module is used to define the corresponding data extraction strategy based on the type of design data, including: Based on the type of the design data, determining a processing path for processing each type of the design data; In each processing path, an extraction method for extracting design data is defined to form a corresponding data extraction strategy; The extracted data obtained by extraction in each processing path using the extraction method are combined to form chip power consumption model data.

13. The chip design simulation device according to claim 12, characterized in that: The type of the design data includes: a logic design type; the data extraction strategy definition module is used to determine a processing path for processing each type of design data based on the type of the design data, including: Determining, based on the logic design data of the logic design type, a first processing path for processing the logic design data; The data extraction strategy definition module is used to define an extraction method for extracting design data in each processing path to form a corresponding data extraction strategy, including: In the first processing path, a first extraction method for extracting logic design data is defined as: Converting the logic design data to form module-level logic design data; Processing the module-level logic design data according to the partition division information of the chip design to obtain first extracted data, wherein the partition division information includes each partition after the chip design is divided, and the modules in each partition; A first data extraction strategy is formed.

14. The chip design simulation device according to claim 13, characterized in that: The type of the design data further includes: a physical design type; the data extraction strategy definition module is used to determine a processing path for processing each type of design data based on the type of the design data, including: determining a second processing path for the physical design data based on the physical design data of the physical design type; The data extraction strategy definition module is used to define an extraction method for extracting design data in each processing path to form a corresponding data extraction strategy, including: In the second processing path, a second extraction method for extracting the physical design data is defined as: Extracting the parasitic parameters of the power distribution network at the partition level from the physical design data to obtain second extracted data; the physical design data describes complete physical design information of the chip design; A second data extraction strategy is formed.

15. The chip design simulation device according to any one of claims 11 to 14, characterized in that: The data extraction strategy determination module is used to determine the corresponding data extraction strategy for each partition based on the type of the design data, including: For each partition, determining a first data extraction strategy based on the logical design data of the logical design type; and determining a second data extraction strategy based on the physical design data of the physical design type; The data extraction strategy determination module is used to extract data from the corresponding type of design data using the determined data extraction strategy to obtain the extracted data corresponding to each type of design data, including: The first data extraction strategy is used to extract data from the logical design data to obtain first extracted data; and the second data extraction strategy is used to extract data from the physical design data to obtain second extracted data.

16. The chip design simulation device according to any one of claims 11 to 14, characterized in that: Also includes: A chip design update judgment module, used to judge whether the chip design has a design update; If yes, then determining the design data changed due to the design update in the design data of each partition, and determining a corresponding data extraction strategy based on the type of the changed design data, so as to extract data for the changed design data and not extract data for the unchanged design data; If not, the data extraction strategy determination module is used to determine a corresponding data extraction strategy for each partition based on the type of the design data.

17. The chip design simulation device according to any one of claims 11 to 14, characterized in that: The chip design simulation module is a power integrity verification module.

18. An electronic device, characterized in that: It comprises a memory and a processor, the memory stores a program, and the processor calls the program stored in the memory to execute the chip design simulation method according to any one of claims 1 to 11.

19. A storage medium, characterized in that: The storage medium stores a program, and when the program is executed, the simulation method for chip design according to any one of claims 1 to 11 is implemented.

20. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the simulation method for chip design according to any one of claims 1 to 11 is implemented.

Images