Pixel driving method, display panel and display device

Abstract

The invention relates to a pixel driving method, a display panel and a display device. The method comprises the steps of switching a first row of horizontal grid lines at the topmost part of a display panel to a high level at the beginning of a frame time so as to drive pixels corresponding to the first row of horizontal grid lines to be charged; switching the next row of horizontal grid lines to a high level according to a sequence from top to bottom in the vertical direction within the frame time, so as to drive pixels corresponding to each row of horizontal grid lines to charge one by one; wherein all the pixels are arranged according to a pixel framework in a point overturning mode. According to the invention, the charging sequence of the pixels of the double-gate architecture in the related technology can be adjusted through the pixel architecture in a point overturning mode, so that the uniformity of a display picture is improved, and the technical problem of insufficient uniformity in the horizontal direction caused by a 1 + 2 line overturning mode is solved.

Description

Technical Field

[0001] The present application relates to the field of liquid crystal display technology, and in particular to a pixel driving method, a display panel and a display device. Background Art

[0002] With the development of liquid crystal display technology, more and more panel manufacturers have adopted cost-reduction methods in order to maintain their competitiveness, such as adopting dual gate architecture (dual gate pixel drive architecture), using two rows of gate lines to open the same row of pixels, which can reduce the number of data lines and source driver integrated circuits by half. In the existing dual gate architecture design, two gate lines open the thin film transistors of a row of sub-pixels at different times for charging. This architecture uses a 1+2 line flipping method in the horizontal direction. This flipping method will cause a large area in the horizontal direction to have the same polarity, which in turn leads to insufficient uniformity in the horizontal direction.

[0003] The 1+2 line flipping method may lead to insufficient uniformity in the horizontal direction, and no effective solution has been proposed so far. Summary of the invention

[0004] The present application provides a pixel driving method, a display panel and a display device to solve the technical problem that a 1+2 line flipping method may lead to insufficient uniformity in the horizontal direction.

[0005] According to one aspect of an embodiment of the present application, the present application provides a pixel driving method, comprising: at the beginning of a frame time, switching the first row of horizontal gate lines at the top of the display panel to a high level to drive the pixels corresponding to the first row of horizontal gate lines to charge; within the one frame time, switching the next row of horizontal gate lines to a high level in a vertical order from top to bottom to drive the pixels corresponding to each row of horizontal gate lines to charge one by one; wherein all pixels are arranged according to a pixel architecture of a dot flipping method, and the pixel architecture of the dot flipping method includes: pixels in any row are connected to multiple data lines and are controlled by the first gate line and the second gate line corresponding to the row, wherein in any row, a pixel is connected to the left and right sides of each data line respectively, the left side pixels of the data lines of the odd columns are connected to the first gate line, the right side pixels of the data lines of the even columns are connected to the first gate line, the right side pixels of the data lines of the odd columns are connected to the second gate line, the left side pixels of the data lines of the even columns are connected to the second gate line, and the polarities of adjacent pixels in the same row are opposite.

[0006] Optionally, the two horizontal gate lines control a row of pixels, and the pixels are connected to a plurality of columns of data lines.

[0007] Optionally, in the process of driving the pixels corresponding to each of the horizontal gate lines to charge, driving the pixels in each row to charge includes: outputting a high level to the first gate line that controls the pixels of the target row, so that the pixels on the left side of the data lines of the odd columns on the target row are charged, and the pixels on the right side of the data lines of the even columns on the target row are charged.

[0008] Optionally, driving the pixels of each row to charge also includes: outputting a low level to the first gate line and outputting a high level to the second gate line that controls the pixels of the target row, so that the pixels on the right side of the data lines of the odd columns on the target row are charged and the pixels on the left side of the data lines of the even columns on the target row are charged.

[0009] Optionally, the method also includes: outputting the polarity of the sub-pixels on the same column as the same polarity, the polarity of the sub-pixels on any two adjacent columns is opposite, and within one frame time, first switching the horizontal gate lines of the odd rows to a high level one by one in a top-down order, and then switching the horizontal gate lines of the even rows to a high level one by one in a top-down order, so that the same data line can charge the sub-pixels in two adjacent columns separately at different times.

[0010] Optionally, in the process of first switching the horizontal gate lines of the odd-numbered rows to a high level one by one in a top-down order, and then switching the horizontal gate lines of the even-numbered rows to a high level one by one in a top-down order, the method further includes: in the first gate line, the second gate line and the third gate line adjacent to every three odd-numbered rows, the rising edge of the control signal of the second gate line is moved forward to before the falling edge of the control signal of the first gate line, and the falling edge of the control signal of the second gate line is moved backward to before the rising edge of the control signal of the third gate line, so that the data of the sub-pixels on the second gate line are obtained by neutralizing the data of the sub-pixels on the first gate line and the third gate line according to a preset ratio; in the fourth gate line, the fifth gate line and the sixth gate line adjacent to every three even-numbered rows, the rising edge of the control signal of the fifth gate line is moved forward to before the falling edge of the control signal of the fourth gate line, and the falling edge of the control signal of the fifth gate line is moved backward to before the rising edge of the control signal of the sixth gate line, so that the data of the sub-pixels on the fifth gate line are obtained by neutralizing the data of the sub-pixels on the fourth gate line and the sixth gate line according to a preset ratio.

[0011] According to another aspect of the embodiments of the present application, the present application provides a display panel, including an array substrate, a color film substrate, and a liquid crystal layer arranged between the array substrate and the color film substrate, the pixel architecture of the array substrate includes: multiple pixels, multiple horizontal gate lines, and multiple data lines, the pixels of any row are connected to multiple data lines, and are controlled by the first gate line and the second gate line corresponding to the row, wherein, in any row, a pixel is connected to the left and right sides of each data line respectively, the left pixels of the data lines of the odd columns are connected to the first gate line, the right pixels of the data lines of the even columns are connected to the first gate line, the right pixels of the data lines of the odd columns are connected to the second gate line, the left pixels of the data lines of the even columns are connected to the second gate line, and the polarities of adjacent pixels in the same row are opposite.

[0012] Optionally, the display panel also includes: a timing controller, which is used to switch multiple horizontal gate lines to a high level one by one in the order of switching from the first row of horizontal gate lines to the next row of horizontal gate lines in the vertical direction within one frame time, so as to drive the pixels corresponding to each of the horizontal gate lines to charge; and is also used to output the polarity of sub-pixels on the same column as the same polarity, and the polarity of sub-pixels on any two adjacent columns is opposite, and within one frame time, the horizontal gate lines of odd rows are first switched to a high level one by one in a top-down order, and the horizontal gate lines of even rows are switched to a high level one by one in a top-down order, so that the same data line can charge two adjacent columns of sub-pixels separately at different times.

[0013] Optionally, the timing controller is also used to control the first gate line, the second gate line and the third gate line adjacent to every three odd rows, and move the rising edge of the control signal of the second gate line forward to before the falling edge of the control signal of the first gate line, and move the falling edge of the control signal of the second gate line backward to before the rising edge of the control signal of the third gate line, so that the data of the sub-pixel on the second gate line is obtained by neutralizing the data of the sub-pixels on the first gate line and the third gate line according to a preset ratio.

[0014] Optionally, the timing controller is also used to control the fourth gate line, the fifth gate line and the sixth gate line adjacent to every three even-numbered rows, and move the rising edge of the control signal of the fifth gate line forward to before the falling edge of the control signal of the fourth gate line, and move the falling edge of the control signal of the fifth gate line backward to before the rising edge of the control signal of the sixth gate line, so that the data of the sub-pixel on the fifth gate line is obtained by neutralizing the data of the sub-pixels on the fourth gate line and the sixth gate line according to a preset ratio.

[0015] According to another aspect of the embodiments of the present application, the present application provides a display device, including a backlight module and the above-mentioned display panel, wherein the backlight module is arranged on the backlight side of the array substrate for providing light source to the display panel.

[0016] The above technical solution provided by the embodiment of the present application has the following advantages compared with the related art:

[0017] The present application provides a pixel driving method, comprising: at the beginning of a frame time, switching the first row of horizontal gate lines at the top of a display panel to a high level to drive the pixels corresponding to the first row of horizontal gate lines to charge; within the frame time, switching the next row of horizontal gate lines to a high level in a vertical order from top to bottom to drive the pixels corresponding to each row of horizontal gate lines to charge one by one; wherein all pixels are arranged according to a pixel architecture of a dot flipping method, and the pixel architecture of the dot flipping method comprises: pixels in any row are connected to multiple data lines and are controlled by the first gate line and the second gate line corresponding to the row, wherein in any row, a pixel is connected to the left and right sides of each data line respectively, the left side pixels of the data lines of the odd columns are connected to the first gate line, the right side pixels of the data lines of the even columns are connected to the first gate line, the right side pixels of the data lines of the odd columns are connected to the second gate line, the left side pixels of the data lines of the even columns are connected to the second gate line, and the polarities of adjacent pixels in the same row are opposite. The present application uses a pixel architecture with a dot flipping method to adjust the charging order of pixels in a dual gate architecture in the related art, thereby improving the uniformity of the displayed image and solving the technical problem that a 1+2 line flipping method may lead to insufficient uniformity in the horizontal direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0020] Figure 1 It is a schematic diagram of a 1+2 line pixel flipping method of a dual gate architecture in the related art;

[0021] Figure 2 This is a schematic diagram of a pixel driving method flow chart in accordance with an embodiment of the present application;

[0022] Figure 3 A schematic diagram of a pixel architecture provided in Embodiment 1 of the present application;

[0023] Figure 4 This is a signal timing diagram of a pixel driving method according to an embodiment of the present application;

[0024] Figure 5 A schematic diagram of another pixel architecture provided in Embodiment 1 of the present application;

[0025] Figure 6 A signal timing diagram of another pixel driving method provided in the first embodiment of the present application;

[0026] Figure 7 A signal timing diagram of another pixel driving method provided in the first embodiment of the present application;

[0027] Figure 8 This is a schematic diagram of the structure of a display panel according to the second embodiment of the present application;

[0028] Fig. 9 This is a schematic diagram of the structure of the display device according to the third embodiment of the present application.

[0029] Reference numerals: 10, pixel; S1, S2, S3, S4, ..., data line; G1, G2, G3, G4, ..., gate line; 100, array substrate; 200, backlight module; 300, color film substrate; 400, liquid crystal layer. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0031] In the subsequent description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present application and have no specific meaning. Therefore, "module" and "component" can be used interchangeably.

[0032] In related technologies, such as Figure 1 As shown, the existing dual gate architecture design uses two rows of gate lines to open the same row of pixels. A row of sub-pixels uses two gate lines to open TFTs (Thin Flim Transistors) at different times for charging. The horizontal direction is a 1+2 line flipping method. This flipping method will cause a large area in the horizontal direction to have the same polarity, which in turn causes insufficient uniformity in the horizontal direction.

[0033] In order to solve the problem mentioned in the background technology, according to one aspect of an embodiment of the present application, a pixel driving method is provided, as shown in Figure 2, the method includes:

[0034] Step S201, at the beginning of a frame time, switching the first row of horizontal gate lines at the top of the display panel to a high level to drive the pixels corresponding to the first row of horizontal gate lines to charge;

[0035] Step S202, within the one frame time, switching the next row of horizontal gate lines to a high level in a vertical order from top to bottom, so as to drive the pixels corresponding to each row of horizontal gate lines to charge one by one;

[0036] Among them, all pixels are arranged according to a pixel architecture of a dot flipping method, and the pixel architecture of the dot flipping method includes: pixels in any row are connected to multiple data lines and are controlled by the first gate line and the second gate line corresponding to the row, wherein, in any row, each data line is connected to a pixel on the left and right sides respectively, the left pixels of the data lines of the odd columns are connected to the first gate line, the right pixels of the data lines of the even columns are connected to the first gate line, the right pixels of the data lines of the odd columns are connected to the second gate line, and the left pixels of the data lines of the even columns are connected to the second gate line, and the polarities of adjacent pixels in the same row are opposite.

[0037] The present application uses a pixel architecture with a dot flipping method to adjust the charging order of pixels in a dual gate architecture in the related art, thereby improving the uniformity of the displayed image and solving the technical problem that a 1+2 line flipping method may lead to insufficient uniformity in the horizontal direction.

[0038] In the embodiment of the present application, the original 1+2 line pixel flipping method in the dual gate architecture is improved to a point flipping method, such as Figure 3 As shown, every two horizontal gate lines control a row of pixels, and each row of pixels is connected to multiple columns of data lines, that is, the pixels of any row are connected to multiple data lines and are controlled by the first gate line and the second gate line corresponding to the row (each row of pixels corresponds to two horizontal gate lines, the upper one is the first gate line, the lower one is the second gate line, and the Figure 3In the embodiment, for the first row, G1 is the first gate line and G2 is the second gate line), wherein in any row, a pixel is connected to the left and right sides of each data line respectively, the left pixels of the data lines of the odd-numbered columns are connected to the first gate line (such as in the first row, the pixels on the left sides of the data lines S1 and S3 are connected to the horizontal gate line G1), the right pixels of the data lines of the even-numbered columns are connected to the first gate line (such as in the first row, the pixels on the right sides of the data lines S2 and S4 are connected to the horizontal gate line G1), the right pixels of the data lines of the odd-numbered columns are connected to the second gate line (such as in the first row, the pixels on the right sides of the data lines S1 and S3 are connected to the horizontal gate line G2), the left pixels of the data lines of the even-numbered columns are connected to the second gate line (such as in the first row, the pixels on the left sides of the data lines S2 and S4 are connected to the horizontal gate line G2), and the polarities of adjacent pixels in the same row are opposite.

[0039] In the embodiment of the present application, the pixel architecture based on the dot flipping method can reduce the area of ​​the same polarity in the display screen, thereby improving the uniformity of the display image.

[0040] In steps S201 and S202, the next row of horizontal gate lines is switched to a high level in a vertical order from top to bottom, so as to drive the pixels corresponding to each row of horizontal gate lines to charge one by one. The control timing can be as follows: Figure 4 shown. Figure 4 In the process, G1 switches from a low level to a high level, and the pixels connected to G1 in the first row are charged. When G1 switches from a high level to a low level, G2 changes from a low level to a high level at the same time. When G1 changes from a high level to a low level, the pixels connected to G1 in the first row are fully charged. During the period when G1 is at a low level, the voltages of these pixels are maintained due to the presence of liquid crystal capacitors. After G2 switches to a high level, the pixels connected to G2 in the first row are charged. When G2 changes from a high level to a low level, the pixels connected to G2 in the first row are fully charged, thereby completing the charging of the pixels in the first row through G1 and G2. When G2 changes from a high level to a low level, G3 switches from a low level to a high level, thereby starting to charge the pixels in the next row. In this way, the sub-pixels of all rows can be charged and maintained within one frame time.

[0041] In an optional embodiment, in the process of driving the pixels corresponding to each of the horizontal gate lines to charge, driving the pixels of each row to charge includes:

[0042] A high level is output to the first gate line controlling the pixels of the target row, so that the pixels on the left side of the data lines of the odd columns on the target row are charged, and the pixels on the right side of the data lines of the even columns on the target row are charged.

[0043] In the present application embodiment, Figure 3As shown, when G1 changes from a low level to a high level, the pixels in the 1st, 4th, 5th, 8th, 9th, 12th columns of the first row begin to charge (i.e., the pixels on the left side of the odd-numbered data lines S1, S3, etc. in the first row are charged, and the pixels on the right side of the even-numbered data lines S2, S4, etc. in the first row are charged), and when G1 changes from a high level to a low level, these sub-pixels are fully charged, and the voltage of the sub-pixels is maintained during the period when G1 is at a low level due to the presence of the liquid crystal capacitor.

[0044] In an optional embodiment, driving the pixels of each row to charge further comprises:

[0045] A low level is output to the first gate line, and a high level is output to the second gate line controlling the pixels of the target row, so that the pixels on the right side of the data lines of the odd columns on the target row are charged and the pixels on the left side of the data lines of the even columns on the target row are charged.

[0046] In the present application embodiment, Figure 3 As shown, when G1 changes from a high level to a low level, G2 changes from a low level to a high level, and the remaining pixels in the first row, the pixels in the 2nd, 3rd, 6th, 7th, 10th, 11th columns, etc. begin to charge (that is, the pixels on the right side of the odd-numbered data lines S1, S3, etc. in the first row are charged, and the pixels on the left side of the even-numbered data lines S2, S4, etc. in the first row are charged), and when G2 changes from a high level to a low level, all the sub-pixels in the first row are charged, and the voltage of the sub-pixels is maintained before G1 and G2 become high levels next time.

[0047] In order to further improve the uniformity of the display image in the horizontal direction, in an optional embodiment, the method further includes:

[0048] The polarity of the sub-pixels on the same column is output as the same polarity, and the polarity of the sub-pixels on any two adjacent columns is opposite. Within one frame time, the horizontal gate lines of the odd-numbered rows are first switched to a high level one by one from top to bottom, and then the horizontal gate lines of the even-numbered rows are switched to a high level one by one from top to bottom, so that the same data line can charge the sub-pixels of two adjacent columns separately at different times.

[0049] In the present application embodiment, Figure 5 As shown, we can output the sub-pixel polarity on each column to the same polarity, and the polarities of the sub-pixels on any two adjacent columns are opposite. However, the odd and even gate lines are not turned on sequentially. Instead, the horizontal gate lines of the odd rows are switched to high level one by one from top to bottom in one frame time, and then the horizontal gate lines of the even rows are switched to high level one by one from top to bottom in one frame time. The specific timing is as follows Figure 6As shown, they are turned on one by one in the order of G1→G3→G5→G7→...→G2059→G2→G4→...→G2160, so that the same data line charges two adjacent columns of sub-pixels separately at different times.

[0050] based on Figure 5 The architecture shown and Figure 6 The timing shown, the present application further proposes a method for doubling the display refresh rate, which is explained below.

[0051] In an optional embodiment, in the process of first switching the horizontal gate lines of odd rows to a high level one by one in a top-down order, and then switching the horizontal gate lines of even rows to a high level one by one in a top-down order, the method further includes:

[0052] In every three odd-numbered rows of adjacent first gate lines, second gate lines and third gate lines, a rising edge of a control signal of the second gate line is moved forward to before a falling edge of a control signal of the first gate line, and a falling edge of a control signal of the second gate line is moved backward to before a rising edge of a control signal of the third gate line, so that data of sub-pixels on the second gate line are obtained by neutralizing data of sub-pixels on the first gate line and the third gate line according to a preset ratio;

[0053] In the fourth gate line, the fifth gate line and the sixth gate line adjacent to every three even rows, the rising edge of the control signal of the fifth gate line is moved forward to before the falling edge of the control signal of the fourth gate line, and the falling edge of the control signal of the fifth gate line is moved backward to before the rising edge of the control signal of the sixth gate line, so that the data of the sub-pixels on the fifth gate line are obtained by neutralizing the data of the sub-pixels on the fourth gate line and the sixth gate line according to a preset ratio.

[0054] In the embodiment of the present application, we can increase the display refresh rate by adjusting the gate timing, which refers to the timing and order of opening and closing the gate lines in the display panel. The gate lines are used to control the flow of electrical signals to the pixels or sub-pixels in the display. By adjusting the timing of the gate lines, the display can control the activation time and duration of each pixel or sub-pixel.

[0055] In the embodiment of the present application, the specific timing for doubling the display refresh rate is as follows: Figure 7As shown, data1 is sent to the sub-pixel controlled by G1, data2 is sent to the sub-pixel controlled by G5, and the sub-pixel controlled by G3 is formed by the neutralization of data1 and data2. By controlling the rising (rising edge) and falling (falling edge) time of G3, the data charged into the G3 sub-pixel can be controlled. Because the final display screen is greatly affected by the falling time, the G3 sub-pixel needs to be charged with less G5 sub-pixel data than the G1 sub-pixel data. Similarly, the G7 sub-pixel is formed by the neutralization of G5 and G9 sub-pixel data. The above preset ratio can be set by controlling the rising (rising edge) and falling (falling edge) time of G3 and G7, and can be selected according to actual needs. Through this timing debugging, the time of each frame can be halved, thereby doubling the display refresh rate.

[0056] The present application uses a pixel architecture with a dot flipping method to adjust the charging order of pixels in a dual gate architecture in the related art, thereby improving the uniformity of the displayed image and solving the technical problem that a 1+2 line flipping method may lead to insufficient uniformity in the horizontal direction.

[0057] In order to solve the problem mentioned in the background technology, according to one aspect of the embodiments of the present application, an embodiment of a display panel is provided, such as Figure 8 As shown, the display panel includes an array substrate 100 , a color filter substrate 300 , and a liquid crystal layer 400 disposed between the array substrate 100 and the color filter substrate 300 .

[0058] Optionally, the array substrate 100 is configured to have the following pixel architecture:

[0059] like Figure 3 As shown, the pixel architecture may include a plurality of pixels 10, a plurality of gate lines (exemplified in the figure as G1, G2, G3, G4, ...) and a plurality of data lines (exemplified in the figure as S1, S2, S3, S4, ...).

[0060] The pixels in any row are connected to multiple data lines and are controlled by the first gate line and the second gate line corresponding to the row, wherein in any row, a pixel is connected to the left and right sides of each data line respectively, the left pixels of the data lines of odd columns are connected to the first gate line, the right pixels of the data lines of even columns are connected to the first gate line, the right pixels of the data lines of odd columns are connected to the second gate line, and the left pixels of the data lines of even columns are connected to the second gate line, and the polarities of adjacent pixels in the same row are opposite.

[0061] like Figure 3As shown, every two horizontal gate lines control a row of pixels, and each row of pixels is connected to multiple columns of data lines, that is, the pixels of any row are connected to multiple data lines and are controlled by the first gate line and the second gate line corresponding to the row (each row of pixels corresponds to two horizontal gate lines, the upper one is the first gate line, the lower one is the second gate line, and the Figure 3 In the embodiment, for the first row, G1 is the first gate line and G2 is the second gate line), wherein in any row, a pixel is connected to the left and right sides of each data line respectively, the left pixels of the data lines of the odd-numbered columns are connected to the first gate line (such as in the first row, the pixels on the left sides of the data lines S1 and S3 are connected to the horizontal gate line G1), the right pixels of the data lines of the even-numbered columns are connected to the first gate line (such as in the first row, the pixels on the right sides of the data lines S2 and S4 are connected to the horizontal gate line G1), the right pixels of the data lines of the odd-numbered columns are connected to the second gate line (such as in the first row, the pixels on the right sides of the data lines S1 and S3 are connected to the horizontal gate line G2), the left pixels of the data lines of the even-numbered columns are connected to the second gate line (such as in the first row, the pixels on the left sides of the data lines S2 and S4 are connected to the horizontal gate line G2), and the polarities of adjacent pixels in the same row are opposite.

[0062] In the embodiment of the present application, the pixel architecture based on the dot flipping method can reduce the area of ​​the same polarity in the display screen, thereby improving the uniformity of the display image.

[0063] Optionally, the display panel further includes:

[0064] A timing controller is used to switch multiple horizontal gate lines to a high level one by one in a frame time in the order of switching from the first row of horizontal gate lines to the next row of horizontal gate lines in the vertical direction, so as to drive the pixels corresponding to each of the horizontal gate lines to charge; it is also used to output the polarity of sub-pixels on the same column as the same polarity, and the polarity of sub-pixels on any two adjacent columns is opposite, and in one frame time, the horizontal gate lines of odd rows are first switched to a high level one by one in a top-down order, and the horizontal gate lines of even rows are then switched to a high level one by one in a top-down order, so that the same data line can charge two adjacent columns of sub-pixels separately at different times.

[0065] In the embodiment of the present application, based on the pixel architecture of the dot flipping method, when G1 switches from a low level to a high level, the pixels connected to G1 in the first row are charged, and when G1 switches from a high level to a low level, G2 changes from a low level to a high level at the same time. When G1 changes from a high level to a low level, the pixels connected to G1 in the first row are fully charged, and the voltages of these pixels are in a maintained state due to the presence of the liquid crystal capacitors during the period when G1 is at a low level. After G2 switches to a high level, the pixels connected to G2 in the first row are charged. When G2 changes from a high level to a low level, the pixels connected to G2 in the first row are fully charged, thereby completing the charging of the pixels in the first row through G1 and G2, and while G2 changes from a high level to a low level, G3 switches from a low level to a high level, thereby starting to charge the pixels in the next row. In this way, the sub-pixels of all rows can be charged and maintained within one frame time.

[0066] Optionally, the timing controller is specifically used for:

[0067] A high level is output to the first gate line controlling the pixels of the target row, so that the pixels on the left side of the data lines of the odd columns on the target row are charged, and the pixels on the right side of the data lines of the even columns on the target row are charged.

[0068] In the present application embodiment, Figure 3 As shown, when G1 changes from a low level to a high level, the pixels in the 1st, 4th, 5th, 8th, 9th, 12th columns of the first row begin to charge (i.e., the pixels on the left side of the odd-numbered data lines S1, S3, etc. in the first row are charged, and the pixels on the right side of the even-numbered data lines S2, S4, etc. in the first row are charged), and when G1 changes from a high level to a low level, these sub-pixels are fully charged, and the voltage of the sub-pixels is maintained during the period when G1 is at a low level due to the presence of the liquid crystal capacitor.

[0069] Optionally, the timing controller is further used for:

[0070] A low level is output to the first gate line, and a high level is output to the second gate line controlling the pixels of the target row, so that the pixels on the right side of the data lines of the odd columns on the target row are charged and the pixels on the left side of the data lines of the even columns on the target row are charged.

[0071] In the present application embodiment, Figure 3As shown, when G1 changes from a high level to a low level, G2 changes from a low level to a high level, and the remaining pixels in the first row, the pixels in the 2nd, 3rd, 6th, 7th, 10th, 11th columns, etc. begin to charge (that is, the pixels on the right side of the odd-numbered data lines S1, S3, etc. in the first row are charged, and the pixels on the left side of the even-numbered data lines S2, S4, etc. in the first row are charged), and when G2 changes from a high level to a low level, all the sub-pixels in the first row are charged, and the voltage of the sub-pixels is maintained before G1 and G2 become high levels next time.

[0072] Optionally, in the process of first switching the horizontal gate lines of odd rows to a high level one by one in a top-down order, and then switching the horizontal gate lines of even rows to a high level one by one in a top-down order, the timing controller is further used to:

[0073] In every three odd-numbered rows of adjacent first gate lines, second gate lines and third gate lines, a rising edge of a control signal of the second gate line is moved forward to before a falling edge of a control signal of the first gate line, and a falling edge of a control signal of the second gate line is moved backward to before a rising edge of a control signal of the third gate line, so that data of sub-pixels on the second gate line are obtained by neutralizing data of sub-pixels on the first gate line and the third gate line according to a preset ratio;

[0074] In the fourth gate line, the fifth gate line and the sixth gate line adjacent to every three even rows, the rising edge of the control signal of the fifth gate line is moved forward to before the falling edge of the control signal of the fourth gate line, and the falling edge of the control signal of the fifth gate line is moved backward to before the rising edge of the control signal of the sixth gate line, so that the data of the sub-pixels on the fifth gate line are obtained by neutralizing the data of the sub-pixels on the fourth gate line and the sixth gate line according to a preset ratio.

[0075] In the embodiment of the present application, we can increase the display refresh rate by adjusting the gate timing, which refers to the timing and order of opening and closing the gate lines in the display panel. The gate lines are used to control the flow of electrical signals to the pixels or sub-pixels in the display. By adjusting the timing of the gate lines, the display can control the activation time and duration of each pixel or sub-pixel.

[0076] In the embodiment of the present application, the specific timing for doubling the display refresh rate is as follows: Figure 7As shown, data1 is sent to the sub-pixel controlled by G1, data2 is sent to the sub-pixel controlled by G5, and the sub-pixel controlled by G3 is formed by the neutralization of data1 and data2. By controlling the rising (rising edge) and falling (falling edge) time of G3, the data charged into the G3 sub-pixel can be controlled. Because the final display screen is greatly affected by the falling time, the G3 sub-pixel needs to be charged with less G5 sub-pixel data than the G1 sub-pixel data. Similarly, the G7 sub-pixel is formed by the neutralization of G5 and G9 sub-pixel data. The above preset ratio can be set by controlling the rising (rising edge) and falling (falling edge) time of G3 and G7, and can be selected according to actual needs. Through this timing debugging, the time of each frame can be halved, thereby doubling the display refresh rate.

[0077] According to another aspect of the embodiments of the present application, the present application provides a display device, such as Fig. 9 As shown, the display device includes a backlight module 200 and the above-mentioned liquid crystal panel. The backlight module 200 is arranged on the backlight side of the array substrate 100 to provide light source to the liquid crystal panel.

[0078] The above description is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest range consistent with the principles and novel features applied for herein.

Claims

1. A pixel driving method, characterized in that: include: At the beginning of a frame time, the first row of horizontal gate lines at the top of the display panel is switched to a high level to drive the pixels corresponding to the first row of horizontal gate lines to charge; In the one frame time, the next row of horizontal gate lines is switched to a high level in a vertical order from top to bottom, so as to drive the pixels corresponding to each row of horizontal gate lines to charge one by one; Among them, all pixels are arranged according to a pixel architecture of a dot flipping method, and the pixel architecture of the dot flipping method includes: pixels in any row are connected to multiple data lines and are controlled by the first gate line and the second gate line corresponding to the row, wherein, in any row, each data line is connected to a pixel on the left and right sides respectively, the left pixels of the data lines of the odd columns are connected to the first gate line, the right pixels of the data lines of the even columns are connected to the first gate line, the right pixels of the data lines of the odd columns are connected to the second gate line, and the left pixels of the data lines of the even columns are connected to the second gate line, and the polarities of adjacent pixels in the same row are opposite.

2. The method according to claim 1, characterized in that In the process of driving the pixels corresponding to each of the horizontal gate lines to charge, driving the pixels of each row to charge includes: A high level is output to the first gate line controlling the pixels of the target row, so that the pixels on the left side of the data lines of the odd columns on the target row are charged, and the pixels on the right side of the data lines of the even columns on the target row are charged.

3. The method according to claim 2, characterized in that Driving the pixel charging of each row also includes: A low level is output to the first gate line, and a high level is output to the second gate line controlling the pixels of the target row, so that the pixels on the right side of the data lines of the odd columns on the target row are charged and the pixels on the left side of the data lines of the even columns on the target row are charged.

4. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: The polarity of the sub-pixels on the same column is output as the same polarity, and the polarity of the sub-pixels on any two adjacent columns is opposite. Within one frame time, the horizontal gate lines of the odd-numbered rows are first switched to a high level one by one from top to bottom, and then the horizontal gate lines of the even-numbered rows are switched to a high level one by one from top to bottom, so that the same data line can charge the sub-pixels of two adjacent columns separately at different times.

5. The method according to claim 4, characterized in that In the process of first switching the horizontal gate lines of odd rows to high level one by one in a top-down order, and then switching the horizontal gate lines of even rows to high level one by one in a top-down order, the method further includes: In every three odd-numbered rows of adjacent first gate lines, second gate lines and third gate lines, a rising edge of a control signal of the second gate line is moved forward to before a falling edge of a control signal of the first gate line, and a falling edge of a control signal of the second gate line is moved backward to before a rising edge of a control signal of the third gate line, so that data of sub-pixels on the second gate line are obtained by neutralizing data of sub-pixels on the first gate line and the third gate line according to a preset ratio; In the fourth gate line, the fifth gate line and the sixth gate line adjacent to every three even rows, the rising edge of the control signal of the fifth gate line is moved forward to before the falling edge of the control signal of the fourth gate line, and the falling edge of the control signal of the fifth gate line is moved backward to before the rising edge of the control signal of the sixth gate line, so that the data of the sub-pixels on the fifth gate line are obtained by neutralizing the data of the sub-pixels on the fourth gate line and the sixth gate line according to a preset ratio.

6. A display panel comprising an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate, characterized in that: The pixel architecture of the array substrate includes: A plurality of pixels, a plurality of horizontal gate lines and a plurality of data lines, the pixels in any row are connected to the plurality of data lines and are controlled by the first gate line and the second gate line corresponding to the row, wherein in any row, a pixel is connected to the left and right sides of each data line respectively, the left pixels of the data lines of the odd-numbered columns are connected to the first gate line, the right pixels of the data lines of the even-numbered columns are connected to the first gate line, the right pixels of the data lines of the odd-numbered columns are connected to the second gate line, the left pixels of the data lines of the even-numbered columns are connected to the second gate line, and the polarities of adjacent pixels in the same row are opposite.

7. The display panel according to claim 6, characterized in that: The display panel further includes: A timing controller is used to switch multiple horizontal gate lines to a high level one by one in a frame time in the order of switching from the first row of horizontal gate lines to the next row of horizontal gate lines in the vertical direction, so as to drive the pixels corresponding to each of the horizontal gate lines to charge; it is also used to output the polarity of sub-pixels on the same column as the same polarity, and the polarity of sub-pixels on any two adjacent columns is opposite, and in one frame time, the horizontal gate lines of odd rows are first switched to a high level one by one in a top-down order, and the horizontal gate lines of even rows are then switched to a high level one by one in a top-down order, so that the same data line can charge two adjacent columns of sub-pixels separately at different times.

8. The display panel according to claim 7, characterized in that: The timing controller is also used to control the first gate line, the second gate line and the third gate line adjacent to each other in every three odd-numbered rows, and to move the rising edge of the control signal of the second gate line forward to before the falling edge of the control signal of the first gate line, and to move the falling edge of the control signal of the second gate line backward to before the rising edge of the control signal of the third gate line, so that the data of the sub-pixels on the second gate line are obtained by neutralizing the data of the sub-pixels on the first gate line and the third gate line according to a preset ratio.

9. The display panel according to claim 7, characterized in that: The timing controller is also used to control the fourth gate line, the fifth gate line and the sixth gate line adjacent to every three even-numbered rows, and to move the rising edge of the control signal of the fifth gate line forward to before the falling edge of the control signal of the fourth gate line, and to move the falling edge of the control signal of the fifth gate line backward to before the rising edge of the control signal of the sixth gate line, so that the data of the sub-pixels on the fifth gate line are obtained by neutralizing the data of the sub-pixels on the fourth gate line and the sixth gate line according to a preset ratio.

10. A display device, characterized in that: It comprises a backlight module and a display panel as claimed in any one of claims 6 to 9, wherein the backlight module is arranged on the backlight side of the array substrate and is used to provide light source to the display panel.

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