Heterogeneous integrated radio frequency chip

Abstract

A heterogeneous integrated radio frequency chip disclosed by the present invention comprises a first chip, a plurality of second chips, a metal solder and a chip carrier, the first chip is provided with a plurality of through holes for accommodating the second chips, the first chip is fixedly connected with the chip carrier through the metal solder, and the plurality of second chips are fixedly connected with the chip carrier through the metal solder. The first chip comprises a metal grounding plate, and the metal grounding plate is fixedly connected with the chip carrier through metal solder. According to the invention, the lattice adaptation problem in the growth process of different epitaxial materials and compatibility of different device preparation processes are realized, and the alignment precision is improved and through hole interconnection is realized due to the plurality of through holes.

Description

Technical Field

[0001] The invention relates to a heterogeneous integrated radio frequency chip, belonging to the technical field of semiconductor integrated circuit manufacturing. Background Art

[0002] With the continuous demand for multi-function, high-density integration, small size, weight and high performance in electronic information systems, heterogeneous integrated semiconductor technology has attracted more and more attention from the industry driven by this demand. In terms of semiconductor integration technology, there are two major technical directions: hybrid integration and monolithic integration. Hybrid integration belongs to the concept of system-level packaging, which is to stack chips of different functional materials into a whole in 3D; monolithic integration is to integrate devices with different functions on a single chip, eliminating the tedious multiple packaging steps.

[0003] Monolithic integration includes transfer processes similar to post-CMOS, heteroepitaxial processes, and epitaxial layer transfer processes. The post-CMOS process will mainly transfer III-V chips to Si-based CMOS chips through micromechanical operations, which is currently a more commonly used transfer solution. Heteroepitaxial growth needs to solve the lattice adaptation problem during the growth of different epitaxial materials and the incompatibility of different device preparation processes, which is technically difficult. The epitaxial layer transfer process needs to consider the alignment accuracy during wafer-level bonding and through-hole interconnection problems, and the process difficulty is also relatively high. At the same time, as the frequency of RF chips becomes higher and higher, the transmission loss and parasitic problems caused by the bonding wires and interconnection through holes will affect the performance of the entire integrated chip. In addition, the bonding material used in the bonding process cannot be ignored in its effect on the heat dissipation of the chip. Summary of the invention

[0004] The technical problem to be solved by the present invention is to overcome the defects of the prior art that "heteroepitaxy needs to solve the lattice adaptation problem in the growth process of different epitaxial materials and the incompatibility problem of different device preparation processes, which is technically difficult. The epitaxial layer transfer process needs to consider the alignment accuracy during wafer-level bonding and the through-hole interconnection problem, and the process difficulty is also relatively high. At the same time, as the frequency of RF chips becomes higher and higher, the transmission loss and parasitic problems caused by the bonding wires and interconnected through-holes will affect the performance of the entire integrated chip. In addition, the bonding material used in the bonding process also has a non-negligible effect on the heat dissipation of the chip" and provide a heterogeneous integrated RF chip.

[0005] Preferably, the present invention provides a heterogeneous integrated radio frequency chip, including a first chip, a plurality of second chips, metal solder and a chip carrier, wherein the first chip is provided with a plurality of through holes for accommodating the second chips, the first chip is fixedly connected to the chip carrier by the metal solder, and the plurality of second chips are fixedly connected to the chip carrier by the metal solder.

[0006] Preferably, the first chip comprises a metal ground plate, and the metal ground plate is fixedly connected to the chip carrier by metal solder.

[0007] Preferably, the first chip includes two microstrip pads, a first microstrip line, a pressure pad, several first devices, and a first substrate material. The microstrip pad on one side is connected to the pressure pad through the first microstrip line, and the pressure pad is connected to one of the several first devices closest to the microstrip pad on the other side through the first microstrip line. The microstrip pad on one side is connected in series with several first devices through the first microstrip line, and one of the several first devices closest to the microstrip pad on the other side is connected to the microstrip pad on the other side through the first microstrip line. The two microstrip pads, the first microstrip line, the pressure pad, and several first devices are fixedly arranged on the first substrate material.

[0008] Preferably, the second chip includes a second microstrip line, a second device, a second substrate material, and a second metal ground plate. Several second chips are connected in series through the second microstrip line, the bonding pad is connected to the second microstrip line through the first microstrip line, the second device is connected in series in the middle of the second microstrip line, the second device and part of the second microstrip line are fixedly arranged on the second substrate material, and the second substrate material is fixedly connected to the second metal ground plate.

[0009] Preferably, the length, width and height of the through hole are 0.01-10 mm greater than the length, width and height of the second chip.

[0010] Preferably, the through hole is adjacent to the pressure pad, and the distance between the through hole and the pressure pad is less than 10 mm.

[0011] The beneficial effects achieved by the present invention are: 1) The present invention solves the technical problem that "heteroepitaxy needs to solve the lattice adaptation problem in the growth process of different epitaxial materials and the incompatibility problem of different device preparation processes, which has great technical difficulty. The epitaxial layer transfer process needs to consider the alignment accuracy during wafer-level bonding and the through-hole interconnection problem, and the process difficulty is also great. At the same time, as the frequency of RF chips becomes higher and higher, the transmission loss and parasitic problems caused by the bonding wires and interconnection through-holes will affect the performance of the entire integrated chip. In addition, the effect of the bonding material used in the bonding process on the heat dissipation of the chip cannot be ignored." The lattice adaptation problem in the growth process of different epitaxial materials and the different device preparation processes are compatible, and the multiple through-holes opened improve the alignment accuracy and realize through-hole interconnection. The first chip and the second chip are designed and manufactured separately, and there is no process compatibility problem. The design and manufacturing are simpler than the epitaxial layer transfer or heteroepitaxial process.

[0012] 2) By forming a through hole that penetrates the first chip on the first chip and ensuring that the contour of the through hole is the same as that of the second chip and the difference in contour size is in the micron level, the electrical signal can be interacted with by greatly reducing transmission losses and parasitic parameters compared to traditional gold wire connections or carrier tape connections between chips, thereby improving the quality of signal transmission.

[0013] 3) By forming a through hole that penetrates the first chip on the first chip and ensuring that the outline is the same as the second chip and the difference in outline size is in the micron level, the chip integration can be greatly improved and the chip weight and size can be reduced.

[0014] 4) Both the first chip and the second chip are welded to the chip carrier through metal solder. The metal solder welding process has better thermal conductivity than the organic solder in 3D packaging, is more conducive to chip heat dissipation, and is very beneficial to the integrated manufacturing of RF chips with high power requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0016] Figure 1 is a schematic diagram of a first chip in some embodiments of the present application; Figure 2 is a schematic cross-sectional view of the first chip at the through hole in some embodiments of the present application; Figure 3 is a schematic diagram of a second chip in some embodiments of the present application; Figure 4 is a schematic cross-sectional view of a second microstrip line in which a second chip is suspended at one end in some embodiments of the present application; Figure 5 is a schematic diagram of a first chip being welded to a chip carrier in some embodiments of the present application; Figure 6 is a schematic diagram of welding a first chip and a second chip to a chip carrier in some embodiments of the present application; Figure 7 is a schematic diagram of a bird's-eye view of some embodiments of the present application; The meaning of the reference numerals is: 1-first chip; 11-microstrip pad; 12-first microstrip line; 13-pressure pad; 14-first device; 15-first substrate material; 16-through hole; 17-metal ground plate; 2-second chip; 21-second microstrip line; 22-second device; 23-second substrate material; 24-second metal ground plate; 3-metal solder; 4-chip carrier; 5-hot pressing welding area. DETAILED DESCRIPTION

[0017] See also Figure 1 The present application discloses a heterogeneous integrated radio frequency chip, including a first chip 1, a plurality of second chips 2, a metal solder 3 and a chip carrier 4. The first chip 1 is provided with a plurality of through holes 16 for accommodating the second chips 2. The first chip 1 is fixedly connected to the chip carrier 4 through the metal solder 3, and the plurality of second chips 2 are fixedly connected to the chip carrier 4 through the metal solder 3.

[0018] In the embodiment of the present application, the first chip 1 includes a metal ground plate 17 , and the metal ground plate 17 is fixedly connected to the chip carrier 4 through the metal solder 3 .

[0019] In an embodiment of the present application, the first chip 1 includes two microstrip pads 11, a first microstrip line 12, a pressure pad 13, several first devices 14, and a first substrate material 15. The microstrip pad 11 on one side is connected to the pressure pad 13 through the first microstrip line 12, and the pressure pad 13 is connected to one of the several first devices 14 that is closest to the microstrip pad 11 on the other side through the first microstrip line 12. The microstrip pad 11 on one side is connected in series with several first devices 14 through the first microstrip line 12, and one of the several first devices 14 that is closest to the microstrip pad 11 on the other side is connected to the microstrip pad 11 on the other side through the first microstrip line 12. The two microstrip pads 11, the first microstrip line 12, the pressure pad 13, and several first devices 14 are fixedly arranged on the first substrate material 15.

[0020] In an embodiment of the present application, the second chip 2 includes a second microstrip line 21, a second device 22, a second substrate material 23, and a second metal ground plate 24. Several second chips 2 are connected in series through the second microstrip line 21. The bonding pad 13 is connected to the second microstrip line 21 through the first microstrip line 12. The second device 22 is connected in series in the middle of the second microstrip line 21. The second device 22 and part of the second microstrip line 21 are fixedly arranged on the second substrate material 23. The second substrate material 23 is fixedly connected to the second metal ground plate 24. The second microstrip line 21 and the first microstrip line 12 are welded between the hot pressing welding area 5.

[0021] In the embodiment of the present application, the length, width and height of the through hole 16 are 0.01-10 mm greater than the length, width and height of the second chip 2 .

[0022] The preparation of the first chip 1 and the second chip 2 in the heterogeneous integrated radio frequency chip includes: 1) Preparation of the first chip 1: According to the actual function and process requirements, the preparation of the wafer front process is designed and completed. After the front process is completed, a through hole 16 penetrating the first chip 1 is formed on the first substrate material 15 by an etching process during the back process, and the wafer is subsequently diced through the back process to obtain an independent first chip 1. The first chip 1 is the chip with the main function or the largest chip area among all chips. It serves as a basic chip to integrate other types of second chips 2 into a whole. The outline of the through hole 16 is as consistent as possible with the outline of the second chip 2, and the outline of the through hole 16 is larger than the outline of the second chip 2 to ensure that the second chip 2 can be placed therein.

[0023] like Figure 1 As shown, the first chip 1 includes a first substrate material 15 for preparing the first chip 1, which can be a semiconductor material such as SiC, sapphire, G1N, G11s, Si or InP; a microstrip pad 11 formed on the first substrate material 15, and the microstrip pad 11 is used to connect the transmission line of the external signal with a gold wire; a first microstrip line 12 formed on the first substrate material 15, and the first microstrip line 12 is connected to 11 for transmitting microwave signals on the first chip 1; a pressure pad 13 formed on the first substrate material 15, one end of the pressure pad 13 is connected to the first microstrip line 12 of the first chip 1, and the other end of the pressure pad 13 is suspended from one end on the second chip 2 The second microstrip line 21 is connected by a process such as hot pressing welding; various active or passive devices 14 are formed on the first substrate material 15, and the first device 14 is a general term for various devices prepared on the first chip 1, which can be a transistor, a diode or a capacitor and an inductor, etc. The first device 14 is connected to the first microstrip line 12; a through hole 16 that penetrates the chip is formed in the first substrate material 15 of the first chip 1, and the edge of the through hole 16 is adjacent to the pressure pad 13, and the spacing is less than 10mm; a first metal ground plate 17 is formed on the back side of the first substrate material 15, and the first metal ground plate 17 is the signal ground of the first microstrip line 12 and various active or passive devices.

[0024] 2) Preparation of the Second Chip 2 According to the actual function and process requirements, the preparation of the wafer front process is designed and completed. After the front process is completed, the substrate material outside the graphic area of ​​the second chip 2 is removed by etching during the back process, so that the microstrip lines at both ends of the second chip 2 become a second microstrip line 21 with one end suspended on the second substrate material 23 of the second chip 2 and the other end suspended in the air. Subsequently, the wafer is processed through the back-end process to obtain an independent second chip 2. The second chip 2 is a type of chip with different materials, processes, and functions from the first chip 1, which can be integrated into the first chip 1 and combined with the first chip 1 into a whole.

[0025] like Figure 3 and Figure 4As shown, the second chip 2 includes a second substrate material 23, which can be a semiconductor material such as SiC, sapphire, G1N, G11s, Si or InP; a second microstrip line 21 with one end suspended on the second substrate material 23, one section of 21 is formed on the upper surface of the second substrate material 23, and the other end is suspended in the air, the part formed on the second substrate material 23 is used to connect various active or passive devices on the second chip 2-second devices 22, and the suspended section is used to connect the pad 13 of the first chip 1; active or passive devices formed on the second substrate material 23; a second metal ground plate 24 formed on the back of the second substrate material 23, and the second metal ground plate 24 is the signal ground of the second microstrip line 21 with one end suspended and various active or passive devices.

[0026] 2. Assembly and welding of the first chip 1 and the second chip 2 in the heterogeneous integrated radio frequency chip.

[0027] After the first chip 1 is prepared, the first metal ground plate 17 of the first chip 1 is soldered to the chip carrier 4 by a metal solder 3 such as gold or tin. Figure 5 As shown, at this time, the first chip 1 has been welded to the chip carrier 4 as a whole, and metal solder remains at the bottom of the through hole 16 that penetrates the first chip 1 .

[0028] After the second chip 2 is prepared, the second chip 2 is passed through the through hole 16 that penetrates the first chip 1 with the bottom facing downward, so that one end of the second chip 2 is suspended, and the suspended end of the second microstrip line 21 is aligned with the pad 13 of the first chip 1, and the second metal ground plate 24 of the second chip 2 is welded to the chip carrier 4 through metal solder 3 such as gold tin. Finally, through welding processes such as hot pressing welding, one end of the second chip 2 is suspended, and the suspended end of the second microstrip line 21 is welded together with the pad 13 of the first chip 1, completing the connection between the first microstrip line 12 of the first chip 1 and the suspended end of the second microstrip line 21 of the second chip 2, and realizing the transmission of microwave signals between the two chips. Figure 6 As shown, at this time, the first chip 1 and the second chip 2 have been welded to the chip carrier 4 as a whole, forming a heterogeneous integrated radio frequency chip described in the present invention.

[0029] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0030] Those skilled in the art will readily appreciate other embodiments of the invention after considering the specification and practicing the invention invented herein. This application is intended to cover any variations, uses or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art that are not invented by the present invention. The specification and examples are intended to be exemplary only, and the true scope and spirit of the invention are indicated by the claims.

[0031] The above specific implementation methods further illustrate the purpose, technical solutions and beneficial effects of the present application in detail. It should be understood that the above are only specific implementation methods of the present application and are not used to limit the protection scope of the present application. Any modifications, equivalent substitutions, improvements, etc. made on the basis of the technical solutions of the present application should be included in the protection scope of the present application.

Claims

1. A heterogeneous integrated radio frequency chip, characterized in that: The invention comprises a first chip (1), a plurality of second chips (2), a metal solder (3) and a chip carrier (4); the first chip (1) is provided with a plurality of through holes (16) for accommodating the second chips (2); the first chip (1) is fixedly connected to the chip carrier (4) via the metal solder (3); and the plurality of second chips (2) are fixedly connected to the chip carrier (4) via the metal solder (3).

2. The heterogeneous integrated radio frequency chip according to claim 1, characterized in that: The first chip (1) comprises a metal grounding plate (17), and the metal grounding plate (17) is fixedly connected to the chip carrier (4) via a metal solder (3).

3. The heterogeneous integrated radio frequency chip according to claim 2, characterized in that: The first chip (1) comprises two microstrip pads (11), a first microstrip line (12), a pressure pad (13), a plurality of first devices (14), and a first substrate material (15); the microstrip pad (11) on one side is connected to the pressure pad (13) via the first microstrip line (12); the pressure pad (13) is connected to the one of the plurality of first devices (14) closest to the microstrip pad (11) on the other side via the first microstrip line (12); the microstrip pad (11) on one side is connected in series to the plurality of first devices (14) via the first microstrip line (12); the one of the plurality of first devices (14) closest to the microstrip pad (11) on the other side is connected to the microstrip pad (11) on the other side via the first microstrip line (12); and the two microstrip pads (11), the first microstrip line (12), the pressure pad (13), and the plurality of first devices (14) are fixedly arranged on the first substrate material (15).

4. The heterogeneous integrated radio frequency chip according to claim 1, characterized in that: The second chip (2) comprises a second microstrip line (21), a second device (22), a second substrate material (23), and a second metal ground plate (24); a plurality of second chips (2) are connected in series via the second microstrip line (21); a bonding pad (13) is connected to the second microstrip line (21) via a first microstrip line (12); a second device (22) is connected in series in the middle of the second microstrip line (21); the second device (22) and a portion of the second microstrip line (21) are fixedly arranged on the second substrate material (23); and the second substrate material (23) is fixedly connected to the second metal ground plate (24).

5. The heterogeneous integrated radio frequency chip according to claim 1, characterized in that: The length, width and height of the through hole (16) are 0.01-10 mm greater than the length, width and height of the second chip (2).

6. The heterogeneous integrated radio frequency chip according to claim 1, characterized in that: The through hole (16) is adjacent to the pressure pad (13), and the distance between the through hole (16) and the pressure pad (13) is less than 10 mm.

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