Surge current debugging method, device and equipment and computer readable storage medium

Abstract

The invention discloses a surge current debugging method, device and equipment and a computer readable storage medium, and relates to the technical field of servers, and the method comprises the steps: adjusting the capacitance of a slow start time control pin connected to a protection device through adjusting the number of switched-on switching devices in rear-end branches, and / or enabling the protection device in each rear-end branch in a peak shifting manner; wherein the rear-end branch comprises a protection device, switching devices and N capacitors, each capacitor is connected with a slow start time control pin of the protection device, and the M capacitors are respectively connected with the corresponding switching devices in series and then are connected with the slow start time control pin of the protection device; 0 lt; m # imgabs0 # N; and acquiring a surge current value of the front-end power supply so as to determine the capacitance of the slow start time control pin of the access protection device and the enabling mode of the protection device according to the surge current value. The method can greatly simplify the debugging operation and improve the debugging efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of servers, and in particular to a surge current debugging method, device, equipment and a computer-readable storage medium. Background Art

[0002] The power supply requirements of different devices supported by the server are different. In order to ensure that each device can work normally, the board usually sets multiple back-end branches for powering the devices, and each back-end branch is connected to the front-end power supply. Each back-end branch includes a protection device to perform overcurrent protection through the protection device. In order to ensure voltage stability, a capacitor is usually set at the input end of the power conversion. At the moment of power on, the protection device is turned on to charge the capacitor, and an inrush current or surge current is formed at this time. If the surge current of the front-end power supply exceeds the short-circuit protection setting value, it will cause the protection to cut off and fail to start normally. For this reason, surge current debugging is required to optimize the board design. However, when performing surge current debugging, the capacitor on the board is manually disassembled and changed, and then the surge current of the front-end power supply is measured. If optimization is still required, the above operation is repeated. The whole process is cumbersome, inefficient and has the risk of damaging the board.

[0003] Therefore, how to solve the above technical defects has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0004] The purpose of the present invention is to provide a surge current debugging method, device, equipment and computer-readable storage medium, which can greatly simplify the debugging operation and improve the debugging efficiency.

[0005] In order to solve the above technical problems, the present invention provides a surge current debugging method, comprising:

[0006] The capacitor connected to the slow-start time control pin of the protection device is adjusted by adjusting the number of switch devices turned on in the back-end branch, and / or the protection devices in each of the back-end branches are enabled at off-peak times; wherein the back-end branch includes the protection device, the switch device and N capacitors, each of which is connected to the slow-start time control pin of the protection device, wherein the M capacitors are respectively connected in series with the corresponding switch devices and then connected to the slow-start time control pin of the protection device; <M N;

[0007] The surge current value of the front-end power supply is obtained so as to determine the capacitance of the slow-start time control pin connected to the protection device and the enabling mode of the protection device that meet the conditions according to the surge current value.

[0008] In some embodiments, obtaining the surge current value of the front-end power supply includes:

[0009] The current register inside the front-end power supply is read to obtain the surge current value, and the surge current value is displayed.

[0010] In some embodiments, adjusting the capacitance of the slow-start time control pin of the connected protection device by adjusting the number of switch devices turned on in the back-end branch, and / or enabling the protection devices in each of the back-end branches at a staggered peak includes:

[0011] If the power is turned on for the i-th time, the switch devices connected in series with the capacitors i-1 times are controlled to be turned on, and the protection devices are enabled at the same time; 1 i M+1;

[0012] If the power is turned on for the M+jth time, the switch devices connected in series with the M capacitors are controlled to be turned on, and the protection devices are enabled at different peak times; wherein j ranges from 2 to the target value, and when j takes different values, the enabling time intervals of the protection devices are different.

[0013] In some embodiments, the back-end branch includes three capacitors; one of the capacitors is directly connected to the slow-start time control pin of the protection device, and two of the capacitors are connected in series with the corresponding switch devices and then connected to the slow-start time control pin of the protection device;

[0014] Correspondingly, adjusting the capacitance of the slow-start time control pin connected to the protection device by adjusting the number of switch devices turned on in the back-end branch, and / or enabling the protection devices in each of the back-end branches in a staggered manner includes:

[0015] Count the number of boot times;

[0016] If it is the first time to start up, the switch devices of the two capacitors connected in series are controlled to be turned off, and after a preset time, the protection devices are enabled at the same time;

[0017] If the device is powered on for the second time, the switch device connected in series with one capacitor is controlled to be turned off, the switch device connected in series with one capacitor is controlled to be turned on, and each protection device is enabled at the same time after a preset time;

[0018] If the power is turned on for the third time, the switch devices of the two capacitors connected in series are controlled to be turned on, and the protection devices are enabled at the same time after a preset time;

[0019] If the power is turned on for the fourth time, the switch devices of the two capacitors connected in series are controlled to be turned on, and each protection device is enabled at a staggered time after a preset time, wherein the enabling time interval of each protection device is the first time interval;

[0020] If the power is turned on for the fifth time, the switch devices connected in series with the two capacitors are controlled to be turned on, and each protection device is enabled at a staggered time after a preset time period; wherein the enabling time interval of each protection device is a second time interval; and the second time interval is greater than the first time interval.

[0021] In some embodiments, it also includes:

[0022] Determining whether the surge current value of the front-end power supply unit meets a preset condition;

[0023] If it is satisfied, it is determined that the capacitance size connected to the protection device and the method of enabling the protection device when the surge current of the front-end power supply is the surge current value are feasible board design solutions.

[0024] In some embodiments, determining whether the surge current value of the front-end power supply meets a preset condition includes:

[0025] Comparing the surge current value of the front-end power supply with the short-circuit protection setting value;

[0026] If the surge current value of the front-end power supply is less than the short-circuit protection setting value and the difference between the surge current value of the front-end power supply and the short-circuit protection setting value reaches a preset threshold, the surge current value of the front-end power supply meets the preset condition.

[0027] In some embodiments, it also includes:

[0028] When there are multiple surge current values ​​that meet the preset conditions, the surge current values ​​that meet the preset conditions are compared, and the feasible board design scheme corresponding to the smallest surge current value is selected as the optimal board design scheme.

[0029] In order to solve the above technical problems, the present invention also provides a surge current debugging device, comprising:

[0030] A control module, used to adjust the capacitance of the slow-start time control pin of the protection device by adjusting the number of switch devices turned on in the back-end branch, and / or to enable the protection devices in each of the back-end branches at off-peak times; wherein the back-end branch includes the protection device, the switch device and N capacitors, each of which is connected to the slow-start time control pin of the protection device, wherein the M capacitors are respectively connected in series with the corresponding switch devices and then connected to the slow-start time control pin of the protection device; <M N;

[0031] The acquisition module is used to obtain the surge current value of the front-end power supply, so as to determine the capacitance size of the slow-start time control pin connected to the protection device and the enabling mode of the protection device according to the surge current value.

[0032] In order to solve the above technical problems, the present invention also provides a surge current debugging device, comprising:

[0033] Memory for storing computer programs;

[0034] A processor is used to implement the steps of the surge current debugging method as described above when executing the computer program.

[0035] In order to solve the above technical problem, the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the surge current debugging method described above are implemented.

[0036] The inrush current debugging method provided by the present invention comprises: adjusting the capacitor connected to the slow-start time control pin of the protection device by adjusting the number of switch devices turned on in the back-end branch, and / or enabling the protection devices in each of the back-end branches at off-peak; wherein the back-end branch comprises the protection device, the switch device and N-way capacitors, each of the capacitors is connected to the slow-start time control pin of the protection device, wherein the M-way capacitors are respectively connected in series with the corresponding switch devices and then connected to the slow-start time control pin of the protection device; <M N; obtaining the surge current value of the front-end power supply, so as to determine the capacitance size of the slow-start time control pin connected to the protection device and the enabling mode of the protection device that meet the conditions according to the surge current value.

[0037] It can be seen that the inrush current debugging method provided by the present invention can change the capacitance of the slow-start time control pin of the protection device connected to the board by controlling the number of switch devices turned on, thereby changing the inrush current and realizing inrush current debugging, without the need to manually disassemble and change the capacitance, thereby greatly simplifying the debugging operation and improving the debugging efficiency. In addition, the inrush current debugging method provided by the present invention can also perform inrush current debugging at the software level, and the protection devices in each back-end branch can be enabled by staggered peaks to change the inrush current and realize inrush current debugging. Compared with the hardware-level debugging solution of manually disassembling and changing the capacitance, the software-level debugging solution provided by the present invention can greatly simplify the debugging operation and improve the debugging efficiency.

[0038] The surge current debugging device, equipment and computer-readable storage medium provided by the present invention all have the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the prior art and the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 A schematic diagram of a flow chart of a surge current debugging method provided by an embodiment of the present invention;

[0041] Figure 2 A schematic diagram of hardware connection provided by an embodiment of the present invention;

[0042] Figure 3 A schematic diagram of a board provided by an embodiment of the present invention;

[0043] Figure 4 A signal timing diagram provided by an embodiment of the present invention;

[0044] Figure 5 A schematic diagram of a surge current debugging device provided by an embodiment of the present invention;

[0045] Figure 6 A schematic diagram of a surge current debugging device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The core of the present invention is to provide a surge current debugging method, device, equipment and computer-readable storage medium, which can greatly simplify the debugging operation and improve the debugging efficiency.

[0047] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] Please refer to Figure 1 , Figure 1 A schematic diagram of a flow chart of a surge current debugging method provided by an embodiment of the present invention, referring to Figure 1 As shown, the method includes:

[0049] S101: adjusting the capacitor connected to the slow-start time control pin of the protection device by adjusting the number of switch devices turned on in the back-end branch, and / or enabling the protection devices in each of the back-end branches at a staggered peak; wherein the back-end branch includes the protection device, the switch device and N capacitors, each of the capacitors is connected to the slow-start time control pin of the protection device, wherein the M capacitors are respectively connected in series with the corresponding switch devices and then connected to the slow-start time control pin of the protection device; <M N.

[0050] The slow-start time control pin of the protection device in the back-end branch is connected to N capacitors, N 2, wherein the M capacitors are connected in series with the switch devices and then connected to the slow-start time control pin of the protection device. The slow-start time control pin is a pin on the protection device specifically used to configure the slow-start time. The slow-start time refers to the time it takes for the voltage to build up from 0 to the target voltage. By adjusting the number of switch devices turned on in the back-end branch, the size of the capacitor connected to the slow-start time control pin of the protection device can be adjusted. The larger the capacitor connected to the slow-start time control pin, the longer the slow-start time of the protection device and the smaller the surge current on the back-end branch. Conversely, the smaller the capacitor connected to the slow-start time control pin, the shorter the slow-start time of the protection device and the larger the surge current on the back-end branch. Therefore, by adjusting the number of switch devices turned on in the back-end branch, the surge current on the back-end branch can be adjusted.

[0051] Among them, in some embodiments, at least one of the capacitors in the back-end branch is directly connected to the slow-start time control pin of the protection device. In this way, when the power is turned on, at least one of the capacitors in the back-end branch is connected to the slow-start time control pin of the protection device, so as to avoid the slow-start time control pin of the protection device in the back-end branch not being able to connect to the capacitor in time.

[0052] The surge current of the front-end power supply is the result of the superposition of the surge currents on each back-end branch. If the protection devices in each back-end branch are turned on at the same time, the surge current peaks on each back-end branch will be superimposed together, resulting in a large total surge current peak value, which is easy to trigger the protection settings of the front-end power supply. Turning on the protection devices in each back-end branch at off-peak times can avoid the surge current peaks on each back-end branch from being superimposed together, thereby reducing the total surge current. The longer the off-peak time, the smaller the total surge current.

[0053] By sending out the enable signals of the protection devices in each back-end branch at different peaks, the protection devices in each back-end branch can be opened at different peaks, thereby changing the total surge current size.

[0054] During the debugging process, the number of switch devices turned on in the back-end branches can be adjusted through the CPLD (Complex Programmable Logic Device), the protection devices in each back-end branch can be enabled at a staggered peak through the CPLD, or both the number of switch devices turned on in the back-end branches can be adjusted through the CPLD and the protection devices in each back-end branch can be enabled at a staggered peak through the CPLD.

[0055] In some embodiments, adjusting the capacitance of the slow-start time control pin of the connected protection device by adjusting the number of switch devices turned on in the back-end branch, and / or enabling the protection devices in each of the back-end branches at a staggered peak includes:

[0056] If the power is turned on for the i-th time, the switch devices connected in series with the capacitors i-1 times are controlled to be turned on, and the protection devices are enabled at the same time; 1 i M+1;

[0057] If the power is turned on for the M+jth time, the switch devices connected in series with the M capacitors are controlled to be turned on, and the protection devices are enabled at different peak times; wherein j ranges from 2 to the target value, and when j takes different values, the enabling time intervals of the protection devices are different.

[0058] The CPLD counts the number of power-on times and transmits the number of power-on times to the BMC (Baseboard Management Controller) for display on the BMC Web.

[0059] The CPLD gradually increases the number of switch devices that are turned on, so as to gradually increase the capacitance connected to the slow-start time control pin of the protection device. Before all the switch devices connected in series with the capacitors are turned on, the CPLD simultaneously enables the protection devices in each back-end branch. Then, when the slow-start time control pin of the protection device is connected to different capacitors and the protection devices in each back-end branch are enabled at the same time, the surge current value of the front-end power supply is obtained. After all the switch devices connected in series with the capacitors are turned on, that is, each capacitor in the back-end branch is connected to the slow-start time control pin of the protection device, the CPLD enables the protection devices in each back-end branch multiple times at off-peak times, and the enabling time interval of each off-peak enabling of the protection devices in each back-end branch is different, and then after each off-peak enabling of the protection devices in the back-end branch, the surge current value of the front-end power supply is obtained.

[0060] It is clear that, in addition to the above embodiments, other methods of adjusting the number of switch devices turned on in the back-end branch and / or enabling the protection devices in each of the back-end branches in a staggered manner may be adopted. For example, by controlling the number of switch devices turned on, the capacitance of the slow-start time control pin connected to the protection device is gradually changed, and under each capacitor connection scheme, the protection devices in each back-end branch are enabled at the same time, and the protection devices in each back-end branch are enabled multiple times in a staggered manner, wherein the enabling time interval of the protection devices in each back-end branch is different each time the staggered enabling is performed.

[0061] Taking the case where the back-end branch includes two capacitors, by controlling the number of switch devices that are turned on, one capacitor is connected to the slow-start time control pin of the protection device, and the protection devices in each back-end branch are enabled at the same time; by controlling the number of switch devices that are turned on, one capacitor is connected to the slow-start time control pin of the protection device, and the protection devices in each back-end branch are enabled at a staggered time, and the enabling time interval is the first time interval; by controlling the number of switch devices that are turned on, one capacitor is connected to the slow-start time control pin of the protection device, and the protection devices in each back-end branch are enabled at a staggered time, and the enabling time interval is the second time interval; the second time interval is different from the first time interval. By controlling the number of switch devices that are turned on, two capacitors are connected to the slow-start time control pin of the protection device, and the protection devices in each rear-end branch are enabled at the same time; by controlling the number of switch devices that are turned on, two capacitors are connected to the slow-start time control pin of the protection device, and the protection devices in each rear-end branch are enabled at a staggered time, and the enabling time interval is a first time interval; by controlling the number of switch devices that are turned on, two capacitors are connected to the slow-start time control pin of the protection device, and the protection devices in each rear-end branch are enabled at a staggered time, and the enabling time interval is a second time interval; the second time interval is different from the first time interval.

[0062] In some embodiments, the back-end branch includes three capacitors; one of the capacitors is directly connected to the slow-start time control pin of the protection device, and two of the capacitors are connected in series with the corresponding switch devices and then connected to the slow-start time control pin of the protection device;

[0063] Correspondingly, adjusting the capacitance of the slow-start time control pin connected to the protection device by adjusting the number of switch devices turned on in the back-end branch, and / or enabling the protection devices in each of the back-end branches in a staggered manner includes:

[0064] Count the number of boot times;

[0065] If it is the first time to start up, the switch devices of the two capacitors connected in series are controlled to be turned off, and after a preset time, the protection devices are enabled at the same time;

[0066] If the device is powered on for the second time, the switch device connected in series with one capacitor is controlled to be turned off, the switch device connected in series with one capacitor is controlled to be turned on, and each protection device is enabled at the same time after a preset time;

[0067] If the power is turned on for the third time, the switch devices of the two capacitors connected in series are controlled to be turned on, and the protection devices are enabled at the same time after a preset time;

[0068] If the power is turned on for the fourth time, the switch devices of the two capacitors connected in series are controlled to be turned on, and each protection device is enabled at a staggered time after a preset time, wherein the enabling time interval of each protection device is the first time interval;

[0069] If the power is turned on for the fifth time, the switch devices connected in series with the two capacitors are controlled to be turned on, and each protection device is enabled at a staggered time after a preset time period; wherein the enabling time interval of each protection device is a second time interval; and the second time interval is greater than the first time interval.

[0070] refer to Figure 2 As shown, the back-end branch includes three capacitors; capacitor C1 is directly connected to the slow-start time control pin SS of the protection device, capacitor C2 is connected in series with the switch device Q1 and then connected to the slow-start time control pin SS of the protection device, and capacitor C3 is connected in series with the switch device Q2 and then connected to the slow-start time control pin SS of the protection device. Figure 2 Here, K1 represents a signal for controlling the switch device Q1 to be turned on or off, and K2 represents a signal for controlling the switch device Q2 to be turned on or off.

[0071] If it is the first time to start up, the switch device Q1 and the switch device Q2 are controlled to be turned off, and after a preset time, the protection devices are enabled at the same time;

[0072] If the device is powered on for the second time, the switch device Q2 is controlled to be turned off, the switch device Q1 is controlled to be turned on, and each of the protection devices is enabled at the same time after a preset time;

[0073] If the power is turned on for the third time, the switch device Q1 and the switch device Q2 are controlled to be turned on, and the protection devices are enabled at the same time after a preset time;

[0074] If the power is turned on for the fourth time, the switch device Q1 and the switch device Q2 are controlled to be turned on, and each protection device is enabled at a staggered time after a preset time, wherein the enabling time interval of each protection device is the first time interval;

[0075] If the power is turned on for the fifth time, the switch device Q1 and the switch device Q2 are controlled to be turned on, and each protection device is enabled at a staggered time after a preset time period; wherein the enabling time interval of each protection device is a second time interval; and the second time interval is greater than the first time interval.

[0076] refer to Figure 3 As shown, taking three back-end branches as an example, the enable signals of each back-end branch are EN1, EN2, and EN3 respectively. Figure 4 The signal timing shown, the control strategy of CPLD is as follows:

[0077] Figure 4 1 to 5 represent the power-on count. When the power-on count is 1, the signals K1 and K2 are at low level, the switch devices Q1 and Q2 are turned off, and after 2t, the enable signals EN1, EN2, and EN3 are at high level, and the protection devices are enabled at the same time.

[0078] When the power-on count is 2, signal K1 is high, K2 is low, switch device Q2 is turned off, control switch device Q1 is turned on, and after 2t, enable signals EN1, EN2, EN3 are high, and each protection device is enabled at the same time.

[0079] When the power-on count is 3, the signal K1 is high level, the signal K2 is high level, the switch device Q1 and the switch device Q2 are turned on, and after 2t, the enable signals EN1, EN2, and EN3 are high level, and each protection device is enabled at the same time.

[0080] When the power-on count is 4, the signal K1 is high level, K2 is high level, the switch device Q1 and the switch device Q2 are turned on, and after 2t, the protection devices are enabled at off-peak times, wherein the time interval for EN1, EN2, and EN3 to become high level is t.

[0081] When the power-on count is 5, the signal K1 is high level, K2 is high level, the switch device Q1 and the switch device Q2 are turned on, and after 2t, the protection devices are enabled at off-peak times, wherein the time interval for EN1, EN2, and EN3 to become high level is 2t.

[0082] When the power-on count reaches 6, the loop count is triggered and starts counting again from 1.

[0083] S102: Obtain the surge current value of the front-end power supply so as to determine, according to the surge current value, the capacitance size of the slow-start time control pin connected to the protection device and the enabling mode of the protection device that meet the conditions.

[0084] Each time the number of switch devices turned on in the back-end branch is adjusted to adjust the capacitance of the slow-start time control pin connected to the protection device, and / or the protection devices in each of the back-end branches are enabled at off-peak, the surge current value of the front-end power supply is obtained, so as to determine the design scheme of the board according to the surge current value of the front-end power supply. The design scheme of the board includes the size of the capacitor connected to the protection device and the way to enable the protection device. The surge current value of the front-end power supply is obtained, and the surge current value is compared with the short-circuit protection setting value of the front-end power supply to determine whether the surge current value has enough margin, that is, to determine whether the surge current value is less than the short-circuit protection setting value of the front-end power supply, and whether the difference with the short-circuit protection setting value reaches the preset threshold. If there is enough margin, the size of the capacitor connected to the protection device and the way to enable the protection device when the surge current of the front-end power supply is the surge current value are feasible design schemes, and the subsequent board design can adopt this feasible design scheme.

[0085] For example, capacitors C1, C2, and C3 are all connected to the slow-start time control pin of the protection device, and the surge current value of the front-end power supply unit obtained when the protection devices in each back-end branch are enabled has sufficient margin. In this case, capacitor C=C1+C2+C3 connected to the slow-start time control pin of the protection device and enabling the protection devices in each back-end branch is a feasible design solution.

[0086] In some embodiments, obtaining the surge current value of the front-end power supply includes:

[0087] The current register inside the front-end power supply is read to obtain the surge current value, and the surge current value is displayed.

[0088] refer to Figure 3 As shown, the current register inside the front-end power supply can be read through the BMC using the current detection lead of the IMON to obtain the surge current value of the front-end power supply and display it on the BMC Web.

[0089] Different from the solution of measuring the surge current value of the front-end power supply by dedicated measuring fixtures and equipment, the method of obtaining the surge current value of the front-end power supply by reading the current register inside the front-end power supply in this embodiment does not require dedicated measuring fixtures and equipment, which can greatly simplify the operation of obtaining the surge current value, avoid dependence on measuring fixtures and equipment, and avoid the problem of being unable to perform measurement operations in a small space, and the surge current value of the front-end power supply at power-on can be intuitively read through BMC remote access.

[0090] When the number of power-on times and the inrush current value of the front-end power supply are displayed through the BMC Web, you can intuitively view the number of power-on times and the inrush current value of the front-end power supply obtained during the current power-on. Among them, only the maximum inrush current value is recorded each time the power is turned on, and the data is refreshed after the power is turned on again.

[0091] In some embodiments, it also includes:

[0092] Determining whether the surge current value of the front-end power supply unit meets a preset condition;

[0093] If it is satisfied, it is determined that the capacitance size connected to the protection device and the method of enabling the protection device when the surge current of the front-end power supply is the surge current value are feasible board design solutions.

[0094] In this embodiment, the design scheme of the board is automatically executed according to the surge current value, for example, it can be executed by the BMC, which does not require manual analysis and can greatly improve efficiency.

[0095] In some embodiments, determining whether the surge current value of the front-end power supply meets a preset condition includes:

[0096] Comparing the surge current value of the front-end power supply with the short-circuit protection setting value;

[0097] If the surge current value of the front-end power supply is less than the short-circuit protection setting value and the difference between the surge current value of the front-end power supply and the short-circuit protection setting value reaches a preset threshold, the surge current value of the front-end power supply meets the preset condition.

[0098] In some embodiments, it also includes:

[0099] When there are multiple surge current values ​​that meet the preset conditions, the surge current values ​​that meet the preset conditions are compared, and the feasible board design scheme corresponding to the smallest surge current value is selected as the optimal board design scheme.

[0100] When there are multiple surge current values ​​that meet the preset conditions, the sizes of the surge current values ​​that meet the preset conditions can be further compared, and the feasible board design scheme corresponding to the smallest surge current value can be selected as the optimal board design scheme, so that the optimal board design scheme can be adopted preferentially.

[0101] For example, capacitors C1, C2, and C3 are all connected to the slow-start time control pin of the protection device, and the surge current value (recorded as surge current value 1) of the front-end power supply unit obtained when the protection devices in each back-end branch are enabled meets the preset conditions. The capacitor C=C1+C2+C3 connected to the slow-start time control pin of the protection device and enabling the protection devices in each back-end branch is a feasible design scheme (recorded as design scheme 1).

[0102] Capacitor C1, capacitor C2 and capacitor C3 are all connected to the slow-start time control pin of the protection device. When the protection devices in each rear-end branch are enabled in a staggered manner, the surge current value (recorded as surge current value 2) of the front-end power supply unit obtained meets the preset conditions. The capacitor C=C1+C2+C3 connected to the slow-start time control pin of the protection device, and staggered enabling of the protection devices in each rear-end branch is a feasible design scheme (recorded as design scheme 2).

[0103] If the surge current value 2 is less than the surge current value 1, then the design scheme 2 is selected as the optimal board design scheme, so that the optimal board design scheme is preferentially adopted.

[0104] In summary, the inrush current debugging method provided by the present invention can change the capacitance of the slow-start time control pin of the protection device connected to the board by controlling the number of switch devices turned on, thereby changing the inrush current and realizing inrush current debugging, without the need to manually disassemble and change the capacitance, thereby greatly simplifying the debugging operation and improving the debugging efficiency. In addition, the inrush current debugging method provided by the present invention can also perform inrush current debugging at the software level, and the protection devices in each back-end branch can be enabled by peak shifting to change the inrush current and realize inrush current debugging. Compared with the hardware-level debugging solution of manually disassembling and changing the capacitance, the software-level debugging solution provided by the present invention can greatly simplify the debugging operation and improve the debugging efficiency.

[0105] The present invention also provides a surge current debugging device, and the device described below can be referred to in correspondence with the method described above. Figure 5 , Figure 5 A schematic diagram of a surge current debugging device provided by an embodiment of the present invention, combined with Figure 5 As shown, the device comprises:

[0106] A control module 10, used to adjust the capacitance of the slow-start time control pin of the protection device by adjusting the number of switch devices turned on in the back-end branch, and / or to enable the protection devices in each of the back-end branches at off-peak times; wherein the back-end branch includes the protection device, the switch device and N capacitors, each of which is connected to the slow-start time control pin of the protection device, wherein the M capacitors are connected in series with the corresponding switch devices and then connected to the slow-start time control pin of the protection device; <M N;

[0107] The acquisition module 20 is used to obtain the surge current value of the front-end power supply, so as to determine the capacitance size of the slow-start time control pin connected to the protection device and the enabling mode of the protection device according to the surge current value.

[0108] Based on the above embodiment, as a specific implementation mode, the acquisition module 20 is specifically used for:

[0109] The current register inside the front-end power supply is read to obtain the surge current value, and the surge current value is displayed.

[0110] Based on the above embodiment, as a specific implementation, the control module 10 includes:

[0111] A first control unit is used for controlling the switch devices of the i-1 capacitors connected in series to conduct when the power is turned on for the i-th time, and enabling each of the protection devices at the same time; i M+1;

[0112] The second control unit is used to control the switching devices of the M-way capacitors connected in series to conduct if the power is turned on for the M+jth time, and enable each protection device at a staggered peak; wherein j takes a value from 2 to a target value, and when j takes different values, the enabling time intervals of each protection device are different.

[0113] Based on the above embodiment, as a specific implementation method, the back-end branch includes three capacitors; one of the capacitors is directly connected to the slow-start time control pin of the protection device, and two of the capacitors are respectively connected in series with the corresponding switch devices and then connected to the slow-start time control pin of the protection device;

[0114] Accordingly, the control module 10 includes:

[0115] Statistical unit, used to count the number of boot times;

[0116] A first control and enable unit, for controlling the switch devices of the two capacitors connected in series to turn off if the device is turned on for the first time, and enabling each of the protection devices at the same time after a preset time;

[0117] A second control and enable unit is used to control the switch device connected in series with one capacitor to be turned off, control the switch device connected in series with one capacitor to be turned on, and enable each protection device at the same time after a preset time period if the device is turned on for the second time;

[0118] A third control and enabling unit, for controlling the switching devices of the two capacitors connected in series to conduct if the device is powered on for the third time, and enabling the protection devices at the same time after a preset time;

[0119] a fourth control and enable unit, configured to control the switch devices connected in series with the two capacitors to be turned on if the device is turned on for the fourth time, and enable each protection device in a staggered manner after a preset time period, wherein the enabling time interval of each protection device is the first time interval;

[0120] The fifth control and enabling unit is used to control the switching devices connected in series with the two capacitors to conduct if the power is turned on for the fifth time, and to enable each protection device in a staggered manner after a preset time period; wherein the enabling time interval of each protection device is a second time interval; and the second time interval is greater than the first time interval.

[0121] Based on the above embodiment, as a specific implementation method, it also includes:

[0122] A judging module, used to judge whether the surge current value of the front-end power supply unit meets a preset condition;

[0123] The determination module is used to determine whether the capacitance value connected to the protection device and the method of enabling the protection device are feasible board design solutions when the surge current of the front-end power supply is the surge current value if the conditions are met.

[0124] Based on the above embodiment, as a specific implementation method, the judgment module includes:

[0125] A comparison unit, used for comparing the surge current value of the front-end power supply with a short-circuit protection setting value;

[0126] A determination unit is used to determine that if the surge current value of the front-end power supply is less than the short-circuit protection setting value and the difference between the surge current value of the front-end power supply and the short-circuit protection setting value reaches a preset threshold, then the surge current value of the front-end power supply meets the preset condition.

[0127] Based on the above embodiment, as a specific implementation method, it also includes:

[0128] The selection module is used to compare the surge current values ​​that meet the preset conditions when there are multiple surge current values ​​that meet the preset conditions, and select the feasible board design scheme corresponding to the smallest surge current value as the optimal board design scheme.

[0129] The present invention also provides a surge current debugging device, referring to Figure 6 As shown, the device includes a memory 1 and a processor 2 .

[0130] Memory 1, used for storing computer programs;

[0131] Processor 2 is used to execute the computer program to implement the following steps:

[0132] The capacitor connected to the slow-start time control pin of the protection device is adjusted by adjusting the number of switch devices turned on in the back-end branch, and / or the protection devices in each of the back-end branches are enabled at off-peak times; wherein the back-end branch includes the protection device, the switch device and N capacitors, each of which is connected to the slow-start time control pin of the protection device, wherein the M capacitors are respectively connected in series with the corresponding switch devices and then connected to the slow-start time control pin of the protection device; <M N; obtaining the surge current value of the front-end power supply, so as to determine the capacitance size of the slow-start time control pin connected to the protection device and the enabling mode of the protection device that meet the conditions according to the surge current value.

[0133] For an introduction to the device provided by the present invention, please refer to the above method embodiment, and the present invention will not be elaborated here.

[0134] The present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the following steps can be implemented:

[0135] The capacitor connected to the slow-start time control pin of the protection device is adjusted by adjusting the number of switch devices turned on in the back-end branch, and / or the protection devices in each of the back-end branches are enabled at off-peak times; wherein the back-end branch includes the protection device, the switch device and N capacitors, each of which is connected to the slow-start time control pin of the protection device, wherein the M capacitors are respectively connected in series with the corresponding switch devices and then connected to the slow-start time control pin of the protection device; <M N; obtaining the surge current value of the front-end power supply, so as to determine the capacitance size of the slow-start time control pin connected to the protection device and the enabling mode of the protection device that meet the conditions according to the surge current value.

[0136] The computer-readable storage medium may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0137] For an introduction to the computer-readable storage medium provided by the present invention, please refer to the above method embodiment, and the present invention will not elaborate on it here.

[0138] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the devices, equipment, and computer-readable storage media disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0139] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0140] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0141] The above is a detailed introduction to the surge current debugging method, device, equipment and computer-readable storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A surge current debugging method, characterized in that: include: The capacitor connected to the slow-start time control pin of the protection device is adjusted by adjusting the number of switch devices turned on in the back-end branch, and / or the protection devices in each of the back-end branches are enabled at off-peak times; wherein the back-end branch includes the protection device, the switch device and N capacitors, each of which is connected to the slow-start time control pin of the protection device, wherein the M capacitors are respectively connected in series with the corresponding switch devices and then connected to the slow-start time control pin of the protection device; <M N; The surge current value of the front-end power supply is obtained so as to determine the capacitance of the slow-start time control pin connected to the protection device and the enabling mode of the protection device that meet the conditions according to the surge current value.

2. The surge current debugging method according to claim 1, characterized in that: Obtaining the surge current value of the front-end power supply includes: The current register inside the front-end power supply is read to obtain the surge current value, and the surge current value is displayed.

3. The surge current debugging method according to claim 1, characterized in that: The method of adjusting the capacitance of the slow-start time control pin of the connected protection device by adjusting the number of switch devices turned on in the back-end branch, and / or enabling the protection devices in each of the back-end branches at a staggered peak comprises: If the power is turned on for the i-th time, the switch devices connected in series with the capacitors i-1 times are controlled to be turned on, and the protection devices are enabled at the same time; 1 i M+1; If the power is turned on for the M+jth time, the switch devices connected in series with the M capacitors are controlled to be turned on, and the protection devices are enabled at different peak times; wherein j ranges from 2 to the target value, and when j takes different values, the enabling time intervals of the protection devices are different.

4. The surge current debugging method according to claim 3, characterized in that: The back-end branch includes three capacitors; one of the capacitors is directly connected to the slow-start time control pin of the protection device, and two of the capacitors are connected in series with the corresponding switch devices and then connected to the slow-start time control pin of the protection device; Correspondingly, adjusting the capacitance of the slow-start time control pin connected to the protection device by adjusting the number of switch devices turned on in the back-end branch, and / or enabling the protection devices in each of the back-end branches in a staggered manner includes: Count the number of boot times; If it is the first time to start up, the switch devices of the two capacitors connected in series are controlled to be turned off, and after a preset time, the protection devices are enabled at the same time; If the device is powered on for the second time, the switch device connected in series with one capacitor is controlled to be turned off, the switch device connected in series with one capacitor is controlled to be turned on, and each protection device is enabled at the same time after a preset time; If the power is turned on for the third time, the switch devices of the two capacitors connected in series are controlled to be turned on, and the protection devices are enabled at the same time after a preset time; If the power is turned on for the fourth time, the switch devices of the two capacitors connected in series are controlled to be turned on, and each protection device is enabled at a staggered time after a preset time, wherein the enabling time interval of each protection device is the first time interval; If the power is turned on for the fifth time, the switch devices connected in series with the two capacitors are controlled to be turned on, and each protection device is enabled at a staggered time after a preset time period; wherein the enabling time interval of each protection device is a second time interval; and the second time interval is greater than the first time interval.

5. The surge current debugging method according to claim 1, characterized in that: Also includes: Determining whether the surge current value of the front-end power supply unit meets a preset condition; If it is satisfied, it is determined that the capacitance size connected to the protection device and the method of enabling the protection device when the surge current of the front-end power supply is the surge current value are feasible board design solutions.

6. The surge current debugging method according to claim 5, characterized in that: Determining whether the surge current value of the front-end power supply meets a preset condition includes: Comparing the surge current value of the front-end power supply with the short-circuit protection setting value; If the surge current value of the front-end power supply is less than the short-circuit protection setting value and the difference between the surge current value of the front-end power supply and the short-circuit protection setting value reaches a preset threshold, the surge current value of the front-end power supply meets the preset condition.

7. The surge current debugging method according to claim 5, characterized in that: Also includes: When there are multiple surge current values ​​that meet the preset conditions, the surge current values ​​that meet the preset conditions are compared, and the feasible board design scheme corresponding to the smallest surge current value is selected as the optimal board design scheme.

8. A surge current debugging device, characterized in that: include: A control module, used to adjust the capacitance of the slow-start time control pin of the protection device by adjusting the number of switch devices turned on in the back-end branch, and / or to enable the protection devices in each of the back-end branches at off-peak times; wherein the back-end branch includes the protection device, the switch device and N capacitors, each of which is connected to the slow-start time control pin of the protection device, wherein the M capacitors are respectively connected in series with the corresponding switch devices and then connected to the slow-start time control pin of the protection device; <M N; The acquisition module is used to obtain the surge current value of the front-end power supply, so as to determine the capacitance size of the slow-start time control pin connected to the protection device and the enabling mode of the protection device according to the surge current value.

9. A surge current debugging device, characterized in that: include: Memory for storing computer programs; A processor is used to implement the steps of the surge current debugging method as described in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the surge current debugging method according to any one of claims 1 to 7 are implemented.

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